Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.27 89.27 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/8.prim_async_alert.3950714911
92.39 3.13 100.00 0.00 93.75 0.00 100.00 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/10.prim_sync_alert.686541497
93.90 1.51 100.00 0.00 95.83 2.08 100.00 0.00 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.864210195
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/12.prim_async_alert.1031022830
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.987414418
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/3.prim_sync_alert.1484200014

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1549864145
/workspace/coverage/default/1.prim_async_alert.1230015934
/workspace/coverage/default/10.prim_async_alert.929346949
/workspace/coverage/default/11.prim_async_alert.4084999019
/workspace/coverage/default/13.prim_async_alert.2898752330
/workspace/coverage/default/14.prim_async_alert.942064113
/workspace/coverage/default/15.prim_async_alert.1322230461
/workspace/coverage/default/16.prim_async_alert.976606782
/workspace/coverage/default/17.prim_async_alert.1625626212
/workspace/coverage/default/18.prim_async_alert.3961691108
/workspace/coverage/default/19.prim_async_alert.3874686492
/workspace/coverage/default/2.prim_async_alert.1776583082
/workspace/coverage/default/3.prim_async_alert.90468340
/workspace/coverage/default/4.prim_async_alert.1341448521
/workspace/coverage/default/5.prim_async_alert.3563742696
/workspace/coverage/default/6.prim_async_alert.3279371527
/workspace/coverage/default/7.prim_async_alert.1892616364
/workspace/coverage/default/9.prim_async_alert.3640448474
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.739133887
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1091108217
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3097682126
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1654881871
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.854347567
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3594328997
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3351952756
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1999886157
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3164018100
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2677714508
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3444561113
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.103322817
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.7556533
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2503441257
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.353501243
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1572568401
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1237369474
/workspace/coverage/sync_alert/0.prim_sync_alert.777692766
/workspace/coverage/sync_alert/1.prim_sync_alert.1913199177
/workspace/coverage/sync_alert/11.prim_sync_alert.628902589
/workspace/coverage/sync_alert/12.prim_sync_alert.1503830232
/workspace/coverage/sync_alert/13.prim_sync_alert.3655956311
/workspace/coverage/sync_alert/14.prim_sync_alert.1285673402
/workspace/coverage/sync_alert/15.prim_sync_alert.3445578685
/workspace/coverage/sync_alert/16.prim_sync_alert.2762833722
/workspace/coverage/sync_alert/17.prim_sync_alert.681588884
/workspace/coverage/sync_alert/18.prim_sync_alert.1579861536
/workspace/coverage/sync_alert/19.prim_sync_alert.3958900021
/workspace/coverage/sync_alert/2.prim_sync_alert.3649419729
/workspace/coverage/sync_alert/4.prim_sync_alert.1713375867
/workspace/coverage/sync_alert/5.prim_sync_alert.1934626846
/workspace/coverage/sync_alert/6.prim_sync_alert.2025155599
/workspace/coverage/sync_alert/7.prim_sync_alert.1245745243
/workspace/coverage/sync_alert/8.prim_sync_alert.4224574693
/workspace/coverage/sync_alert/9.prim_sync_alert.3174333181
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1986227519
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.15925475
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.468090401
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.373756206
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.570003075
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3261344407
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3911177687
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3354528479
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.207347741
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.72563260
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1943409054
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1362956044
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2266741412
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3526057648
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1995179467
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.16566541
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3451106108
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1879621287
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1895541208
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3219770667



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/10.prim_async_alert.929346949 Jun 11 03:43:20 PM PDT 24 Jun 11 03:43:22 PM PDT 24 12316813 ps
T2 /workspace/coverage/default/8.prim_async_alert.3950714911 Jun 11 03:43:21 PM PDT 24 Jun 11 03:43:24 PM PDT 24 12579361 ps
T3 /workspace/coverage/default/16.prim_async_alert.976606782 Jun 11 03:43:23 PM PDT 24 Jun 11 03:43:26 PM PDT 24 11868933 ps
T16 /workspace/coverage/default/13.prim_async_alert.2898752330 Jun 11 03:43:22 PM PDT 24 Jun 11 03:43:25 PM PDT 24 10829973 ps
T8 /workspace/coverage/default/1.prim_async_alert.1230015934 Jun 11 03:43:14 PM PDT 24 Jun 11 03:43:16 PM PDT 24 11489285 ps
T9 /workspace/coverage/default/18.prim_async_alert.3961691108 Jun 11 03:43:22 PM PDT 24 Jun 11 03:43:25 PM PDT 24 11039743 ps
T7 /workspace/coverage/default/0.prim_async_alert.1549864145 Jun 11 03:43:15 PM PDT 24 Jun 11 03:43:18 PM PDT 24 10239931 ps
T17 /workspace/coverage/default/7.prim_async_alert.1892616364 Jun 11 03:43:20 PM PDT 24 Jun 11 03:43:23 PM PDT 24 11556418 ps
T18 /workspace/coverage/default/19.prim_async_alert.3874686492 Jun 11 03:43:19 PM PDT 24 Jun 11 03:43:22 PM PDT 24 11896222 ps
T19 /workspace/coverage/default/6.prim_async_alert.3279371527 Jun 11 03:43:15 PM PDT 24 Jun 11 03:43:17 PM PDT 24 11460205 ps
T23 /workspace/coverage/default/3.prim_async_alert.90468340 Jun 11 03:43:15 PM PDT 24 Jun 11 03:43:17 PM PDT 24 10938890 ps
T48 /workspace/coverage/default/5.prim_async_alert.3563742696 Jun 11 03:43:15 PM PDT 24 Jun 11 03:43:19 PM PDT 24 10095421 ps
T11 /workspace/coverage/default/17.prim_async_alert.1625626212 Jun 11 03:43:24 PM PDT 24 Jun 11 03:43:26 PM PDT 24 11893430 ps
T20 /workspace/coverage/default/9.prim_async_alert.3640448474 Jun 11 03:43:23 PM PDT 24 Jun 11 03:43:25 PM PDT 24 10546579 ps
T12 /workspace/coverage/default/12.prim_async_alert.1031022830 Jun 11 03:43:21 PM PDT 24 Jun 11 03:43:24 PM PDT 24 11865198 ps
T21 /workspace/coverage/default/4.prim_async_alert.1341448521 Jun 11 03:43:18 PM PDT 24 Jun 11 03:43:21 PM PDT 24 11046399 ps
T49 /workspace/coverage/default/11.prim_async_alert.4084999019 Jun 11 03:43:21 PM PDT 24 Jun 11 03:43:24 PM PDT 24 11230824 ps
T22 /workspace/coverage/default/15.prim_async_alert.1322230461 Jun 11 03:43:21 PM PDT 24 Jun 11 03:43:24 PM PDT 24 11050460 ps
T50 /workspace/coverage/default/2.prim_async_alert.1776583082 Jun 11 03:43:16 PM PDT 24 Jun 11 03:43:20 PM PDT 24 11425186 ps
T51 /workspace/coverage/default/14.prim_async_alert.942064113 Jun 11 03:43:21 PM PDT 24 Jun 11 03:43:24 PM PDT 24 11096231 ps
T39 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.739133887 Jun 11 01:08:28 PM PDT 24 Jun 11 01:08:30 PM PDT 24 29592628 ps
T15 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.353501243 Jun 11 01:08:29 PM PDT 24 Jun 11 01:08:30 PM PDT 24 29669596 ps
T40 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3444561113 Jun 11 01:08:28 PM PDT 24 Jun 11 01:08:29 PM PDT 24 29805307 ps
T41 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3351952756 Jun 11 01:08:38 PM PDT 24 Jun 11 01:08:40 PM PDT 24 31278564 ps
T42 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.864210195 Jun 11 01:08:39 PM PDT 24 Jun 11 01:08:40 PM PDT 24 31118943 ps
T43 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3097682126 Jun 11 01:08:40 PM PDT 24 Jun 11 01:08:42 PM PDT 24 29952736 ps
T44 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.854347567 Jun 11 01:08:39 PM PDT 24 Jun 11 01:08:41 PM PDT 24 30881307 ps
T45 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1572568401 Jun 11 01:08:31 PM PDT 24 Jun 11 01:08:32 PM PDT 24 29890343 ps
T46 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.103322817 Jun 11 01:08:31 PM PDT 24 Jun 11 01:08:32 PM PDT 24 29650691 ps
T47 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1237369474 Jun 11 01:08:39 PM PDT 24 Jun 11 01:08:41 PM PDT 24 30747527 ps
T52 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1091108217 Jun 11 01:08:41 PM PDT 24 Jun 11 01:08:42 PM PDT 24 30229123 ps
T53 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2503441257 Jun 11 01:08:28 PM PDT 24 Jun 11 01:08:29 PM PDT 24 28970474 ps
T54 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1654881871 Jun 11 01:08:38 PM PDT 24 Jun 11 01:08:39 PM PDT 24 31965441 ps
T4 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.987414418 Jun 11 01:08:29 PM PDT 24 Jun 11 01:08:30 PM PDT 24 28355807 ps
T55 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.7556533 Jun 11 01:08:27 PM PDT 24 Jun 11 01:08:28 PM PDT 24 31006882 ps
T38 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1999886157 Jun 11 01:08:40 PM PDT 24 Jun 11 01:08:41 PM PDT 24 30679665 ps
T13 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3594328997 Jun 11 01:08:39 PM PDT 24 Jun 11 01:08:41 PM PDT 24 30763877 ps
T56 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2677714508 Jun 11 01:08:28 PM PDT 24 Jun 11 01:08:29 PM PDT 24 29883622 ps
T14 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3164018100 Jun 11 01:08:38 PM PDT 24 Jun 11 01:08:40 PM PDT 24 31087871 ps
T24 /workspace/coverage/sync_alert/0.prim_sync_alert.777692766 Jun 11 02:46:04 PM PDT 24 Jun 11 02:46:06 PM PDT 24 8962663 ps
T25 /workspace/coverage/sync_alert/15.prim_sync_alert.3445578685 Jun 11 02:46:13 PM PDT 24 Jun 11 02:46:14 PM PDT 24 9892468 ps
T34 /workspace/coverage/sync_alert/8.prim_sync_alert.4224574693 Jun 11 02:46:03 PM PDT 24 Jun 11 02:46:05 PM PDT 24 8939954 ps
T35 /workspace/coverage/sync_alert/7.prim_sync_alert.1245745243 Jun 11 02:46:05 PM PDT 24 Jun 11 02:46:07 PM PDT 24 8761158 ps
T36 /workspace/coverage/sync_alert/10.prim_sync_alert.686541497 Jun 11 02:46:05 PM PDT 24 Jun 11 02:46:06 PM PDT 24 9470617 ps
T26 /workspace/coverage/sync_alert/17.prim_sync_alert.681588884 Jun 11 02:46:22 PM PDT 24 Jun 11 02:46:24 PM PDT 24 9162310 ps
T27 /workspace/coverage/sync_alert/19.prim_sync_alert.3958900021 Jun 11 02:46:11 PM PDT 24 Jun 11 02:46:13 PM PDT 24 9199053 ps
T37 /workspace/coverage/sync_alert/5.prim_sync_alert.1934626846 Jun 11 02:46:05 PM PDT 24 Jun 11 02:46:07 PM PDT 24 9063612 ps
T28 /workspace/coverage/sync_alert/6.prim_sync_alert.2025155599 Jun 11 02:46:03 PM PDT 24 Jun 11 02:46:04 PM PDT 24 10464262 ps
T29 /workspace/coverage/sync_alert/9.prim_sync_alert.3174333181 Jun 11 02:46:03 PM PDT 24 Jun 11 02:46:05 PM PDT 24 8726259 ps
T57 /workspace/coverage/sync_alert/4.prim_sync_alert.1713375867 Jun 11 02:46:05 PM PDT 24 Jun 11 02:46:07 PM PDT 24 9577488 ps
T30 /workspace/coverage/sync_alert/13.prim_sync_alert.3655956311 Jun 11 02:46:16 PM PDT 24 Jun 11 02:46:18 PM PDT 24 9514252 ps
T10 /workspace/coverage/sync_alert/3.prim_sync_alert.1484200014 Jun 11 02:46:04 PM PDT 24 Jun 11 02:46:06 PM PDT 24 8815228 ps
T58 /workspace/coverage/sync_alert/1.prim_sync_alert.1913199177 Jun 11 02:46:04 PM PDT 24 Jun 11 02:46:06 PM PDT 24 8252214 ps
T31 /workspace/coverage/sync_alert/2.prim_sync_alert.3649419729 Jun 11 02:46:00 PM PDT 24 Jun 11 02:46:02 PM PDT 24 9490890 ps
T59 /workspace/coverage/sync_alert/12.prim_sync_alert.1503830232 Jun 11 02:46:13 PM PDT 24 Jun 11 02:46:15 PM PDT 24 9843542 ps
T60 /workspace/coverage/sync_alert/14.prim_sync_alert.1285673402 Jun 11 02:46:15 PM PDT 24 Jun 11 02:46:18 PM PDT 24 9917630 ps
T32 /workspace/coverage/sync_alert/18.prim_sync_alert.1579861536 Jun 11 02:46:21 PM PDT 24 Jun 11 02:46:24 PM PDT 24 9402718 ps
T33 /workspace/coverage/sync_alert/16.prim_sync_alert.2762833722 Jun 11 02:46:16 PM PDT 24 Jun 11 02:46:19 PM PDT 24 10250265 ps
T61 /workspace/coverage/sync_alert/11.prim_sync_alert.628902589 Jun 11 02:46:12 PM PDT 24 Jun 11 02:46:13 PM PDT 24 8702025 ps
T62 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.16566541 Jun 11 03:24:45 PM PDT 24 Jun 11 03:24:47 PM PDT 24 26011904 ps
T63 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2266741412 Jun 11 03:24:48 PM PDT 24 Jun 11 03:24:50 PM PDT 24 29705400 ps
T64 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1943409054 Jun 11 03:24:45 PM PDT 24 Jun 11 03:24:47 PM PDT 24 27611954 ps
T65 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3451106108 Jun 11 03:24:46 PM PDT 24 Jun 11 03:24:48 PM PDT 24 29928983 ps
T66 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.468090401 Jun 11 03:24:47 PM PDT 24 Jun 11 03:24:49 PM PDT 24 28142006 ps
T67 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3261344407 Jun 11 03:24:45 PM PDT 24 Jun 11 03:24:46 PM PDT 24 31694564 ps
T68 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.373756206 Jun 11 03:24:47 PM PDT 24 Jun 11 03:24:50 PM PDT 24 31164464 ps
T5 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3354528479 Jun 11 03:24:46 PM PDT 24 Jun 11 03:24:48 PM PDT 24 28830587 ps
T69 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.207347741 Jun 11 03:24:47 PM PDT 24 Jun 11 03:24:49 PM PDT 24 28925390 ps
T6 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1995179467 Jun 11 03:24:46 PM PDT 24 Jun 11 03:24:48 PM PDT 24 26604954 ps
T70 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1895541208 Jun 11 03:24:45 PM PDT 24 Jun 11 03:24:47 PM PDT 24 29593729 ps
T71 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.15925475 Jun 11 03:24:49 PM PDT 24 Jun 11 03:24:51 PM PDT 24 27252205 ps
T72 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1986227519 Jun 11 03:24:46 PM PDT 24 Jun 11 03:24:48 PM PDT 24 26046232 ps
T73 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3911177687 Jun 11 03:24:48 PM PDT 24 Jun 11 03:24:50 PM PDT 24 26661013 ps
T74 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.72563260 Jun 11 03:24:47 PM PDT 24 Jun 11 03:24:49 PM PDT 24 28002994 ps
T75 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1362956044 Jun 11 03:24:49 PM PDT 24 Jun 11 03:24:51 PM PDT 24 27757788 ps
T76 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3526057648 Jun 11 03:24:48 PM PDT 24 Jun 11 03:24:50 PM PDT 24 27260324 ps
T77 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3219770667 Jun 11 03:24:45 PM PDT 24 Jun 11 03:24:47 PM PDT 24 30190156 ps
T78 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1879621287 Jun 11 03:24:49 PM PDT 24 Jun 11 03:24:52 PM PDT 24 26603649 ps
T79 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.570003075 Jun 11 03:24:48 PM PDT 24 Jun 11 03:24:50 PM PDT 24 27321986 ps

Test location /workspace/coverage/default/8.prim_async_alert.3950714911
Short name T2
Test name
Test status
Simulation time 12579361 ps
CPU time 0.38 seconds
Started Jun 11 03:43:21 PM PDT 24
Finished Jun 11 03:43:24 PM PDT 24
Peak memory 145700 kb
Host smart-62ade1b9-bb3a-42c9-a697-c84185fb482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950714911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3950714911
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.686541497
Short name T36
Test name
Test status
Simulation time 9470617 ps
CPU time 0.39 seconds
Started Jun 11 02:46:05 PM PDT 24
Finished Jun 11 02:46:06 PM PDT 24
Peak memory 145632 kb
Host smart-c1c0149c-2be3-458c-bd55-93f805a8eebd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=686541497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.686541497
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.864210195
Short name T42
Test name
Test status
Simulation time 31118943 ps
CPU time 0.4 seconds
Started Jun 11 01:08:39 PM PDT 24
Finished Jun 11 01:08:40 PM PDT 24
Peak memory 145296 kb
Host smart-14411d25-6777-4ff8-a2f4-02349e673c3c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=864210195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.864210195
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1031022830
Short name T12
Test name
Test status
Simulation time 11865198 ps
CPU time 0.38 seconds
Started Jun 11 03:43:21 PM PDT 24
Finished Jun 11 03:43:24 PM PDT 24
Peak memory 145840 kb
Host smart-803b09d5-d154-41b1-991a-5a8d0189bfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031022830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1031022830
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.987414418
Short name T4
Test name
Test status
Simulation time 28355807 ps
CPU time 0.39 seconds
Started Jun 11 01:08:29 PM PDT 24
Finished Jun 11 01:08:30 PM PDT 24
Peak memory 145288 kb
Host smart-f1ca7af4-bf3c-4802-ae69-7c4c8ee33ff3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=987414418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.987414418
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1484200014
Short name T10
Test name
Test status
Simulation time 8815228 ps
CPU time 0.4 seconds
Started Jun 11 02:46:04 PM PDT 24
Finished Jun 11 02:46:06 PM PDT 24
Peak memory 145560 kb
Host smart-14e74a94-5971-4195-afef-b3fb359fa47b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1484200014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1484200014
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1549864145
Short name T7
Test name
Test status
Simulation time 10239931 ps
CPU time 0.38 seconds
Started Jun 11 03:43:15 PM PDT 24
Finished Jun 11 03:43:18 PM PDT 24
Peak memory 145756 kb
Host smart-fd14f1d3-f34c-4f24-95ad-e045a1a76d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549864145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1549864145
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1230015934
Short name T8
Test name
Test status
Simulation time 11489285 ps
CPU time 0.39 seconds
Started Jun 11 03:43:14 PM PDT 24
Finished Jun 11 03:43:16 PM PDT 24
Peak memory 145780 kb
Host smart-1a0eb308-1e48-45c9-a81f-31d8767bf2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230015934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1230015934
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.929346949
Short name T1
Test name
Test status
Simulation time 12316813 ps
CPU time 0.38 seconds
Started Jun 11 03:43:20 PM PDT 24
Finished Jun 11 03:43:22 PM PDT 24
Peak memory 145788 kb
Host smart-2421c8ba-0578-456a-b192-14896edc4e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929346949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.929346949
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.4084999019
Short name T49
Test name
Test status
Simulation time 11230824 ps
CPU time 0.43 seconds
Started Jun 11 03:43:21 PM PDT 24
Finished Jun 11 03:43:24 PM PDT 24
Peak memory 145816 kb
Host smart-5957e536-7615-4879-b12c-ffc9965fed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084999019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4084999019
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2898752330
Short name T16
Test name
Test status
Simulation time 10829973 ps
CPU time 0.39 seconds
Started Jun 11 03:43:22 PM PDT 24
Finished Jun 11 03:43:25 PM PDT 24
Peak memory 145824 kb
Host smart-b013944d-3436-4c73-8222-073c3fe92750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898752330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2898752330
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.942064113
Short name T51
Test name
Test status
Simulation time 11096231 ps
CPU time 0.38 seconds
Started Jun 11 03:43:21 PM PDT 24
Finished Jun 11 03:43:24 PM PDT 24
Peak memory 145736 kb
Host smart-b87c554e-236b-4c4c-8f31-627af23e6055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942064113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.942064113
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1322230461
Short name T22
Test name
Test status
Simulation time 11050460 ps
CPU time 0.39 seconds
Started Jun 11 03:43:21 PM PDT 24
Finished Jun 11 03:43:24 PM PDT 24
Peak memory 145808 kb
Host smart-e769703c-ca13-4edb-b0d1-faee39cac518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322230461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1322230461
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.976606782
Short name T3
Test name
Test status
Simulation time 11868933 ps
CPU time 0.39 seconds
Started Jun 11 03:43:23 PM PDT 24
Finished Jun 11 03:43:26 PM PDT 24
Peak memory 145780 kb
Host smart-ad5794ed-cc88-4673-adb3-9ae121e22b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976606782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.976606782
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1625626212
Short name T11
Test name
Test status
Simulation time 11893430 ps
CPU time 0.4 seconds
Started Jun 11 03:43:24 PM PDT 24
Finished Jun 11 03:43:26 PM PDT 24
Peak memory 145828 kb
Host smart-27634a30-5a10-48dd-a08e-c1c9369c6e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625626212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1625626212
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3961691108
Short name T9
Test name
Test status
Simulation time 11039743 ps
CPU time 0.38 seconds
Started Jun 11 03:43:22 PM PDT 24
Finished Jun 11 03:43:25 PM PDT 24
Peak memory 145824 kb
Host smart-cccd334a-b655-4d10-b1c4-93af36c535da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961691108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3961691108
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3874686492
Short name T18
Test name
Test status
Simulation time 11896222 ps
CPU time 0.39 seconds
Started Jun 11 03:43:19 PM PDT 24
Finished Jun 11 03:43:22 PM PDT 24
Peak memory 145804 kb
Host smart-e62ed3a5-4739-4a97-985f-1036ef688f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874686492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3874686492
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.1776583082
Short name T50
Test name
Test status
Simulation time 11425186 ps
CPU time 0.39 seconds
Started Jun 11 03:43:16 PM PDT 24
Finished Jun 11 03:43:20 PM PDT 24
Peak memory 145796 kb
Host smart-482b7cff-12bd-4360-9fdc-6f85a8e5d345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776583082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1776583082
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.90468340
Short name T23
Test name
Test status
Simulation time 10938890 ps
CPU time 0.38 seconds
Started Jun 11 03:43:15 PM PDT 24
Finished Jun 11 03:43:17 PM PDT 24
Peak memory 145788 kb
Host smart-1a35c1a1-444d-47dd-805b-ddec598f161d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90468340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.90468340
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1341448521
Short name T21
Test name
Test status
Simulation time 11046399 ps
CPU time 0.39 seconds
Started Jun 11 03:43:18 PM PDT 24
Finished Jun 11 03:43:21 PM PDT 24
Peak memory 145812 kb
Host smart-d3c63bce-46ff-4454-bdec-a26920a8023c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341448521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1341448521
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3563742696
Short name T48
Test name
Test status
Simulation time 10095421 ps
CPU time 0.4 seconds
Started Jun 11 03:43:15 PM PDT 24
Finished Jun 11 03:43:19 PM PDT 24
Peak memory 145796 kb
Host smart-d0b81e9f-c62f-4edd-a203-b71279a836f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563742696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3563742696
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3279371527
Short name T19
Test name
Test status
Simulation time 11460205 ps
CPU time 0.4 seconds
Started Jun 11 03:43:15 PM PDT 24
Finished Jun 11 03:43:17 PM PDT 24
Peak memory 145708 kb
Host smart-1e0c40af-c351-4d1e-8096-69926f5dc926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279371527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3279371527
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1892616364
Short name T17
Test name
Test status
Simulation time 11556418 ps
CPU time 0.42 seconds
Started Jun 11 03:43:20 PM PDT 24
Finished Jun 11 03:43:23 PM PDT 24
Peak memory 145872 kb
Host smart-a1b91100-2861-4139-88ff-0a19aecbcb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892616364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1892616364
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3640448474
Short name T20
Test name
Test status
Simulation time 10546579 ps
CPU time 0.39 seconds
Started Jun 11 03:43:23 PM PDT 24
Finished Jun 11 03:43:25 PM PDT 24
Peak memory 145832 kb
Host smart-800023b1-6911-411a-b4ef-7e709dcc12b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640448474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3640448474
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.739133887
Short name T39
Test name
Test status
Simulation time 29592628 ps
CPU time 0.39 seconds
Started Jun 11 01:08:28 PM PDT 24
Finished Jun 11 01:08:30 PM PDT 24
Peak memory 145324 kb
Host smart-aca23490-58f0-4bc9-b5a5-569d4104d6f3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=739133887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.739133887
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1091108217
Short name T52
Test name
Test status
Simulation time 30229123 ps
CPU time 0.4 seconds
Started Jun 11 01:08:41 PM PDT 24
Finished Jun 11 01:08:42 PM PDT 24
Peak memory 145328 kb
Host smart-914a8e66-8156-46b0-9ad2-f4d295d75ce9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1091108217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1091108217
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3097682126
Short name T43
Test name
Test status
Simulation time 29952736 ps
CPU time 0.43 seconds
Started Jun 11 01:08:40 PM PDT 24
Finished Jun 11 01:08:42 PM PDT 24
Peak memory 145284 kb
Host smart-1d2d579c-14e0-4293-be3b-6b1ae575c25e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3097682126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3097682126
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1654881871
Short name T54
Test name
Test status
Simulation time 31965441 ps
CPU time 0.41 seconds
Started Jun 11 01:08:38 PM PDT 24
Finished Jun 11 01:08:39 PM PDT 24
Peak memory 145240 kb
Host smart-49c2c6d8-482c-4edc-bf35-e70556466f62
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1654881871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1654881871
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.854347567
Short name T44
Test name
Test status
Simulation time 30881307 ps
CPU time 0.4 seconds
Started Jun 11 01:08:39 PM PDT 24
Finished Jun 11 01:08:41 PM PDT 24
Peak memory 145316 kb
Host smart-f447eaf0-2092-46b9-b37a-b983d3072a45
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=854347567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.854347567
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3594328997
Short name T13
Test name
Test status
Simulation time 30763877 ps
CPU time 0.4 seconds
Started Jun 11 01:08:39 PM PDT 24
Finished Jun 11 01:08:41 PM PDT 24
Peak memory 145272 kb
Host smart-1170348e-d51e-4c8d-b8c0-ef88fc8ce48c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3594328997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3594328997
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3351952756
Short name T41
Test name
Test status
Simulation time 31278564 ps
CPU time 0.41 seconds
Started Jun 11 01:08:38 PM PDT 24
Finished Jun 11 01:08:40 PM PDT 24
Peak memory 145240 kb
Host smart-26befe68-cd16-4fa5-9df2-6580ec32b965
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3351952756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3351952756
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1999886157
Short name T38
Test name
Test status
Simulation time 30679665 ps
CPU time 0.4 seconds
Started Jun 11 01:08:40 PM PDT 24
Finished Jun 11 01:08:41 PM PDT 24
Peak memory 145320 kb
Host smart-99c88157-0c63-4d8a-be77-2b1e7e7a0291
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1999886157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1999886157
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3164018100
Short name T14
Test name
Test status
Simulation time 31087871 ps
CPU time 0.4 seconds
Started Jun 11 01:08:38 PM PDT 24
Finished Jun 11 01:08:40 PM PDT 24
Peak memory 145220 kb
Host smart-c10b1713-fc66-4659-98b4-887a58e567d8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3164018100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3164018100
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2677714508
Short name T56
Test name
Test status
Simulation time 29883622 ps
CPU time 0.41 seconds
Started Jun 11 01:08:28 PM PDT 24
Finished Jun 11 01:08:29 PM PDT 24
Peak memory 145224 kb
Host smart-dfd7609a-348f-4413-bf7a-0eb54207be0b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2677714508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2677714508
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3444561113
Short name T40
Test name
Test status
Simulation time 29805307 ps
CPU time 0.39 seconds
Started Jun 11 01:08:28 PM PDT 24
Finished Jun 11 01:08:29 PM PDT 24
Peak memory 145312 kb
Host smart-3fed5c45-ff5f-4151-a211-03fa0c79b3ec
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3444561113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3444561113
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.103322817
Short name T46
Test name
Test status
Simulation time 29650691 ps
CPU time 0.39 seconds
Started Jun 11 01:08:31 PM PDT 24
Finished Jun 11 01:08:32 PM PDT 24
Peak memory 145308 kb
Host smart-c6f33f93-ec87-4730-8422-bd1734555152
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=103322817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.103322817
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.7556533
Short name T55
Test name
Test status
Simulation time 31006882 ps
CPU time 0.39 seconds
Started Jun 11 01:08:27 PM PDT 24
Finished Jun 11 01:08:28 PM PDT 24
Peak memory 145268 kb
Host smart-a51c8af8-eff7-4e9f-b2fe-3a3ee2291b93
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=7556533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.7556533
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2503441257
Short name T53
Test name
Test status
Simulation time 28970474 ps
CPU time 0.39 seconds
Started Jun 11 01:08:28 PM PDT 24
Finished Jun 11 01:08:29 PM PDT 24
Peak memory 145324 kb
Host smart-7b24a13b-e230-4ab7-b48c-9abfb4eb7ae6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2503441257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2503441257
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.353501243
Short name T15
Test name
Test status
Simulation time 29669596 ps
CPU time 0.4 seconds
Started Jun 11 01:08:29 PM PDT 24
Finished Jun 11 01:08:30 PM PDT 24
Peak memory 145296 kb
Host smart-8fa3087a-48f3-4a43-8d79-217e9c3b8b15
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=353501243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.353501243
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1572568401
Short name T45
Test name
Test status
Simulation time 29890343 ps
CPU time 0.39 seconds
Started Jun 11 01:08:31 PM PDT 24
Finished Jun 11 01:08:32 PM PDT 24
Peak memory 145304 kb
Host smart-259fa4ec-71ec-47f3-bd52-ed9f426893d7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1572568401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1572568401
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1237369474
Short name T47
Test name
Test status
Simulation time 30747527 ps
CPU time 0.4 seconds
Started Jun 11 01:08:39 PM PDT 24
Finished Jun 11 01:08:41 PM PDT 24
Peak memory 145276 kb
Host smart-6a7bb2d7-86ef-4166-94bf-ff27b6438a87
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1237369474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1237369474
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.777692766
Short name T24
Test name
Test status
Simulation time 8962663 ps
CPU time 0.37 seconds
Started Jun 11 02:46:04 PM PDT 24
Finished Jun 11 02:46:06 PM PDT 24
Peak memory 145620 kb
Host smart-b2e67df6-a7d2-4500-9db3-8ad4eba69ff8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=777692766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.777692766
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1913199177
Short name T58
Test name
Test status
Simulation time 8252214 ps
CPU time 0.39 seconds
Started Jun 11 02:46:04 PM PDT 24
Finished Jun 11 02:46:06 PM PDT 24
Peak memory 145592 kb
Host smart-2dbcc432-2a7a-435f-81be-e6ba3d10fae6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1913199177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1913199177
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.628902589
Short name T61
Test name
Test status
Simulation time 8702025 ps
CPU time 0.38 seconds
Started Jun 11 02:46:12 PM PDT 24
Finished Jun 11 02:46:13 PM PDT 24
Peak memory 145572 kb
Host smart-1e0840c7-91fb-4e25-a959-b844db427300
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=628902589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.628902589
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.1503830232
Short name T59
Test name
Test status
Simulation time 9843542 ps
CPU time 0.39 seconds
Started Jun 11 02:46:13 PM PDT 24
Finished Jun 11 02:46:15 PM PDT 24
Peak memory 145572 kb
Host smart-bb722d2b-9262-4075-ad4a-18bb3724059e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1503830232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1503830232
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3655956311
Short name T30
Test name
Test status
Simulation time 9514252 ps
CPU time 0.39 seconds
Started Jun 11 02:46:16 PM PDT 24
Finished Jun 11 02:46:18 PM PDT 24
Peak memory 145592 kb
Host smart-75e320ba-a85b-4c1e-be84-b020293b5eae
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3655956311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3655956311
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.1285673402
Short name T60
Test name
Test status
Simulation time 9917630 ps
CPU time 0.38 seconds
Started Jun 11 02:46:15 PM PDT 24
Finished Jun 11 02:46:18 PM PDT 24
Peak memory 145532 kb
Host smart-777aa996-0176-45c2-8310-3a7101481d34
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1285673402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1285673402
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3445578685
Short name T25
Test name
Test status
Simulation time 9892468 ps
CPU time 0.39 seconds
Started Jun 11 02:46:13 PM PDT 24
Finished Jun 11 02:46:14 PM PDT 24
Peak memory 145460 kb
Host smart-ce89f8da-50b4-4961-b808-3ad6519542ed
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3445578685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3445578685
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2762833722
Short name T33
Test name
Test status
Simulation time 10250265 ps
CPU time 0.4 seconds
Started Jun 11 02:46:16 PM PDT 24
Finished Jun 11 02:46:19 PM PDT 24
Peak memory 145592 kb
Host smart-4ac00c9d-9cab-40cb-bb99-03ddfd653055
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2762833722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2762833722
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.681588884
Short name T26
Test name
Test status
Simulation time 9162310 ps
CPU time 0.39 seconds
Started Jun 11 02:46:22 PM PDT 24
Finished Jun 11 02:46:24 PM PDT 24
Peak memory 145596 kb
Host smart-6500e9e5-7637-4ef4-ab32-a59aa8809da8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=681588884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.681588884
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1579861536
Short name T32
Test name
Test status
Simulation time 9402718 ps
CPU time 0.41 seconds
Started Jun 11 02:46:21 PM PDT 24
Finished Jun 11 02:46:24 PM PDT 24
Peak memory 145564 kb
Host smart-4b514950-24a6-45b8-bf88-53bde4a5b466
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1579861536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1579861536
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3958900021
Short name T27
Test name
Test status
Simulation time 9199053 ps
CPU time 0.37 seconds
Started Jun 11 02:46:11 PM PDT 24
Finished Jun 11 02:46:13 PM PDT 24
Peak memory 145592 kb
Host smart-2ccb8d79-36dd-4c22-b122-beccb58c993c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3958900021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3958900021
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3649419729
Short name T31
Test name
Test status
Simulation time 9490890 ps
CPU time 0.37 seconds
Started Jun 11 02:46:00 PM PDT 24
Finished Jun 11 02:46:02 PM PDT 24
Peak memory 145580 kb
Host smart-a2494d1e-7a4f-4e63-8ad0-99ad386b56ae
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3649419729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3649419729
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1713375867
Short name T57
Test name
Test status
Simulation time 9577488 ps
CPU time 0.41 seconds
Started Jun 11 02:46:05 PM PDT 24
Finished Jun 11 02:46:07 PM PDT 24
Peak memory 145592 kb
Host smart-5f4068f0-b5b5-49a6-aae5-4db2de353421
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1713375867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1713375867
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1934626846
Short name T37
Test name
Test status
Simulation time 9063612 ps
CPU time 0.38 seconds
Started Jun 11 02:46:05 PM PDT 24
Finished Jun 11 02:46:07 PM PDT 24
Peak memory 145560 kb
Host smart-e5ea2f3a-ad52-4ee4-8a26-353544dd5249
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1934626846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1934626846
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2025155599
Short name T28
Test name
Test status
Simulation time 10464262 ps
CPU time 0.38 seconds
Started Jun 11 02:46:03 PM PDT 24
Finished Jun 11 02:46:04 PM PDT 24
Peak memory 145560 kb
Host smart-fde79b93-97f6-418c-afc0-289ad02a89c0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2025155599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2025155599
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1245745243
Short name T35
Test name
Test status
Simulation time 8761158 ps
CPU time 0.42 seconds
Started Jun 11 02:46:05 PM PDT 24
Finished Jun 11 02:46:07 PM PDT 24
Peak memory 145596 kb
Host smart-ebd7eb38-9fc6-40ed-84e2-0f4658d54dc7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1245745243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1245745243
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.4224574693
Short name T34
Test name
Test status
Simulation time 8939954 ps
CPU time 0.4 seconds
Started Jun 11 02:46:03 PM PDT 24
Finished Jun 11 02:46:05 PM PDT 24
Peak memory 145464 kb
Host smart-6b597f14-1622-4638-97b2-c46667fae5ac
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4224574693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.4224574693
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3174333181
Short name T29
Test name
Test status
Simulation time 8726259 ps
CPU time 0.4 seconds
Started Jun 11 02:46:03 PM PDT 24
Finished Jun 11 02:46:05 PM PDT 24
Peak memory 145608 kb
Host smart-9a9d500d-7918-4e60-a4a5-12f5e050dde2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3174333181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3174333181
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1986227519
Short name T72
Test name
Test status
Simulation time 26046232 ps
CPU time 0.39 seconds
Started Jun 11 03:24:46 PM PDT 24
Finished Jun 11 03:24:48 PM PDT 24
Peak memory 145616 kb
Host smart-1379ded9-37ac-4355-b3c9-6a156c4beda5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1986227519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1986227519
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.15925475
Short name T71
Test name
Test status
Simulation time 27252205 ps
CPU time 0.41 seconds
Started Jun 11 03:24:49 PM PDT 24
Finished Jun 11 03:24:51 PM PDT 24
Peak memory 145576 kb
Host smart-dbd51de7-7567-45c6-92fe-c07e79e393ba
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=15925475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.15925475
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.468090401
Short name T66
Test name
Test status
Simulation time 28142006 ps
CPU time 0.45 seconds
Started Jun 11 03:24:47 PM PDT 24
Finished Jun 11 03:24:49 PM PDT 24
Peak memory 145604 kb
Host smart-49b66571-ee79-4334-9fd5-81789795b334
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=468090401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.468090401
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.373756206
Short name T68
Test name
Test status
Simulation time 31164464 ps
CPU time 0.41 seconds
Started Jun 11 03:24:47 PM PDT 24
Finished Jun 11 03:24:50 PM PDT 24
Peak memory 145576 kb
Host smart-055e2b04-7ce8-4fa9-ad00-6e8273047bc8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=373756206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.373756206
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.570003075
Short name T79
Test name
Test status
Simulation time 27321986 ps
CPU time 0.41 seconds
Started Jun 11 03:24:48 PM PDT 24
Finished Jun 11 03:24:50 PM PDT 24
Peak memory 145588 kb
Host smart-31d86b5c-ea31-41d9-af1d-75d884444bd8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=570003075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.570003075
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3261344407
Short name T67
Test name
Test status
Simulation time 31694564 ps
CPU time 0.39 seconds
Started Jun 11 03:24:45 PM PDT 24
Finished Jun 11 03:24:46 PM PDT 24
Peak memory 145548 kb
Host smart-928fb873-1815-49c0-8b8a-6e32bdea906e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3261344407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3261344407
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3911177687
Short name T73
Test name
Test status
Simulation time 26661013 ps
CPU time 0.41 seconds
Started Jun 11 03:24:48 PM PDT 24
Finished Jun 11 03:24:50 PM PDT 24
Peak memory 145592 kb
Host smart-7f781706-e99c-4567-b02e-efcea8e7c644
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3911177687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3911177687
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3354528479
Short name T5
Test name
Test status
Simulation time 28830587 ps
CPU time 0.4 seconds
Started Jun 11 03:24:46 PM PDT 24
Finished Jun 11 03:24:48 PM PDT 24
Peak memory 145592 kb
Host smart-fe23a9ba-1f78-4a63-9de1-8c985abd34b3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3354528479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3354528479
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.207347741
Short name T69
Test name
Test status
Simulation time 28925390 ps
CPU time 0.4 seconds
Started Jun 11 03:24:47 PM PDT 24
Finished Jun 11 03:24:49 PM PDT 24
Peak memory 145680 kb
Host smart-3c8e92a6-411c-423d-a510-b1afb79c8695
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=207347741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.207347741
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.72563260
Short name T74
Test name
Test status
Simulation time 28002994 ps
CPU time 0.38 seconds
Started Jun 11 03:24:47 PM PDT 24
Finished Jun 11 03:24:49 PM PDT 24
Peak memory 145608 kb
Host smart-a991d706-8034-4c2a-9f88-7d0ca1764ea3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=72563260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.72563260
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1943409054
Short name T64
Test name
Test status
Simulation time 27611954 ps
CPU time 0.39 seconds
Started Jun 11 03:24:45 PM PDT 24
Finished Jun 11 03:24:47 PM PDT 24
Peak memory 145612 kb
Host smart-c9daf8ab-90d3-4841-917c-d09438a6138d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1943409054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1943409054
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1362956044
Short name T75
Test name
Test status
Simulation time 27757788 ps
CPU time 0.39 seconds
Started Jun 11 03:24:49 PM PDT 24
Finished Jun 11 03:24:51 PM PDT 24
Peak memory 145592 kb
Host smart-5ad4c766-2ba4-448e-b5e7-690888b19363
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1362956044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1362956044
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2266741412
Short name T63
Test name
Test status
Simulation time 29705400 ps
CPU time 0.39 seconds
Started Jun 11 03:24:48 PM PDT 24
Finished Jun 11 03:24:50 PM PDT 24
Peak memory 145588 kb
Host smart-3f477239-9804-422a-9f5f-8914fe945671
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2266741412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2266741412
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3526057648
Short name T76
Test name
Test status
Simulation time 27260324 ps
CPU time 0.39 seconds
Started Jun 11 03:24:48 PM PDT 24
Finished Jun 11 03:24:50 PM PDT 24
Peak memory 145588 kb
Host smart-a91f981c-41f6-431d-a29d-a500947eae66
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3526057648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3526057648
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1995179467
Short name T6
Test name
Test status
Simulation time 26604954 ps
CPU time 0.39 seconds
Started Jun 11 03:24:46 PM PDT 24
Finished Jun 11 03:24:48 PM PDT 24
Peak memory 145604 kb
Host smart-56f0b0a6-2fd1-4558-802f-8ad1cf359601
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1995179467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1995179467
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.16566541
Short name T62
Test name
Test status
Simulation time 26011904 ps
CPU time 0.4 seconds
Started Jun 11 03:24:45 PM PDT 24
Finished Jun 11 03:24:47 PM PDT 24
Peak memory 145604 kb
Host smart-b10ab7a7-f384-49c3-93c1-3e4177b776ca
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=16566541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.16566541
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3451106108
Short name T65
Test name
Test status
Simulation time 29928983 ps
CPU time 0.4 seconds
Started Jun 11 03:24:46 PM PDT 24
Finished Jun 11 03:24:48 PM PDT 24
Peak memory 145600 kb
Host smart-9616f7ba-2f2a-4f85-9858-eef5fc4c7f13
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3451106108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3451106108
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1879621287
Short name T78
Test name
Test status
Simulation time 26603649 ps
CPU time 0.4 seconds
Started Jun 11 03:24:49 PM PDT 24
Finished Jun 11 03:24:52 PM PDT 24
Peak memory 145588 kb
Host smart-eea5ee3a-78ed-4108-87db-922bcf8fa79e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1879621287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1879621287
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1895541208
Short name T70
Test name
Test status
Simulation time 29593729 ps
CPU time 0.39 seconds
Started Jun 11 03:24:45 PM PDT 24
Finished Jun 11 03:24:47 PM PDT 24
Peak memory 145596 kb
Host smart-ab9ef3aa-6347-4eb5-aa9b-6fde946f5e92
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1895541208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1895541208
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3219770667
Short name T77
Test name
Test status
Simulation time 30190156 ps
CPU time 0.39 seconds
Started Jun 11 03:24:45 PM PDT 24
Finished Jun 11 03:24:47 PM PDT 24
Peak memory 145576 kb
Host smart-119e70b7-31a3-46e1-923a-615b5a6a79b5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3219770667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3219770667
Directory /workspace/9.prim_sync_fatal_alert/latest
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