Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.32 88.32 100.00 100.00 91.67 91.67 96.43 96.43 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/5.prim_async_alert.534211393
91.45 3.13 100.00 0.00 91.67 0.00 96.43 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/16.prim_sync_alert.1436378805
94.15 2.70 100.00 0.00 93.75 2.08 100.00 3.57 89.29 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.357089797
94.85 0.69 100.00 0.00 97.92 4.17 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/1.prim_async_alert.3347467055

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2008911718
/workspace/coverage/default/10.prim_async_alert.2837885198
/workspace/coverage/default/11.prim_async_alert.1934703783
/workspace/coverage/default/12.prim_async_alert.4272099811
/workspace/coverage/default/13.prim_async_alert.2130909262
/workspace/coverage/default/14.prim_async_alert.4037305952
/workspace/coverage/default/15.prim_async_alert.1525182488
/workspace/coverage/default/16.prim_async_alert.1530544445
/workspace/coverage/default/17.prim_async_alert.3799257077
/workspace/coverage/default/18.prim_async_alert.2588809272
/workspace/coverage/default/19.prim_async_alert.374022925
/workspace/coverage/default/2.prim_async_alert.4043748290
/workspace/coverage/default/3.prim_async_alert.1203355161
/workspace/coverage/default/4.prim_async_alert.4123254256
/workspace/coverage/default/6.prim_async_alert.3821051208
/workspace/coverage/default/7.prim_async_alert.1973002115
/workspace/coverage/default/8.prim_async_alert.16981153
/workspace/coverage/default/9.prim_async_alert.4095913218
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.333831047
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1136716086
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1722528800
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1909659340
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.359696818
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.969953102
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.832962788
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4278077594
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1998962923
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2471196588
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2233729175
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.888685617
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.503455444
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3408557853
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.224068474
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3430889910
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2512548490
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3828967695
/workspace/coverage/sync_alert/0.prim_sync_alert.3374579296
/workspace/coverage/sync_alert/1.prim_sync_alert.1970427145
/workspace/coverage/sync_alert/10.prim_sync_alert.1162206747
/workspace/coverage/sync_alert/11.prim_sync_alert.67507021
/workspace/coverage/sync_alert/12.prim_sync_alert.3656128621
/workspace/coverage/sync_alert/13.prim_sync_alert.1878261854
/workspace/coverage/sync_alert/14.prim_sync_alert.3281088116
/workspace/coverage/sync_alert/15.prim_sync_alert.3445749866
/workspace/coverage/sync_alert/17.prim_sync_alert.3649985333
/workspace/coverage/sync_alert/18.prim_sync_alert.2357171941
/workspace/coverage/sync_alert/19.prim_sync_alert.420029425
/workspace/coverage/sync_alert/2.prim_sync_alert.3191571168
/workspace/coverage/sync_alert/3.prim_sync_alert.2399238000
/workspace/coverage/sync_alert/4.prim_sync_alert.3741609107
/workspace/coverage/sync_alert/5.prim_sync_alert.2371774827
/workspace/coverage/sync_alert/6.prim_sync_alert.4021013183
/workspace/coverage/sync_alert/7.prim_sync_alert.1657274459
/workspace/coverage/sync_alert/8.prim_sync_alert.4057568099
/workspace/coverage/sync_alert/9.prim_sync_alert.897011072
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.766395987
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3922455929
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3847838390
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2983476461
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3235324623
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2052963730
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.587803664
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4137582766
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1189940338
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1519071663
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.614403324
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.276262711
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1119723192
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2632138609
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1778089690
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3345807109
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.202581762
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3730659546
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3561107977
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3342164980



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/6.prim_async_alert.3821051208 Jun 13 12:16:43 PM PDT 24 Jun 13 12:16:44 PM PDT 24 10652715 ps
T2 /workspace/coverage/default/1.prim_async_alert.3347467055 Jun 13 12:16:47 PM PDT 24 Jun 13 12:16:48 PM PDT 24 10992944 ps
T3 /workspace/coverage/default/4.prim_async_alert.4123254256 Jun 13 12:16:44 PM PDT 24 Jun 13 12:16:45 PM PDT 24 10956230 ps
T8 /workspace/coverage/default/2.prim_async_alert.4043748290 Jun 13 12:16:46 PM PDT 24 Jun 13 12:16:48 PM PDT 24 11042395 ps
T7 /workspace/coverage/default/13.prim_async_alert.2130909262 Jun 13 12:16:47 PM PDT 24 Jun 13 12:16:49 PM PDT 24 11373451 ps
T17 /workspace/coverage/default/9.prim_async_alert.4095913218 Jun 13 12:16:44 PM PDT 24 Jun 13 12:16:45 PM PDT 24 10950202 ps
T9 /workspace/coverage/default/12.prim_async_alert.4272099811 Jun 13 12:16:51 PM PDT 24 Jun 13 12:16:52 PM PDT 24 10806082 ps
T14 /workspace/coverage/default/15.prim_async_alert.1525182488 Jun 13 12:16:47 PM PDT 24 Jun 13 12:16:49 PM PDT 24 10459391 ps
T10 /workspace/coverage/default/10.prim_async_alert.2837885198 Jun 13 12:16:47 PM PDT 24 Jun 13 12:16:48 PM PDT 24 11488322 ps
T15 /workspace/coverage/default/5.prim_async_alert.534211393 Jun 13 12:16:51 PM PDT 24 Jun 13 12:16:52 PM PDT 24 10854573 ps
T11 /workspace/coverage/default/16.prim_async_alert.1530544445 Jun 13 12:16:47 PM PDT 24 Jun 13 12:16:49 PM PDT 24 12217383 ps
T13 /workspace/coverage/default/14.prim_async_alert.4037305952 Jun 13 12:20:09 PM PDT 24 Jun 13 12:20:09 PM PDT 24 10772750 ps
T12 /workspace/coverage/default/8.prim_async_alert.16981153 Jun 13 12:16:46 PM PDT 24 Jun 13 12:16:48 PM PDT 24 11586333 ps
T18 /workspace/coverage/default/19.prim_async_alert.374022925 Jun 13 12:16:55 PM PDT 24 Jun 13 12:16:58 PM PDT 24 11517645 ps
T19 /workspace/coverage/default/18.prim_async_alert.2588809272 Jun 13 12:16:55 PM PDT 24 Jun 13 12:16:58 PM PDT 24 10835487 ps
T16 /workspace/coverage/default/17.prim_async_alert.3799257077 Jun 13 12:16:46 PM PDT 24 Jun 13 12:16:48 PM PDT 24 11656876 ps
T20 /workspace/coverage/default/11.prim_async_alert.1934703783 Jun 13 12:16:55 PM PDT 24 Jun 13 12:16:58 PM PDT 24 11824787 ps
T39 /workspace/coverage/default/3.prim_async_alert.1203355161 Jun 13 12:16:45 PM PDT 24 Jun 13 12:16:46 PM PDT 24 10575145 ps
T47 /workspace/coverage/default/7.prim_async_alert.1973002115 Jun 13 12:16:44 PM PDT 24 Jun 13 12:16:45 PM PDT 24 11569229 ps
T37 /workspace/coverage/default/0.prim_async_alert.2008911718 Jun 13 12:16:46 PM PDT 24 Jun 13 12:16:48 PM PDT 24 11070182 ps
T40 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1136716086 Jun 13 12:18:19 PM PDT 24 Jun 13 12:18:20 PM PDT 24 30492484 ps
T41 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.969953102 Jun 13 12:16:55 PM PDT 24 Jun 13 12:16:58 PM PDT 24 29834550 ps
T4 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.357089797 Jun 13 12:16:55 PM PDT 24 Jun 13 12:16:58 PM PDT 24 32771505 ps
T42 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1722528800 Jun 13 12:16:55 PM PDT 24 Jun 13 12:16:59 PM PDT 24 29717746 ps
T43 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.832962788 Jun 13 12:16:54 PM PDT 24 Jun 13 12:16:57 PM PDT 24 29210415 ps
T44 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.503455444 Jun 13 12:16:55 PM PDT 24 Jun 13 12:16:58 PM PDT 24 28927262 ps
T5 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4278077594 Jun 13 12:16:53 PM PDT 24 Jun 13 12:16:54 PM PDT 24 30116115 ps
T45 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3430889910 Jun 13 12:16:51 PM PDT 24 Jun 13 12:16:52 PM PDT 24 30248943 ps
T38 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.888685617 Jun 13 12:21:40 PM PDT 24 Jun 13 12:21:41 PM PDT 24 30957267 ps
T46 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.359696818 Jun 13 12:21:41 PM PDT 24 Jun 13 12:21:42 PM PDT 24 29108715 ps
T6 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.224068474 Jun 13 12:18:19 PM PDT 24 Jun 13 12:18:20 PM PDT 24 29596753 ps
T48 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2471196588 Jun 13 12:16:56 PM PDT 24 Jun 13 12:16:59 PM PDT 24 31267656 ps
T49 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2233729175 Jun 13 12:16:46 PM PDT 24 Jun 13 12:16:48 PM PDT 24 30759719 ps
T50 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.333831047 Jun 13 12:16:47 PM PDT 24 Jun 13 12:16:49 PM PDT 24 30652529 ps
T51 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3408557853 Jun 13 12:16:54 PM PDT 24 Jun 13 12:16:57 PM PDT 24 30033209 ps
T52 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1998962923 Jun 13 12:16:55 PM PDT 24 Jun 13 12:16:58 PM PDT 24 30490981 ps
T53 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3828967695 Jun 13 12:16:54 PM PDT 24 Jun 13 12:16:57 PM PDT 24 28902768 ps
T54 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2512548490 Jun 13 12:18:23 PM PDT 24 Jun 13 12:18:24 PM PDT 24 29193686 ps
T55 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1909659340 Jun 13 12:16:54 PM PDT 24 Jun 13 12:16:57 PM PDT 24 29951032 ps
T30 /workspace/coverage/sync_alert/12.prim_sync_alert.3656128621 Jun 13 12:16:54 PM PDT 24 Jun 13 12:16:56 PM PDT 24 8142848 ps
T31 /workspace/coverage/sync_alert/15.prim_sync_alert.3445749866 Jun 13 12:16:54 PM PDT 24 Jun 13 12:16:55 PM PDT 24 8956373 ps
T21 /workspace/coverage/sync_alert/14.prim_sync_alert.3281088116 Jun 13 12:16:53 PM PDT 24 Jun 13 12:16:55 PM PDT 24 8991926 ps
T32 /workspace/coverage/sync_alert/0.prim_sync_alert.3374579296 Jun 13 12:20:21 PM PDT 24 Jun 13 12:20:22 PM PDT 24 9194414 ps
T33 /workspace/coverage/sync_alert/7.prim_sync_alert.1657274459 Jun 13 12:17:49 PM PDT 24 Jun 13 12:17:50 PM PDT 24 9097476 ps
T22 /workspace/coverage/sync_alert/16.prim_sync_alert.1436378805 Jun 13 12:16:55 PM PDT 24 Jun 13 12:16:59 PM PDT 24 8817135 ps
T34 /workspace/coverage/sync_alert/5.prim_sync_alert.2371774827 Jun 13 12:16:54 PM PDT 24 Jun 13 12:16:56 PM PDT 24 9270285 ps
T35 /workspace/coverage/sync_alert/3.prim_sync_alert.2399238000 Jun 13 12:21:54 PM PDT 24 Jun 13 12:21:55 PM PDT 24 9339259 ps
T23 /workspace/coverage/sync_alert/8.prim_sync_alert.4057568099 Jun 13 12:16:53 PM PDT 24 Jun 13 12:16:54 PM PDT 24 9806430 ps
T36 /workspace/coverage/sync_alert/19.prim_sync_alert.420029425 Jun 13 12:17:30 PM PDT 24 Jun 13 12:17:30 PM PDT 24 9584499 ps
T24 /workspace/coverage/sync_alert/18.prim_sync_alert.2357171941 Jun 13 12:17:51 PM PDT 24 Jun 13 12:17:52 PM PDT 24 10223572 ps
T25 /workspace/coverage/sync_alert/9.prim_sync_alert.897011072 Jun 13 12:16:54 PM PDT 24 Jun 13 12:16:55 PM PDT 24 9622165 ps
T56 /workspace/coverage/sync_alert/2.prim_sync_alert.3191571168 Jun 13 12:21:39 PM PDT 24 Jun 13 12:21:40 PM PDT 24 10104104 ps
T57 /workspace/coverage/sync_alert/13.prim_sync_alert.1878261854 Jun 13 12:16:55 PM PDT 24 Jun 13 12:16:57 PM PDT 24 9049610 ps
T58 /workspace/coverage/sync_alert/6.prim_sync_alert.4021013183 Jun 13 12:16:47 PM PDT 24 Jun 13 12:16:49 PM PDT 24 9400129 ps
T59 /workspace/coverage/sync_alert/11.prim_sync_alert.67507021 Jun 13 12:16:54 PM PDT 24 Jun 13 12:16:55 PM PDT 24 9692136 ps
T26 /workspace/coverage/sync_alert/1.prim_sync_alert.1970427145 Jun 13 12:16:55 PM PDT 24 Jun 13 12:16:58 PM PDT 24 10313126 ps
T60 /workspace/coverage/sync_alert/10.prim_sync_alert.1162206747 Jun 13 12:16:55 PM PDT 24 Jun 13 12:16:58 PM PDT 24 9675896 ps
T61 /workspace/coverage/sync_alert/17.prim_sync_alert.3649985333 Jun 13 12:21:55 PM PDT 24 Jun 13 12:21:55 PM PDT 24 10139412 ps
T62 /workspace/coverage/sync_alert/4.prim_sync_alert.3741609107 Jun 13 12:18:09 PM PDT 24 Jun 13 12:18:10 PM PDT 24 8287225 ps
T63 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1119723192 Jun 13 12:18:09 PM PDT 24 Jun 13 12:18:10 PM PDT 24 28186284 ps
T27 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1189940338 Jun 13 12:18:39 PM PDT 24 Jun 13 12:18:40 PM PDT 24 26537730 ps
T64 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1519071663 Jun 13 12:21:58 PM PDT 24 Jun 13 12:21:59 PM PDT 24 28677900 ps
T65 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3345807109 Jun 13 12:19:39 PM PDT 24 Jun 13 12:19:40 PM PDT 24 25384948 ps
T66 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.766395987 Jun 13 12:22:28 PM PDT 24 Jun 13 12:22:29 PM PDT 24 27678226 ps
T28 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.614403324 Jun 13 12:21:59 PM PDT 24 Jun 13 12:22:00 PM PDT 24 27591062 ps
T67 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.587803664 Jun 13 12:18:41 PM PDT 24 Jun 13 12:18:42 PM PDT 24 28179056 ps
T29 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3847838390 Jun 13 12:19:56 PM PDT 24 Jun 13 12:19:56 PM PDT 24 26855056 ps
T68 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.202581762 Jun 13 12:18:38 PM PDT 24 Jun 13 12:18:38 PM PDT 24 28349944 ps
T69 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2052963730 Jun 13 12:21:40 PM PDT 24 Jun 13 12:21:41 PM PDT 24 27055921 ps
T70 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3561107977 Jun 13 12:21:50 PM PDT 24 Jun 13 12:21:51 PM PDT 24 26227762 ps
T71 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3730659546 Jun 13 12:21:49 PM PDT 24 Jun 13 12:21:50 PM PDT 24 27751410 ps
T72 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3922455929 Jun 13 12:17:50 PM PDT 24 Jun 13 12:17:51 PM PDT 24 28642385 ps
T73 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3342164980 Jun 13 12:17:49 PM PDT 24 Jun 13 12:17:50 PM PDT 24 26179008 ps
T74 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2983476461 Jun 13 12:18:40 PM PDT 24 Jun 13 12:18:41 PM PDT 24 27916155 ps
T75 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2632138609 Jun 13 12:17:10 PM PDT 24 Jun 13 12:17:11 PM PDT 24 26708643 ps
T76 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1778089690 Jun 13 12:18:38 PM PDT 24 Jun 13 12:18:39 PM PDT 24 27129646 ps
T77 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3235324623 Jun 13 12:17:42 PM PDT 24 Jun 13 12:17:42 PM PDT 24 27025208 ps
T78 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.276262711 Jun 13 12:22:17 PM PDT 24 Jun 13 12:22:18 PM PDT 24 26652194 ps
T79 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4137582766 Jun 13 12:17:39 PM PDT 24 Jun 13 12:17:39 PM PDT 24 28312586 ps

Test location /workspace/coverage/default/5.prim_async_alert.534211393
Short name T15
Test name
Test status
Simulation time 10854573 ps
CPU time 0.39 seconds
Started Jun 13 12:16:51 PM PDT 24
Finished Jun 13 12:16:52 PM PDT 24
Peak memory 145656 kb
Host smart-78275abb-d1a8-4733-ab82-8aaec8a2c3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534211393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.534211393
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1436378805
Short name T22
Test name
Test status
Simulation time 8817135 ps
CPU time 0.37 seconds
Started Jun 13 12:16:55 PM PDT 24
Finished Jun 13 12:16:59 PM PDT 24
Peak memory 145236 kb
Host smart-c72b6479-3a85-47db-b204-4a7363884030
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1436378805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1436378805
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.357089797
Short name T4
Test name
Test status
Simulation time 32771505 ps
CPU time 0.52 seconds
Started Jun 13 12:16:55 PM PDT 24
Finished Jun 13 12:16:58 PM PDT 24
Peak memory 142828 kb
Host smart-33102a09-8834-4391-9f66-670adf04b839
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=357089797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.357089797
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3347467055
Short name T2
Test name
Test status
Simulation time 10992944 ps
CPU time 0.37 seconds
Started Jun 13 12:16:47 PM PDT 24
Finished Jun 13 12:16:48 PM PDT 24
Peak memory 145184 kb
Host smart-25860529-26f8-4113-a444-ae0315a45a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347467055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3347467055
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2008911718
Short name T37
Test name
Test status
Simulation time 11070182 ps
CPU time 0.41 seconds
Started Jun 13 12:16:46 PM PDT 24
Finished Jun 13 12:16:48 PM PDT 24
Peak memory 142156 kb
Host smart-a4c466e2-32a6-4c2a-95aa-43b64dd1e5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008911718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2008911718
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2837885198
Short name T10
Test name
Test status
Simulation time 11488322 ps
CPU time 0.39 seconds
Started Jun 13 12:16:47 PM PDT 24
Finished Jun 13 12:16:48 PM PDT 24
Peak memory 145660 kb
Host smart-6431a750-d6a0-45a3-acc6-278758fb4a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837885198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2837885198
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1934703783
Short name T20
Test name
Test status
Simulation time 11824787 ps
CPU time 0.5 seconds
Started Jun 13 12:16:55 PM PDT 24
Finished Jun 13 12:16:58 PM PDT 24
Peak memory 143640 kb
Host smart-bb284311-023c-4034-be32-cab661928a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934703783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1934703783
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.4272099811
Short name T9
Test name
Test status
Simulation time 10806082 ps
CPU time 0.39 seconds
Started Jun 13 12:16:51 PM PDT 24
Finished Jun 13 12:16:52 PM PDT 24
Peak memory 145656 kb
Host smart-9bdedd19-ac54-47d4-8d11-b3bb8aac421d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272099811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.4272099811
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2130909262
Short name T7
Test name
Test status
Simulation time 11373451 ps
CPU time 0.37 seconds
Started Jun 13 12:16:47 PM PDT 24
Finished Jun 13 12:16:49 PM PDT 24
Peak memory 145152 kb
Host smart-175ee21b-d121-42aa-8593-c88a76c162a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130909262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2130909262
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.4037305952
Short name T13
Test name
Test status
Simulation time 10772750 ps
CPU time 0.39 seconds
Started Jun 13 12:20:09 PM PDT 24
Finished Jun 13 12:20:09 PM PDT 24
Peak memory 145552 kb
Host smart-a75ce0e2-9241-4106-9a68-dc28cd2763c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037305952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.4037305952
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1525182488
Short name T14
Test name
Test status
Simulation time 10459391 ps
CPU time 0.39 seconds
Started Jun 13 12:16:47 PM PDT 24
Finished Jun 13 12:16:49 PM PDT 24
Peak memory 145660 kb
Host smart-02c5b188-b6e3-41ef-8826-074e1e46a3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525182488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1525182488
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1530544445
Short name T11
Test name
Test status
Simulation time 12217383 ps
CPU time 0.39 seconds
Started Jun 13 12:16:47 PM PDT 24
Finished Jun 13 12:16:49 PM PDT 24
Peak memory 145152 kb
Host smart-9088ccaf-35c5-4cbf-b54e-17310cfa1a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530544445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1530544445
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3799257077
Short name T16
Test name
Test status
Simulation time 11656876 ps
CPU time 0.43 seconds
Started Jun 13 12:16:46 PM PDT 24
Finished Jun 13 12:16:48 PM PDT 24
Peak memory 142996 kb
Host smart-1cae2b49-9e78-410b-a58d-7720c79198ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799257077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3799257077
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2588809272
Short name T19
Test name
Test status
Simulation time 10835487 ps
CPU time 0.38 seconds
Started Jun 13 12:16:55 PM PDT 24
Finished Jun 13 12:16:58 PM PDT 24
Peak memory 145352 kb
Host smart-4fc6f6ff-4426-4edb-833b-9854f7e5c39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588809272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2588809272
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.374022925
Short name T18
Test name
Test status
Simulation time 11517645 ps
CPU time 0.49 seconds
Started Jun 13 12:16:55 PM PDT 24
Finished Jun 13 12:16:58 PM PDT 24
Peak memory 143948 kb
Host smart-ffb58fa3-ca1f-4256-8610-1837a9f73327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374022925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.374022925
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.4043748290
Short name T8
Test name
Test status
Simulation time 11042395 ps
CPU time 0.42 seconds
Started Jun 13 12:16:46 PM PDT 24
Finished Jun 13 12:16:48 PM PDT 24
Peak memory 143908 kb
Host smart-ecc847ae-f5ff-4116-a19b-402e4a307edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043748290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.4043748290
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1203355161
Short name T39
Test name
Test status
Simulation time 10575145 ps
CPU time 0.4 seconds
Started Jun 13 12:16:45 PM PDT 24
Finished Jun 13 12:16:46 PM PDT 24
Peak memory 145656 kb
Host smart-389079a4-abbc-4a7f-a7a2-b269d8618d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203355161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1203355161
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.4123254256
Short name T3
Test name
Test status
Simulation time 10956230 ps
CPU time 0.42 seconds
Started Jun 13 12:16:44 PM PDT 24
Finished Jun 13 12:16:45 PM PDT 24
Peak memory 145656 kb
Host smart-91f33e66-b23e-49c9-8f7a-62a992ead648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123254256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.4123254256
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3821051208
Short name T1
Test name
Test status
Simulation time 10652715 ps
CPU time 0.39 seconds
Started Jun 13 12:16:43 PM PDT 24
Finished Jun 13 12:16:44 PM PDT 24
Peak memory 145524 kb
Host smart-a6efd43b-39d6-4ccd-bdcf-45f091dadea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821051208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3821051208
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1973002115
Short name T47
Test name
Test status
Simulation time 11569229 ps
CPU time 0.39 seconds
Started Jun 13 12:16:44 PM PDT 24
Finished Jun 13 12:16:45 PM PDT 24
Peak memory 145656 kb
Host smart-7235d4aa-afdb-4d8a-9a65-92a8d3f6de74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973002115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1973002115
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.16981153
Short name T12
Test name
Test status
Simulation time 11586333 ps
CPU time 0.38 seconds
Started Jun 13 12:16:46 PM PDT 24
Finished Jun 13 12:16:48 PM PDT 24
Peak memory 144220 kb
Host smart-acc125a6-300f-4446-bc38-74b20c702c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16981153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.16981153
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.4095913218
Short name T17
Test name
Test status
Simulation time 10950202 ps
CPU time 0.38 seconds
Started Jun 13 12:16:44 PM PDT 24
Finished Jun 13 12:16:45 PM PDT 24
Peak memory 145656 kb
Host smart-090c80d1-9563-4a18-aae4-f9c88a00e1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095913218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.4095913218
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.333831047
Short name T50
Test name
Test status
Simulation time 30652529 ps
CPU time 0.39 seconds
Started Jun 13 12:16:47 PM PDT 24
Finished Jun 13 12:16:49 PM PDT 24
Peak memory 144736 kb
Host smart-eeb197a8-20dc-432e-b64c-82e1f6712b81
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=333831047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.333831047
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1136716086
Short name T40
Test name
Test status
Simulation time 30492484 ps
CPU time 0.46 seconds
Started Jun 13 12:18:19 PM PDT 24
Finished Jun 13 12:18:20 PM PDT 24
Peak memory 145024 kb
Host smart-e42f6038-d915-48ca-8bbb-31b334c22c6c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1136716086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1136716086
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1722528800
Short name T42
Test name
Test status
Simulation time 29717746 ps
CPU time 0.41 seconds
Started Jun 13 12:16:55 PM PDT 24
Finished Jun 13 12:16:59 PM PDT 24
Peak memory 145136 kb
Host smart-311d18de-26de-4e5d-8bcf-6e8edd53c0b9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1722528800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1722528800
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1909659340
Short name T55
Test name
Test status
Simulation time 29951032 ps
CPU time 0.4 seconds
Started Jun 13 12:16:54 PM PDT 24
Finished Jun 13 12:16:57 PM PDT 24
Peak memory 144900 kb
Host smart-0df06994-2c75-416f-8e54-265c193eda7b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1909659340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1909659340
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.359696818
Short name T46
Test name
Test status
Simulation time 29108715 ps
CPU time 0.39 seconds
Started Jun 13 12:21:41 PM PDT 24
Finished Jun 13 12:21:42 PM PDT 24
Peak memory 144856 kb
Host smart-b301f928-4351-47fd-9aaa-f3dfbebb10e5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=359696818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.359696818
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.969953102
Short name T41
Test name
Test status
Simulation time 29834550 ps
CPU time 0.5 seconds
Started Jun 13 12:16:55 PM PDT 24
Finished Jun 13 12:16:58 PM PDT 24
Peak memory 143824 kb
Host smart-4f903aae-240f-48fe-870b-37363d0094fb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=969953102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.969953102
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.832962788
Short name T43
Test name
Test status
Simulation time 29210415 ps
CPU time 0.39 seconds
Started Jun 13 12:16:54 PM PDT 24
Finished Jun 13 12:16:57 PM PDT 24
Peak memory 144900 kb
Host smart-b5fe4121-fa13-4192-9b47-de5c5672e552
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=832962788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.832962788
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4278077594
Short name T5
Test name
Test status
Simulation time 30116115 ps
CPU time 0.43 seconds
Started Jun 13 12:16:53 PM PDT 24
Finished Jun 13 12:16:54 PM PDT 24
Peak memory 145288 kb
Host smart-d9152255-72e9-494a-ae6d-f661b44279bc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4278077594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.4278077594
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1998962923
Short name T52
Test name
Test status
Simulation time 30490981 ps
CPU time 0.53 seconds
Started Jun 13 12:16:55 PM PDT 24
Finished Jun 13 12:16:58 PM PDT 24
Peak memory 142600 kb
Host smart-65135e4e-e91d-4ee9-8541-d83cf129c9a3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1998962923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1998962923
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2471196588
Short name T48
Test name
Test status
Simulation time 31267656 ps
CPU time 0.43 seconds
Started Jun 13 12:16:56 PM PDT 24
Finished Jun 13 12:16:59 PM PDT 24
Peak memory 145432 kb
Host smart-106567fb-c304-465e-85d2-8ccb902f1b6f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2471196588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2471196588
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2233729175
Short name T49
Test name
Test status
Simulation time 30759719 ps
CPU time 0.43 seconds
Started Jun 13 12:16:46 PM PDT 24
Finished Jun 13 12:16:48 PM PDT 24
Peak memory 143852 kb
Host smart-17dc8690-ec26-49d2-8f6f-0037fb8b5ba1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2233729175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2233729175
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.888685617
Short name T38
Test name
Test status
Simulation time 30957267 ps
CPU time 0.38 seconds
Started Jun 13 12:21:40 PM PDT 24
Finished Jun 13 12:21:41 PM PDT 24
Peak memory 145252 kb
Host smart-3242146d-6091-4dd5-acc5-2456ece5870f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=888685617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.888685617
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.503455444
Short name T44
Test name
Test status
Simulation time 28927262 ps
CPU time 0.53 seconds
Started Jun 13 12:16:55 PM PDT 24
Finished Jun 13 12:16:58 PM PDT 24
Peak memory 142652 kb
Host smart-617bd9fa-325b-4a46-a791-95fef377ef77
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=503455444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.503455444
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3408557853
Short name T51
Test name
Test status
Simulation time 30033209 ps
CPU time 0.4 seconds
Started Jun 13 12:16:54 PM PDT 24
Finished Jun 13 12:16:57 PM PDT 24
Peak memory 144916 kb
Host smart-863f864f-42cb-4ba6-b383-252dcf4c502d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3408557853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3408557853
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.224068474
Short name T6
Test name
Test status
Simulation time 29596753 ps
CPU time 0.42 seconds
Started Jun 13 12:18:19 PM PDT 24
Finished Jun 13 12:18:20 PM PDT 24
Peak memory 145044 kb
Host smart-06ac2e1a-e4a8-41d1-a978-986b6652d56c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=224068474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.224068474
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3430889910
Short name T45
Test name
Test status
Simulation time 30248943 ps
CPU time 0.4 seconds
Started Jun 13 12:16:51 PM PDT 24
Finished Jun 13 12:16:52 PM PDT 24
Peak memory 145280 kb
Host smart-72db54c1-d790-4fc3-ae5d-76e77ed01773
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3430889910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3430889910
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2512548490
Short name T54
Test name
Test status
Simulation time 29193686 ps
CPU time 0.44 seconds
Started Jun 13 12:18:23 PM PDT 24
Finished Jun 13 12:18:24 PM PDT 24
Peak memory 145064 kb
Host smart-620233c5-b576-4f8e-8c3f-3bf0b531bd5e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2512548490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2512548490
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3828967695
Short name T53
Test name
Test status
Simulation time 28902768 ps
CPU time 0.38 seconds
Started Jun 13 12:16:54 PM PDT 24
Finished Jun 13 12:16:57 PM PDT 24
Peak memory 144796 kb
Host smart-b3791f83-0807-45de-9506-4fe3a61ede7b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3828967695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3828967695
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3374579296
Short name T32
Test name
Test status
Simulation time 9194414 ps
CPU time 0.41 seconds
Started Jun 13 12:20:21 PM PDT 24
Finished Jun 13 12:20:22 PM PDT 24
Peak memory 145380 kb
Host smart-2fce9592-c8b4-4e8c-b0be-16b36d8812f1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3374579296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3374579296
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1970427145
Short name T26
Test name
Test status
Simulation time 10313126 ps
CPU time 0.38 seconds
Started Jun 13 12:16:55 PM PDT 24
Finished Jun 13 12:16:58 PM PDT 24
Peak memory 145720 kb
Host smart-cdc04c1f-2662-4fad-a4bd-eacea020e954
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1970427145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1970427145
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1162206747
Short name T60
Test name
Test status
Simulation time 9675896 ps
CPU time 0.5 seconds
Started Jun 13 12:16:55 PM PDT 24
Finished Jun 13 12:16:58 PM PDT 24
Peak memory 144180 kb
Host smart-b13069ec-a34e-4845-a5e3-f95891e39899
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1162206747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1162206747
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.67507021
Short name T59
Test name
Test status
Simulation time 9692136 ps
CPU time 0.37 seconds
Started Jun 13 12:16:54 PM PDT 24
Finished Jun 13 12:16:55 PM PDT 24
Peak memory 145040 kb
Host smart-56ebfc3f-d8de-4f2a-965d-282ab59689e5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=67507021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.67507021
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3656128621
Short name T30
Test name
Test status
Simulation time 8142848 ps
CPU time 0.37 seconds
Started Jun 13 12:16:54 PM PDT 24
Finished Jun 13 12:16:56 PM PDT 24
Peak memory 145044 kb
Host smart-0d99a5f4-38ca-4762-894e-7ef97dfdf890
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3656128621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3656128621
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1878261854
Short name T57
Test name
Test status
Simulation time 9049610 ps
CPU time 0.37 seconds
Started Jun 13 12:16:55 PM PDT 24
Finished Jun 13 12:16:57 PM PDT 24
Peak memory 145100 kb
Host smart-a9f32e88-b8e7-4e3e-8e22-2f4097d72416
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1878261854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1878261854
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3281088116
Short name T21
Test name
Test status
Simulation time 8991926 ps
CPU time 0.45 seconds
Started Jun 13 12:16:53 PM PDT 24
Finished Jun 13 12:16:55 PM PDT 24
Peak memory 144808 kb
Host smart-62d79216-bd36-4e2b-a0dd-5d6e55a4de84
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3281088116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3281088116
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3445749866
Short name T31
Test name
Test status
Simulation time 8956373 ps
CPU time 0.37 seconds
Started Jun 13 12:16:54 PM PDT 24
Finished Jun 13 12:16:55 PM PDT 24
Peak memory 145044 kb
Host smart-b8762d64-c9e8-47de-8961-88fa78486f04
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3445749866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3445749866
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3649985333
Short name T61
Test name
Test status
Simulation time 10139412 ps
CPU time 0.37 seconds
Started Jun 13 12:21:55 PM PDT 24
Finished Jun 13 12:21:55 PM PDT 24
Peak memory 145180 kb
Host smart-a1c4b2b8-74b4-4d40-92c3-0b6c97219244
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3649985333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3649985333
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2357171941
Short name T24
Test name
Test status
Simulation time 10223572 ps
CPU time 0.48 seconds
Started Jun 13 12:17:51 PM PDT 24
Finished Jun 13 12:17:52 PM PDT 24
Peak memory 145832 kb
Host smart-0acb0599-f8c5-4bf3-abda-28d0184d4f5c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2357171941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2357171941
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.420029425
Short name T36
Test name
Test status
Simulation time 9584499 ps
CPU time 0.38 seconds
Started Jun 13 12:17:30 PM PDT 24
Finished Jun 13 12:17:30 PM PDT 24
Peak memory 145256 kb
Host smart-77f164c9-b9bb-440b-ac52-8bc72f4e9e33
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=420029425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.420029425
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3191571168
Short name T56
Test name
Test status
Simulation time 10104104 ps
CPU time 0.42 seconds
Started Jun 13 12:21:39 PM PDT 24
Finished Jun 13 12:21:40 PM PDT 24
Peak memory 145840 kb
Host smart-9e5c0f6d-f872-4f19-bd26-6a1404f12a48
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3191571168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3191571168
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2399238000
Short name T35
Test name
Test status
Simulation time 9339259 ps
CPU time 0.38 seconds
Started Jun 13 12:21:54 PM PDT 24
Finished Jun 13 12:21:55 PM PDT 24
Peak memory 145184 kb
Host smart-807f4333-82ae-48b3-bcfd-eb832a748e70
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2399238000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2399238000
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3741609107
Short name T62
Test name
Test status
Simulation time 8287225 ps
CPU time 0.4 seconds
Started Jun 13 12:18:09 PM PDT 24
Finished Jun 13 12:18:10 PM PDT 24
Peak memory 145272 kb
Host smart-e58cc560-a069-41b6-bb69-6c207be5748b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3741609107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3741609107
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2371774827
Short name T34
Test name
Test status
Simulation time 9270285 ps
CPU time 0.38 seconds
Started Jun 13 12:16:54 PM PDT 24
Finished Jun 13 12:16:56 PM PDT 24
Peak memory 145044 kb
Host smart-9ca521ed-6845-4633-9e9c-ece35b262b4c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2371774827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2371774827
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.4021013183
Short name T58
Test name
Test status
Simulation time 9400129 ps
CPU time 0.37 seconds
Started Jun 13 12:16:47 PM PDT 24
Finished Jun 13 12:16:49 PM PDT 24
Peak memory 144976 kb
Host smart-e21a79eb-a7e4-4a6a-b5f2-689b8a28e165
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4021013183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.4021013183
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1657274459
Short name T33
Test name
Test status
Simulation time 9097476 ps
CPU time 0.38 seconds
Started Jun 13 12:17:49 PM PDT 24
Finished Jun 13 12:17:50 PM PDT 24
Peak memory 145316 kb
Host smart-e1fee4ff-3c97-4cb1-b49c-d83c9445e43d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1657274459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1657274459
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.4057568099
Short name T23
Test name
Test status
Simulation time 9806430 ps
CPU time 0.38 seconds
Started Jun 13 12:16:53 PM PDT 24
Finished Jun 13 12:16:54 PM PDT 24
Peak memory 145372 kb
Host smart-9d11cdab-07a2-49fc-ad2c-4c3aa50452e4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4057568099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.4057568099
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.897011072
Short name T25
Test name
Test status
Simulation time 9622165 ps
CPU time 0.39 seconds
Started Jun 13 12:16:54 PM PDT 24
Finished Jun 13 12:16:55 PM PDT 24
Peak memory 144988 kb
Host smart-ebafa4db-b496-464d-a15f-32d5ce1b8f11
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=897011072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.897011072
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.766395987
Short name T66
Test name
Test status
Simulation time 27678226 ps
CPU time 0.42 seconds
Started Jun 13 12:22:28 PM PDT 24
Finished Jun 13 12:22:29 PM PDT 24
Peak memory 145844 kb
Host smart-c6acef80-64b9-49ef-84ab-21f118f5a7ee
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=766395987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.766395987
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3922455929
Short name T72
Test name
Test status
Simulation time 28642385 ps
CPU time 0.39 seconds
Started Jun 13 12:17:50 PM PDT 24
Finished Jun 13 12:17:51 PM PDT 24
Peak memory 145424 kb
Host smart-6f959afe-e9f4-4140-9a2c-85e1fc007cd9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3922455929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3922455929
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3847838390
Short name T29
Test name
Test status
Simulation time 26855056 ps
CPU time 0.4 seconds
Started Jun 13 12:19:56 PM PDT 24
Finished Jun 13 12:19:56 PM PDT 24
Peak memory 145468 kb
Host smart-ae59b971-8d36-42f8-b674-618ea66db69b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3847838390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3847838390
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2983476461
Short name T74
Test name
Test status
Simulation time 27916155 ps
CPU time 0.4 seconds
Started Jun 13 12:18:40 PM PDT 24
Finished Jun 13 12:18:41 PM PDT 24
Peak memory 145404 kb
Host smart-4a91d08a-dab2-4b39-8620-ab0b76dadf94
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2983476461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2983476461
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3235324623
Short name T77
Test name
Test status
Simulation time 27025208 ps
CPU time 0.4 seconds
Started Jun 13 12:17:42 PM PDT 24
Finished Jun 13 12:17:42 PM PDT 24
Peak memory 145728 kb
Host smart-94fe56e9-7dd4-402a-9fab-7cd5109bce04
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3235324623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3235324623
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2052963730
Short name T69
Test name
Test status
Simulation time 27055921 ps
CPU time 0.41 seconds
Started Jun 13 12:21:40 PM PDT 24
Finished Jun 13 12:21:41 PM PDT 24
Peak memory 144992 kb
Host smart-08cff173-62cf-44a5-a964-2afe2e7f9cce
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2052963730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2052963730
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.587803664
Short name T67
Test name
Test status
Simulation time 28179056 ps
CPU time 0.4 seconds
Started Jun 13 12:18:41 PM PDT 24
Finished Jun 13 12:18:42 PM PDT 24
Peak memory 145460 kb
Host smart-b38c0a45-4473-46b5-8cda-226efecab61e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=587803664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.587803664
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4137582766
Short name T79
Test name
Test status
Simulation time 28312586 ps
CPU time 0.4 seconds
Started Jun 13 12:17:39 PM PDT 24
Finished Jun 13 12:17:39 PM PDT 24
Peak memory 145260 kb
Host smart-2e1e0020-0fdc-4d04-ba37-618fbfecb8d6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4137582766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.4137582766
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1189940338
Short name T27
Test name
Test status
Simulation time 26537730 ps
CPU time 0.39 seconds
Started Jun 13 12:18:39 PM PDT 24
Finished Jun 13 12:18:40 PM PDT 24
Peak memory 145428 kb
Host smart-5a65a521-d1ec-45a3-81d7-bd53e5c37de2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1189940338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1189940338
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1519071663
Short name T64
Test name
Test status
Simulation time 28677900 ps
CPU time 0.39 seconds
Started Jun 13 12:21:58 PM PDT 24
Finished Jun 13 12:21:59 PM PDT 24
Peak memory 146348 kb
Host smart-6242863c-807d-4c2f-a264-197c9852e30c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1519071663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1519071663
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.614403324
Short name T28
Test name
Test status
Simulation time 27591062 ps
CPU time 0.44 seconds
Started Jun 13 12:21:59 PM PDT 24
Finished Jun 13 12:22:00 PM PDT 24
Peak memory 145128 kb
Host smart-aa5658b8-7629-4858-9b9f-433f4aeec7fe
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=614403324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.614403324
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.276262711
Short name T78
Test name
Test status
Simulation time 26652194 ps
CPU time 0.38 seconds
Started Jun 13 12:22:17 PM PDT 24
Finished Jun 13 12:22:18 PM PDT 24
Peak memory 146260 kb
Host smart-3801f084-056c-47d2-a454-f5b689d18613
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=276262711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.276262711
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1119723192
Short name T63
Test name
Test status
Simulation time 28186284 ps
CPU time 0.41 seconds
Started Jun 13 12:18:09 PM PDT 24
Finished Jun 13 12:18:10 PM PDT 24
Peak memory 145272 kb
Host smart-d2d8f126-7554-4c8b-ba3d-090e0bd43fa5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1119723192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1119723192
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2632138609
Short name T75
Test name
Test status
Simulation time 26708643 ps
CPU time 0.4 seconds
Started Jun 13 12:17:10 PM PDT 24
Finished Jun 13 12:17:11 PM PDT 24
Peak memory 146344 kb
Host smart-0dd0495c-1df9-4cf8-8a5b-20bdbc5f03b2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2632138609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2632138609
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1778089690
Short name T76
Test name
Test status
Simulation time 27129646 ps
CPU time 0.4 seconds
Started Jun 13 12:18:38 PM PDT 24
Finished Jun 13 12:18:39 PM PDT 24
Peak memory 145380 kb
Host smart-ebd3322a-816f-4475-ac61-772219ba0b27
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1778089690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1778089690
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3345807109
Short name T65
Test name
Test status
Simulation time 25384948 ps
CPU time 0.41 seconds
Started Jun 13 12:19:39 PM PDT 24
Finished Jun 13 12:19:40 PM PDT 24
Peak memory 145384 kb
Host smart-2228dae1-80b2-421f-b4ee-47cd7247499b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3345807109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3345807109
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.202581762
Short name T68
Test name
Test status
Simulation time 28349944 ps
CPU time 0.39 seconds
Started Jun 13 12:18:38 PM PDT 24
Finished Jun 13 12:18:38 PM PDT 24
Peak memory 145388 kb
Host smart-e29ad85d-429e-4aa2-9688-e3cbb9ef0649
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=202581762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.202581762
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3730659546
Short name T71
Test name
Test status
Simulation time 27751410 ps
CPU time 0.4 seconds
Started Jun 13 12:21:49 PM PDT 24
Finished Jun 13 12:21:50 PM PDT 24
Peak memory 146280 kb
Host smart-f08fcf48-b15f-4019-9fdc-526dac653055
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3730659546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3730659546
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3561107977
Short name T70
Test name
Test status
Simulation time 26227762 ps
CPU time 0.4 seconds
Started Jun 13 12:21:50 PM PDT 24
Finished Jun 13 12:21:51 PM PDT 24
Peak memory 145060 kb
Host smart-f9e4043a-1445-4789-a038-8676d488e213
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3561107977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3561107977
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3342164980
Short name T73
Test name
Test status
Simulation time 26179008 ps
CPU time 0.37 seconds
Started Jun 13 12:17:49 PM PDT 24
Finished Jun 13 12:17:50 PM PDT 24
Peak memory 145412 kb
Host smart-3621acbb-965b-41fe-a824-9bafd050fc80
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3342164980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3342164980
Directory /workspace/9.prim_sync_fatal_alert/latest
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