| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.32 | 88.32 | 100.00 | 100.00 | 91.67 | 91.67 | 96.43 | 96.43 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/11.prim_async_alert.2649612393 |
| 91.80 | 3.48 | 100.00 | 0.00 | 93.75 | 2.08 | 96.43 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/7.prim_sync_alert.4171602746 |
| 93.90 | 2.11 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 3.57 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2776300234 |
| 94.85 | 0.94 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.260678498 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/5.prim_sync_alert.91246320 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.2740174292 |
| /workspace/coverage/default/1.prim_async_alert.1118765497 |
| /workspace/coverage/default/10.prim_async_alert.772887909 |
| /workspace/coverage/default/12.prim_async_alert.1733597362 |
| /workspace/coverage/default/13.prim_async_alert.3658058204 |
| /workspace/coverage/default/14.prim_async_alert.3570557757 |
| /workspace/coverage/default/15.prim_async_alert.1623270696 |
| /workspace/coverage/default/16.prim_async_alert.3437106844 |
| /workspace/coverage/default/17.prim_async_alert.3205292034 |
| /workspace/coverage/default/18.prim_async_alert.2889854170 |
| /workspace/coverage/default/2.prim_async_alert.354071622 |
| /workspace/coverage/default/3.prim_async_alert.1644223220 |
| /workspace/coverage/default/4.prim_async_alert.2213370060 |
| /workspace/coverage/default/5.prim_async_alert.1604838958 |
| /workspace/coverage/default/6.prim_async_alert.2769015089 |
| /workspace/coverage/default/7.prim_async_alert.3102200566 |
| /workspace/coverage/default/8.prim_async_alert.2134948412 |
| /workspace/coverage/default/9.prim_async_alert.893133067 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4035464949 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.570321142 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3552630672 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1287149655 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2097092427 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.304673941 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3455001146 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3714708592 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3801037040 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2755377394 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.741718055 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.863956933 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.132540980 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1951383188 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.597779466 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2209971657 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.4195878857 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.3488450317 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3279109909 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.3185149363 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.4210616206 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.932289859 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1043832411 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.2976428090 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.3605454420 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.52638367 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.464031128 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.2931322081 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.310152057 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.2291303128 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.2577436135 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1692377726 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.2979719551 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.2717756620 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1552622786 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1595934113 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.78435321 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.221170393 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1414365055 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3809377189 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.760761529 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4105004542 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1695185392 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4027474324 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1066736189 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1006269673 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3495326454 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4142571743 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2355867862 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3207096255 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1500001421 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2659610950 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1177386037 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/10.prim_async_alert.772887909 | Jun 21 04:20:51 PM PDT 24 | Jun 21 04:20:54 PM PDT 24 | 11732002 ps | ||
| T2 | /workspace/coverage/default/17.prim_async_alert.3205292034 | Jun 21 04:21:01 PM PDT 24 | Jun 21 04:21:04 PM PDT 24 | 11058786 ps | ||
| T3 | /workspace/coverage/default/0.prim_async_alert.2740174292 | Jun 21 04:20:52 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 11843178 ps | ||
| T15 | /workspace/coverage/default/13.prim_async_alert.3658058204 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 11359043 ps | ||
| T13 | /workspace/coverage/default/4.prim_async_alert.2213370060 | Jun 21 04:20:51 PM PDT 24 | Jun 21 04:20:53 PM PDT 24 | 10776459 ps | ||
| T12 | /workspace/coverage/default/14.prim_async_alert.3570557757 | Jun 21 04:20:52 PM PDT 24 | Jun 21 04:20:55 PM PDT 24 | 12442085 ps | ||
| T7 | /workspace/coverage/default/3.prim_async_alert.1644223220 | Jun 21 04:20:51 PM PDT 24 | Jun 21 04:20:53 PM PDT 24 | 10057303 ps | ||
| T20 | /workspace/coverage/default/12.prim_async_alert.1733597362 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 10849424 ps | ||
| T8 | /workspace/coverage/default/9.prim_async_alert.893133067 | Jun 21 04:20:52 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 10845167 ps | ||
| T18 | /workspace/coverage/default/11.prim_async_alert.2649612393 | Jun 21 04:21:26 PM PDT 24 | Jun 21 04:21:27 PM PDT 24 | 10842910 ps | ||
| T9 | /workspace/coverage/default/1.prim_async_alert.1118765497 | Jun 21 04:20:44 PM PDT 24 | Jun 21 04:20:45 PM PDT 24 | 10026384 ps | ||
| T21 | /workspace/coverage/default/5.prim_async_alert.1604838958 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:58 PM PDT 24 | 11098865 ps | ||
| T22 | /workspace/coverage/default/18.prim_async_alert.2889854170 | Jun 21 04:21:00 PM PDT 24 | Jun 21 04:21:02 PM PDT 24 | 10366909 ps | ||
| T50 | /workspace/coverage/default/2.prim_async_alert.354071622 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 11822086 ps | ||
| T10 | /workspace/coverage/default/6.prim_async_alert.2769015089 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 10617007 ps | ||
| T41 | /workspace/coverage/default/15.prim_async_alert.1623270696 | Jun 21 04:20:51 PM PDT 24 | Jun 21 04:20:53 PM PDT 24 | 11354980 ps | ||
| T51 | /workspace/coverage/default/16.prim_async_alert.3437106844 | Jun 21 04:20:52 PM PDT 24 | Jun 21 04:20:56 PM PDT 24 | 11330735 ps | ||
| T16 | /workspace/coverage/default/8.prim_async_alert.2134948412 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 11836165 ps | ||
| T52 | /workspace/coverage/default/7.prim_async_alert.3102200566 | Jun 21 04:20:52 PM PDT 24 | Jun 21 04:20:56 PM PDT 24 | 11676479 ps | ||
| T42 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2097092427 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:58 PM PDT 24 | 31704906 ps | ||
| T43 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3455001146 | Jun 21 04:21:34 PM PDT 24 | Jun 21 04:21:35 PM PDT 24 | 29761891 ps | ||
| T44 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1951383188 | Jun 21 04:21:01 PM PDT 24 | Jun 21 04:21:03 PM PDT 24 | 30062340 ps | ||
| T45 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3801037040 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:59 PM PDT 24 | 29853193 ps | ||
| T46 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1287149655 | Jun 21 04:21:00 PM PDT 24 | Jun 21 04:21:02 PM PDT 24 | 29729715 ps | ||
| T47 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2776300234 | Jun 21 04:20:51 PM PDT 24 | Jun 21 04:20:54 PM PDT 24 | 29155447 ps | ||
| T48 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.863956933 | Jun 21 04:20:52 PM PDT 24 | Jun 21 04:20:56 PM PDT 24 | 29391291 ps | ||
| T49 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3714708592 | Jun 21 04:20:54 PM PDT 24 | Jun 21 04:20:59 PM PDT 24 | 29424277 ps | ||
| T19 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.132540980 | Jun 21 04:21:33 PM PDT 24 | Jun 21 04:21:35 PM PDT 24 | 30395427 ps | ||
| T14 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2755377394 | Jun 21 04:20:54 PM PDT 24 | Jun 21 04:20:59 PM PDT 24 | 30687757 ps | ||
| T53 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.597779466 | Jun 21 04:21:01 PM PDT 24 | Jun 21 04:21:04 PM PDT 24 | 30653253 ps | ||
| T54 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2209971657 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 31471345 ps | ||
| T55 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4035464949 | Jun 21 04:20:51 PM PDT 24 | Jun 21 04:20:52 PM PDT 24 | 29694710 ps | ||
| T56 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.741718055 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 30498461 ps | ||
| T17 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.304673941 | Jun 21 04:20:52 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 31586342 ps | ||
| T57 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.570321142 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 32106674 ps | ||
| T58 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3552630672 | Jun 21 04:21:01 PM PDT 24 | Jun 21 04:21:04 PM PDT 24 | 30033794 ps | ||
| T31 | /workspace/coverage/sync_alert/16.prim_sync_alert.3605454420 | Jun 21 04:22:13 PM PDT 24 | Jun 21 04:22:14 PM PDT 24 | 7836349 ps | ||
| T32 | /workspace/coverage/sync_alert/17.prim_sync_alert.52638367 | Jun 21 04:20:49 PM PDT 24 | Jun 21 04:20:51 PM PDT 24 | 8572611 ps | ||
| T33 | /workspace/coverage/sync_alert/7.prim_sync_alert.4171602746 | Jun 21 04:20:52 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 9103851 ps | ||
| T34 | /workspace/coverage/sync_alert/9.prim_sync_alert.2717756620 | Jun 21 04:20:52 PM PDT 24 | Jun 21 04:20:56 PM PDT 24 | 8787581 ps | ||
| T35 | /workspace/coverage/sync_alert/14.prim_sync_alert.1043832411 | Jun 21 04:22:01 PM PDT 24 | Jun 21 04:22:02 PM PDT 24 | 10109199 ps | ||
| T36 | /workspace/coverage/sync_alert/6.prim_sync_alert.1692377726 | Jun 21 04:20:52 PM PDT 24 | Jun 21 04:20:56 PM PDT 24 | 9887487 ps | ||
| T23 | /workspace/coverage/sync_alert/19.prim_sync_alert.2931322081 | Jun 21 04:22:02 PM PDT 24 | Jun 21 04:22:04 PM PDT 24 | 9485031 ps | ||
| T24 | /workspace/coverage/sync_alert/10.prim_sync_alert.3279109909 | Jun 21 04:22:15 PM PDT 24 | Jun 21 04:22:16 PM PDT 24 | 8604099 ps | ||
| T37 | /workspace/coverage/sync_alert/3.prim_sync_alert.2291303128 | Jun 21 04:21:26 PM PDT 24 | Jun 21 04:21:27 PM PDT 24 | 9405433 ps | ||
| T38 | /workspace/coverage/sync_alert/1.prim_sync_alert.3488450317 | Jun 21 04:20:44 PM PDT 24 | Jun 21 04:20:45 PM PDT 24 | 9791282 ps | ||
| T39 | /workspace/coverage/sync_alert/15.prim_sync_alert.2976428090 | Jun 21 04:20:54 PM PDT 24 | Jun 21 04:20:59 PM PDT 24 | 8312917 ps | ||
| T40 | /workspace/coverage/sync_alert/13.prim_sync_alert.932289859 | Jun 21 04:20:49 PM PDT 24 | Jun 21 04:20:51 PM PDT 24 | 9651321 ps | ||
| T25 | /workspace/coverage/sync_alert/0.prim_sync_alert.4195878857 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:59 PM PDT 24 | 8613943 ps | ||
| T59 | /workspace/coverage/sync_alert/2.prim_sync_alert.310152057 | Jun 21 04:21:00 PM PDT 24 | Jun 21 04:21:02 PM PDT 24 | 9330993 ps | ||
| T60 | /workspace/coverage/sync_alert/8.prim_sync_alert.2979719551 | Jun 21 04:20:52 PM PDT 24 | Jun 21 04:20:56 PM PDT 24 | 8924021 ps | ||
| T61 | /workspace/coverage/sync_alert/18.prim_sync_alert.464031128 | Jun 21 04:20:54 PM PDT 24 | Jun 21 04:20:59 PM PDT 24 | 8960871 ps | ||
| T62 | /workspace/coverage/sync_alert/11.prim_sync_alert.3185149363 | Jun 21 04:20:52 PM PDT 24 | Jun 21 04:20:56 PM PDT 24 | 8422631 ps | ||
| T11 | /workspace/coverage/sync_alert/5.prim_sync_alert.91246320 | Jun 21 04:21:01 PM PDT 24 | Jun 21 04:21:04 PM PDT 24 | 9799088 ps | ||
| T63 | /workspace/coverage/sync_alert/4.prim_sync_alert.2577436135 | Jun 21 04:21:33 PM PDT 24 | Jun 21 04:21:34 PM PDT 24 | 8527791 ps | ||
| T64 | /workspace/coverage/sync_alert/12.prim_sync_alert.4210616206 | Jun 21 04:22:14 PM PDT 24 | Jun 21 04:22:16 PM PDT 24 | 8584266 ps | ||
| T4 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.260678498 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:58 PM PDT 24 | 28864643 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4105004542 | Jun 21 04:22:00 PM PDT 24 | Jun 21 04:22:02 PM PDT 24 | 29249569 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.760761529 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 27164435 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1500001421 | Jun 21 04:22:00 PM PDT 24 | Jun 21 04:22:02 PM PDT 24 | 26255041 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1177386037 | Jun 21 04:22:02 PM PDT 24 | Jun 21 04:22:04 PM PDT 24 | 27361468 ps | ||
| T26 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1695185392 | Jun 21 04:25:24 PM PDT 24 | Jun 21 04:25:26 PM PDT 24 | 26624711 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1006269673 | Jun 21 04:22:12 PM PDT 24 | Jun 21 04:22:13 PM PDT 24 | 28206133 ps | ||
| T27 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2355867862 | Jun 21 04:22:14 PM PDT 24 | Jun 21 04:22:16 PM PDT 24 | 27950133 ps | ||
| T28 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4027474324 | Jun 21 04:22:15 PM PDT 24 | Jun 21 04:22:16 PM PDT 24 | 26220161 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4142571743 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 28659974 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3495326454 | Jun 21 04:20:54 PM PDT 24 | Jun 21 04:20:59 PM PDT 24 | 27067510 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1066736189 | Jun 21 04:22:13 PM PDT 24 | Jun 21 04:22:14 PM PDT 24 | 27160372 ps | ||
| T29 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1414365055 | Jun 21 04:20:46 PM PDT 24 | Jun 21 04:20:47 PM PDT 24 | 27480166 ps | ||
| T30 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.78435321 | Jun 21 04:22:15 PM PDT 24 | Jun 21 04:22:17 PM PDT 24 | 27370693 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1595934113 | Jun 21 04:20:53 PM PDT 24 | Jun 21 04:20:57 PM PDT 24 | 28863439 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1552622786 | Jun 21 04:22:15 PM PDT 24 | Jun 21 04:22:16 PM PDT 24 | 27058222 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3207096255 | Jun 21 04:22:13 PM PDT 24 | Jun 21 04:22:14 PM PDT 24 | 28441301 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3809377189 | Jun 21 04:22:00 PM PDT 24 | Jun 21 04:22:02 PM PDT 24 | 27624861 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2659610950 | Jun 21 04:20:54 PM PDT 24 | Jun 21 04:20:59 PM PDT 24 | 27439838 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.221170393 | Jun 21 04:22:13 PM PDT 24 | Jun 21 04:22:15 PM PDT 24 | 27406936 ps |
| Test location | /workspace/coverage/default/11.prim_async_alert.2649612393 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10842910 ps |
| CPU time | 0.37 seconds |
| Started | Jun 21 04:21:26 PM PDT 24 |
| Finished | Jun 21 04:21:27 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-d72ba420-aa19-4157-910e-401db39af11a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2649612393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2649612393 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.4171602746 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9103851 ps |
| CPU time | 0.36 seconds |
| Started | Jun 21 04:20:52 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-4d785439-ca28-4587-b31a-511d4bfacd36 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4171602746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.4171602746 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2776300234 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 29155447 ps |
| CPU time | 0.41 seconds |
| Started | Jun 21 04:20:51 PM PDT 24 |
| Finished | Jun 21 04:20:54 PM PDT 24 |
| Peak memory | 145328 kb |
| Host | smart-76f2613f-00e7-439b-810e-3334abbc010d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2776300234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2776300234 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.260678498 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28864643 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:58 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-e92b8821-b1fe-41c3-99d8-786ba8f9d6c9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=260678498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.260678498 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.91246320 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9799088 ps |
| CPU time | 0.41 seconds |
| Started | Jun 21 04:21:01 PM PDT 24 |
| Finished | Jun 21 04:21:04 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-413a76ea-19d0-4bce-a988-61e3fd3eade7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=91246320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.91246320 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.2740174292 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11843178 ps |
| CPU time | 0.37 seconds |
| Started | Jun 21 04:20:52 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 145324 kb |
| Host | smart-f84001a6-bcc9-457c-9ae1-ba08f739bec2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2740174292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2740174292 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1118765497 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10026384 ps |
| CPU time | 0.42 seconds |
| Started | Jun 21 04:20:44 PM PDT 24 |
| Finished | Jun 21 04:20:45 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-6403b9e9-5e7a-4a1d-a237-6e2bd0c37c8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1118765497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1118765497 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.772887909 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11732002 ps |
| CPU time | 0.44 seconds |
| Started | Jun 21 04:20:51 PM PDT 24 |
| Finished | Jun 21 04:20:54 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-73866b1e-2fdb-46c4-a28a-e10d14c010a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772887909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.772887909 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.1733597362 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10849424 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-9459b590-4126-42ac-a8cb-4961f250e69f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733597362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1733597362 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3658058204 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11359043 ps |
| CPU time | 0.43 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 144100 kb |
| Host | smart-d32c1b9f-7f12-4094-92e5-283852b17142 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3658058204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3658058204 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.3570557757 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12442085 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:20:52 PM PDT 24 |
| Finished | Jun 21 04:20:55 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-d80fdf22-b5cf-4ed4-8026-81b88dea024c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570557757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3570557757 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1623270696 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11354980 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:20:51 PM PDT 24 |
| Finished | Jun 21 04:20:53 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-20e302e3-acdd-469c-93a9-2429d825928d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623270696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1623270696 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.3437106844 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 11330735 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:20:52 PM PDT 24 |
| Finished | Jun 21 04:20:56 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-8919550a-075b-4215-9d0b-9d1d4371ab8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3437106844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3437106844 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.3205292034 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11058786 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:21:01 PM PDT 24 |
| Finished | Jun 21 04:21:04 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-749223f7-9083-4c8e-bdb7-b5bccd136dbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205292034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3205292034 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.2889854170 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10366909 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:21:00 PM PDT 24 |
| Finished | Jun 21 04:21:02 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-b3b338c1-b6b1-44f9-bbfa-e6dfd1f8c5a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2889854170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2889854170 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.354071622 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11822086 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-c2d97561-20aa-494a-85b1-7e992e1a109f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=354071622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.354071622 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.1644223220 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10057303 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:20:51 PM PDT 24 |
| Finished | Jun 21 04:20:53 PM PDT 24 |
| Peak memory | 145272 kb |
| Host | smart-5e162e30-bc12-4ab4-b256-3e88fd831b2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1644223220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1644223220 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.2213370060 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10776459 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:20:51 PM PDT 24 |
| Finished | Jun 21 04:20:53 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-1acf8e4c-f773-4bc3-884c-43c5b6e43c2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213370060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2213370060 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.1604838958 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11098865 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:58 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-dc56c35f-8d3e-49f1-b028-22e2288e5ded |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604838958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1604838958 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2769015089 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10617007 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-ae7033b3-7071-40ec-8c4d-84341862c54f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769015089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2769015089 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.3102200566 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 11676479 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:20:52 PM PDT 24 |
| Finished | Jun 21 04:20:56 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-d1fff9dd-96f6-4dcf-aa45-f91b65b3854e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3102200566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3102200566 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.2134948412 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11836165 ps |
| CPU time | 0.43 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 144288 kb |
| Host | smart-e68ccdc6-7333-47a5-b472-dabdc2917517 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2134948412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2134948412 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.893133067 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10845167 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:20:52 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-0d0facef-fead-4f11-9f5c-22d01f642661 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=893133067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.893133067 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4035464949 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29694710 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:20:51 PM PDT 24 |
| Finished | Jun 21 04:20:52 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-e8b2ad07-211d-43b8-ae80-e0e6e2547a3d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4035464949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4035464949 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.570321142 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 32106674 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-0bb24543-b964-46b6-94f3-acb7408437f6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=570321142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.570321142 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3552630672 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 30033794 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:21:01 PM PDT 24 |
| Finished | Jun 21 04:21:04 PM PDT 24 |
| Peak memory | 144744 kb |
| Host | smart-cc4c1135-c6ef-4408-a112-f154eb263a70 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3552630672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3552630672 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1287149655 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29729715 ps |
| CPU time | 0.41 seconds |
| Started | Jun 21 04:21:00 PM PDT 24 |
| Finished | Jun 21 04:21:02 PM PDT 24 |
| Peak memory | 144732 kb |
| Host | smart-e85a02ab-051c-4e19-8ae2-0f05265ee2e8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1287149655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1287149655 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2097092427 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 31704906 ps |
| CPU time | 0.41 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:58 PM PDT 24 |
| Peak memory | 145328 kb |
| Host | smart-e58213da-d974-40d3-a50c-b1d2dbfb56c8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2097092427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2097092427 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.304673941 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 31586342 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:20:52 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 144812 kb |
| Host | smart-a01cd48d-076f-4761-b7e7-eebbe9eddef3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=304673941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.304673941 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3455001146 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 29761891 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:21:34 PM PDT 24 |
| Finished | Jun 21 04:21:35 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-314bc827-0b83-4c78-8eb4-187896c19e01 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3455001146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3455001146 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3714708592 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29424277 ps |
| CPU time | 0.43 seconds |
| Started | Jun 21 04:20:54 PM PDT 24 |
| Finished | Jun 21 04:20:59 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-6bb874af-ea0d-4ab8-bb54-66612938e34a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3714708592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3714708592 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3801037040 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29853193 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:59 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-b097bd1c-15c6-47d9-a88e-93e3c0fd60a2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3801037040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3801037040 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2755377394 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 30687757 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:20:54 PM PDT 24 |
| Finished | Jun 21 04:20:59 PM PDT 24 |
| Peak memory | 145328 kb |
| Host | smart-b6a97249-ee69-45a4-b77a-084426b8bf8e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2755377394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2755377394 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.741718055 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 30498461 ps |
| CPU time | 0.43 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 144008 kb |
| Host | smart-09f58671-96ba-412a-a098-b2a483252595 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=741718055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.741718055 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.863956933 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 29391291 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:20:52 PM PDT 24 |
| Finished | Jun 21 04:20:56 PM PDT 24 |
| Peak memory | 145328 kb |
| Host | smart-3286c6a1-73a7-44f1-bfca-90c0d6e588c9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=863956933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.863956933 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.132540980 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 30395427 ps |
| CPU time | 0.42 seconds |
| Started | Jun 21 04:21:33 PM PDT 24 |
| Finished | Jun 21 04:21:35 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-8a34999b-b775-45a5-82cd-e59041d124b5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=132540980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.132540980 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1951383188 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30062340 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:21:01 PM PDT 24 |
| Finished | Jun 21 04:21:03 PM PDT 24 |
| Peak memory | 144748 kb |
| Host | smart-a513d722-8b76-4ef0-98ed-0fceaeae0d8e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1951383188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1951383188 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.597779466 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30653253 ps |
| CPU time | 0.42 seconds |
| Started | Jun 21 04:21:01 PM PDT 24 |
| Finished | Jun 21 04:21:04 PM PDT 24 |
| Peak memory | 144756 kb |
| Host | smart-4a89aa82-754f-47f6-9e33-939b0b45103c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=597779466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.597779466 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2209971657 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 31471345 ps |
| CPU time | 0.41 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 144740 kb |
| Host | smart-4de7aac4-cdf3-4cc3-87cb-194f50103cd1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2209971657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2209971657 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.4195878857 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8613943 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:59 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-2ed5994f-295c-4288-9c60-4bafd4f9d99c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4195878857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.4195878857 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.3488450317 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9791282 ps |
| CPU time | 0.42 seconds |
| Started | Jun 21 04:20:44 PM PDT 24 |
| Finished | Jun 21 04:20:45 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-be30b88d-d1c5-45e6-b732-97e7a3981e32 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3488450317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3488450317 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3279109909 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8604099 ps |
| CPU time | 0.41 seconds |
| Started | Jun 21 04:22:15 PM PDT 24 |
| Finished | Jun 21 04:22:16 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-75227f05-7155-498e-9982-880539af9e6a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3279109909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3279109909 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.3185149363 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 8422631 ps |
| CPU time | 0.37 seconds |
| Started | Jun 21 04:20:52 PM PDT 24 |
| Finished | Jun 21 04:20:56 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-c3ff6fcf-1470-4f21-adf0-007fd424c076 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3185149363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3185149363 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.4210616206 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 8584266 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:22:14 PM PDT 24 |
| Finished | Jun 21 04:22:16 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-189bfa51-7994-487a-bbab-bfea817a5c41 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4210616206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.4210616206 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.932289859 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9651321 ps |
| CPU time | 0.44 seconds |
| Started | Jun 21 04:20:49 PM PDT 24 |
| Finished | Jun 21 04:20:51 PM PDT 24 |
| Peak memory | 143752 kb |
| Host | smart-20742e27-18c9-46dd-a8c1-dba757a26dbf |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=932289859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.932289859 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1043832411 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10109199 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:22:01 PM PDT 24 |
| Finished | Jun 21 04:22:02 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-81371556-b483-4243-a44f-3728c247f40f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1043832411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1043832411 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.2976428090 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8312917 ps |
| CPU time | 0.37 seconds |
| Started | Jun 21 04:20:54 PM PDT 24 |
| Finished | Jun 21 04:20:59 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-b753e71d-391e-43d3-80bc-ab8d339cdda2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2976428090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2976428090 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.3605454420 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7836349 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:22:13 PM PDT 24 |
| Finished | Jun 21 04:22:14 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-f95e097d-d80a-4604-be2f-f3bd8c35e2ad |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3605454420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3605454420 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.52638367 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8572611 ps |
| CPU time | 0.43 seconds |
| Started | Jun 21 04:20:49 PM PDT 24 |
| Finished | Jun 21 04:20:51 PM PDT 24 |
| Peak memory | 144208 kb |
| Host | smart-dfaba3dc-9863-4d7c-aa97-6a5bde403d5e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=52638367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.52638367 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.464031128 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 8960871 ps |
| CPU time | 0.37 seconds |
| Started | Jun 21 04:20:54 PM PDT 24 |
| Finished | Jun 21 04:20:59 PM PDT 24 |
| Peak memory | 144860 kb |
| Host | smart-24962d57-c026-483e-b191-d04352706167 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=464031128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.464031128 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.2931322081 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9485031 ps |
| CPU time | 0.44 seconds |
| Started | Jun 21 04:22:02 PM PDT 24 |
| Finished | Jun 21 04:22:04 PM PDT 24 |
| Peak memory | 143268 kb |
| Host | smart-f75b8f43-8595-40fc-a583-d774cf5288f3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2931322081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2931322081 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.310152057 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9330993 ps |
| CPU time | 0.48 seconds |
| Started | Jun 21 04:21:00 PM PDT 24 |
| Finished | Jun 21 04:21:02 PM PDT 24 |
| Peak memory | 145864 kb |
| Host | smart-4a28b1e7-9154-4be9-8c95-95f8dfa0e109 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=310152057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.310152057 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.2291303128 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9405433 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:21:26 PM PDT 24 |
| Finished | Jun 21 04:21:27 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-1c92ad11-2b4a-4b6e-87ae-99c3d6352259 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2291303128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2291303128 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.2577436135 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 8527791 ps |
| CPU time | 0.37 seconds |
| Started | Jun 21 04:21:33 PM PDT 24 |
| Finished | Jun 21 04:21:34 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-b4dceb29-12d2-4908-8e44-91d71e1696a2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2577436135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2577436135 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1692377726 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9887487 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:20:52 PM PDT 24 |
| Finished | Jun 21 04:20:56 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-6b45f8b3-4d24-4bc4-b524-530331867d4d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1692377726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1692377726 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.2979719551 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8924021 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:20:52 PM PDT 24 |
| Finished | Jun 21 04:20:56 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-40616b18-d39f-4a28-9d05-b4bd14b330b3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2979719551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2979719551 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.2717756620 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8787581 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:20:52 PM PDT 24 |
| Finished | Jun 21 04:20:56 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-0a2a4471-861f-4762-8fbd-d98da250577b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2717756620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2717756620 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1552622786 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27058222 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:22:15 PM PDT 24 |
| Finished | Jun 21 04:22:16 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-77b6dad0-b16b-4acc-9da8-183383d7c4aa |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1552622786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1552622786 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1595934113 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28863439 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 144804 kb |
| Host | smart-97b7f7f8-e889-4290-bd09-79d72f01ad73 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1595934113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1595934113 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.78435321 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 27370693 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:22:15 PM PDT 24 |
| Finished | Jun 21 04:22:17 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-a8458598-5ed0-4aa3-9886-8604bdbce1e7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=78435321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.78435321 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.221170393 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27406936 ps |
| CPU time | 0.42 seconds |
| Started | Jun 21 04:22:13 PM PDT 24 |
| Finished | Jun 21 04:22:15 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-fac161ee-8c50-42a8-af1c-cb2ef4e67f27 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=221170393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.221170393 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1414365055 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 27480166 ps |
| CPU time | 0.46 seconds |
| Started | Jun 21 04:20:46 PM PDT 24 |
| Finished | Jun 21 04:20:47 PM PDT 24 |
| Peak memory | 145844 kb |
| Host | smart-e4a8e0fb-8f5e-4a33-a5ca-3b39328edb9d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1414365055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1414365055 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3809377189 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27624861 ps |
| CPU time | 0.45 seconds |
| Started | Jun 21 04:22:00 PM PDT 24 |
| Finished | Jun 21 04:22:02 PM PDT 24 |
| Peak memory | 144104 kb |
| Host | smart-1e5d424e-a76a-45b7-90c3-ec4e630e853c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3809377189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3809377189 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.760761529 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27164435 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 144828 kb |
| Host | smart-87eb921a-98bb-4dd5-8e60-b530afbb474c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=760761529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.760761529 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4105004542 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 29249569 ps |
| CPU time | 0.48 seconds |
| Started | Jun 21 04:22:00 PM PDT 24 |
| Finished | Jun 21 04:22:02 PM PDT 24 |
| Peak memory | 143736 kb |
| Host | smart-ac6d440f-f871-41ce-a6dc-2fe0d1fc54a9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4105004542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.4105004542 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1695185392 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 26624711 ps |
| CPU time | 0.41 seconds |
| Started | Jun 21 04:25:24 PM PDT 24 |
| Finished | Jun 21 04:25:26 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-94e8eb21-22e7-44ae-8ef0-cb20b64a24f1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1695185392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1695185392 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4027474324 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 26220161 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:22:15 PM PDT 24 |
| Finished | Jun 21 04:22:16 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-0b908886-bc86-4dfc-b008-1df511f58bc8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4027474324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.4027474324 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1066736189 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27160372 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:22:13 PM PDT 24 |
| Finished | Jun 21 04:22:14 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-8b51cd77-632a-4519-8c63-0abb03ebdc4e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1066736189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1066736189 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1006269673 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28206133 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:22:12 PM PDT 24 |
| Finished | Jun 21 04:22:13 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-c35e01e9-c5d5-4cd7-bb3d-32b9d20aa2a2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1006269673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1006269673 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3495326454 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27067510 ps |
| CPU time | 0.38 seconds |
| Started | Jun 21 04:20:54 PM PDT 24 |
| Finished | Jun 21 04:20:59 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-0473a53b-fba9-40f3-b96d-ee862726ea30 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3495326454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3495326454 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4142571743 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 28659974 ps |
| CPU time | 0.39 seconds |
| Started | Jun 21 04:20:53 PM PDT 24 |
| Finished | Jun 21 04:20:57 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-4fb971d6-20d9-4133-9f16-8c64a236e199 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4142571743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.4142571743 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2355867862 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 27950133 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:22:14 PM PDT 24 |
| Finished | Jun 21 04:22:16 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-01b656ce-cf38-4dcf-8f99-d24be1e7c77f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2355867862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2355867862 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3207096255 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28441301 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:22:13 PM PDT 24 |
| Finished | Jun 21 04:22:14 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-a582966f-fa81-4d7e-8d33-aac59e6b7494 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3207096255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3207096255 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1500001421 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26255041 ps |
| CPU time | 0.4 seconds |
| Started | Jun 21 04:22:00 PM PDT 24 |
| Finished | Jun 21 04:22:02 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-c4f3c5c8-d858-4156-bbc2-a681fb09a983 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1500001421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1500001421 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2659610950 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27439838 ps |
| CPU time | 0.37 seconds |
| Started | Jun 21 04:20:54 PM PDT 24 |
| Finished | Jun 21 04:20:59 PM PDT 24 |
| Peak memory | 144876 kb |
| Host | smart-7f601186-e9eb-432c-8df5-2b2177388aed |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2659610950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2659610950 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1177386037 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27361468 ps |
| CPU time | 0.48 seconds |
| Started | Jun 21 04:22:02 PM PDT 24 |
| Finished | Jun 21 04:22:04 PM PDT 24 |
| Peak memory | 143140 kb |
| Host | smart-ffc6bd79-ff2f-4701-8d3c-6d294154d78e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1177386037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1177386037 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |