| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.08 | 88.08 | 100.00 | 100.00 | 93.75 | 93.75 | 96.43 | 96.43 | 75.00 | 75.00 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/3.prim_async_alert.1334437001 |
| 91.20 | 3.13 | 100.00 | 0.00 | 93.75 | 0.00 | 96.43 | 0.00 | 82.14 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/14.prim_sync_alert.438740249 |
| 93.31 | 2.11 | 100.00 | 0.00 | 95.83 | 2.08 | 96.43 | 0.00 | 85.71 | 3.57 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1507791703 |
| 94.50 | 1.19 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 3.57 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/9.prim_async_alert.125572154 |
| 95.19 | 0.69 | 100.00 | 0.00 | 100.00 | 4.17 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.832856720 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.3580686554 |
| /workspace/coverage/default/1.prim_async_alert.3592421889 |
| /workspace/coverage/default/10.prim_async_alert.2627955388 |
| /workspace/coverage/default/11.prim_async_alert.3603466059 |
| /workspace/coverage/default/12.prim_async_alert.3119874880 |
| /workspace/coverage/default/13.prim_async_alert.1222579283 |
| /workspace/coverage/default/14.prim_async_alert.1835192964 |
| /workspace/coverage/default/15.prim_async_alert.383538744 |
| /workspace/coverage/default/16.prim_async_alert.101491927 |
| /workspace/coverage/default/17.prim_async_alert.1571237099 |
| /workspace/coverage/default/18.prim_async_alert.2005159680 |
| /workspace/coverage/default/19.prim_async_alert.219736634 |
| /workspace/coverage/default/2.prim_async_alert.738838137 |
| /workspace/coverage/default/4.prim_async_alert.2533857590 |
| /workspace/coverage/default/5.prim_async_alert.3518550167 |
| /workspace/coverage/default/6.prim_async_alert.396512789 |
| /workspace/coverage/default/7.prim_async_alert.2630111689 |
| /workspace/coverage/default/8.prim_async_alert.2137300569 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2640783819 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3024383398 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3623540352 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.426688820 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3209757619 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3996668315 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1289041241 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4049549711 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.906339570 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3297464803 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.797705064 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3478900613 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.227742266 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3616164532 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4087571803 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1901955373 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3270335211 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3455981124 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.588744502 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.4064077239 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.1429013932 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.3893409242 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3138895222 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1019810322 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.3216135950 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.918111844 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.331239682 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.961479541 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.578284230 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.237111663 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.1847361743 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.701892774 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.1533930265 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.310741406 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.349875792 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.2205013797 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.656511323 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.10544399 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1201976670 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.18803907 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.989425004 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3624777486 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3493766569 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2944803003 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.877850208 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.599933912 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3771766518 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.203742673 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3444241156 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2760280906 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1724291417 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1027437879 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3180136416 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1200149271 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1111671382 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.704347413 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_async_alert.3119874880 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:48 PM PDT 24 | 10968105 ps | ||
| T2 | /workspace/coverage/default/10.prim_async_alert.2627955388 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:50 PM PDT 24 | 11118173 ps | ||
| T3 | /workspace/coverage/default/3.prim_async_alert.1334437001 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 10621777 ps | ||
| T7 | /workspace/coverage/default/2.prim_async_alert.738838137 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:50 PM PDT 24 | 11817192 ps | ||
| T6 | /workspace/coverage/default/16.prim_async_alert.101491927 | Jun 22 04:16:51 PM PDT 24 | Jun 22 04:16:52 PM PDT 24 | 12230592 ps | ||
| T10 | /workspace/coverage/default/19.prim_async_alert.219736634 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:48 PM PDT 24 | 10794370 ps | ||
| T19 | /workspace/coverage/default/4.prim_async_alert.2533857590 | Jun 22 04:16:52 PM PDT 24 | Jun 22 04:16:53 PM PDT 24 | 11969357 ps | ||
| T8 | /workspace/coverage/default/8.prim_async_alert.2137300569 | Jun 22 04:16:48 PM PDT 24 | Jun 22 04:16:50 PM PDT 24 | 12474350 ps | ||
| T9 | /workspace/coverage/default/13.prim_async_alert.1222579283 | Jun 22 04:16:45 PM PDT 24 | Jun 22 04:16:47 PM PDT 24 | 11452108 ps | ||
| T20 | /workspace/coverage/default/0.prim_async_alert.3580686554 | Jun 22 04:16:52 PM PDT 24 | Jun 22 04:16:53 PM PDT 24 | 11602977 ps | ||
| T21 | /workspace/coverage/default/7.prim_async_alert.2630111689 | Jun 22 04:16:45 PM PDT 24 | Jun 22 04:16:45 PM PDT 24 | 10896365 ps | ||
| T22 | /workspace/coverage/default/15.prim_async_alert.383538744 | Jun 22 04:16:45 PM PDT 24 | Jun 22 04:16:47 PM PDT 24 | 10331391 ps | ||
| T11 | /workspace/coverage/default/9.prim_async_alert.125572154 | Jun 22 04:16:51 PM PDT 24 | Jun 22 04:16:52 PM PDT 24 | 11816257 ps | ||
| T49 | /workspace/coverage/default/11.prim_async_alert.3603466059 | Jun 22 04:16:51 PM PDT 24 | Jun 22 04:16:52 PM PDT 24 | 11423642 ps | ||
| T23 | /workspace/coverage/default/14.prim_async_alert.1835192964 | Jun 22 04:16:51 PM PDT 24 | Jun 22 04:16:53 PM PDT 24 | 10768292 ps | ||
| T50 | /workspace/coverage/default/5.prim_async_alert.3518550167 | Jun 22 04:18:04 PM PDT 24 | Jun 22 04:18:05 PM PDT 24 | 11061341 ps | ||
| T14 | /workspace/coverage/default/17.prim_async_alert.1571237099 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:48 PM PDT 24 | 12618483 ps | ||
| T24 | /workspace/coverage/default/6.prim_async_alert.396512789 | Jun 22 04:16:40 PM PDT 24 | Jun 22 04:16:42 PM PDT 24 | 10992596 ps | ||
| T15 | /workspace/coverage/default/1.prim_async_alert.3592421889 | Jun 22 04:16:49 PM PDT 24 | Jun 22 04:16:51 PM PDT 24 | 11075060 ps | ||
| T17 | /workspace/coverage/default/18.prim_async_alert.2005159680 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 11640587 ps | ||
| T43 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3616164532 | Jun 22 04:16:40 PM PDT 24 | Jun 22 04:16:42 PM PDT 24 | 32020848 ps | ||
| T44 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3270335211 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 30076645 ps | ||
| T45 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3996668315 | Jun 22 04:16:45 PM PDT 24 | Jun 22 04:16:46 PM PDT 24 | 30382945 ps | ||
| T46 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2640783819 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:50 PM PDT 24 | 30791109 ps | ||
| T47 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3024383398 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:48 PM PDT 24 | 28774082 ps | ||
| T18 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3297464803 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:48 PM PDT 24 | 30449790 ps | ||
| T12 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.227742266 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:48 PM PDT 24 | 30470822 ps | ||
| T16 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.797705064 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:47 PM PDT 24 | 30680524 ps | ||
| T48 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3209757619 | Jun 22 04:16:52 PM PDT 24 | Jun 22 04:16:53 PM PDT 24 | 30406239 ps | ||
| T41 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1507791703 | Jun 22 04:16:45 PM PDT 24 | Jun 22 04:16:46 PM PDT 24 | 30143170 ps | ||
| T13 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3478900613 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:50 PM PDT 24 | 31912196 ps | ||
| T51 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4087571803 | Jun 22 04:16:52 PM PDT 24 | Jun 22 04:16:53 PM PDT 24 | 31415584 ps | ||
| T52 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4049549711 | Jun 22 04:16:45 PM PDT 24 | Jun 22 04:16:47 PM PDT 24 | 32205592 ps | ||
| T53 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3623540352 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 27782207 ps | ||
| T54 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3455981124 | Jun 22 04:16:52 PM PDT 24 | Jun 22 04:16:53 PM PDT 24 | 30620815 ps | ||
| T55 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1289041241 | Jun 22 04:16:44 PM PDT 24 | Jun 22 04:16:45 PM PDT 24 | 29316114 ps | ||
| T42 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1901955373 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:48 PM PDT 24 | 30327918 ps | ||
| T40 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.906339570 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:48 PM PDT 24 | 32656103 ps | ||
| T56 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.426688820 | Jun 22 04:16:48 PM PDT 24 | Jun 22 04:16:50 PM PDT 24 | 31089634 ps | ||
| T34 | /workspace/coverage/sync_alert/11.prim_sync_alert.3893409242 | Jun 22 04:16:48 PM PDT 24 | Jun 22 04:16:50 PM PDT 24 | 9371955 ps | ||
| T35 | /workspace/coverage/sync_alert/9.prim_sync_alert.656511323 | Jun 22 04:16:45 PM PDT 24 | Jun 22 04:16:47 PM PDT 24 | 9219492 ps | ||
| T25 | /workspace/coverage/sync_alert/6.prim_sync_alert.310741406 | Jun 22 04:16:45 PM PDT 24 | Jun 22 04:16:46 PM PDT 24 | 8689146 ps | ||
| T36 | /workspace/coverage/sync_alert/12.prim_sync_alert.3138895222 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 9235951 ps | ||
| T37 | /workspace/coverage/sync_alert/16.prim_sync_alert.918111844 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:50 PM PDT 24 | 9111593 ps | ||
| T26 | /workspace/coverage/sync_alert/1.prim_sync_alert.4064077239 | Jun 22 04:17:48 PM PDT 24 | Jun 22 04:17:50 PM PDT 24 | 9029984 ps | ||
| T27 | /workspace/coverage/sync_alert/4.prim_sync_alert.701892774 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:48 PM PDT 24 | 9446744 ps | ||
| T38 | /workspace/coverage/sync_alert/14.prim_sync_alert.438740249 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:50 PM PDT 24 | 9196664 ps | ||
| T28 | /workspace/coverage/sync_alert/2.prim_sync_alert.237111663 | Jun 22 04:17:48 PM PDT 24 | Jun 22 04:17:50 PM PDT 24 | 8844375 ps | ||
| T39 | /workspace/coverage/sync_alert/0.prim_sync_alert.588744502 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 8883002 ps | ||
| T29 | /workspace/coverage/sync_alert/8.prim_sync_alert.2205013797 | Jun 22 04:18:04 PM PDT 24 | Jun 22 04:18:05 PM PDT 24 | 10450118 ps | ||
| T30 | /workspace/coverage/sync_alert/13.prim_sync_alert.1019810322 | Jun 22 04:22:10 PM PDT 24 | Jun 22 04:22:11 PM PDT 24 | 8827193 ps | ||
| T57 | /workspace/coverage/sync_alert/17.prim_sync_alert.331239682 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 9341188 ps | ||
| T58 | /workspace/coverage/sync_alert/7.prim_sync_alert.349875792 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 8753582 ps | ||
| T31 | /workspace/coverage/sync_alert/5.prim_sync_alert.1533930265 | Jun 22 04:17:49 PM PDT 24 | Jun 22 04:17:50 PM PDT 24 | 9373020 ps | ||
| T32 | /workspace/coverage/sync_alert/10.prim_sync_alert.1429013932 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 9907166 ps | ||
| T59 | /workspace/coverage/sync_alert/18.prim_sync_alert.961479541 | Jun 22 04:17:48 PM PDT 24 | Jun 22 04:17:50 PM PDT 24 | 8922488 ps | ||
| T33 | /workspace/coverage/sync_alert/19.prim_sync_alert.578284230 | Jun 22 04:17:48 PM PDT 24 | Jun 22 04:17:50 PM PDT 24 | 9353327 ps | ||
| T60 | /workspace/coverage/sync_alert/15.prim_sync_alert.3216135950 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 8369116 ps | ||
| T61 | /workspace/coverage/sync_alert/3.prim_sync_alert.1847361743 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 8736747 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.704347413 | Jun 22 04:17:19 PM PDT 24 | Jun 22 04:17:20 PM PDT 24 | 27685330 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.877850208 | Jun 22 04:16:49 PM PDT 24 | Jun 22 04:16:51 PM PDT 24 | 27323301 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.989425004 | Jun 22 04:17:45 PM PDT 24 | Jun 22 04:17:47 PM PDT 24 | 27197599 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1724291417 | Jun 22 04:16:48 PM PDT 24 | Jun 22 04:16:50 PM PDT 24 | 27260844 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1027437879 | Jun 22 04:17:18 PM PDT 24 | Jun 22 04:17:19 PM PDT 24 | 29459070 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3493766569 | Jun 22 04:17:45 PM PDT 24 | Jun 22 04:17:46 PM PDT 24 | 28738464 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1201976670 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 26159222 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.18803907 | Jun 22 04:18:01 PM PDT 24 | Jun 22 04:18:02 PM PDT 24 | 27074631 ps | ||
| T4 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1200149271 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 28531282 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3771766518 | Jun 22 04:22:52 PM PDT 24 | Jun 22 04:22:53 PM PDT 24 | 28420707 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1111671382 | Jun 22 04:17:19 PM PDT 24 | Jun 22 04:17:20 PM PDT 24 | 26091735 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3624777486 | Jun 22 04:16:40 PM PDT 24 | Jun 22 04:16:42 PM PDT 24 | 27066583 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.599933912 | Jun 22 04:18:01 PM PDT 24 | Jun 22 04:18:02 PM PDT 24 | 27726708 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2944803003 | Jun 22 04:18:56 PM PDT 24 | Jun 22 04:18:57 PM PDT 24 | 26980895 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.10544399 | Jun 22 04:17:48 PM PDT 24 | Jun 22 04:17:50 PM PDT 24 | 27440150 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2760280906 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 28723642 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3444241156 | Jun 22 04:18:56 PM PDT 24 | Jun 22 04:18:57 PM PDT 24 | 26184141 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.832856720 | Jun 22 04:16:47 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 28658002 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.203742673 | Jun 22 04:17:46 PM PDT 24 | Jun 22 04:17:47 PM PDT 24 | 25993484 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3180136416 | Jun 22 04:16:46 PM PDT 24 | Jun 22 04:16:49 PM PDT 24 | 27700883 ps |
| Test location | /workspace/coverage/default/3.prim_async_alert.1334437001 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10621777 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145884 kb |
| Host | smart-29bea65f-38db-4087-a439-40e9a6259f56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1334437001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1334437001 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.438740249 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9196664 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:50 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-3f5682cd-ebc8-414b-bfb7-c7cb8b7f0d79 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=438740249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.438740249 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1507791703 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30143170 ps |
| CPU time | 0.43 seconds |
| Started | Jun 22 04:16:45 PM PDT 24 |
| Finished | Jun 22 04:16:46 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-050fdd5a-0229-4bb6-9613-50b4a9c3dc79 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1507791703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1507791703 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.125572154 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11816257 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:16:51 PM PDT 24 |
| Finished | Jun 22 04:16:52 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-a9cd179f-990b-4041-8d0f-b5a063374290 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125572154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.125572154 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.832856720 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 28658002 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-af96c4f5-bb82-41b4-97f6-d90af2f91d74 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=832856720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.832856720 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.3580686554 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11602977 ps |
| CPU time | 0.37 seconds |
| Started | Jun 22 04:16:52 PM PDT 24 |
| Finished | Jun 22 04:16:53 PM PDT 24 |
| Peak memory | 145512 kb |
| Host | smart-dccd1f82-f3b4-4c49-a382-03f4115c1b5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580686554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3580686554 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.3592421889 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11075060 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:49 PM PDT 24 |
| Finished | Jun 22 04:16:51 PM PDT 24 |
| Peak memory | 145512 kb |
| Host | smart-99329ff6-8211-4b3d-8865-55544f2071d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3592421889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3592421889 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.2627955388 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11118173 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:50 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-b929d1f8-77a0-4678-ba69-2bbb4a5b9157 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2627955388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2627955388 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.3603466059 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11423642 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:51 PM PDT 24 |
| Finished | Jun 22 04:16:52 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-c8d588c1-ca3a-4c5f-a927-332c4c737629 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3603466059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3603466059 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.3119874880 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10968105 ps |
| CPU time | 0.42 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:48 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-97875acd-8776-43bd-b0cb-25f8028cb230 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3119874880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3119874880 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.1222579283 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11452108 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:16:45 PM PDT 24 |
| Finished | Jun 22 04:16:47 PM PDT 24 |
| Peak memory | 146088 kb |
| Host | smart-c94bf6b4-4ab6-43a8-9881-8de4c9f8e41d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222579283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1222579283 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1835192964 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10768292 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:16:51 PM PDT 24 |
| Finished | Jun 22 04:16:53 PM PDT 24 |
| Peak memory | 145908 kb |
| Host | smart-64969317-c994-40a8-aed5-80b4e8f6d29e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835192964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1835192964 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.383538744 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10331391 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:16:45 PM PDT 24 |
| Finished | Jun 22 04:16:47 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-3c360dd4-a253-4fd9-a5fc-f9e8b478cf9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383538744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.383538744 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.101491927 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 12230592 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:51 PM PDT 24 |
| Finished | Jun 22 04:16:52 PM PDT 24 |
| Peak memory | 145512 kb |
| Host | smart-34130c64-fbcb-41dd-964d-bddb11879a6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101491927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.101491927 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.1571237099 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12618483 ps |
| CPU time | 0.37 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:48 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-7c7e990d-b385-462a-9ed0-7a8ba857d743 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1571237099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1571237099 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.2005159680 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11640587 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145892 kb |
| Host | smart-5324af79-1da5-48c5-a51b-138ff167ac11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2005159680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2005159680 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.219736634 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10794370 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:48 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-69e7038e-302a-4a6f-beb1-76310caa0291 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219736634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.219736634 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.738838137 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11817192 ps |
| CPU time | 0.37 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:50 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-ed09710d-7812-434f-9ee2-3857c1393cc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738838137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.738838137 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.2533857590 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11969357 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:52 PM PDT 24 |
| Finished | Jun 22 04:16:53 PM PDT 24 |
| Peak memory | 145512 kb |
| Host | smart-66c5858a-8a49-4676-9369-a564115b06c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533857590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2533857590 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3518550167 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11061341 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:18:04 PM PDT 24 |
| Finished | Jun 22 04:18:05 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-17b153f8-10ed-4dcc-b70c-4c0b867ba4ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3518550167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3518550167 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.396512789 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10992596 ps |
| CPU time | 0.46 seconds |
| Started | Jun 22 04:16:40 PM PDT 24 |
| Finished | Jun 22 04:16:42 PM PDT 24 |
| Peak memory | 144376 kb |
| Host | smart-6cd01d64-cbd5-48f3-8064-4d2889429b76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=396512789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.396512789 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.2630111689 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10896365 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:16:45 PM PDT 24 |
| Finished | Jun 22 04:16:45 PM PDT 24 |
| Peak memory | 145908 kb |
| Host | smart-1100eb08-5f31-4fe2-b24e-ab252050ea83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630111689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2630111689 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.2137300569 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12474350 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:48 PM PDT 24 |
| Finished | Jun 22 04:16:50 PM PDT 24 |
| Peak memory | 145836 kb |
| Host | smart-8477134e-fe01-45e0-8961-e1a2d6fcd669 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137300569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2137300569 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2640783819 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 30791109 ps |
| CPU time | 0.42 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:50 PM PDT 24 |
| Peak memory | 145360 kb |
| Host | smart-0d6b50e4-ced7-4441-8814-33e211f2052b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2640783819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2640783819 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3024383398 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 28774082 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:48 PM PDT 24 |
| Peak memory | 144724 kb |
| Host | smart-a7581351-38c0-473f-bcae-af9908496d72 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3024383398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3024383398 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3623540352 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 27782207 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145364 kb |
| Host | smart-3ea70967-e3da-4e9a-a940-1f92f81cb2e6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3623540352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3623540352 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.426688820 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 31089634 ps |
| CPU time | 0.42 seconds |
| Started | Jun 22 04:16:48 PM PDT 24 |
| Finished | Jun 22 04:16:50 PM PDT 24 |
| Peak memory | 145364 kb |
| Host | smart-71ea7770-9fa0-4127-b81b-3142e4a6e6c4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=426688820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.426688820 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3209757619 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30406239 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:16:52 PM PDT 24 |
| Finished | Jun 22 04:16:53 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-a478c867-55c7-4480-bf20-875d04cc9c83 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3209757619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3209757619 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3996668315 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30382945 ps |
| CPU time | 0.42 seconds |
| Started | Jun 22 04:16:45 PM PDT 24 |
| Finished | Jun 22 04:16:46 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-abcf0195-4267-4fcd-94e5-49b843db90d3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3996668315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3996668315 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1289041241 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29316114 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:16:44 PM PDT 24 |
| Finished | Jun 22 04:16:45 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-489e3c3d-cca5-4f08-8f17-504306253922 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1289041241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1289041241 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4049549711 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 32205592 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:16:45 PM PDT 24 |
| Finished | Jun 22 04:16:47 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-bf384fb9-39b3-48ce-824a-86a944d6d095 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4049549711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.4049549711 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.906339570 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 32656103 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:48 PM PDT 24 |
| Peak memory | 144732 kb |
| Host | smart-e43d5708-b94a-435a-9d95-50ae841a45bf |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=906339570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.906339570 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3297464803 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 30449790 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:48 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-d81198d5-3465-4a93-aaa8-fd7689e5ec34 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3297464803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3297464803 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.797705064 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 30680524 ps |
| CPU time | 0.44 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:47 PM PDT 24 |
| Peak memory | 145404 kb |
| Host | smart-d5b52903-0182-45b7-85b3-503ff54f6783 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=797705064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.797705064 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3478900613 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 31912196 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:50 PM PDT 24 |
| Peak memory | 144776 kb |
| Host | smart-5a3402a1-4a60-4793-8afa-508061a5eb0b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3478900613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3478900613 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.227742266 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 30470822 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:48 PM PDT 24 |
| Peak memory | 145404 kb |
| Host | smart-68d3e6b6-cc67-4c45-9905-4ee43ca81a2a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=227742266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.227742266 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3616164532 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 32020848 ps |
| CPU time | 0.49 seconds |
| Started | Jun 22 04:16:40 PM PDT 24 |
| Finished | Jun 22 04:16:42 PM PDT 24 |
| Peak memory | 144080 kb |
| Host | smart-55ff2133-7eb6-448c-b1e0-1b0a98df51cf |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3616164532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3616164532 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4087571803 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 31415584 ps |
| CPU time | 0.42 seconds |
| Started | Jun 22 04:16:52 PM PDT 24 |
| Finished | Jun 22 04:16:53 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-13cef680-09e4-44a2-aae4-e7785b8a0034 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4087571803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.4087571803 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1901955373 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30327918 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:48 PM PDT 24 |
| Peak memory | 144740 kb |
| Host | smart-583eb97a-eecd-41ba-aaab-eeb5ac7da369 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1901955373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1901955373 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3270335211 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30076645 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145360 kb |
| Host | smart-f859cf1c-5522-4d20-b000-fb1d6cbc6803 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3270335211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3270335211 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3455981124 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30620815 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:16:52 PM PDT 24 |
| Finished | Jun 22 04:16:53 PM PDT 24 |
| Peak memory | 145404 kb |
| Host | smart-1b17fa69-62b5-4f9e-9ed9-6112cae108c2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3455981124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3455981124 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.588744502 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8883002 ps |
| CPU time | 0.37 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-25e4aa81-83c4-4748-ac2f-2d1aeb28801a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=588744502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.588744502 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.4064077239 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9029984 ps |
| CPU time | 0.48 seconds |
| Started | Jun 22 04:17:48 PM PDT 24 |
| Finished | Jun 22 04:17:50 PM PDT 24 |
| Peak memory | 143512 kb |
| Host | smart-14dbad58-abe1-4a8e-8691-c22d9f8b88a3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4064077239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.4064077239 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.1429013932 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9907166 ps |
| CPU time | 0.37 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-ce80752e-c669-4d5a-a699-a5bc9e1913dd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1429013932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1429013932 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.3893409242 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9371955 ps |
| CPU time | 0.37 seconds |
| Started | Jun 22 04:16:48 PM PDT 24 |
| Finished | Jun 22 04:16:50 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-975af655-e0cc-4778-9c93-e084ee4eb309 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3893409242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3893409242 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3138895222 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9235951 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-92fcb4d6-f7ac-4a9c-b8ba-879a4681230a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3138895222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3138895222 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1019810322 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8827193 ps |
| CPU time | 0.42 seconds |
| Started | Jun 22 04:22:10 PM PDT 24 |
| Finished | Jun 22 04:22:11 PM PDT 24 |
| Peak memory | 145836 kb |
| Host | smart-286d72e8-1772-4199-a588-9a4104e9bb7e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1019810322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1019810322 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.3216135950 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8369116 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-56172244-9793-4a5d-9630-0bd66ea3eb84 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3216135950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3216135950 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.918111844 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9111593 ps |
| CPU time | 0.36 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:50 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-d415445d-d564-4058-9332-8cc601f5068c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=918111844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.918111844 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.331239682 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9341188 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:47 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-188c9e60-2ea5-4c43-a1af-98b4ffc252d2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=331239682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.331239682 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.961479541 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8922488 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:17:48 PM PDT 24 |
| Finished | Jun 22 04:17:50 PM PDT 24 |
| Peak memory | 144600 kb |
| Host | smart-786ca39e-6b9f-49fa-b364-44604e9e0ed8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=961479541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.961479541 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.578284230 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9353327 ps |
| CPU time | 0.47 seconds |
| Started | Jun 22 04:17:48 PM PDT 24 |
| Finished | Jun 22 04:17:50 PM PDT 24 |
| Peak memory | 143452 kb |
| Host | smart-865b0342-9313-44fb-9a9f-8178a0ba1599 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=578284230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.578284230 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.237111663 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8844375 ps |
| CPU time | 0.46 seconds |
| Started | Jun 22 04:17:48 PM PDT 24 |
| Finished | Jun 22 04:17:50 PM PDT 24 |
| Peak memory | 144028 kb |
| Host | smart-b49cedab-32ef-4386-8c05-f949e4965c1e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=237111663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.237111663 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.1847361743 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 8736747 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-f94f521c-cf4d-46fa-b8de-602e6e75a8b7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1847361743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1847361743 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.701892774 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9446744 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:48 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-3e9f5d35-acc8-438f-aca2-6d65cc17753b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=701892774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.701892774 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1533930265 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9373020 ps |
| CPU time | 0.36 seconds |
| Started | Jun 22 04:17:49 PM PDT 24 |
| Finished | Jun 22 04:17:50 PM PDT 24 |
| Peak memory | 144896 kb |
| Host | smart-96496999-9ae6-45e5-8e6b-f3d03fdd150e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1533930265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1533930265 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.310741406 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8689146 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:16:45 PM PDT 24 |
| Finished | Jun 22 04:16:46 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-68a50f3b-83fa-46fb-b7e3-6dc642f2de1e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=310741406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.310741406 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.349875792 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8753582 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-8b8501fc-4c50-43f3-987a-aae9820a7b5d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=349875792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.349875792 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.2205013797 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10450118 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:18:04 PM PDT 24 |
| Finished | Jun 22 04:18:05 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-f4de306c-02cc-4ee9-a174-e226ca294621 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2205013797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2205013797 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.656511323 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9219492 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:16:45 PM PDT 24 |
| Finished | Jun 22 04:16:47 PM PDT 24 |
| Peak memory | 145692 kb |
| Host | smart-bb1c6a39-e461-489c-9462-d12e86aec8cc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=656511323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.656511323 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.10544399 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27440150 ps |
| CPU time | 0.47 seconds |
| Started | Jun 22 04:17:48 PM PDT 24 |
| Finished | Jun 22 04:17:50 PM PDT 24 |
| Peak memory | 144252 kb |
| Host | smart-1b8f326a-6500-433e-83aa-9650af501c17 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=10544399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.10544399 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1201976670 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26159222 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-3890c3c5-5c73-48fa-91fb-b1d4edd5acef |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1201976670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1201976670 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.18803907 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27074631 ps |
| CPU time | 0.45 seconds |
| Started | Jun 22 04:18:01 PM PDT 24 |
| Finished | Jun 22 04:18:02 PM PDT 24 |
| Peak memory | 145412 kb |
| Host | smart-94e859da-181f-4dd1-b53d-41d4f0b79135 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=18803907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.18803907 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.989425004 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27197599 ps |
| CPU time | 0.43 seconds |
| Started | Jun 22 04:17:45 PM PDT 24 |
| Finished | Jun 22 04:17:47 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-065482c1-98b0-4bcd-95ba-70f02b641055 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=989425004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.989425004 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3624777486 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27066583 ps |
| CPU time | 0.51 seconds |
| Started | Jun 22 04:16:40 PM PDT 24 |
| Finished | Jun 22 04:16:42 PM PDT 24 |
| Peak memory | 144392 kb |
| Host | smart-09c7080e-6969-4430-b3fd-cfb3c6df4a9c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3624777486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3624777486 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3493766569 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28738464 ps |
| CPU time | 0.43 seconds |
| Started | Jun 22 04:17:45 PM PDT 24 |
| Finished | Jun 22 04:17:46 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-92edbced-3a3e-4c3e-a535-5a67ee114307 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3493766569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3493766569 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2944803003 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26980895 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:18:56 PM PDT 24 |
| Finished | Jun 22 04:18:57 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-c101b8d8-dddb-4eb7-94cc-59bf6ed8fd29 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2944803003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2944803003 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.877850208 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27323301 ps |
| CPU time | 0.5 seconds |
| Started | Jun 22 04:16:49 PM PDT 24 |
| Finished | Jun 22 04:16:51 PM PDT 24 |
| Peak memory | 145844 kb |
| Host | smart-b9e3ca9a-d8f5-42e2-8c8c-3038ccd75a90 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=877850208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.877850208 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.599933912 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27726708 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:18:01 PM PDT 24 |
| Finished | Jun 22 04:18:02 PM PDT 24 |
| Peak memory | 145400 kb |
| Host | smart-7b574b23-7bfd-404a-99a9-6c024ec63597 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=599933912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.599933912 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3771766518 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28420707 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:22:52 PM PDT 24 |
| Finished | Jun 22 04:22:53 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-992e369e-0f41-4bd1-8188-432824852c27 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3771766518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3771766518 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.203742673 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 25993484 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:17:46 PM PDT 24 |
| Finished | Jun 22 04:17:47 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-08ea5d7d-1469-4aeb-a17a-13e5b0853112 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=203742673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.203742673 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3444241156 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 26184141 ps |
| CPU time | 0.43 seconds |
| Started | Jun 22 04:18:56 PM PDT 24 |
| Finished | Jun 22 04:18:57 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-879fd3b7-1c9c-48d2-a199-818cbe273f08 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3444241156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3444241156 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2760280906 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 28723642 ps |
| CPU time | 0.38 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-991dcf38-e949-4813-bf85-bb2cb3ea95ba |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2760280906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2760280906 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1724291417 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27260844 ps |
| CPU time | 0.4 seconds |
| Started | Jun 22 04:16:48 PM PDT 24 |
| Finished | Jun 22 04:16:50 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-0dd950a2-b952-4e26-9803-2fb68cf21043 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1724291417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1724291417 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1027437879 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 29459070 ps |
| CPU time | 0.42 seconds |
| Started | Jun 22 04:17:18 PM PDT 24 |
| Finished | Jun 22 04:17:19 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-49020493-031e-43e6-8616-a8ca5a5fac81 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1027437879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1027437879 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3180136416 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 27700883 ps |
| CPU time | 0.39 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-258a493a-052e-4357-9249-7ef82cba73be |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3180136416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3180136416 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1200149271 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28531282 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:16:46 PM PDT 24 |
| Finished | Jun 22 04:16:49 PM PDT 24 |
| Peak memory | 145336 kb |
| Host | smart-f657daf4-3b12-4024-9e31-6a1f698f9da4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1200149271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1200149271 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1111671382 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26091735 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:17:19 PM PDT 24 |
| Finished | Jun 22 04:17:20 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-c06e39e1-1c47-4f0c-a3a7-95e1e4f31bee |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1111671382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1111671382 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.704347413 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27685330 ps |
| CPU time | 0.41 seconds |
| Started | Jun 22 04:17:19 PM PDT 24 |
| Finished | Jun 22 04:17:20 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-f803ea6c-6994-4c96-b0b2-fdf3575f61f0 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=704347413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.704347413 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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