Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 78
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.88 88.88 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/17.prim_async_alert.3925162883
92.35 3.48 100.00 0.00 95.83 2.08 100.00 0.00 85.71 7.14 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/8.prim_sync_alert.923011165
94.50 2.15 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 9.30 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2270996660
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/11.prim_async_alert.1025740750
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.828245047

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3953273184
/workspace/coverage/default/1.prim_async_alert.390616281
/workspace/coverage/default/10.prim_async_alert.233193161
/workspace/coverage/default/12.prim_async_alert.1660248181
/workspace/coverage/default/13.prim_async_alert.1210661071
/workspace/coverage/default/14.prim_async_alert.865029051
/workspace/coverage/default/15.prim_async_alert.4074821407
/workspace/coverage/default/16.prim_async_alert.3668564616
/workspace/coverage/default/18.prim_async_alert.1960340471
/workspace/coverage/default/19.prim_async_alert.3746880981
/workspace/coverage/default/3.prim_async_alert.2962528382
/workspace/coverage/default/4.prim_async_alert.1070063862
/workspace/coverage/default/5.prim_async_alert.2408709720
/workspace/coverage/default/6.prim_async_alert.883671094
/workspace/coverage/default/7.prim_async_alert.3716922291
/workspace/coverage/default/8.prim_async_alert.1925326016
/workspace/coverage/default/9.prim_async_alert.1540253615
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2872722303
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3264505744
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.514965917
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1496617003
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1096926779
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3421955582
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3614778631
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.670363762
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1053925437
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1858077756
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3578333595
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4027405050
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1061350802
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4196303085
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1910361974
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.640988946
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2980344296
/workspace/coverage/sync_alert/0.prim_sync_alert.2200421392
/workspace/coverage/sync_alert/1.prim_sync_alert.3373761495
/workspace/coverage/sync_alert/10.prim_sync_alert.2716535262
/workspace/coverage/sync_alert/11.prim_sync_alert.158398890
/workspace/coverage/sync_alert/12.prim_sync_alert.583187759
/workspace/coverage/sync_alert/13.prim_sync_alert.469894356
/workspace/coverage/sync_alert/14.prim_sync_alert.2243116742
/workspace/coverage/sync_alert/15.prim_sync_alert.3143679399
/workspace/coverage/sync_alert/16.prim_sync_alert.3189296176
/workspace/coverage/sync_alert/17.prim_sync_alert.3729695427
/workspace/coverage/sync_alert/18.prim_sync_alert.2185462714
/workspace/coverage/sync_alert/19.prim_sync_alert.2208026214
/workspace/coverage/sync_alert/2.prim_sync_alert.708489808
/workspace/coverage/sync_alert/3.prim_sync_alert.2590283388
/workspace/coverage/sync_alert/4.prim_sync_alert.1397487299
/workspace/coverage/sync_alert/5.prim_sync_alert.1506330586
/workspace/coverage/sync_alert/6.prim_sync_alert.6276982
/workspace/coverage/sync_alert/7.prim_sync_alert.1224419166
/workspace/coverage/sync_alert/9.prim_sync_alert.658064061
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3423608154
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3573237990
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4257625615
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1872181415
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2293394864
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1176339781
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.636499076
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.707544468
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1587534252
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.721000116
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4111181632
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3784847605
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2166142641
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1203422417
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1519189191
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2315294419
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.387014020
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3608093266
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1343933362
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3453905654



Total test records in report: 78
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/16.prim_async_alert.3668564616 Jun 23 04:24:30 PM PDT 24 Jun 23 04:24:32 PM PDT 24 11326147 ps
T2 /workspace/coverage/default/14.prim_async_alert.865029051 Jun 23 04:23:30 PM PDT 24 Jun 23 04:23:31 PM PDT 24 11137151 ps
T3 /workspace/coverage/default/15.prim_async_alert.4074821407 Jun 23 04:22:53 PM PDT 24 Jun 23 04:22:54 PM PDT 24 12316766 ps
T11 /workspace/coverage/default/0.prim_async_alert.3953273184 Jun 23 04:23:07 PM PDT 24 Jun 23 04:23:08 PM PDT 24 10609867 ps
T17 /workspace/coverage/default/10.prim_async_alert.233193161 Jun 23 04:19:00 PM PDT 24 Jun 23 04:19:01 PM PDT 24 11560293 ps
T18 /workspace/coverage/default/3.prim_async_alert.2962528382 Jun 23 04:20:31 PM PDT 24 Jun 23 04:20:32 PM PDT 24 10150633 ps
T19 /workspace/coverage/default/19.prim_async_alert.3746880981 Jun 23 04:19:39 PM PDT 24 Jun 23 04:19:40 PM PDT 24 10915706 ps
T6 /workspace/coverage/default/9.prim_async_alert.1540253615 Jun 23 04:22:53 PM PDT 24 Jun 23 04:22:54 PM PDT 24 11512463 ps
T9 /workspace/coverage/default/1.prim_async_alert.390616281 Jun 23 04:22:41 PM PDT 24 Jun 23 04:22:43 PM PDT 24 11108692 ps
T10 /workspace/coverage/default/17.prim_async_alert.3925162883 Jun 23 04:21:24 PM PDT 24 Jun 23 04:21:25 PM PDT 24 12870135 ps
T20 /workspace/coverage/default/7.prim_async_alert.3716922291 Jun 23 04:22:53 PM PDT 24 Jun 23 04:22:54 PM PDT 24 11177028 ps
T21 /workspace/coverage/default/13.prim_async_alert.1210661071 Jun 23 04:23:30 PM PDT 24 Jun 23 04:23:31 PM PDT 24 10932483 ps
T22 /workspace/coverage/default/12.prim_async_alert.1660248181 Jun 23 04:22:54 PM PDT 24 Jun 23 04:22:56 PM PDT 24 10872984 ps
T45 /workspace/coverage/default/18.prim_async_alert.1960340471 Jun 23 04:23:09 PM PDT 24 Jun 23 04:23:09 PM PDT 24 11398811 ps
T12 /workspace/coverage/default/8.prim_async_alert.1925326016 Jun 23 04:21:41 PM PDT 24 Jun 23 04:21:41 PM PDT 24 11764409 ps
T13 /workspace/coverage/default/5.prim_async_alert.2408709720 Jun 23 04:20:29 PM PDT 24 Jun 23 04:20:29 PM PDT 24 12417469 ps
T23 /workspace/coverage/default/4.prim_async_alert.1070063862 Jun 23 04:20:30 PM PDT 24 Jun 23 04:20:30 PM PDT 24 12595767 ps
T46 /workspace/coverage/default/11.prim_async_alert.1025740750 Jun 23 04:23:08 PM PDT 24 Jun 23 04:23:09 PM PDT 24 10629825 ps
T24 /workspace/coverage/default/6.prim_async_alert.883671094 Jun 23 04:21:42 PM PDT 24 Jun 23 04:21:43 PM PDT 24 11430091 ps
T14 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2270996660 Jun 23 05:37:13 PM PDT 24 Jun 23 05:37:13 PM PDT 24 30887100 ps
T25 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.640988946 Jun 23 05:37:16 PM PDT 24 Jun 23 05:37:17 PM PDT 24 30500841 ps
T16 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3421955582 Jun 23 05:37:17 PM PDT 24 Jun 23 05:37:18 PM PDT 24 28426383 ps
T39 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2872722303 Jun 23 05:37:14 PM PDT 24 Jun 23 05:37:16 PM PDT 24 31144775 ps
T40 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1858077756 Jun 23 05:37:13 PM PDT 24 Jun 23 05:37:14 PM PDT 24 27971747 ps
T41 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3578333595 Jun 23 05:37:17 PM PDT 24 Jun 23 05:37:18 PM PDT 24 29802655 ps
T4 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.828245047 Jun 23 05:37:15 PM PDT 24 Jun 23 05:37:16 PM PDT 24 30014147 ps
T42 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1496617003 Jun 23 05:37:18 PM PDT 24 Jun 23 05:37:19 PM PDT 24 29647701 ps
T43 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3264505744 Jun 23 05:37:13 PM PDT 24 Jun 23 05:37:15 PM PDT 24 30168591 ps
T44 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1096926779 Jun 23 05:37:14 PM PDT 24 Jun 23 05:37:15 PM PDT 24 31875106 ps
T15 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4027405050 Jun 23 05:37:12 PM PDT 24 Jun 23 05:37:13 PM PDT 24 28298249 ps
T47 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1910361974 Jun 23 05:37:18 PM PDT 24 Jun 23 05:37:19 PM PDT 24 30891730 ps
T48 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3614778631 Jun 23 05:37:17 PM PDT 24 Jun 23 05:37:18 PM PDT 24 30485877 ps
T49 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.670363762 Jun 23 05:37:20 PM PDT 24 Jun 23 05:37:21 PM PDT 24 29183849 ps
T50 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1061350802 Jun 23 05:37:19 PM PDT 24 Jun 23 05:37:20 PM PDT 24 31735036 ps
T51 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.514965917 Jun 23 05:37:17 PM PDT 24 Jun 23 05:37:18 PM PDT 24 29214675 ps
T52 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2980344296 Jun 23 05:37:15 PM PDT 24 Jun 23 05:37:16 PM PDT 24 31359911 ps
T53 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4196303085 Jun 23 05:37:20 PM PDT 24 Jun 23 05:37:21 PM PDT 24 30356736 ps
T54 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1053925437 Jun 23 05:37:19 PM PDT 24 Jun 23 05:37:21 PM PDT 24 29391385 ps
T35 /workspace/coverage/sync_alert/9.prim_sync_alert.658064061 Jun 23 05:45:42 PM PDT 24 Jun 23 05:45:43 PM PDT 24 10494844 ps
T26 /workspace/coverage/sync_alert/6.prim_sync_alert.6276982 Jun 23 05:45:40 PM PDT 24 Jun 23 05:45:41 PM PDT 24 10202126 ps
T27 /workspace/coverage/sync_alert/0.prim_sync_alert.2200421392 Jun 23 05:45:40 PM PDT 24 Jun 23 05:45:41 PM PDT 24 9513590 ps
T7 /workspace/coverage/sync_alert/8.prim_sync_alert.923011165 Jun 23 05:45:44 PM PDT 24 Jun 23 05:45:44 PM PDT 24 8409741 ps
T36 /workspace/coverage/sync_alert/1.prim_sync_alert.3373761495 Jun 23 05:45:38 PM PDT 24 Jun 23 05:45:38 PM PDT 24 10087410 ps
T37 /workspace/coverage/sync_alert/5.prim_sync_alert.1506330586 Jun 23 05:45:43 PM PDT 24 Jun 23 05:45:43 PM PDT 24 8664115 ps
T28 /workspace/coverage/sync_alert/10.prim_sync_alert.2716535262 Jun 23 05:45:42 PM PDT 24 Jun 23 05:45:43 PM PDT 24 9964331 ps
T8 /workspace/coverage/sync_alert/12.prim_sync_alert.583187759 Jun 23 05:45:42 PM PDT 24 Jun 23 05:45:42 PM PDT 24 8441731 ps
T29 /workspace/coverage/sync_alert/3.prim_sync_alert.2590283388 Jun 23 05:45:43 PM PDT 24 Jun 23 05:45:44 PM PDT 24 8674512 ps
T38 /workspace/coverage/sync_alert/15.prim_sync_alert.3143679399 Jun 23 05:45:46 PM PDT 24 Jun 23 05:45:46 PM PDT 24 9522548 ps
T30 /workspace/coverage/sync_alert/17.prim_sync_alert.3729695427 Jun 23 05:45:47 PM PDT 24 Jun 23 05:45:48 PM PDT 24 10202324 ps
T55 /workspace/coverage/sync_alert/11.prim_sync_alert.158398890 Jun 23 05:45:42 PM PDT 24 Jun 23 05:45:43 PM PDT 24 8806058 ps
T31 /workspace/coverage/sync_alert/13.prim_sync_alert.469894356 Jun 23 05:45:42 PM PDT 24 Jun 23 05:45:43 PM PDT 24 8633698 ps
T32 /workspace/coverage/sync_alert/2.prim_sync_alert.708489808 Jun 23 05:45:43 PM PDT 24 Jun 23 05:45:44 PM PDT 24 9590973 ps
T33 /workspace/coverage/sync_alert/7.prim_sync_alert.1224419166 Jun 23 05:45:41 PM PDT 24 Jun 23 05:45:42 PM PDT 24 9830576 ps
T34 /workspace/coverage/sync_alert/4.prim_sync_alert.1397487299 Jun 23 05:45:43 PM PDT 24 Jun 23 05:45:43 PM PDT 24 8907542 ps
T56 /workspace/coverage/sync_alert/14.prim_sync_alert.2243116742 Jun 23 05:45:48 PM PDT 24 Jun 23 05:45:49 PM PDT 24 8605058 ps
T57 /workspace/coverage/sync_alert/19.prim_sync_alert.2208026214 Jun 23 05:45:46 PM PDT 24 Jun 23 05:45:47 PM PDT 24 8951565 ps
T58 /workspace/coverage/sync_alert/16.prim_sync_alert.3189296176 Jun 23 05:45:47 PM PDT 24 Jun 23 05:45:48 PM PDT 24 8920406 ps
T59 /workspace/coverage/sync_alert/18.prim_sync_alert.2185462714 Jun 23 05:45:46 PM PDT 24 Jun 23 05:45:47 PM PDT 24 8865333 ps
T60 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3423608154 Jun 23 05:48:59 PM PDT 24 Jun 23 05:49:00 PM PDT 24 28600366 ps
T61 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.707544468 Jun 23 05:49:01 PM PDT 24 Jun 23 05:49:01 PM PDT 24 28850022 ps
T62 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4257625615 Jun 23 05:49:02 PM PDT 24 Jun 23 05:49:03 PM PDT 24 28270050 ps
T63 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3573237990 Jun 23 05:49:07 PM PDT 24 Jun 23 05:49:08 PM PDT 24 28380052 ps
T64 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3784847605 Jun 23 05:49:01 PM PDT 24 Jun 23 05:49:02 PM PDT 24 26708126 ps
T5 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1872181415 Jun 23 05:49:02 PM PDT 24 Jun 23 05:49:03 PM PDT 24 27848451 ps
T65 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1587534252 Jun 23 05:48:59 PM PDT 24 Jun 23 05:49:00 PM PDT 24 27899175 ps
T66 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.721000116 Jun 23 05:49:02 PM PDT 24 Jun 23 05:49:03 PM PDT 24 28253646 ps
T67 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.387014020 Jun 23 05:49:00 PM PDT 24 Jun 23 05:49:01 PM PDT 24 26821020 ps
T68 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2293394864 Jun 23 05:49:02 PM PDT 24 Jun 23 05:49:02 PM PDT 24 28073370 ps
T69 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1519189191 Jun 23 05:49:00 PM PDT 24 Jun 23 05:49:01 PM PDT 24 27679672 ps
T70 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4111181632 Jun 23 05:49:07 PM PDT 24 Jun 23 05:49:08 PM PDT 24 26218339 ps
T71 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2166142641 Jun 23 05:49:00 PM PDT 24 Jun 23 05:49:01 PM PDT 24 25015604 ps
T72 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2315294419 Jun 23 05:49:07 PM PDT 24 Jun 23 05:49:08 PM PDT 24 27258577 ps
T73 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1343933362 Jun 23 05:48:58 PM PDT 24 Jun 23 05:48:59 PM PDT 24 29260241 ps
T74 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3608093266 Jun 23 05:49:01 PM PDT 24 Jun 23 05:49:02 PM PDT 24 27810694 ps
T75 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3453905654 Jun 23 05:49:01 PM PDT 24 Jun 23 05:49:02 PM PDT 24 27029936 ps
T76 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1176339781 Jun 23 05:49:06 PM PDT 24 Jun 23 05:49:07 PM PDT 24 28885588 ps
T77 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1203422417 Jun 23 05:49:04 PM PDT 24 Jun 23 05:49:05 PM PDT 24 26525012 ps
T78 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.636499076 Jun 23 05:49:01 PM PDT 24 Jun 23 05:49:02 PM PDT 24 26588465 ps

Test location /workspace/coverage/default/17.prim_async_alert.3925162883
Short name T10
Test name
Test status
Simulation time 12870135 ps
CPU time 0.39 seconds
Started Jun 23 04:21:24 PM PDT 24
Finished Jun 23 04:21:25 PM PDT 24
Peak memory 145568 kb
Host smart-7cb96250-c47f-42fd-a7f8-94934966c46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925162883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3925162883
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.923011165
Short name T7
Test name
Test status
Simulation time 8409741 ps
CPU time 0.38 seconds
Started Jun 23 05:45:44 PM PDT 24
Finished Jun 23 05:45:44 PM PDT 24
Peak memory 145592 kb
Host smart-aad55bf4-85d1-47ae-a88a-9e2b69ea0c26
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=923011165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.923011165
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2270996660
Short name T14
Test name
Test status
Simulation time 30887100 ps
CPU time 0.39 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:13 PM PDT 24
Peak memory 145336 kb
Host smart-85a19fc5-cbf4-442f-a4dc-ec4c7affeb1c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2270996660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2270996660
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1025740750
Short name T46
Test name
Test status
Simulation time 10629825 ps
CPU time 0.41 seconds
Started Jun 23 04:23:08 PM PDT 24
Finished Jun 23 04:23:09 PM PDT 24
Peak memory 145444 kb
Host smart-bc6af970-14b3-4824-add4-39cd4b798b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025740750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1025740750
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.828245047
Short name T4
Test name
Test status
Simulation time 30014147 ps
CPU time 0.4 seconds
Started Jun 23 05:37:15 PM PDT 24
Finished Jun 23 05:37:16 PM PDT 24
Peak memory 145348 kb
Host smart-abeafbc8-b2a6-4eb3-a360-fb1a4033a5b1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=828245047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.828245047
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3953273184
Short name T11
Test name
Test status
Simulation time 10609867 ps
CPU time 0.39 seconds
Started Jun 23 04:23:07 PM PDT 24
Finished Jun 23 04:23:08 PM PDT 24
Peak memory 145620 kb
Host smart-d6c443de-c39b-4460-9446-61476ccb0643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953273184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3953273184
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.390616281
Short name T9
Test name
Test status
Simulation time 11108692 ps
CPU time 0.41 seconds
Started Jun 23 04:22:41 PM PDT 24
Finished Jun 23 04:22:43 PM PDT 24
Peak memory 145172 kb
Host smart-6545cdba-a3ce-49ee-ac3f-f3812b8b0287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390616281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.390616281
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.233193161
Short name T17
Test name
Test status
Simulation time 11560293 ps
CPU time 0.41 seconds
Started Jun 23 04:19:00 PM PDT 24
Finished Jun 23 04:19:01 PM PDT 24
Peak memory 145884 kb
Host smart-4ea20200-ddbd-4659-ad8c-998a10b0ecd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233193161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.233193161
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1660248181
Short name T22
Test name
Test status
Simulation time 10872984 ps
CPU time 0.44 seconds
Started Jun 23 04:22:54 PM PDT 24
Finished Jun 23 04:22:56 PM PDT 24
Peak memory 145184 kb
Host smart-582073de-c0c9-416e-8206-a58c853dd7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660248181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1660248181
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1210661071
Short name T21
Test name
Test status
Simulation time 10932483 ps
CPU time 0.39 seconds
Started Jun 23 04:23:30 PM PDT 24
Finished Jun 23 04:23:31 PM PDT 24
Peak memory 144956 kb
Host smart-f1cc0965-bdbe-4888-83b9-13356ce4c86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210661071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1210661071
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.865029051
Short name T2
Test name
Test status
Simulation time 11137151 ps
CPU time 0.41 seconds
Started Jun 23 04:23:30 PM PDT 24
Finished Jun 23 04:23:31 PM PDT 24
Peak memory 145148 kb
Host smart-e8dd81c8-944f-49df-8587-58c7baeca01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865029051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.865029051
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.4074821407
Short name T3
Test name
Test status
Simulation time 12316766 ps
CPU time 0.41 seconds
Started Jun 23 04:22:53 PM PDT 24
Finished Jun 23 04:22:54 PM PDT 24
Peak memory 145244 kb
Host smart-6e785f83-5518-4460-9bd9-bbd24e21766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074821407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.4074821407
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3668564616
Short name T1
Test name
Test status
Simulation time 11326147 ps
CPU time 0.47 seconds
Started Jun 23 04:24:30 PM PDT 24
Finished Jun 23 04:24:32 PM PDT 24
Peak memory 145248 kb
Host smart-b1b061d1-5792-4b4d-840f-4139f0595f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668564616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3668564616
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1960340471
Short name T45
Test name
Test status
Simulation time 11398811 ps
CPU time 0.38 seconds
Started Jun 23 04:23:09 PM PDT 24
Finished Jun 23 04:23:09 PM PDT 24
Peak memory 145444 kb
Host smart-af4ad787-1a63-485d-9485-00da6f66f8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960340471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1960340471
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3746880981
Short name T19
Test name
Test status
Simulation time 10915706 ps
CPU time 0.41 seconds
Started Jun 23 04:19:39 PM PDT 24
Finished Jun 23 04:19:40 PM PDT 24
Peak memory 145532 kb
Host smart-797fce58-6d82-4a25-8b53-64c2f2627f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746880981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3746880981
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2962528382
Short name T18
Test name
Test status
Simulation time 10150633 ps
CPU time 0.4 seconds
Started Jun 23 04:20:31 PM PDT 24
Finished Jun 23 04:20:32 PM PDT 24
Peak memory 145484 kb
Host smart-a1cceddc-04cd-45e1-9cbe-ab104298afff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962528382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2962528382
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1070063862
Short name T23
Test name
Test status
Simulation time 12595767 ps
CPU time 0.4 seconds
Started Jun 23 04:20:30 PM PDT 24
Finished Jun 23 04:20:30 PM PDT 24
Peak memory 145884 kb
Host smart-6a79f487-d944-4fa2-b0f7-d6468505b280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070063862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1070063862
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2408709720
Short name T13
Test name
Test status
Simulation time 12417469 ps
CPU time 0.41 seconds
Started Jun 23 04:20:29 PM PDT 24
Finished Jun 23 04:20:29 PM PDT 24
Peak memory 145488 kb
Host smart-dfba366f-5876-4267-80a6-11a09830e886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408709720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2408709720
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.883671094
Short name T24
Test name
Test status
Simulation time 11430091 ps
CPU time 0.38 seconds
Started Jun 23 04:21:42 PM PDT 24
Finished Jun 23 04:21:43 PM PDT 24
Peak memory 145852 kb
Host smart-e06e4f3e-7555-4f67-86da-48724d9240cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883671094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.883671094
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3716922291
Short name T20
Test name
Test status
Simulation time 11177028 ps
CPU time 0.4 seconds
Started Jun 23 04:22:53 PM PDT 24
Finished Jun 23 04:22:54 PM PDT 24
Peak memory 145168 kb
Host smart-b09486dc-efd6-4af8-958f-7561d4fd2535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716922291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3716922291
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1925326016
Short name T12
Test name
Test status
Simulation time 11764409 ps
CPU time 0.39 seconds
Started Jun 23 04:21:41 PM PDT 24
Finished Jun 23 04:21:41 PM PDT 24
Peak memory 145608 kb
Host smart-03511861-2dae-4b2f-9d7d-56918953ce62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925326016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1925326016
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1540253615
Short name T6
Test name
Test status
Simulation time 11512463 ps
CPU time 0.42 seconds
Started Jun 23 04:22:53 PM PDT 24
Finished Jun 23 04:22:54 PM PDT 24
Peak memory 144424 kb
Host smart-3fb6f102-0a69-4bf8-a93c-59297e60c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540253615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1540253615
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2872722303
Short name T39
Test name
Test status
Simulation time 31144775 ps
CPU time 0.39 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:16 PM PDT 24
Peak memory 145348 kb
Host smart-16ea73d5-a314-435c-9ced-716175464ea1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2872722303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2872722303
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3264505744
Short name T43
Test name
Test status
Simulation time 30168591 ps
CPU time 0.45 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:15 PM PDT 24
Peak memory 145292 kb
Host smart-b4bbed81-84c7-4c13-836b-9aa4889dbabf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3264505744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3264505744
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.514965917
Short name T51
Test name
Test status
Simulation time 29214675 ps
CPU time 0.4 seconds
Started Jun 23 05:37:17 PM PDT 24
Finished Jun 23 05:37:18 PM PDT 24
Peak memory 145336 kb
Host smart-604d54bf-1cd1-44df-9e52-dbc5a2675e43
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=514965917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.514965917
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1496617003
Short name T42
Test name
Test status
Simulation time 29647701 ps
CPU time 0.4 seconds
Started Jun 23 05:37:18 PM PDT 24
Finished Jun 23 05:37:19 PM PDT 24
Peak memory 145348 kb
Host smart-f179ad3c-6bc0-4c29-a604-6864f6f43667
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1496617003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1496617003
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1096926779
Short name T44
Test name
Test status
Simulation time 31875106 ps
CPU time 0.4 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:15 PM PDT 24
Peak memory 145348 kb
Host smart-de15e93d-d50f-4858-8210-761bc8008dc3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1096926779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1096926779
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3421955582
Short name T16
Test name
Test status
Simulation time 28426383 ps
CPU time 0.41 seconds
Started Jun 23 05:37:17 PM PDT 24
Finished Jun 23 05:37:18 PM PDT 24
Peak memory 145336 kb
Host smart-b7b09cea-779a-4c01-a7cb-6a202238262a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3421955582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3421955582
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3614778631
Short name T48
Test name
Test status
Simulation time 30485877 ps
CPU time 0.41 seconds
Started Jun 23 05:37:17 PM PDT 24
Finished Jun 23 05:37:18 PM PDT 24
Peak memory 145304 kb
Host smart-8a022d51-29c1-453e-9446-b43212bb5b17
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3614778631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3614778631
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.670363762
Short name T49
Test name
Test status
Simulation time 29183849 ps
CPU time 0.39 seconds
Started Jun 23 05:37:20 PM PDT 24
Finished Jun 23 05:37:21 PM PDT 24
Peak memory 145336 kb
Host smart-e3ee3785-6776-4c2b-93dc-bf9b4afdd085
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=670363762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.670363762
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1053925437
Short name T54
Test name
Test status
Simulation time 29391385 ps
CPU time 0.46 seconds
Started Jun 23 05:37:19 PM PDT 24
Finished Jun 23 05:37:21 PM PDT 24
Peak memory 145348 kb
Host smart-ec444b09-8a82-41b9-991b-ebf8f7382922
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1053925437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1053925437
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1858077756
Short name T40
Test name
Test status
Simulation time 27971747 ps
CPU time 0.4 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:14 PM PDT 24
Peak memory 145336 kb
Host smart-838501c6-c092-4c94-944a-c3135d4a3e28
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1858077756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1858077756
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3578333595
Short name T41
Test name
Test status
Simulation time 29802655 ps
CPU time 0.41 seconds
Started Jun 23 05:37:17 PM PDT 24
Finished Jun 23 05:37:18 PM PDT 24
Peak memory 145336 kb
Host smart-ebc33283-776d-4575-9a18-42381633639a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3578333595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3578333595
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4027405050
Short name T15
Test name
Test status
Simulation time 28298249 ps
CPU time 0.39 seconds
Started Jun 23 05:37:12 PM PDT 24
Finished Jun 23 05:37:13 PM PDT 24
Peak memory 145288 kb
Host smart-2a93fdbd-0880-4d66-bda8-4834c8608647
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4027405050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.4027405050
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1061350802
Short name T50
Test name
Test status
Simulation time 31735036 ps
CPU time 0.39 seconds
Started Jun 23 05:37:19 PM PDT 24
Finished Jun 23 05:37:20 PM PDT 24
Peak memory 145348 kb
Host smart-8305e22b-8e0c-43e3-b8ff-1fc3afcfe10a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1061350802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1061350802
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4196303085
Short name T53
Test name
Test status
Simulation time 30356736 ps
CPU time 0.4 seconds
Started Jun 23 05:37:20 PM PDT 24
Finished Jun 23 05:37:21 PM PDT 24
Peak memory 145248 kb
Host smart-f18ba1a3-7d0d-4e95-86bf-959c8b702023
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4196303085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.4196303085
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1910361974
Short name T47
Test name
Test status
Simulation time 30891730 ps
CPU time 0.44 seconds
Started Jun 23 05:37:18 PM PDT 24
Finished Jun 23 05:37:19 PM PDT 24
Peak memory 145308 kb
Host smart-b208db16-f17e-4279-802a-6c2f8621d528
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1910361974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1910361974
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.640988946
Short name T25
Test name
Test status
Simulation time 30500841 ps
CPU time 0.4 seconds
Started Jun 23 05:37:16 PM PDT 24
Finished Jun 23 05:37:17 PM PDT 24
Peak memory 145332 kb
Host smart-20c37b56-6f95-4f30-baf9-7f2d56d13b16
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=640988946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.640988946
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2980344296
Short name T52
Test name
Test status
Simulation time 31359911 ps
CPU time 0.42 seconds
Started Jun 23 05:37:15 PM PDT 24
Finished Jun 23 05:37:16 PM PDT 24
Peak memory 145392 kb
Host smart-52758bf3-be6d-4604-805c-55a79450dd55
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2980344296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2980344296
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2200421392
Short name T27
Test name
Test status
Simulation time 9513590 ps
CPU time 0.39 seconds
Started Jun 23 05:45:40 PM PDT 24
Finished Jun 23 05:45:41 PM PDT 24
Peak memory 145584 kb
Host smart-226815bf-6158-4a03-adb0-5649692904b6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2200421392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2200421392
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3373761495
Short name T36
Test name
Test status
Simulation time 10087410 ps
CPU time 0.38 seconds
Started Jun 23 05:45:38 PM PDT 24
Finished Jun 23 05:45:38 PM PDT 24
Peak memory 145580 kb
Host smart-5da5ce57-4150-44f1-925e-bcdf196fd7d6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3373761495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3373761495
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2716535262
Short name T28
Test name
Test status
Simulation time 9964331 ps
CPU time 0.37 seconds
Started Jun 23 05:45:42 PM PDT 24
Finished Jun 23 05:45:43 PM PDT 24
Peak memory 145696 kb
Host smart-2c6e79ad-1078-4618-a13a-a927de0ca95c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2716535262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2716535262
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.158398890
Short name T55
Test name
Test status
Simulation time 8806058 ps
CPU time 0.36 seconds
Started Jun 23 05:45:42 PM PDT 24
Finished Jun 23 05:45:43 PM PDT 24
Peak memory 145600 kb
Host smart-00b08146-4030-4c17-baf2-db4cc90a1fa8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=158398890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.158398890
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.583187759
Short name T8
Test name
Test status
Simulation time 8441731 ps
CPU time 0.37 seconds
Started Jun 23 05:45:42 PM PDT 24
Finished Jun 23 05:45:42 PM PDT 24
Peak memory 145596 kb
Host smart-38b642bf-eb84-4d68-b0bc-1c4d36b14997
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=583187759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.583187759
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.469894356
Short name T31
Test name
Test status
Simulation time 8633698 ps
CPU time 0.38 seconds
Started Jun 23 05:45:42 PM PDT 24
Finished Jun 23 05:45:43 PM PDT 24
Peak memory 145592 kb
Host smart-0896a506-5537-4b0b-a281-b93ef1408b92
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=469894356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.469894356
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2243116742
Short name T56
Test name
Test status
Simulation time 8605058 ps
CPU time 0.38 seconds
Started Jun 23 05:45:48 PM PDT 24
Finished Jun 23 05:45:49 PM PDT 24
Peak memory 145584 kb
Host smart-02096d9d-1e87-4ef8-9e02-6c8ae2a8ebc9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2243116742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2243116742
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3143679399
Short name T38
Test name
Test status
Simulation time 9522548 ps
CPU time 0.38 seconds
Started Jun 23 05:45:46 PM PDT 24
Finished Jun 23 05:45:46 PM PDT 24
Peak memory 145676 kb
Host smart-5549dec4-50b7-4e8b-8923-03fede18dbfc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3143679399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3143679399
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3189296176
Short name T58
Test name
Test status
Simulation time 8920406 ps
CPU time 0.39 seconds
Started Jun 23 05:45:47 PM PDT 24
Finished Jun 23 05:45:48 PM PDT 24
Peak memory 145552 kb
Host smart-6c782166-5d00-44f2-98b3-600761f732e1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3189296176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3189296176
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3729695427
Short name T30
Test name
Test status
Simulation time 10202324 ps
CPU time 0.38 seconds
Started Jun 23 05:45:47 PM PDT 24
Finished Jun 23 05:45:48 PM PDT 24
Peak memory 145600 kb
Host smart-a23faed1-ac5d-4666-add4-835e7f9498b5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3729695427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3729695427
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2185462714
Short name T59
Test name
Test status
Simulation time 8865333 ps
CPU time 0.37 seconds
Started Jun 23 05:45:46 PM PDT 24
Finished Jun 23 05:45:47 PM PDT 24
Peak memory 145584 kb
Host smart-36efcaf7-f918-4d84-a27b-3814008aa31c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2185462714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2185462714
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2208026214
Short name T57
Test name
Test status
Simulation time 8951565 ps
CPU time 0.38 seconds
Started Jun 23 05:45:46 PM PDT 24
Finished Jun 23 05:45:47 PM PDT 24
Peak memory 145580 kb
Host smart-79dded72-1fc4-404a-9b5a-3310c523cac6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2208026214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2208026214
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.708489808
Short name T32
Test name
Test status
Simulation time 9590973 ps
CPU time 0.38 seconds
Started Jun 23 05:45:43 PM PDT 24
Finished Jun 23 05:45:44 PM PDT 24
Peak memory 145588 kb
Host smart-0eeffd3b-b7cd-4d6d-afd2-c5b625eb73c7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=708489808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.708489808
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2590283388
Short name T29
Test name
Test status
Simulation time 8674512 ps
CPU time 0.37 seconds
Started Jun 23 05:45:43 PM PDT 24
Finished Jun 23 05:45:44 PM PDT 24
Peak memory 145580 kb
Host smart-4c309364-5db8-439e-ae6c-9984d94563fe
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2590283388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2590283388
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1397487299
Short name T34
Test name
Test status
Simulation time 8907542 ps
CPU time 0.39 seconds
Started Jun 23 05:45:43 PM PDT 24
Finished Jun 23 05:45:43 PM PDT 24
Peak memory 145596 kb
Host smart-768c40c6-4747-45d9-8a6b-166311568dbe
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1397487299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1397487299
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1506330586
Short name T37
Test name
Test status
Simulation time 8664115 ps
CPU time 0.39 seconds
Started Jun 23 05:45:43 PM PDT 24
Finished Jun 23 05:45:43 PM PDT 24
Peak memory 145552 kb
Host smart-a75aab7f-c2eb-483a-82de-2b1f497a9341
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1506330586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1506330586
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.6276982
Short name T26
Test name
Test status
Simulation time 10202126 ps
CPU time 0.37 seconds
Started Jun 23 05:45:40 PM PDT 24
Finished Jun 23 05:45:41 PM PDT 24
Peak memory 145596 kb
Host smart-0514024d-30e3-417a-863b-9f5d83bb8aef
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=6276982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.6276982
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1224419166
Short name T33
Test name
Test status
Simulation time 9830576 ps
CPU time 0.38 seconds
Started Jun 23 05:45:41 PM PDT 24
Finished Jun 23 05:45:42 PM PDT 24
Peak memory 145600 kb
Host smart-7414fd75-43e9-43cf-a6c7-77d79f627be8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1224419166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1224419166
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.658064061
Short name T35
Test name
Test status
Simulation time 10494844 ps
CPU time 0.4 seconds
Started Jun 23 05:45:42 PM PDT 24
Finished Jun 23 05:45:43 PM PDT 24
Peak memory 145560 kb
Host smart-dcb1f231-a199-4c4c-92bc-88e5dafe998a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=658064061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.658064061
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3423608154
Short name T60
Test name
Test status
Simulation time 28600366 ps
CPU time 0.4 seconds
Started Jun 23 05:48:59 PM PDT 24
Finished Jun 23 05:49:00 PM PDT 24
Peak memory 145524 kb
Host smart-710aa799-73f2-4307-87b7-5ef5904b3041
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3423608154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3423608154
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3573237990
Short name T63
Test name
Test status
Simulation time 28380052 ps
CPU time 0.4 seconds
Started Jun 23 05:49:07 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 145592 kb
Host smart-54b52a27-bda8-4ae9-b8ca-e85934281000
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3573237990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3573237990
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4257625615
Short name T62
Test name
Test status
Simulation time 28270050 ps
CPU time 0.45 seconds
Started Jun 23 05:49:02 PM PDT 24
Finished Jun 23 05:49:03 PM PDT 24
Peak memory 145600 kb
Host smart-ef8dcc4b-6b4f-4494-b65f-89652aa97273
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4257625615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.4257625615
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1872181415
Short name T5
Test name
Test status
Simulation time 27848451 ps
CPU time 0.42 seconds
Started Jun 23 05:49:02 PM PDT 24
Finished Jun 23 05:49:03 PM PDT 24
Peak memory 145600 kb
Host smart-3cecc6a9-72ba-4ba5-b210-ae1c2ed539f5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1872181415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1872181415
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2293394864
Short name T68
Test name
Test status
Simulation time 28073370 ps
CPU time 0.41 seconds
Started Jun 23 05:49:02 PM PDT 24
Finished Jun 23 05:49:02 PM PDT 24
Peak memory 145596 kb
Host smart-cc5c6bc3-0ecc-47c2-aca9-e568b22c3787
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2293394864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2293394864
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1176339781
Short name T76
Test name
Test status
Simulation time 28885588 ps
CPU time 0.4 seconds
Started Jun 23 05:49:06 PM PDT 24
Finished Jun 23 05:49:07 PM PDT 24
Peak memory 145716 kb
Host smart-fb7df6b0-fa5b-43d1-b820-e780d62f18c9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1176339781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1176339781
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.636499076
Short name T78
Test name
Test status
Simulation time 26588465 ps
CPU time 0.4 seconds
Started Jun 23 05:49:01 PM PDT 24
Finished Jun 23 05:49:02 PM PDT 24
Peak memory 145512 kb
Host smart-92b58319-52ff-450e-9472-d90e09ddfb45
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=636499076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.636499076
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.707544468
Short name T61
Test name
Test status
Simulation time 28850022 ps
CPU time 0.4 seconds
Started Jun 23 05:49:01 PM PDT 24
Finished Jun 23 05:49:01 PM PDT 24
Peak memory 145588 kb
Host smart-b51015cd-405e-442a-8a7a-c0cf359d72ba
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=707544468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.707544468
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1587534252
Short name T65
Test name
Test status
Simulation time 27899175 ps
CPU time 0.4 seconds
Started Jun 23 05:48:59 PM PDT 24
Finished Jun 23 05:49:00 PM PDT 24
Peak memory 145600 kb
Host smart-e520075a-2775-4ad1-911b-3785aabb79ca
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1587534252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1587534252
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.721000116
Short name T66
Test name
Test status
Simulation time 28253646 ps
CPU time 0.41 seconds
Started Jun 23 05:49:02 PM PDT 24
Finished Jun 23 05:49:03 PM PDT 24
Peak memory 145564 kb
Host smart-52909db5-6a1c-4e0a-add6-add88835aeb4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=721000116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.721000116
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4111181632
Short name T70
Test name
Test status
Simulation time 26218339 ps
CPU time 0.41 seconds
Started Jun 23 05:49:07 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 145716 kb
Host smart-a3307124-39b6-4407-895f-4ff900f94b95
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4111181632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.4111181632
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3784847605
Short name T64
Test name
Test status
Simulation time 26708126 ps
CPU time 0.39 seconds
Started Jun 23 05:49:01 PM PDT 24
Finished Jun 23 05:49:02 PM PDT 24
Peak memory 145608 kb
Host smart-70a07d11-6b0d-4765-90b5-3b6b7d95cac2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3784847605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3784847605
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2166142641
Short name T71
Test name
Test status
Simulation time 25015604 ps
CPU time 0.38 seconds
Started Jun 23 05:49:00 PM PDT 24
Finished Jun 23 05:49:01 PM PDT 24
Peak memory 145588 kb
Host smart-6f355d23-2415-43b4-8d00-86ff36ff2c50
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2166142641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2166142641
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1203422417
Short name T77
Test name
Test status
Simulation time 26525012 ps
CPU time 0.39 seconds
Started Jun 23 05:49:04 PM PDT 24
Finished Jun 23 05:49:05 PM PDT 24
Peak memory 145520 kb
Host smart-6e9c6bc6-156b-4903-a1e1-48a708a801df
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1203422417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1203422417
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1519189191
Short name T69
Test name
Test status
Simulation time 27679672 ps
CPU time 0.4 seconds
Started Jun 23 05:49:00 PM PDT 24
Finished Jun 23 05:49:01 PM PDT 24
Peak memory 145556 kb
Host smart-46517700-87df-4a17-89b5-41fc79e7af45
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1519189191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1519189191
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2315294419
Short name T72
Test name
Test status
Simulation time 27258577 ps
CPU time 0.39 seconds
Started Jun 23 05:49:07 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 145592 kb
Host smart-c149e54a-da2b-48d1-8c0e-efb174c89beb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2315294419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2315294419
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.387014020
Short name T67
Test name
Test status
Simulation time 26821020 ps
CPU time 0.4 seconds
Started Jun 23 05:49:00 PM PDT 24
Finished Jun 23 05:49:01 PM PDT 24
Peak memory 145592 kb
Host smart-787e2fd6-232b-410f-98cc-8c59c2ed4e45
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=387014020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.387014020
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3608093266
Short name T74
Test name
Test status
Simulation time 27810694 ps
CPU time 0.4 seconds
Started Jun 23 05:49:01 PM PDT 24
Finished Jun 23 05:49:02 PM PDT 24
Peak memory 145588 kb
Host smart-db5e30c9-e44f-4035-9217-2012c1d0d572
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3608093266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3608093266
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1343933362
Short name T73
Test name
Test status
Simulation time 29260241 ps
CPU time 0.38 seconds
Started Jun 23 05:48:58 PM PDT 24
Finished Jun 23 05:48:59 PM PDT 24
Peak memory 145604 kb
Host smart-199b08e1-fc0d-4b9a-8d60-f7815bc74e0d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1343933362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1343933362
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3453905654
Short name T75
Test name
Test status
Simulation time 27029936 ps
CPU time 0.42 seconds
Started Jun 23 05:49:01 PM PDT 24
Finished Jun 23 05:49:02 PM PDT 24
Peak memory 145576 kb
Host smart-d4efb0cb-f467-4443-b786-a5ec5436ff7c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3453905654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3453905654
Directory /workspace/9.prim_sync_fatal_alert/latest
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