Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.88 88.88 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/8.prim_async_alert.747905893
92.01 3.13 100.00 0.00 93.75 0.00 100.00 0.00 85.71 7.14 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/11.prim_sync_alert.2211361061
93.90 1.90 100.00 0.00 95.83 2.08 100.00 0.00 85.71 0.00 95.83 0.00 86.05 9.30 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1872045892
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/13.prim_async_alert.3094658801
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/8.prim_sync_alert.2852764756
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2121071326

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.151050708
/workspace/coverage/default/1.prim_async_alert.860192092
/workspace/coverage/default/10.prim_async_alert.2578822777
/workspace/coverage/default/11.prim_async_alert.2407487977
/workspace/coverage/default/12.prim_async_alert.774849178
/workspace/coverage/default/14.prim_async_alert.1217657377
/workspace/coverage/default/15.prim_async_alert.688511612
/workspace/coverage/default/16.prim_async_alert.3394931140
/workspace/coverage/default/17.prim_async_alert.2685854269
/workspace/coverage/default/18.prim_async_alert.648681742
/workspace/coverage/default/19.prim_async_alert.1467376088
/workspace/coverage/default/2.prim_async_alert.2693253731
/workspace/coverage/default/3.prim_async_alert.1772105954
/workspace/coverage/default/4.prim_async_alert.3015131041
/workspace/coverage/default/5.prim_async_alert.146711711
/workspace/coverage/default/6.prim_async_alert.3429961932
/workspace/coverage/default/7.prim_async_alert.3279208063
/workspace/coverage/default/9.prim_async_alert.4219390303
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.66405315
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.584018398
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2685187850
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1640398973
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2490347855
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1652720055
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2377623430
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1939509651
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3338020333
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1011677700
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.71439868
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2246850651
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.349712987
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2539581512
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1536962537
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.287479211
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.245617794
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1418739128
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3545821508
/workspace/coverage/sync_alert/0.prim_sync_alert.4216766195
/workspace/coverage/sync_alert/1.prim_sync_alert.3543444313
/workspace/coverage/sync_alert/10.prim_sync_alert.4063867658
/workspace/coverage/sync_alert/12.prim_sync_alert.1819528673
/workspace/coverage/sync_alert/13.prim_sync_alert.3201956151
/workspace/coverage/sync_alert/14.prim_sync_alert.3661898745
/workspace/coverage/sync_alert/15.prim_sync_alert.4036789613
/workspace/coverage/sync_alert/16.prim_sync_alert.3827020778
/workspace/coverage/sync_alert/17.prim_sync_alert.3389085137
/workspace/coverage/sync_alert/18.prim_sync_alert.2282919910
/workspace/coverage/sync_alert/19.prim_sync_alert.3739917845
/workspace/coverage/sync_alert/2.prim_sync_alert.977014479
/workspace/coverage/sync_alert/3.prim_sync_alert.3388835572
/workspace/coverage/sync_alert/4.prim_sync_alert.27410788
/workspace/coverage/sync_alert/5.prim_sync_alert.1814443251
/workspace/coverage/sync_alert/6.prim_sync_alert.4186337674
/workspace/coverage/sync_alert/7.prim_sync_alert.2450574580
/workspace/coverage/sync_alert/9.prim_sync_alert.3369600411
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3184848521
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2659320551
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2913611275
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3145805459
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3726953229
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3545126451
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3667957509
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4007480370
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1942466283
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3900995785
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2116715517
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2223836294
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.435855181
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2479353214
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3067164927
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2597487693
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4137473037
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.423148314
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2767162892



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.prim_async_alert.151050708 Jun 24 04:16:18 PM PDT 24 Jun 24 04:16:19 PM PDT 24 11341042 ps
T2 /workspace/coverage/default/19.prim_async_alert.1467376088 Jun 24 04:17:55 PM PDT 24 Jun 24 04:17:56 PM PDT 24 10974920 ps
T3 /workspace/coverage/default/3.prim_async_alert.1772105954 Jun 24 04:21:48 PM PDT 24 Jun 24 04:21:49 PM PDT 24 11027022 ps
T8 /workspace/coverage/default/8.prim_async_alert.747905893 Jun 24 04:22:18 PM PDT 24 Jun 24 04:22:19 PM PDT 24 12104473 ps
T17 /workspace/coverage/default/15.prim_async_alert.688511612 Jun 24 04:21:49 PM PDT 24 Jun 24 04:21:51 PM PDT 24 12013632 ps
T18 /workspace/coverage/default/6.prim_async_alert.3429961932 Jun 24 04:21:23 PM PDT 24 Jun 24 04:21:24 PM PDT 24 11519746 ps
T11 /workspace/coverage/default/16.prim_async_alert.3394931140 Jun 24 04:18:09 PM PDT 24 Jun 24 04:18:10 PM PDT 24 11764021 ps
T15 /workspace/coverage/default/14.prim_async_alert.1217657377 Jun 24 04:16:26 PM PDT 24 Jun 24 04:16:27 PM PDT 24 11125878 ps
T19 /workspace/coverage/default/11.prim_async_alert.2407487977 Jun 24 04:22:00 PM PDT 24 Jun 24 04:22:01 PM PDT 24 10765171 ps
T12 /workspace/coverage/default/9.prim_async_alert.4219390303 Jun 24 04:22:20 PM PDT 24 Jun 24 04:22:20 PM PDT 24 12544878 ps
T20 /workspace/coverage/default/12.prim_async_alert.774849178 Jun 24 04:16:32 PM PDT 24 Jun 24 04:16:33 PM PDT 24 10845440 ps
T16 /workspace/coverage/default/17.prim_async_alert.2685854269 Jun 24 04:16:52 PM PDT 24 Jun 24 04:16:53 PM PDT 24 10911203 ps
T13 /workspace/coverage/default/2.prim_async_alert.2693253731 Jun 24 04:21:37 PM PDT 24 Jun 24 04:21:38 PM PDT 24 11860197 ps
T6 /workspace/coverage/default/13.prim_async_alert.3094658801 Jun 24 04:22:11 PM PDT 24 Jun 24 04:22:12 PM PDT 24 11135467 ps
T47 /workspace/coverage/default/10.prim_async_alert.2578822777 Jun 24 04:19:19 PM PDT 24 Jun 24 04:19:20 PM PDT 24 12669492 ps
T21 /workspace/coverage/default/5.prim_async_alert.146711711 Jun 24 04:16:29 PM PDT 24 Jun 24 04:16:29 PM PDT 24 11472786 ps
T22 /workspace/coverage/default/4.prim_async_alert.3015131041 Jun 24 04:22:09 PM PDT 24 Jun 24 04:22:10 PM PDT 24 12206063 ps
T14 /workspace/coverage/default/7.prim_async_alert.3279208063 Jun 24 04:16:20 PM PDT 24 Jun 24 04:16:22 PM PDT 24 12056305 ps
T23 /workspace/coverage/default/1.prim_async_alert.860192092 Jun 24 04:18:01 PM PDT 24 Jun 24 04:18:02 PM PDT 24 10920763 ps
T48 /workspace/coverage/default/18.prim_async_alert.648681742 Jun 24 04:22:05 PM PDT 24 Jun 24 04:22:05 PM PDT 24 10986111 ps
T24 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.66405315 Jun 24 05:05:02 PM PDT 24 Jun 24 05:05:03 PM PDT 24 27766911 ps
T25 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2377623430 Jun 24 05:05:04 PM PDT 24 Jun 24 05:05:05 PM PDT 24 30327766 ps
T7 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1872045892 Jun 24 05:05:05 PM PDT 24 Jun 24 05:05:06 PM PDT 24 28922314 ps
T40 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3545821508 Jun 24 05:05:04 PM PDT 24 Jun 24 05:05:06 PM PDT 24 30303391 ps
T41 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1536962537 Jun 24 05:05:05 PM PDT 24 Jun 24 05:05:07 PM PDT 24 29830070 ps
T42 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1652720055 Jun 24 05:05:04 PM PDT 24 Jun 24 05:05:06 PM PDT 24 29430639 ps
T43 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.71439868 Jun 24 05:05:05 PM PDT 24 Jun 24 05:05:07 PM PDT 24 28875657 ps
T44 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.287479211 Jun 24 05:05:04 PM PDT 24 Jun 24 05:05:06 PM PDT 24 29935328 ps
T45 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.584018398 Jun 24 05:05:03 PM PDT 24 Jun 24 05:05:04 PM PDT 24 30255379 ps
T46 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.245617794 Jun 24 05:05:03 PM PDT 24 Jun 24 05:05:05 PM PDT 24 29924112 ps
T49 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2685187850 Jun 24 05:05:04 PM PDT 24 Jun 24 05:05:06 PM PDT 24 28634536 ps
T50 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.349712987 Jun 24 05:05:03 PM PDT 24 Jun 24 05:05:05 PM PDT 24 29280108 ps
T51 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1640398973 Jun 24 05:05:03 PM PDT 24 Jun 24 05:05:05 PM PDT 24 28900961 ps
T52 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2246850651 Jun 24 05:05:02 PM PDT 24 Jun 24 05:05:04 PM PDT 24 29692833 ps
T53 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2539581512 Jun 24 05:05:04 PM PDT 24 Jun 24 05:05:06 PM PDT 24 32382449 ps
T54 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1939509651 Jun 24 05:05:03 PM PDT 24 Jun 24 05:05:05 PM PDT 24 29478901 ps
T39 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1418739128 Jun 24 05:05:03 PM PDT 24 Jun 24 05:05:05 PM PDT 24 29853808 ps
T55 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3338020333 Jun 24 05:05:03 PM PDT 24 Jun 24 05:05:05 PM PDT 24 30710564 ps
T56 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2490347855 Jun 24 05:05:02 PM PDT 24 Jun 24 05:05:04 PM PDT 24 30659087 ps
T57 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1011677700 Jun 24 05:05:03 PM PDT 24 Jun 24 05:05:05 PM PDT 24 30307939 ps
T26 /workspace/coverage/sync_alert/3.prim_sync_alert.3388835572 Jun 24 04:21:31 PM PDT 24 Jun 24 04:21:32 PM PDT 24 8974146 ps
T9 /workspace/coverage/sync_alert/8.prim_sync_alert.2852764756 Jun 24 04:22:04 PM PDT 24 Jun 24 04:22:05 PM PDT 24 9488460 ps
T27 /workspace/coverage/sync_alert/13.prim_sync_alert.3201956151 Jun 24 04:21:21 PM PDT 24 Jun 24 04:21:22 PM PDT 24 9416937 ps
T28 /workspace/coverage/sync_alert/15.prim_sync_alert.4036789613 Jun 24 04:22:11 PM PDT 24 Jun 24 04:22:12 PM PDT 24 10101578 ps
T34 /workspace/coverage/sync_alert/12.prim_sync_alert.1819528673 Jun 24 04:17:22 PM PDT 24 Jun 24 04:17:23 PM PDT 24 9402021 ps
T29 /workspace/coverage/sync_alert/2.prim_sync_alert.977014479 Jun 24 04:16:43 PM PDT 24 Jun 24 04:16:44 PM PDT 24 8163939 ps
T35 /workspace/coverage/sync_alert/9.prim_sync_alert.3369600411 Jun 24 04:17:22 PM PDT 24 Jun 24 04:17:23 PM PDT 24 8787044 ps
T36 /workspace/coverage/sync_alert/11.prim_sync_alert.2211361061 Jun 24 04:16:27 PM PDT 24 Jun 24 04:16:28 PM PDT 24 9294197 ps
T37 /workspace/coverage/sync_alert/19.prim_sync_alert.3739917845 Jun 24 04:18:16 PM PDT 24 Jun 24 04:18:17 PM PDT 24 8873067 ps
T38 /workspace/coverage/sync_alert/0.prim_sync_alert.4216766195 Jun 24 04:22:12 PM PDT 24 Jun 24 04:22:13 PM PDT 24 9145807 ps
T58 /workspace/coverage/sync_alert/10.prim_sync_alert.4063867658 Jun 24 04:19:03 PM PDT 24 Jun 24 04:19:03 PM PDT 24 9044300 ps
T59 /workspace/coverage/sync_alert/18.prim_sync_alert.2282919910 Jun 24 04:22:11 PM PDT 24 Jun 24 04:22:12 PM PDT 24 10121741 ps
T60 /workspace/coverage/sync_alert/17.prim_sync_alert.3389085137 Jun 24 04:22:10 PM PDT 24 Jun 24 04:22:12 PM PDT 24 9159898 ps
T61 /workspace/coverage/sync_alert/1.prim_sync_alert.3543444313 Jun 24 04:21:32 PM PDT 24 Jun 24 04:21:33 PM PDT 24 8932020 ps
T62 /workspace/coverage/sync_alert/16.prim_sync_alert.3827020778 Jun 24 04:22:11 PM PDT 24 Jun 24 04:22:12 PM PDT 24 9167032 ps
T30 /workspace/coverage/sync_alert/4.prim_sync_alert.27410788 Jun 24 04:22:16 PM PDT 24 Jun 24 04:22:17 PM PDT 24 8947940 ps
T31 /workspace/coverage/sync_alert/5.prim_sync_alert.1814443251 Jun 24 04:16:43 PM PDT 24 Jun 24 04:16:44 PM PDT 24 9351553 ps
T63 /workspace/coverage/sync_alert/6.prim_sync_alert.4186337674 Jun 24 04:17:23 PM PDT 24 Jun 24 04:17:23 PM PDT 24 9291734 ps
T32 /workspace/coverage/sync_alert/14.prim_sync_alert.3661898745 Jun 24 04:18:38 PM PDT 24 Jun 24 04:18:39 PM PDT 24 9778973 ps
T64 /workspace/coverage/sync_alert/7.prim_sync_alert.2450574580 Jun 24 04:16:48 PM PDT 24 Jun 24 04:16:49 PM PDT 24 9012676 ps
T33 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3667957509 Jun 24 04:21:23 PM PDT 24 Jun 24 04:21:24 PM PDT 24 26431670 ps
T65 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2116715517 Jun 24 04:21:47 PM PDT 24 Jun 24 04:21:48 PM PDT 24 25230200 ps
T66 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1942466283 Jun 24 04:21:23 PM PDT 24 Jun 24 04:21:24 PM PDT 24 26490550 ps
T10 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2659320551 Jun 24 04:17:26 PM PDT 24 Jun 24 04:17:26 PM PDT 24 27392866 ps
T4 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2121071326 Jun 24 04:18:15 PM PDT 24 Jun 24 04:18:15 PM PDT 24 27337639 ps
T67 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2767162892 Jun 24 04:22:16 PM PDT 24 Jun 24 04:22:17 PM PDT 24 26581686 ps
T68 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4007480370 Jun 24 04:22:19 PM PDT 24 Jun 24 04:22:20 PM PDT 24 29884205 ps
T69 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3545126451 Jun 24 04:16:24 PM PDT 24 Jun 24 04:16:25 PM PDT 24 28026323 ps
T5 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2597487693 Jun 24 04:22:09 PM PDT 24 Jun 24 04:22:10 PM PDT 24 28482358 ps
T70 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3726953229 Jun 24 04:21:37 PM PDT 24 Jun 24 04:21:38 PM PDT 24 27543336 ps
T71 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4137473037 Jun 24 04:22:03 PM PDT 24 Jun 24 04:22:04 PM PDT 24 26971933 ps
T72 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3900995785 Jun 24 04:21:38 PM PDT 24 Jun 24 04:21:39 PM PDT 24 27660680 ps
T73 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2479353214 Jun 24 04:22:10 PM PDT 24 Jun 24 04:22:11 PM PDT 24 29151733 ps
T74 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.423148314 Jun 24 04:22:10 PM PDT 24 Jun 24 04:22:12 PM PDT 24 26075495 ps
T75 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3184848521 Jun 24 04:18:40 PM PDT 24 Jun 24 04:18:40 PM PDT 24 26681439 ps
T76 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3145805459 Jun 24 04:17:14 PM PDT 24 Jun 24 04:17:14 PM PDT 24 28061313 ps
T77 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2913611275 Jun 24 04:18:32 PM PDT 24 Jun 24 04:18:33 PM PDT 24 28995312 ps
T78 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2223836294 Jun 24 04:22:02 PM PDT 24 Jun 24 04:22:03 PM PDT 24 25617171 ps
T79 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3067164927 Jun 24 04:22:16 PM PDT 24 Jun 24 04:22:17 PM PDT 24 28847878 ps
T80 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.435855181 Jun 24 04:21:48 PM PDT 24 Jun 24 04:21:49 PM PDT 24 28013702 ps

Test location /workspace/coverage/default/8.prim_async_alert.747905893
Short name T8
Test name
Test status
Simulation time 12104473 ps
CPU time 0.41 seconds
Started Jun 24 04:22:18 PM PDT 24
Finished Jun 24 04:22:19 PM PDT 24
Peak memory 145172 kb
Host smart-b4f3bca8-5997-4b7c-8733-24107acdb64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747905893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.747905893
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2211361061
Short name T36
Test name
Test status
Simulation time 9294197 ps
CPU time 0.39 seconds
Started Jun 24 04:16:27 PM PDT 24
Finished Jun 24 04:16:28 PM PDT 24
Peak memory 145708 kb
Host smart-a9445fef-cfd4-4492-b6bf-c6a1c9d3f5a8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2211361061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2211361061
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1872045892
Short name T7
Test name
Test status
Simulation time 28922314 ps
CPU time 0.42 seconds
Started Jun 24 05:05:05 PM PDT 24
Finished Jun 24 05:05:06 PM PDT 24
Peak memory 145332 kb
Host smart-87ef25b7-a7d7-49ac-b095-6c65b0c35e8b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1872045892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1872045892
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3094658801
Short name T6
Test name
Test status
Simulation time 11135467 ps
CPU time 0.38 seconds
Started Jun 24 04:22:11 PM PDT 24
Finished Jun 24 04:22:12 PM PDT 24
Peak memory 145292 kb
Host smart-2e50b8e8-6cde-4324-8134-53aa70c6c314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094658801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3094658801
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2852764756
Short name T9
Test name
Test status
Simulation time 9488460 ps
CPU time 0.38 seconds
Started Jun 24 04:22:04 PM PDT 24
Finished Jun 24 04:22:05 PM PDT 24
Peak memory 145212 kb
Host smart-40c7a256-7528-4dae-abea-9853add9a164
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2852764756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2852764756
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2121071326
Short name T4
Test name
Test status
Simulation time 27337639 ps
CPU time 0.41 seconds
Started Jun 24 04:18:15 PM PDT 24
Finished Jun 24 04:18:15 PM PDT 24
Peak memory 145176 kb
Host smart-460b3412-51ef-471f-a01a-6b60e47c5e4e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2121071326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2121071326
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.151050708
Short name T1
Test name
Test status
Simulation time 11341042 ps
CPU time 0.5 seconds
Started Jun 24 04:16:18 PM PDT 24
Finished Jun 24 04:16:19 PM PDT 24
Peak memory 145152 kb
Host smart-37b15cff-caa3-4742-92ec-8ba357f10cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151050708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.151050708
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.860192092
Short name T23
Test name
Test status
Simulation time 10920763 ps
CPU time 0.41 seconds
Started Jun 24 04:18:01 PM PDT 24
Finished Jun 24 04:18:02 PM PDT 24
Peak memory 145900 kb
Host smart-84feb88c-8372-4a94-9285-21c85fd339cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860192092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.860192092
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2578822777
Short name T47
Test name
Test status
Simulation time 12669492 ps
CPU time 0.39 seconds
Started Jun 24 04:19:19 PM PDT 24
Finished Jun 24 04:19:20 PM PDT 24
Peak memory 145588 kb
Host smart-c90e2d67-70a1-4929-83d1-1f5e314abdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578822777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2578822777
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2407487977
Short name T19
Test name
Test status
Simulation time 10765171 ps
CPU time 0.39 seconds
Started Jun 24 04:22:00 PM PDT 24
Finished Jun 24 04:22:01 PM PDT 24
Peak memory 145884 kb
Host smart-e970787a-b90a-4141-a123-920fdae52c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407487977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2407487977
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.774849178
Short name T20
Test name
Test status
Simulation time 10845440 ps
CPU time 0.37 seconds
Started Jun 24 04:16:32 PM PDT 24
Finished Jun 24 04:16:33 PM PDT 24
Peak memory 145528 kb
Host smart-4074da6c-aee9-4a4b-80d5-ba1f490be6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774849178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.774849178
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1217657377
Short name T15
Test name
Test status
Simulation time 11125878 ps
CPU time 0.4 seconds
Started Jun 24 04:16:26 PM PDT 24
Finished Jun 24 04:16:27 PM PDT 24
Peak memory 145436 kb
Host smart-08ad3aee-1e71-470a-9f31-ef809a190291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217657377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1217657377
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.688511612
Short name T17
Test name
Test status
Simulation time 12013632 ps
CPU time 0.43 seconds
Started Jun 24 04:21:49 PM PDT 24
Finished Jun 24 04:21:51 PM PDT 24
Peak memory 145148 kb
Host smart-a1707fd2-be3c-40aa-8c75-8553e4f895bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688511612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.688511612
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3394931140
Short name T11
Test name
Test status
Simulation time 11764021 ps
CPU time 0.41 seconds
Started Jun 24 04:18:09 PM PDT 24
Finished Jun 24 04:18:10 PM PDT 24
Peak memory 145592 kb
Host smart-5f91e10f-f8c0-44cb-85d7-ded0d1b33d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394931140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3394931140
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2685854269
Short name T16
Test name
Test status
Simulation time 10911203 ps
CPU time 0.39 seconds
Started Jun 24 04:16:52 PM PDT 24
Finished Jun 24 04:16:53 PM PDT 24
Peak memory 145532 kb
Host smart-8ee09c26-724f-4661-b686-105c92a7a8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685854269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2685854269
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.648681742
Short name T48
Test name
Test status
Simulation time 10986111 ps
CPU time 0.38 seconds
Started Jun 24 04:22:05 PM PDT 24
Finished Jun 24 04:22:05 PM PDT 24
Peak memory 145808 kb
Host smart-0ab13e1b-9f43-4216-b303-923d61af727e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648681742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.648681742
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1467376088
Short name T2
Test name
Test status
Simulation time 10974920 ps
CPU time 0.41 seconds
Started Jun 24 04:17:55 PM PDT 24
Finished Jun 24 04:17:56 PM PDT 24
Peak memory 145592 kb
Host smart-57c54983-e763-48ca-8e2c-f0d27817fb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467376088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1467376088
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2693253731
Short name T13
Test name
Test status
Simulation time 11860197 ps
CPU time 0.38 seconds
Started Jun 24 04:21:37 PM PDT 24
Finished Jun 24 04:21:38 PM PDT 24
Peak memory 145524 kb
Host smart-502fdef9-000f-4b28-8cff-788f2d441a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693253731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2693253731
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1772105954
Short name T3
Test name
Test status
Simulation time 11027022 ps
CPU time 0.39 seconds
Started Jun 24 04:21:48 PM PDT 24
Finished Jun 24 04:21:49 PM PDT 24
Peak memory 144824 kb
Host smart-8c770ef5-72e5-47dc-b079-dc97972fa32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772105954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1772105954
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3015131041
Short name T22
Test name
Test status
Simulation time 12206063 ps
CPU time 0.41 seconds
Started Jun 24 04:22:09 PM PDT 24
Finished Jun 24 04:22:10 PM PDT 24
Peak memory 145696 kb
Host smart-c7135a4c-db49-421d-ab04-87ce15a9ead1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015131041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3015131041
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.146711711
Short name T21
Test name
Test status
Simulation time 11472786 ps
CPU time 0.39 seconds
Started Jun 24 04:16:29 PM PDT 24
Finished Jun 24 04:16:29 PM PDT 24
Peak memory 145508 kb
Host smart-c616c422-2d79-4df2-b16b-fc165a4ca644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146711711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.146711711
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3429961932
Short name T18
Test name
Test status
Simulation time 11519746 ps
CPU time 0.43 seconds
Started Jun 24 04:21:23 PM PDT 24
Finished Jun 24 04:21:24 PM PDT 24
Peak memory 143864 kb
Host smart-206bab99-5306-497f-99ef-16016ce69527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429961932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3429961932
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3279208063
Short name T14
Test name
Test status
Simulation time 12056305 ps
CPU time 0.46 seconds
Started Jun 24 04:16:20 PM PDT 24
Finished Jun 24 04:16:22 PM PDT 24
Peak memory 145240 kb
Host smart-49debe9c-f574-4eb8-b8e5-dca56b3a3ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279208063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3279208063
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.4219390303
Short name T12
Test name
Test status
Simulation time 12544878 ps
CPU time 0.4 seconds
Started Jun 24 04:22:20 PM PDT 24
Finished Jun 24 04:22:20 PM PDT 24
Peak memory 145436 kb
Host smart-308a1da0-a6d2-4ef4-b4f1-b4683121e20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219390303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.4219390303
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.66405315
Short name T24
Test name
Test status
Simulation time 27766911 ps
CPU time 0.41 seconds
Started Jun 24 05:05:02 PM PDT 24
Finished Jun 24 05:05:03 PM PDT 24
Peak memory 145324 kb
Host smart-236551a5-15ba-41de-bd56-6e247a73d6b9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=66405315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.66405315
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.584018398
Short name T45
Test name
Test status
Simulation time 30255379 ps
CPU time 0.41 seconds
Started Jun 24 05:05:03 PM PDT 24
Finished Jun 24 05:05:04 PM PDT 24
Peak memory 145304 kb
Host smart-85d57551-920d-4fde-b04f-1b8547d997e3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=584018398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.584018398
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2685187850
Short name T49
Test name
Test status
Simulation time 28634536 ps
CPU time 0.4 seconds
Started Jun 24 05:05:04 PM PDT 24
Finished Jun 24 05:05:06 PM PDT 24
Peak memory 145248 kb
Host smart-1aff2a09-d220-4f4a-83b6-9ef531b0a31b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2685187850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2685187850
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1640398973
Short name T51
Test name
Test status
Simulation time 28900961 ps
CPU time 0.4 seconds
Started Jun 24 05:05:03 PM PDT 24
Finished Jun 24 05:05:05 PM PDT 24
Peak memory 145336 kb
Host smart-7e3a56d2-793d-464a-a7a5-790887b69d1e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1640398973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1640398973
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2490347855
Short name T56
Test name
Test status
Simulation time 30659087 ps
CPU time 0.46 seconds
Started Jun 24 05:05:02 PM PDT 24
Finished Jun 24 05:05:04 PM PDT 24
Peak memory 145208 kb
Host smart-d228f498-f565-472f-9508-41736aefde3c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2490347855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2490347855
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1652720055
Short name T42
Test name
Test status
Simulation time 29430639 ps
CPU time 0.4 seconds
Started Jun 24 05:05:04 PM PDT 24
Finished Jun 24 05:05:06 PM PDT 24
Peak memory 145296 kb
Host smart-e4480684-7661-4055-85d0-f825d47dd6c7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1652720055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1652720055
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2377623430
Short name T25
Test name
Test status
Simulation time 30327766 ps
CPU time 0.4 seconds
Started Jun 24 05:05:04 PM PDT 24
Finished Jun 24 05:05:05 PM PDT 24
Peak memory 145336 kb
Host smart-99f1ca93-b7f7-4473-bf1f-5430a78c3850
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2377623430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2377623430
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1939509651
Short name T54
Test name
Test status
Simulation time 29478901 ps
CPU time 0.42 seconds
Started Jun 24 05:05:03 PM PDT 24
Finished Jun 24 05:05:05 PM PDT 24
Peak memory 145336 kb
Host smart-65db946e-8e42-4f56-b2ce-db88cdd4a912
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1939509651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1939509651
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3338020333
Short name T55
Test name
Test status
Simulation time 30710564 ps
CPU time 0.41 seconds
Started Jun 24 05:05:03 PM PDT 24
Finished Jun 24 05:05:05 PM PDT 24
Peak memory 145328 kb
Host smart-f6f4e2bc-8366-4ba2-ae6d-210480004842
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3338020333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3338020333
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1011677700
Short name T57
Test name
Test status
Simulation time 30307939 ps
CPU time 0.43 seconds
Started Jun 24 05:05:03 PM PDT 24
Finished Jun 24 05:05:05 PM PDT 24
Peak memory 145208 kb
Host smart-abb82a3c-2cd2-4ca9-beae-9308ec3ca327
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1011677700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1011677700
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.71439868
Short name T43
Test name
Test status
Simulation time 28875657 ps
CPU time 0.41 seconds
Started Jun 24 05:05:05 PM PDT 24
Finished Jun 24 05:05:07 PM PDT 24
Peak memory 145256 kb
Host smart-9abf0fa6-4510-47f8-b660-222b3c9e0bd0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=71439868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.71439868
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2246850651
Short name T52
Test name
Test status
Simulation time 29692833 ps
CPU time 0.41 seconds
Started Jun 24 05:05:02 PM PDT 24
Finished Jun 24 05:05:04 PM PDT 24
Peak memory 145248 kb
Host smart-c13b5d6a-2aca-41dc-b4ce-881240f6f3bc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2246850651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2246850651
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.349712987
Short name T50
Test name
Test status
Simulation time 29280108 ps
CPU time 0.41 seconds
Started Jun 24 05:05:03 PM PDT 24
Finished Jun 24 05:05:05 PM PDT 24
Peak memory 145332 kb
Host smart-1a9f292e-0e48-4010-99e2-5956917cf041
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=349712987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.349712987
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2539581512
Short name T53
Test name
Test status
Simulation time 32382449 ps
CPU time 0.41 seconds
Started Jun 24 05:05:04 PM PDT 24
Finished Jun 24 05:05:06 PM PDT 24
Peak memory 145252 kb
Host smart-b8b9e92b-f133-4e43-9720-7b16a8effd98
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2539581512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2539581512
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1536962537
Short name T41
Test name
Test status
Simulation time 29830070 ps
CPU time 0.39 seconds
Started Jun 24 05:05:05 PM PDT 24
Finished Jun 24 05:05:07 PM PDT 24
Peak memory 145248 kb
Host smart-3c7dfba8-6288-44dd-afad-f6f7152c17d7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1536962537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1536962537
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.287479211
Short name T44
Test name
Test status
Simulation time 29935328 ps
CPU time 0.43 seconds
Started Jun 24 05:05:04 PM PDT 24
Finished Jun 24 05:05:06 PM PDT 24
Peak memory 145248 kb
Host smart-4568eafc-8043-4cc3-9725-7c00d5944a45
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=287479211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.287479211
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.245617794
Short name T46
Test name
Test status
Simulation time 29924112 ps
CPU time 0.41 seconds
Started Jun 24 05:05:03 PM PDT 24
Finished Jun 24 05:05:05 PM PDT 24
Peak memory 145296 kb
Host smart-7b41f833-f8ad-413b-99b0-bda2988d62e9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=245617794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.245617794
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1418739128
Short name T39
Test name
Test status
Simulation time 29853808 ps
CPU time 0.42 seconds
Started Jun 24 05:05:03 PM PDT 24
Finished Jun 24 05:05:05 PM PDT 24
Peak memory 145332 kb
Host smart-28cfd86a-f44f-437f-b58a-67f9e7fbc554
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1418739128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1418739128
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3545821508
Short name T40
Test name
Test status
Simulation time 30303391 ps
CPU time 0.41 seconds
Started Jun 24 05:05:04 PM PDT 24
Finished Jun 24 05:05:06 PM PDT 24
Peak memory 145320 kb
Host smart-912bc7b1-bd7c-4ca4-8e37-670c61fe8995
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3545821508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3545821508
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.4216766195
Short name T38
Test name
Test status
Simulation time 9145807 ps
CPU time 0.37 seconds
Started Jun 24 04:22:12 PM PDT 24
Finished Jun 24 04:22:13 PM PDT 24
Peak memory 145228 kb
Host smart-8be8804d-5e33-4064-b4fe-ef1f21760e2b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4216766195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.4216766195
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3543444313
Short name T61
Test name
Test status
Simulation time 8932020 ps
CPU time 0.36 seconds
Started Jun 24 04:21:32 PM PDT 24
Finished Jun 24 04:21:33 PM PDT 24
Peak memory 144988 kb
Host smart-c6f142dc-2a8e-4762-924e-01ef6f980c58
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3543444313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3543444313
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.4063867658
Short name T58
Test name
Test status
Simulation time 9044300 ps
CPU time 0.38 seconds
Started Jun 24 04:19:03 PM PDT 24
Finished Jun 24 04:19:03 PM PDT 24
Peak memory 145232 kb
Host smart-5ac9cccf-917f-4649-a3cb-bee450be1d30
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4063867658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.4063867658
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.1819528673
Short name T34
Test name
Test status
Simulation time 9402021 ps
CPU time 0.41 seconds
Started Jun 24 04:17:22 PM PDT 24
Finished Jun 24 04:17:23 PM PDT 24
Peak memory 145704 kb
Host smart-c43a6f39-5a2b-468a-9c56-889dfaaba95c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1819528673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1819528673
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3201956151
Short name T27
Test name
Test status
Simulation time 9416937 ps
CPU time 0.42 seconds
Started Jun 24 04:21:21 PM PDT 24
Finished Jun 24 04:21:22 PM PDT 24
Peak memory 145832 kb
Host smart-7a0ef34d-f948-4fa2-a754-b89078a508f5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3201956151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3201956151
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3661898745
Short name T32
Test name
Test status
Simulation time 9778973 ps
CPU time 0.39 seconds
Started Jun 24 04:18:38 PM PDT 24
Finished Jun 24 04:18:39 PM PDT 24
Peak memory 145208 kb
Host smart-290d3ba5-733a-448e-b5c3-2f36c3b99c35
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3661898745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3661898745
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.4036789613
Short name T28
Test name
Test status
Simulation time 10101578 ps
CPU time 0.45 seconds
Started Jun 24 04:22:11 PM PDT 24
Finished Jun 24 04:22:12 PM PDT 24
Peak memory 144240 kb
Host smart-67127a2d-0371-4ac8-a161-a009deeb1347
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4036789613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.4036789613
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3827020778
Short name T62
Test name
Test status
Simulation time 9167032 ps
CPU time 0.41 seconds
Started Jun 24 04:22:11 PM PDT 24
Finished Jun 24 04:22:12 PM PDT 24
Peak memory 144944 kb
Host smart-231e72be-72c3-43a6-9521-d61f4f44bd4b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3827020778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3827020778
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3389085137
Short name T60
Test name
Test status
Simulation time 9159898 ps
CPU time 0.46 seconds
Started Jun 24 04:22:10 PM PDT 24
Finished Jun 24 04:22:12 PM PDT 24
Peak memory 143452 kb
Host smart-aaf6529c-217a-41bd-86d6-0498077819f5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3389085137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3389085137
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2282919910
Short name T59
Test name
Test status
Simulation time 10121741 ps
CPU time 0.38 seconds
Started Jun 24 04:22:11 PM PDT 24
Finished Jun 24 04:22:12 PM PDT 24
Peak memory 144908 kb
Host smart-fe8a3b3a-c80f-48a3-8336-bcdf97133a12
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2282919910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2282919910
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3739917845
Short name T37
Test name
Test status
Simulation time 8873067 ps
CPU time 0.39 seconds
Started Jun 24 04:18:16 PM PDT 24
Finished Jun 24 04:18:17 PM PDT 24
Peak memory 145220 kb
Host smart-a383acb9-6a0c-42aa-a2cc-158ed84ec213
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3739917845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3739917845
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.977014479
Short name T29
Test name
Test status
Simulation time 8163939 ps
CPU time 0.38 seconds
Started Jun 24 04:16:43 PM PDT 24
Finished Jun 24 04:16:44 PM PDT 24
Peak memory 145224 kb
Host smart-4bd64c99-8dd7-4531-96d7-cc03f93cf275
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=977014479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.977014479
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3388835572
Short name T26
Test name
Test status
Simulation time 8974146 ps
CPU time 0.4 seconds
Started Jun 24 04:21:31 PM PDT 24
Finished Jun 24 04:21:32 PM PDT 24
Peak memory 145836 kb
Host smart-f597ec58-5b00-4913-9544-2cd01419fbd5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3388835572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3388835572
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.27410788
Short name T30
Test name
Test status
Simulation time 8947940 ps
CPU time 0.37 seconds
Started Jun 24 04:22:16 PM PDT 24
Finished Jun 24 04:22:17 PM PDT 24
Peak memory 145048 kb
Host smart-696e3b48-1180-459f-8d37-b2880841fea4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=27410788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.27410788
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1814443251
Short name T31
Test name
Test status
Simulation time 9351553 ps
CPU time 0.43 seconds
Started Jun 24 04:16:43 PM PDT 24
Finished Jun 24 04:16:44 PM PDT 24
Peak memory 145292 kb
Host smart-4c538289-0ec9-4065-a9ef-fee2749a1eee
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1814443251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1814443251
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.4186337674
Short name T63
Test name
Test status
Simulation time 9291734 ps
CPU time 0.4 seconds
Started Jun 24 04:17:23 PM PDT 24
Finished Jun 24 04:17:23 PM PDT 24
Peak memory 145700 kb
Host smart-29e7f52b-90a4-43c6-81a5-393db5ac788a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4186337674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.4186337674
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2450574580
Short name T64
Test name
Test status
Simulation time 9012676 ps
CPU time 0.43 seconds
Started Jun 24 04:16:48 PM PDT 24
Finished Jun 24 04:16:49 PM PDT 24
Peak memory 145836 kb
Host smart-95718156-f89e-4c65-8a54-607b606414ef
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2450574580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2450574580
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3369600411
Short name T35
Test name
Test status
Simulation time 8787044 ps
CPU time 0.41 seconds
Started Jun 24 04:17:22 PM PDT 24
Finished Jun 24 04:17:23 PM PDT 24
Peak memory 145700 kb
Host smart-aad481ae-4d5b-41e8-91a7-3621dfeb9f29
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3369600411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3369600411
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3184848521
Short name T75
Test name
Test status
Simulation time 26681439 ps
CPU time 0.42 seconds
Started Jun 24 04:18:40 PM PDT 24
Finished Jun 24 04:18:40 PM PDT 24
Peak memory 145292 kb
Host smart-497791be-4de0-461d-8860-415007967dd6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3184848521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3184848521
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2659320551
Short name T10
Test name
Test status
Simulation time 27392866 ps
CPU time 0.41 seconds
Started Jun 24 04:17:26 PM PDT 24
Finished Jun 24 04:17:26 PM PDT 24
Peak memory 145292 kb
Host smart-b0bfa8c1-90a0-4eb9-9d9b-28d3cf8da272
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2659320551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2659320551
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2913611275
Short name T77
Test name
Test status
Simulation time 28995312 ps
CPU time 0.41 seconds
Started Jun 24 04:18:32 PM PDT 24
Finished Jun 24 04:18:33 PM PDT 24
Peak memory 145304 kb
Host smart-f0e1f63c-1a02-4e30-b6b4-bddd0e1458a8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2913611275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2913611275
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3145805459
Short name T76
Test name
Test status
Simulation time 28061313 ps
CPU time 0.42 seconds
Started Jun 24 04:17:14 PM PDT 24
Finished Jun 24 04:17:14 PM PDT 24
Peak memory 145712 kb
Host smart-2c6d7e55-7578-4687-9cba-5debe992778d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3145805459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3145805459
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3726953229
Short name T70
Test name
Test status
Simulation time 27543336 ps
CPU time 0.39 seconds
Started Jun 24 04:21:37 PM PDT 24
Finished Jun 24 04:21:38 PM PDT 24
Peak memory 145260 kb
Host smart-068dba1e-9074-40e3-a991-dd99bdf62657
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3726953229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3726953229
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3545126451
Short name T69
Test name
Test status
Simulation time 28026323 ps
CPU time 0.41 seconds
Started Jun 24 04:16:24 PM PDT 24
Finished Jun 24 04:16:25 PM PDT 24
Peak memory 145232 kb
Host smart-b2b66748-9900-43c3-9334-f7a971c72e33
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3545126451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3545126451
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3667957509
Short name T33
Test name
Test status
Simulation time 26431670 ps
CPU time 0.44 seconds
Started Jun 24 04:21:23 PM PDT 24
Finished Jun 24 04:21:24 PM PDT 24
Peak memory 143668 kb
Host smart-84c38435-d921-4ce0-b8c5-592d7b3dd728
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3667957509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3667957509
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4007480370
Short name T68
Test name
Test status
Simulation time 29884205 ps
CPU time 0.42 seconds
Started Jun 24 04:22:19 PM PDT 24
Finished Jun 24 04:22:20 PM PDT 24
Peak memory 145056 kb
Host smart-bc926821-f042-4a36-8142-c801ef461e71
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4007480370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.4007480370
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1942466283
Short name T66
Test name
Test status
Simulation time 26490550 ps
CPU time 0.42 seconds
Started Jun 24 04:21:23 PM PDT 24
Finished Jun 24 04:21:24 PM PDT 24
Peak memory 144332 kb
Host smart-54990ef5-1a4d-4996-8712-e8949db73eb7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1942466283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1942466283
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3900995785
Short name T72
Test name
Test status
Simulation time 27660680 ps
CPU time 0.39 seconds
Started Jun 24 04:21:38 PM PDT 24
Finished Jun 24 04:21:39 PM PDT 24
Peak memory 145260 kb
Host smart-d741a1df-e2e5-4583-aa13-f202ce3346c6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3900995785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3900995785
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2116715517
Short name T65
Test name
Test status
Simulation time 25230200 ps
CPU time 0.42 seconds
Started Jun 24 04:21:47 PM PDT 24
Finished Jun 24 04:21:48 PM PDT 24
Peak memory 145848 kb
Host smart-042c4646-5a4b-4a8b-856a-e8006f168722
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2116715517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2116715517
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2223836294
Short name T78
Test name
Test status
Simulation time 25617171 ps
CPU time 0.42 seconds
Started Jun 24 04:22:02 PM PDT 24
Finished Jun 24 04:22:03 PM PDT 24
Peak memory 145168 kb
Host smart-8642530c-8714-439f-a7f1-69ce0424e874
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2223836294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2223836294
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.435855181
Short name T80
Test name
Test status
Simulation time 28013702 ps
CPU time 0.43 seconds
Started Jun 24 04:21:48 PM PDT 24
Finished Jun 24 04:21:49 PM PDT 24
Peak memory 144676 kb
Host smart-55415966-8b3b-4ce3-bc95-15103bc58097
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=435855181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.435855181
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2479353214
Short name T73
Test name
Test status
Simulation time 29151733 ps
CPU time 0.39 seconds
Started Jun 24 04:22:10 PM PDT 24
Finished Jun 24 04:22:11 PM PDT 24
Peak memory 145172 kb
Host smart-f32e260c-88bc-4176-adec-d96140fea1f2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2479353214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2479353214
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3067164927
Short name T79
Test name
Test status
Simulation time 28847878 ps
CPU time 0.45 seconds
Started Jun 24 04:22:16 PM PDT 24
Finished Jun 24 04:22:17 PM PDT 24
Peak memory 145056 kb
Host smart-4232e24c-2f0c-4a45-afd3-08637a95ac93
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3067164927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3067164927
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2597487693
Short name T5
Test name
Test status
Simulation time 28482358 ps
CPU time 0.4 seconds
Started Jun 24 04:22:09 PM PDT 24
Finished Jun 24 04:22:10 PM PDT 24
Peak memory 145424 kb
Host smart-42c5586c-77c8-4b54-82b2-c28748283ac7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2597487693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2597487693
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4137473037
Short name T71
Test name
Test status
Simulation time 26971933 ps
CPU time 0.39 seconds
Started Jun 24 04:22:03 PM PDT 24
Finished Jun 24 04:22:04 PM PDT 24
Peak memory 145168 kb
Host smart-0bc27b04-7634-4715-acae-a3f1bc1c9560
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4137473037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.4137473037
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.423148314
Short name T74
Test name
Test status
Simulation time 26075495 ps
CPU time 0.45 seconds
Started Jun 24 04:22:10 PM PDT 24
Finished Jun 24 04:22:12 PM PDT 24
Peak memory 143672 kb
Host smart-d4f287e9-2240-401d-a2d1-291d4f6d4bea
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=423148314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.423148314
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2767162892
Short name T67
Test name
Test status
Simulation time 26581686 ps
CPU time 0.45 seconds
Started Jun 24 04:22:16 PM PDT 24
Finished Jun 24 04:22:17 PM PDT 24
Peak memory 144824 kb
Host smart-2304045d-49d8-48d2-80c7-4d2bba705bcd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2767162892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2767162892
Directory /workspace/9.prim_sync_fatal_alert/latest
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