Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.61 89.61 100.00 100.00 95.83 95.83 100.00 100.00 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/1.prim_async_alert.1262695605
92.74 3.13 100.00 0.00 95.83 0.00 100.00 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/10.prim_sync_alert.1912963208
94.50 1.76 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1705297918
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1176543963

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3679484207
/workspace/coverage/default/10.prim_async_alert.2787188525
/workspace/coverage/default/11.prim_async_alert.4232122206
/workspace/coverage/default/12.prim_async_alert.960106728
/workspace/coverage/default/13.prim_async_alert.4144720278
/workspace/coverage/default/14.prim_async_alert.3822356534
/workspace/coverage/default/15.prim_async_alert.3987384721
/workspace/coverage/default/16.prim_async_alert.1922810307
/workspace/coverage/default/17.prim_async_alert.1082882796
/workspace/coverage/default/18.prim_async_alert.2130058920
/workspace/coverage/default/19.prim_async_alert.1739852434
/workspace/coverage/default/2.prim_async_alert.162080829
/workspace/coverage/default/3.prim_async_alert.380996957
/workspace/coverage/default/4.prim_async_alert.381102317
/workspace/coverage/default/5.prim_async_alert.2612372117
/workspace/coverage/default/6.prim_async_alert.88968413
/workspace/coverage/default/7.prim_async_alert.3801596082
/workspace/coverage/default/8.prim_async_alert.1281670738
/workspace/coverage/default/9.prim_async_alert.2618685247
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3903852998
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4064399929
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3752876055
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.742179225
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4293201215
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.843825047
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1222195801
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4198783027
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1034962987
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1687978805
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2120543613
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1122363721
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.480591683
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.582531056
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1896956603
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1946450043
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1444401065
/workspace/coverage/sync_alert/0.prim_sync_alert.1880987751
/workspace/coverage/sync_alert/1.prim_sync_alert.3336718164
/workspace/coverage/sync_alert/11.prim_sync_alert.2731282997
/workspace/coverage/sync_alert/12.prim_sync_alert.2430040004
/workspace/coverage/sync_alert/13.prim_sync_alert.3530471135
/workspace/coverage/sync_alert/14.prim_sync_alert.3735703728
/workspace/coverage/sync_alert/15.prim_sync_alert.2689328718
/workspace/coverage/sync_alert/16.prim_sync_alert.573168809
/workspace/coverage/sync_alert/17.prim_sync_alert.47117335
/workspace/coverage/sync_alert/18.prim_sync_alert.3054414814
/workspace/coverage/sync_alert/19.prim_sync_alert.3111116036
/workspace/coverage/sync_alert/2.prim_sync_alert.1391007888
/workspace/coverage/sync_alert/3.prim_sync_alert.4257918153
/workspace/coverage/sync_alert/4.prim_sync_alert.139856359
/workspace/coverage/sync_alert/5.prim_sync_alert.3229898731
/workspace/coverage/sync_alert/6.prim_sync_alert.1582202857
/workspace/coverage/sync_alert/7.prim_sync_alert.2042880982
/workspace/coverage/sync_alert/8.prim_sync_alert.1092919476
/workspace/coverage/sync_alert/9.prim_sync_alert.3695312936
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.394612099
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.467853996
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2574192657
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1432276942
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1588201260
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2977395605
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.750995597
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.236562004
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4031895298
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2114884365
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3649758922
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1187574476
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2127429294
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.556666442
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2795616296
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3509188874
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3853338410
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2169565803
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.530621246
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.712277748



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/18.prim_async_alert.2130058920 Jun 25 04:42:27 PM PDT 24 Jun 25 04:42:29 PM PDT 24 10968622 ps
T2 /workspace/coverage/default/7.prim_async_alert.3801596082 Jun 25 04:42:13 PM PDT 24 Jun 25 04:42:15 PM PDT 24 10238404 ps
T3 /workspace/coverage/default/14.prim_async_alert.3822356534 Jun 25 04:42:17 PM PDT 24 Jun 25 04:42:20 PM PDT 24 11270861 ps
T11 /workspace/coverage/default/12.prim_async_alert.960106728 Jun 25 04:42:18 PM PDT 24 Jun 25 04:42:22 PM PDT 24 11705611 ps
T9 /workspace/coverage/default/2.prim_async_alert.162080829 Jun 25 04:42:10 PM PDT 24 Jun 25 04:42:11 PM PDT 24 12155159 ps
T7 /workspace/coverage/default/1.prim_async_alert.1262695605 Jun 25 04:42:13 PM PDT 24 Jun 25 04:42:14 PM PDT 24 12095023 ps
T16 /workspace/coverage/default/10.prim_async_alert.2787188525 Jun 25 04:42:23 PM PDT 24 Jun 25 04:42:26 PM PDT 24 11203597 ps
T18 /workspace/coverage/default/9.prim_async_alert.2618685247 Jun 25 04:42:11 PM PDT 24 Jun 25 04:42:13 PM PDT 24 11209489 ps
T17 /workspace/coverage/default/19.prim_async_alert.1739852434 Jun 25 04:42:27 PM PDT 24 Jun 25 04:42:29 PM PDT 24 11381317 ps
T8 /workspace/coverage/default/4.prim_async_alert.381102317 Jun 25 04:42:21 PM PDT 24 Jun 25 04:42:24 PM PDT 24 10938092 ps
T10 /workspace/coverage/default/5.prim_async_alert.2612372117 Jun 25 04:42:16 PM PDT 24 Jun 25 04:42:18 PM PDT 24 11766888 ps
T19 /workspace/coverage/default/6.prim_async_alert.88968413 Jun 25 04:42:19 PM PDT 24 Jun 25 04:42:22 PM PDT 24 11444232 ps
T20 /workspace/coverage/default/3.prim_async_alert.380996957 Jun 25 04:42:26 PM PDT 24 Jun 25 04:42:33 PM PDT 24 11778036 ps
T46 /workspace/coverage/default/15.prim_async_alert.3987384721 Jun 25 04:42:32 PM PDT 24 Jun 25 04:42:34 PM PDT 24 10779040 ps
T21 /workspace/coverage/default/13.prim_async_alert.4144720278 Jun 25 04:42:17 PM PDT 24 Jun 25 04:42:19 PM PDT 24 10595890 ps
T47 /workspace/coverage/default/16.prim_async_alert.1922810307 Jun 25 04:42:31 PM PDT 24 Jun 25 04:42:33 PM PDT 24 12553215 ps
T22 /workspace/coverage/default/17.prim_async_alert.1082882796 Jun 25 04:42:22 PM PDT 24 Jun 25 04:42:25 PM PDT 24 10811329 ps
T48 /workspace/coverage/default/8.prim_async_alert.1281670738 Jun 25 04:42:23 PM PDT 24 Jun 25 04:42:26 PM PDT 24 11539905 ps
T23 /workspace/coverage/default/11.prim_async_alert.4232122206 Jun 25 04:42:19 PM PDT 24 Jun 25 04:42:22 PM PDT 24 10140486 ps
T15 /workspace/coverage/default/0.prim_async_alert.3679484207 Jun 25 04:42:25 PM PDT 24 Jun 25 04:42:27 PM PDT 24 11064544 ps
T38 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3752876055 Jun 25 04:42:31 PM PDT 24 Jun 25 04:42:38 PM PDT 24 29765433 ps
T39 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.582531056 Jun 25 04:42:29 PM PDT 24 Jun 25 04:42:31 PM PDT 24 30269672 ps
T40 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2120543613 Jun 25 04:42:29 PM PDT 24 Jun 25 04:42:31 PM PDT 24 29236833 ps
T12 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1705297918 Jun 25 04:42:34 PM PDT 24 Jun 25 04:42:35 PM PDT 24 30896134 ps
T4 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1176543963 Jun 25 04:42:31 PM PDT 24 Jun 25 04:42:33 PM PDT 24 30690248 ps
T41 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1444401065 Jun 25 04:42:29 PM PDT 24 Jun 25 04:42:31 PM PDT 24 28665458 ps
T42 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3903852998 Jun 25 04:42:21 PM PDT 24 Jun 25 04:42:24 PM PDT 24 29778140 ps
T43 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1946450043 Jun 25 04:42:17 PM PDT 24 Jun 25 04:42:20 PM PDT 24 30423934 ps
T44 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.843825047 Jun 25 04:42:31 PM PDT 24 Jun 25 04:42:33 PM PDT 24 29062572 ps
T45 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1034962987 Jun 25 04:42:19 PM PDT 24 Jun 25 04:42:22 PM PDT 24 27572232 ps
T49 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.742179225 Jun 25 04:42:21 PM PDT 24 Jun 25 04:42:24 PM PDT 24 28968170 ps
T13 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1222195801 Jun 25 04:42:32 PM PDT 24 Jun 25 04:42:33 PM PDT 24 31024571 ps
T50 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4064399929 Jun 25 04:42:19 PM PDT 24 Jun 25 04:42:22 PM PDT 24 29180778 ps
T51 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4293201215 Jun 25 04:42:29 PM PDT 24 Jun 25 04:42:31 PM PDT 24 31241054 ps
T52 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.480591683 Jun 25 04:42:21 PM PDT 24 Jun 25 04:42:24 PM PDT 24 31069695 ps
T14 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1122363721 Jun 25 04:42:17 PM PDT 24 Jun 25 04:42:20 PM PDT 24 30963377 ps
T53 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1687978805 Jun 25 04:42:25 PM PDT 24 Jun 25 04:42:27 PM PDT 24 30914574 ps
T54 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1896956603 Jun 25 04:42:26 PM PDT 24 Jun 25 04:42:28 PM PDT 24 29331823 ps
T55 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4198783027 Jun 25 04:42:33 PM PDT 24 Jun 25 04:42:35 PM PDT 24 31253322 ps
T33 /workspace/coverage/sync_alert/12.prim_sync_alert.2430040004 Jun 25 04:42:25 PM PDT 24 Jun 25 04:42:27 PM PDT 24 9239320 ps
T24 /workspace/coverage/sync_alert/7.prim_sync_alert.2042880982 Jun 25 04:42:28 PM PDT 24 Jun 25 04:42:29 PM PDT 24 10165394 ps
T25 /workspace/coverage/sync_alert/10.prim_sync_alert.1912963208 Jun 25 04:42:21 PM PDT 24 Jun 25 04:42:24 PM PDT 24 9163712 ps
T26 /workspace/coverage/sync_alert/1.prim_sync_alert.3336718164 Jun 25 04:42:19 PM PDT 24 Jun 25 04:42:22 PM PDT 24 8910742 ps
T27 /workspace/coverage/sync_alert/17.prim_sync_alert.47117335 Jun 25 04:42:28 PM PDT 24 Jun 25 04:42:30 PM PDT 24 9706441 ps
T28 /workspace/coverage/sync_alert/5.prim_sync_alert.3229898731 Jun 25 04:42:18 PM PDT 24 Jun 25 04:42:21 PM PDT 24 9496332 ps
T29 /workspace/coverage/sync_alert/11.prim_sync_alert.2731282997 Jun 25 04:42:19 PM PDT 24 Jun 25 04:42:22 PM PDT 24 9999022 ps
T34 /workspace/coverage/sync_alert/15.prim_sync_alert.2689328718 Jun 25 04:42:33 PM PDT 24 Jun 25 04:42:35 PM PDT 24 8767691 ps
T35 /workspace/coverage/sync_alert/13.prim_sync_alert.3530471135 Jun 25 04:42:19 PM PDT 24 Jun 25 04:42:22 PM PDT 24 9105583 ps
T36 /workspace/coverage/sync_alert/0.prim_sync_alert.1880987751 Jun 25 04:42:47 PM PDT 24 Jun 25 04:42:48 PM PDT 24 8914449 ps
T37 /workspace/coverage/sync_alert/19.prim_sync_alert.3111116036 Jun 25 04:42:20 PM PDT 24 Jun 25 04:42:23 PM PDT 24 9518045 ps
T56 /workspace/coverage/sync_alert/4.prim_sync_alert.139856359 Jun 25 04:42:14 PM PDT 24 Jun 25 04:42:16 PM PDT 24 8944922 ps
T30 /workspace/coverage/sync_alert/18.prim_sync_alert.3054414814 Jun 25 04:42:23 PM PDT 24 Jun 25 04:42:25 PM PDT 24 10321948 ps
T31 /workspace/coverage/sync_alert/3.prim_sync_alert.4257918153 Jun 25 04:42:34 PM PDT 24 Jun 25 04:42:35 PM PDT 24 9596198 ps
T57 /workspace/coverage/sync_alert/8.prim_sync_alert.1092919476 Jun 25 04:42:22 PM PDT 24 Jun 25 04:42:25 PM PDT 24 9492210 ps
T32 /workspace/coverage/sync_alert/14.prim_sync_alert.3735703728 Jun 25 04:42:22 PM PDT 24 Jun 25 04:42:25 PM PDT 24 8603065 ps
T58 /workspace/coverage/sync_alert/2.prim_sync_alert.1391007888 Jun 25 04:42:16 PM PDT 24 Jun 25 04:42:18 PM PDT 24 9523012 ps
T59 /workspace/coverage/sync_alert/6.prim_sync_alert.1582202857 Jun 25 04:42:22 PM PDT 24 Jun 25 04:42:25 PM PDT 24 9082393 ps
T60 /workspace/coverage/sync_alert/9.prim_sync_alert.3695312936 Jun 25 04:42:19 PM PDT 24 Jun 25 04:42:22 PM PDT 24 9677395 ps
T61 /workspace/coverage/sync_alert/16.prim_sync_alert.573168809 Jun 25 04:42:22 PM PDT 24 Jun 25 04:42:24 PM PDT 24 9241283 ps
T62 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2169565803 Jun 25 04:42:18 PM PDT 24 Jun 25 04:42:21 PM PDT 24 27851755 ps
T63 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.750995597 Jun 25 04:42:21 PM PDT 24 Jun 25 04:42:24 PM PDT 24 27649137 ps
T64 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3649758922 Jun 25 04:42:29 PM PDT 24 Jun 25 04:42:31 PM PDT 24 28174861 ps
T65 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2114884365 Jun 25 04:42:21 PM PDT 24 Jun 25 04:42:24 PM PDT 24 27140923 ps
T66 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.712277748 Jun 25 04:42:24 PM PDT 24 Jun 25 04:42:26 PM PDT 24 28341852 ps
T67 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1588201260 Jun 25 04:42:20 PM PDT 24 Jun 25 04:42:23 PM PDT 24 26611614 ps
T68 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2574192657 Jun 25 04:42:33 PM PDT 24 Jun 25 04:42:34 PM PDT 24 30071142 ps
T69 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.467853996 Jun 25 04:43:03 PM PDT 24 Jun 25 04:43:04 PM PDT 24 26607314 ps
T70 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2795616296 Jun 25 04:42:22 PM PDT 24 Jun 25 04:42:25 PM PDT 24 28263128 ps
T71 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1187574476 Jun 25 04:42:27 PM PDT 24 Jun 25 04:42:33 PM PDT 24 29698278 ps
T5 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.394612099 Jun 25 04:42:36 PM PDT 24 Jun 25 04:42:37 PM PDT 24 27984953 ps
T72 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2977395605 Jun 25 04:42:21 PM PDT 24 Jun 25 04:42:24 PM PDT 24 26709478 ps
T73 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3509188874 Jun 25 04:42:28 PM PDT 24 Jun 25 04:42:30 PM PDT 24 27501618 ps
T6 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1432276942 Jun 25 04:42:18 PM PDT 24 Jun 25 04:42:21 PM PDT 24 27049503 ps
T74 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2127429294 Jun 25 04:42:21 PM PDT 24 Jun 25 04:42:24 PM PDT 24 29027960 ps
T75 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.556666442 Jun 25 04:42:25 PM PDT 24 Jun 25 04:42:27 PM PDT 24 28880397 ps
T76 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3853338410 Jun 25 04:42:28 PM PDT 24 Jun 25 04:42:29 PM PDT 24 25806375 ps
T77 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.236562004 Jun 25 04:42:18 PM PDT 24 Jun 25 04:42:21 PM PDT 24 28152708 ps
T78 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4031895298 Jun 25 04:42:36 PM PDT 24 Jun 25 04:42:37 PM PDT 24 27613040 ps
T79 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.530621246 Jun 25 04:42:27 PM PDT 24 Jun 25 04:42:28 PM PDT 24 25696519 ps

Test location /workspace/coverage/default/1.prim_async_alert.1262695605
Short name T7
Test name
Test status
Simulation time 12095023 ps
CPU time 0.4 seconds
Started Jun 25 04:42:13 PM PDT 24
Finished Jun 25 04:42:14 PM PDT 24
Peak memory 145528 kb
Host smart-c586bbff-10a5-4299-9d59-9bfafd4be918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262695605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1262695605
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1912963208
Short name T25
Test name
Test status
Simulation time 9163712 ps
CPU time 0.4 seconds
Started Jun 25 04:42:21 PM PDT 24
Finished Jun 25 04:42:24 PM PDT 24
Peak memory 145336 kb
Host smart-f9145944-5d6c-4c2a-9274-be04e64623b8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1912963208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1912963208
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1705297918
Short name T12
Test name
Test status
Simulation time 30896134 ps
CPU time 0.42 seconds
Started Jun 25 04:42:34 PM PDT 24
Finished Jun 25 04:42:35 PM PDT 24
Peak memory 145096 kb
Host smart-cd0732ed-fb45-475d-a6e1-949045b06877
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1705297918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1705297918
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1176543963
Short name T4
Test name
Test status
Simulation time 30690248 ps
CPU time 0.41 seconds
Started Jun 25 04:42:31 PM PDT 24
Finished Jun 25 04:42:33 PM PDT 24
Peak memory 145100 kb
Host smart-3fd05218-5ff6-4349-9fd9-0d9351feecea
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1176543963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1176543963
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3679484207
Short name T15
Test name
Test status
Simulation time 11064544 ps
CPU time 0.39 seconds
Started Jun 25 04:42:25 PM PDT 24
Finished Jun 25 04:42:27 PM PDT 24
Peak memory 145144 kb
Host smart-d7128cd6-1add-4c72-94fa-ea9aa0d8e641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679484207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3679484207
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2787188525
Short name T16
Test name
Test status
Simulation time 11203597 ps
CPU time 0.44 seconds
Started Jun 25 04:42:23 PM PDT 24
Finished Jun 25 04:42:26 PM PDT 24
Peak memory 144688 kb
Host smart-a5f54150-f1d8-45f4-8035-24c9f80b6031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787188525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2787188525
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.4232122206
Short name T23
Test name
Test status
Simulation time 10140486 ps
CPU time 0.39 seconds
Started Jun 25 04:42:19 PM PDT 24
Finished Jun 25 04:42:22 PM PDT 24
Peak memory 145532 kb
Host smart-ee90b402-2b24-4066-97b7-4117ca60e9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232122206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4232122206
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.960106728
Short name T11
Test name
Test status
Simulation time 11705611 ps
CPU time 0.4 seconds
Started Jun 25 04:42:18 PM PDT 24
Finished Jun 25 04:42:22 PM PDT 24
Peak memory 145784 kb
Host smart-f225d288-c8b9-4982-9ac1-bcc366fe91c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960106728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.960106728
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.4144720278
Short name T21
Test name
Test status
Simulation time 10595890 ps
CPU time 0.39 seconds
Started Jun 25 04:42:17 PM PDT 24
Finished Jun 25 04:42:19 PM PDT 24
Peak memory 145444 kb
Host smart-0b9977ae-ae31-4bdc-870d-d4bb0bdb3fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144720278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.4144720278
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.3822356534
Short name T3
Test name
Test status
Simulation time 11270861 ps
CPU time 0.4 seconds
Started Jun 25 04:42:17 PM PDT 24
Finished Jun 25 04:42:20 PM PDT 24
Peak memory 145532 kb
Host smart-a56869ba-a679-4cb3-942e-c9fb614671f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822356534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3822356534
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.3987384721
Short name T46
Test name
Test status
Simulation time 10779040 ps
CPU time 0.45 seconds
Started Jun 25 04:42:32 PM PDT 24
Finished Jun 25 04:42:34 PM PDT 24
Peak memory 145576 kb
Host smart-48221d25-feea-4456-99bd-13cbbe41917e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987384721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3987384721
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1922810307
Short name T47
Test name
Test status
Simulation time 12553215 ps
CPU time 0.38 seconds
Started Jun 25 04:42:31 PM PDT 24
Finished Jun 25 04:42:33 PM PDT 24
Peak memory 145532 kb
Host smart-487c5caf-ae13-4a5d-ab9d-afeb866e98f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922810307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1922810307
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1082882796
Short name T22
Test name
Test status
Simulation time 10811329 ps
CPU time 0.4 seconds
Started Jun 25 04:42:22 PM PDT 24
Finished Jun 25 04:42:25 PM PDT 24
Peak memory 145588 kb
Host smart-73c8a4ed-ce85-4aba-80d8-2e562eab2026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082882796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1082882796
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2130058920
Short name T1
Test name
Test status
Simulation time 10968622 ps
CPU time 0.4 seconds
Started Jun 25 04:42:27 PM PDT 24
Finished Jun 25 04:42:29 PM PDT 24
Peak memory 145548 kb
Host smart-33a9d282-e3f9-48cc-9faf-100f5b243bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130058920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2130058920
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1739852434
Short name T17
Test name
Test status
Simulation time 11381317 ps
CPU time 0.4 seconds
Started Jun 25 04:42:27 PM PDT 24
Finished Jun 25 04:42:29 PM PDT 24
Peak memory 145512 kb
Host smart-d0d0b94b-afd4-43e6-86b6-0a5d01266a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739852434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1739852434
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.162080829
Short name T9
Test name
Test status
Simulation time 12155159 ps
CPU time 0.42 seconds
Started Jun 25 04:42:10 PM PDT 24
Finished Jun 25 04:42:11 PM PDT 24
Peak memory 145492 kb
Host smart-f489604f-eda6-476c-9b62-89f707f0371d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162080829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.162080829
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.380996957
Short name T20
Test name
Test status
Simulation time 11778036 ps
CPU time 0.39 seconds
Started Jun 25 04:42:26 PM PDT 24
Finished Jun 25 04:42:33 PM PDT 24
Peak memory 145492 kb
Host smart-5af3d9aa-958f-4a4b-abe5-56ef43ddef43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380996957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.380996957
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.381102317
Short name T8
Test name
Test status
Simulation time 10938092 ps
CPU time 0.39 seconds
Started Jun 25 04:42:21 PM PDT 24
Finished Jun 25 04:42:24 PM PDT 24
Peak memory 145512 kb
Host smart-06f5701f-57c8-4572-97fc-504e3aeb7df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381102317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.381102317
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2612372117
Short name T10
Test name
Test status
Simulation time 11766888 ps
CPU time 0.38 seconds
Started Jun 25 04:42:16 PM PDT 24
Finished Jun 25 04:42:18 PM PDT 24
Peak memory 145572 kb
Host smart-d6642d96-8f62-4cd5-908b-08d24b2d176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612372117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2612372117
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.88968413
Short name T19
Test name
Test status
Simulation time 11444232 ps
CPU time 0.41 seconds
Started Jun 25 04:42:19 PM PDT 24
Finished Jun 25 04:42:22 PM PDT 24
Peak memory 145508 kb
Host smart-a3e510d6-61e3-454f-9f7b-c045c8632b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88968413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.88968413
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3801596082
Short name T2
Test name
Test status
Simulation time 10238404 ps
CPU time 0.4 seconds
Started Jun 25 04:42:13 PM PDT 24
Finished Jun 25 04:42:15 PM PDT 24
Peak memory 145784 kb
Host smart-00971aa7-dc9c-45b1-88d9-867143022e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801596082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3801596082
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1281670738
Short name T48
Test name
Test status
Simulation time 11539905 ps
CPU time 0.43 seconds
Started Jun 25 04:42:23 PM PDT 24
Finished Jun 25 04:42:26 PM PDT 24
Peak memory 144872 kb
Host smart-280f3810-81ee-4e2e-be4a-43da2a50136f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281670738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1281670738
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2618685247
Short name T18
Test name
Test status
Simulation time 11209489 ps
CPU time 0.4 seconds
Started Jun 25 04:42:11 PM PDT 24
Finished Jun 25 04:42:13 PM PDT 24
Peak memory 145872 kb
Host smart-eae8b2e0-15ec-417e-8f0f-53bc474cf0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618685247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2618685247
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3903852998
Short name T42
Test name
Test status
Simulation time 29778140 ps
CPU time 0.4 seconds
Started Jun 25 04:42:21 PM PDT 24
Finished Jun 25 04:42:24 PM PDT 24
Peak memory 145100 kb
Host smart-2317ad3a-736f-4cba-aed3-f4161f81a17f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3903852998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3903852998
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4064399929
Short name T50
Test name
Test status
Simulation time 29180778 ps
CPU time 0.42 seconds
Started Jun 25 04:42:19 PM PDT 24
Finished Jun 25 04:42:22 PM PDT 24
Peak memory 144960 kb
Host smart-f3821416-8802-43b3-b826-01bbec26b0dc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4064399929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.4064399929
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3752876055
Short name T38
Test name
Test status
Simulation time 29765433 ps
CPU time 0.44 seconds
Started Jun 25 04:42:31 PM PDT 24
Finished Jun 25 04:42:38 PM PDT 24
Peak memory 145064 kb
Host smart-dd258aad-e47d-4934-9a5b-e44f0662669a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3752876055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3752876055
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.742179225
Short name T49
Test name
Test status
Simulation time 28968170 ps
CPU time 0.41 seconds
Started Jun 25 04:42:21 PM PDT 24
Finished Jun 25 04:42:24 PM PDT 24
Peak memory 145156 kb
Host smart-7dc97495-5ea1-4ec5-9d31-e81c19cdcef6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=742179225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.742179225
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4293201215
Short name T51
Test name
Test status
Simulation time 31241054 ps
CPU time 0.4 seconds
Started Jun 25 04:42:29 PM PDT 24
Finished Jun 25 04:42:31 PM PDT 24
Peak memory 145096 kb
Host smart-9c965564-6a18-4c33-8d9d-bf2b7e88dd38
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4293201215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.4293201215
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.843825047
Short name T44
Test name
Test status
Simulation time 29062572 ps
CPU time 0.39 seconds
Started Jun 25 04:42:31 PM PDT 24
Finished Jun 25 04:42:33 PM PDT 24
Peak memory 145100 kb
Host smart-2c33f0d2-d92b-4a2b-978c-a52a2b5af191
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=843825047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.843825047
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1222195801
Short name T13
Test name
Test status
Simulation time 31024571 ps
CPU time 0.42 seconds
Started Jun 25 04:42:32 PM PDT 24
Finished Jun 25 04:42:33 PM PDT 24
Peak memory 145168 kb
Host smart-d839654f-ffcc-418b-b9f5-c9c0118608a9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1222195801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1222195801
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4198783027
Short name T55
Test name
Test status
Simulation time 31253322 ps
CPU time 0.42 seconds
Started Jun 25 04:42:33 PM PDT 24
Finished Jun 25 04:42:35 PM PDT 24
Peak memory 145100 kb
Host smart-9fbe134b-e284-4e3e-ab4e-8a47d7504c29
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4198783027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.4198783027
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1034962987
Short name T45
Test name
Test status
Simulation time 27572232 ps
CPU time 0.44 seconds
Started Jun 25 04:42:19 PM PDT 24
Finished Jun 25 04:42:22 PM PDT 24
Peak memory 145144 kb
Host smart-9f617579-858f-4715-9233-565dd6175a81
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1034962987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1034962987
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1687978805
Short name T53
Test name
Test status
Simulation time 30914574 ps
CPU time 0.41 seconds
Started Jun 25 04:42:25 PM PDT 24
Finished Jun 25 04:42:27 PM PDT 24
Peak memory 145104 kb
Host smart-d357586f-6aef-4c7c-9eeb-7a079b66e539
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1687978805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1687978805
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2120543613
Short name T40
Test name
Test status
Simulation time 29236833 ps
CPU time 0.41 seconds
Started Jun 25 04:42:29 PM PDT 24
Finished Jun 25 04:42:31 PM PDT 24
Peak memory 145060 kb
Host smart-fd4bb53e-19ed-40ee-b664-1ae8bc97ee7f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2120543613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2120543613
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1122363721
Short name T14
Test name
Test status
Simulation time 30963377 ps
CPU time 0.42 seconds
Started Jun 25 04:42:17 PM PDT 24
Finished Jun 25 04:42:20 PM PDT 24
Peak memory 145012 kb
Host smart-4b2b36c2-896d-4715-98e5-830cee2b9435
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1122363721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1122363721
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.480591683
Short name T52
Test name
Test status
Simulation time 31069695 ps
CPU time 0.43 seconds
Started Jun 25 04:42:21 PM PDT 24
Finished Jun 25 04:42:24 PM PDT 24
Peak memory 145092 kb
Host smart-cc6c6a5a-dea3-46a5-b9a8-f7c8cec7bf43
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=480591683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.480591683
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.582531056
Short name T39
Test name
Test status
Simulation time 30269672 ps
CPU time 0.4 seconds
Started Jun 25 04:42:29 PM PDT 24
Finished Jun 25 04:42:31 PM PDT 24
Peak memory 145128 kb
Host smart-fbb3a2af-748c-465a-8a70-9e402eb62e04
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=582531056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.582531056
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1896956603
Short name T54
Test name
Test status
Simulation time 29331823 ps
CPU time 0.42 seconds
Started Jun 25 04:42:26 PM PDT 24
Finished Jun 25 04:42:28 PM PDT 24
Peak memory 145024 kb
Host smart-5bc98f7b-631b-4052-a634-6305714977b1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1896956603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1896956603
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1946450043
Short name T43
Test name
Test status
Simulation time 30423934 ps
CPU time 0.45 seconds
Started Jun 25 04:42:17 PM PDT 24
Finished Jun 25 04:42:20 PM PDT 24
Peak memory 145120 kb
Host smart-6d69f2ae-6a4f-4f4f-be68-8de4a213ee49
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1946450043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1946450043
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1444401065
Short name T41
Test name
Test status
Simulation time 28665458 ps
CPU time 0.42 seconds
Started Jun 25 04:42:29 PM PDT 24
Finished Jun 25 04:42:31 PM PDT 24
Peak memory 145064 kb
Host smart-f5cb2ca9-fa11-4a9d-b6eb-8733616e09ae
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1444401065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1444401065
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1880987751
Short name T36
Test name
Test status
Simulation time 8914449 ps
CPU time 0.39 seconds
Started Jun 25 04:42:47 PM PDT 24
Finished Jun 25 04:42:48 PM PDT 24
Peak memory 145248 kb
Host smart-297f6594-c9ef-4761-af63-bf1b72335438
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1880987751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1880987751
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3336718164
Short name T26
Test name
Test status
Simulation time 8910742 ps
CPU time 0.37 seconds
Started Jun 25 04:42:19 PM PDT 24
Finished Jun 25 04:42:22 PM PDT 24
Peak memory 145376 kb
Host smart-73e1fc92-3538-4d01-a44a-d29e1cf608ee
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3336718164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3336718164
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2731282997
Short name T29
Test name
Test status
Simulation time 9999022 ps
CPU time 0.39 seconds
Started Jun 25 04:42:19 PM PDT 24
Finished Jun 25 04:42:22 PM PDT 24
Peak memory 145268 kb
Host smart-14898fc6-f748-4486-bdcc-be9ec4c7b907
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2731282997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2731282997
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2430040004
Short name T33
Test name
Test status
Simulation time 9239320 ps
CPU time 0.38 seconds
Started Jun 25 04:42:25 PM PDT 24
Finished Jun 25 04:42:27 PM PDT 24
Peak memory 145268 kb
Host smart-7038bb48-77e9-48b4-981e-0cb6e2d4848e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2430040004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2430040004
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3530471135
Short name T35
Test name
Test status
Simulation time 9105583 ps
CPU time 0.43 seconds
Started Jun 25 04:42:19 PM PDT 24
Finished Jun 25 04:42:22 PM PDT 24
Peak memory 145264 kb
Host smart-f8be6278-5a79-448b-a554-402dbe705d76
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3530471135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3530471135
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3735703728
Short name T32
Test name
Test status
Simulation time 8603065 ps
CPU time 0.39 seconds
Started Jun 25 04:42:22 PM PDT 24
Finished Jun 25 04:42:25 PM PDT 24
Peak memory 145144 kb
Host smart-81af256e-186c-489d-8619-ad018d35d638
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3735703728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3735703728
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2689328718
Short name T34
Test name
Test status
Simulation time 8767691 ps
CPU time 0.39 seconds
Started Jun 25 04:42:33 PM PDT 24
Finished Jun 25 04:42:35 PM PDT 24
Peak memory 145388 kb
Host smart-b0a54d91-13cb-47fc-9339-ccb325752428
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2689328718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2689328718
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.573168809
Short name T61
Test name
Test status
Simulation time 9241283 ps
CPU time 0.4 seconds
Started Jun 25 04:42:22 PM PDT 24
Finished Jun 25 04:42:24 PM PDT 24
Peak memory 145240 kb
Host smart-919d645e-81d7-4968-8a9d-b5572915d861
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=573168809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.573168809
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.47117335
Short name T27
Test name
Test status
Simulation time 9706441 ps
CPU time 0.36 seconds
Started Jun 25 04:42:28 PM PDT 24
Finished Jun 25 04:42:30 PM PDT 24
Peak memory 145380 kb
Host smart-5be487bb-0f85-44d0-a456-dd50f557b631
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=47117335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.47117335
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3054414814
Short name T30
Test name
Test status
Simulation time 10321948 ps
CPU time 0.4 seconds
Started Jun 25 04:42:23 PM PDT 24
Finished Jun 25 04:42:25 PM PDT 24
Peak memory 145292 kb
Host smart-11910c4b-f64b-44bb-b9e6-0fe9529a85d4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3054414814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3054414814
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3111116036
Short name T37
Test name
Test status
Simulation time 9518045 ps
CPU time 0.38 seconds
Started Jun 25 04:42:20 PM PDT 24
Finished Jun 25 04:42:23 PM PDT 24
Peak memory 145284 kb
Host smart-2057e3c6-ae2a-4ac6-8ef7-507f6206e753
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3111116036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3111116036
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1391007888
Short name T58
Test name
Test status
Simulation time 9523012 ps
CPU time 0.39 seconds
Started Jun 25 04:42:16 PM PDT 24
Finished Jun 25 04:42:18 PM PDT 24
Peak memory 146408 kb
Host smart-bd1eb732-46d5-43c4-a80d-3050494ebc77
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1391007888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1391007888
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.4257918153
Short name T31
Test name
Test status
Simulation time 9596198 ps
CPU time 0.37 seconds
Started Jun 25 04:42:34 PM PDT 24
Finished Jun 25 04:42:35 PM PDT 24
Peak memory 145376 kb
Host smart-090e6c90-b3ca-4ad7-89c0-ca57e786d8e5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4257918153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.4257918153
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.139856359
Short name T56
Test name
Test status
Simulation time 8944922 ps
CPU time 0.39 seconds
Started Jun 25 04:42:14 PM PDT 24
Finished Jun 25 04:42:16 PM PDT 24
Peak memory 145276 kb
Host smart-fcb9024f-1cc6-4a9d-b88e-fec8dc20b2e9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=139856359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.139856359
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3229898731
Short name T28
Test name
Test status
Simulation time 9496332 ps
CPU time 0.39 seconds
Started Jun 25 04:42:18 PM PDT 24
Finished Jun 25 04:42:21 PM PDT 24
Peak memory 145368 kb
Host smart-044954f3-f358-4390-8805-c4750810d603
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3229898731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3229898731
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1582202857
Short name T59
Test name
Test status
Simulation time 9082393 ps
CPU time 0.4 seconds
Started Jun 25 04:42:22 PM PDT 24
Finished Jun 25 04:42:25 PM PDT 24
Peak memory 145272 kb
Host smart-bf0e2e53-173e-48af-be92-88866b137290
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1582202857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1582202857
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2042880982
Short name T24
Test name
Test status
Simulation time 10165394 ps
CPU time 0.46 seconds
Started Jun 25 04:42:28 PM PDT 24
Finished Jun 25 04:42:29 PM PDT 24
Peak memory 145388 kb
Host smart-0d537416-636c-4753-acf0-f76b31944906
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2042880982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2042880982
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1092919476
Short name T57
Test name
Test status
Simulation time 9492210 ps
CPU time 0.39 seconds
Started Jun 25 04:42:22 PM PDT 24
Finished Jun 25 04:42:25 PM PDT 24
Peak memory 145272 kb
Host smart-bc6fa39e-a0c2-459c-aabf-056685607af2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1092919476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1092919476
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3695312936
Short name T60
Test name
Test status
Simulation time 9677395 ps
CPU time 0.38 seconds
Started Jun 25 04:42:19 PM PDT 24
Finished Jun 25 04:42:22 PM PDT 24
Peak memory 145276 kb
Host smart-c48f79ca-ec12-4163-afe5-6275d294219a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3695312936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3695312936
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.394612099
Short name T5
Test name
Test status
Simulation time 27984953 ps
CPU time 0.41 seconds
Started Jun 25 04:42:36 PM PDT 24
Finished Jun 25 04:42:37 PM PDT 24
Peak memory 145256 kb
Host smart-8cef1c68-61de-4b74-a616-3f893a59949f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=394612099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.394612099
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.467853996
Short name T69
Test name
Test status
Simulation time 26607314 ps
CPU time 0.42 seconds
Started Jun 25 04:43:03 PM PDT 24
Finished Jun 25 04:43:04 PM PDT 24
Peak memory 145296 kb
Host smart-21d5477a-9b67-4e0b-8a6f-e6c78570772a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=467853996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.467853996
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2574192657
Short name T68
Test name
Test status
Simulation time 30071142 ps
CPU time 0.4 seconds
Started Jun 25 04:42:33 PM PDT 24
Finished Jun 25 04:42:34 PM PDT 24
Peak memory 145300 kb
Host smart-e1f91cbf-8211-4181-8b33-aa1b0c1849f0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2574192657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2574192657
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1432276942
Short name T6
Test name
Test status
Simulation time 27049503 ps
CPU time 0.44 seconds
Started Jun 25 04:42:18 PM PDT 24
Finished Jun 25 04:42:21 PM PDT 24
Peak memory 145228 kb
Host smart-b34eef64-b511-4ec0-9d64-d826e198564b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1432276942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1432276942
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1588201260
Short name T67
Test name
Test status
Simulation time 26611614 ps
CPU time 0.41 seconds
Started Jun 25 04:42:20 PM PDT 24
Finished Jun 25 04:42:23 PM PDT 24
Peak memory 145260 kb
Host smart-5670de82-8b4a-4f6d-a855-56c1235bd2ed
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1588201260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1588201260
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2977395605
Short name T72
Test name
Test status
Simulation time 26709478 ps
CPU time 0.4 seconds
Started Jun 25 04:42:21 PM PDT 24
Finished Jun 25 04:42:24 PM PDT 24
Peak memory 145280 kb
Host smart-909d046f-e6fe-40bb-875b-c5ba1ee1c2b7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2977395605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2977395605
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.750995597
Short name T63
Test name
Test status
Simulation time 27649137 ps
CPU time 0.41 seconds
Started Jun 25 04:42:21 PM PDT 24
Finished Jun 25 04:42:24 PM PDT 24
Peak memory 145704 kb
Host smart-3a3301de-8ae4-4f1d-b214-8f93e2b74460
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=750995597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.750995597
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.236562004
Short name T77
Test name
Test status
Simulation time 28152708 ps
CPU time 0.43 seconds
Started Jun 25 04:42:18 PM PDT 24
Finished Jun 25 04:42:21 PM PDT 24
Peak memory 145220 kb
Host smart-b14517b8-c304-4e5f-91d9-5ba142655812
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=236562004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.236562004
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4031895298
Short name T78
Test name
Test status
Simulation time 27613040 ps
CPU time 0.4 seconds
Started Jun 25 04:42:36 PM PDT 24
Finished Jun 25 04:42:37 PM PDT 24
Peak memory 145380 kb
Host smart-775a25e9-7864-4945-8d48-c7d4dfe1e852
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4031895298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.4031895298
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2114884365
Short name T65
Test name
Test status
Simulation time 27140923 ps
CPU time 0.41 seconds
Started Jun 25 04:42:21 PM PDT 24
Finished Jun 25 04:42:24 PM PDT 24
Peak memory 145712 kb
Host smart-4e1f2606-e64a-4a0a-9bc6-ef2bbb282b5f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2114884365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2114884365
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3649758922
Short name T64
Test name
Test status
Simulation time 28174861 ps
CPU time 0.4 seconds
Started Jun 25 04:42:29 PM PDT 24
Finished Jun 25 04:42:31 PM PDT 24
Peak memory 145280 kb
Host smart-4708074d-b6b6-4c42-8a8a-f08f36b75013
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3649758922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3649758922
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1187574476
Short name T71
Test name
Test status
Simulation time 29698278 ps
CPU time 0.42 seconds
Started Jun 25 04:42:27 PM PDT 24
Finished Jun 25 04:42:33 PM PDT 24
Peak memory 146344 kb
Host smart-dd45aaed-01be-47e1-9dd9-6fc164111286
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1187574476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1187574476
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2127429294
Short name T74
Test name
Test status
Simulation time 29027960 ps
CPU time 0.4 seconds
Started Jun 25 04:42:21 PM PDT 24
Finished Jun 25 04:42:24 PM PDT 24
Peak memory 145268 kb
Host smart-c3eee272-ebae-4cbe-b801-b328916184b7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2127429294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2127429294
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.556666442
Short name T75
Test name
Test status
Simulation time 28880397 ps
CPU time 0.39 seconds
Started Jun 25 04:42:25 PM PDT 24
Finished Jun 25 04:42:27 PM PDT 24
Peak memory 144948 kb
Host smart-25bd4bab-3e44-4441-bbf3-95fd129619d8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=556666442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.556666442
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2795616296
Short name T70
Test name
Test status
Simulation time 28263128 ps
CPU time 0.42 seconds
Started Jun 25 04:42:22 PM PDT 24
Finished Jun 25 04:42:25 PM PDT 24
Peak memory 145252 kb
Host smart-2c4a8dc0-bac8-4985-a9c1-b6a64d0034fe
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2795616296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2795616296
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3509188874
Short name T73
Test name
Test status
Simulation time 27501618 ps
CPU time 0.41 seconds
Started Jun 25 04:42:28 PM PDT 24
Finished Jun 25 04:42:30 PM PDT 24
Peak memory 145380 kb
Host smart-9816e603-5317-4d2c-b008-ae22033c9e29
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3509188874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3509188874
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3853338410
Short name T76
Test name
Test status
Simulation time 25806375 ps
CPU time 0.39 seconds
Started Jun 25 04:42:28 PM PDT 24
Finished Jun 25 04:42:29 PM PDT 24
Peak memory 145368 kb
Host smart-d368415a-9819-44be-9d82-c4a36638e052
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3853338410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3853338410
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2169565803
Short name T62
Test name
Test status
Simulation time 27851755 ps
CPU time 0.39 seconds
Started Jun 25 04:42:18 PM PDT 24
Finished Jun 25 04:42:21 PM PDT 24
Peak memory 145112 kb
Host smart-e138875c-20d8-4ea2-a60e-80b830852eb0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2169565803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2169565803
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.530621246
Short name T79
Test name
Test status
Simulation time 25696519 ps
CPU time 0.43 seconds
Started Jun 25 04:42:27 PM PDT 24
Finished Jun 25 04:42:28 PM PDT 24
Peak memory 145376 kb
Host smart-70749e60-ccb7-42b6-b323-b344cab8a24c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=530621246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.530621246
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.712277748
Short name T66
Test name
Test status
Simulation time 28341852 ps
CPU time 0.42 seconds
Started Jun 25 04:42:24 PM PDT 24
Finished Jun 25 04:42:26 PM PDT 24
Peak memory 145296 kb
Host smart-cabe9d3e-7a5e-48de-95af-256f117e02bf
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=712277748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.712277748
Directory /workspace/9.prim_sync_fatal_alert/latest
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