Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 78
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.88 88.88 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/19.prim_async_alert.3377082101
91.41 2.53 100.00 0.00 93.75 0.00 100.00 0.00 82.14 3.57 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/14.prim_sync_alert.3949623455
93.31 1.90 100.00 0.00 95.83 2.08 100.00 0.00 82.14 0.00 95.83 0.00 86.05 9.30 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1453638205
94.50 1.19 100.00 0.00 95.83 0.00 100.00 0.00 89.29 7.14 95.83 0.00 86.05 0.00 /workspace/coverage/default/0.prim_async_alert.3664502547
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.722877686
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1033902240

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.2847312099
/workspace/coverage/default/10.prim_async_alert.597520733
/workspace/coverage/default/12.prim_async_alert.2574072191
/workspace/coverage/default/13.prim_async_alert.1604813994
/workspace/coverage/default/14.prim_async_alert.1685599924
/workspace/coverage/default/15.prim_async_alert.848169674
/workspace/coverage/default/16.prim_async_alert.2372872229
/workspace/coverage/default/17.prim_async_alert.2898409350
/workspace/coverage/default/18.prim_async_alert.3219564973
/workspace/coverage/default/2.prim_async_alert.3632959975
/workspace/coverage/default/3.prim_async_alert.1906922897
/workspace/coverage/default/4.prim_async_alert.1980807777
/workspace/coverage/default/5.prim_async_alert.1981979221
/workspace/coverage/default/6.prim_async_alert.60586664
/workspace/coverage/default/7.prim_async_alert.1095711511
/workspace/coverage/default/8.prim_async_alert.1130009651
/workspace/coverage/default/9.prim_async_alert.191666087
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.760083081
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2468447934
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3241176851
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4062292429
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1665631423
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1944980993
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.495742947
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3433644685
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1825972154
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1294394983
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3943629832
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3973331101
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1306015952
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4219491726
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4059093497
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2749819004
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1858908855
/workspace/coverage/sync_alert/0.prim_sync_alert.2578608687
/workspace/coverage/sync_alert/1.prim_sync_alert.2403465255
/workspace/coverage/sync_alert/10.prim_sync_alert.761148221
/workspace/coverage/sync_alert/11.prim_sync_alert.422126488
/workspace/coverage/sync_alert/12.prim_sync_alert.737038122
/workspace/coverage/sync_alert/13.prim_sync_alert.1743655299
/workspace/coverage/sync_alert/15.prim_sync_alert.3466578156
/workspace/coverage/sync_alert/16.prim_sync_alert.2126309406
/workspace/coverage/sync_alert/17.prim_sync_alert.3041292292
/workspace/coverage/sync_alert/18.prim_sync_alert.983730730
/workspace/coverage/sync_alert/19.prim_sync_alert.3422845451
/workspace/coverage/sync_alert/2.prim_sync_alert.264763632
/workspace/coverage/sync_alert/3.prim_sync_alert.3165999718
/workspace/coverage/sync_alert/4.prim_sync_alert.836422514
/workspace/coverage/sync_alert/5.prim_sync_alert.1996522429
/workspace/coverage/sync_alert/6.prim_sync_alert.2133824129
/workspace/coverage/sync_alert/7.prim_sync_alert.1259830728
/workspace/coverage/sync_alert/8.prim_sync_alert.208550479
/workspace/coverage/sync_alert/9.prim_sync_alert.2319585136
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2198177881
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.988243378
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3920087405
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.413693594
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1329978996
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1333468481
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.656779895
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2588451498
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1990544677
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3098099213
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2058651033
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.959754757
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2019391733
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1543672265
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.427616303
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3757552077
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.575159974
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3666040998
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.576931172



Total test records in report: 78
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/14.prim_async_alert.1685599924 Jun 26 04:17:49 PM PDT 24 Jun 26 04:17:51 PM PDT 24 10997971 ps
T2 /workspace/coverage/default/6.prim_async_alert.60586664 Jun 26 04:23:33 PM PDT 24 Jun 26 04:23:35 PM PDT 24 11098007 ps
T3 /workspace/coverage/default/4.prim_async_alert.1980807777 Jun 26 04:23:55 PM PDT 24 Jun 26 04:23:57 PM PDT 24 11614598 ps
T8 /workspace/coverage/default/19.prim_async_alert.3377082101 Jun 26 04:18:01 PM PDT 24 Jun 26 04:18:02 PM PDT 24 12155929 ps
T9 /workspace/coverage/default/13.prim_async_alert.1604813994 Jun 26 04:23:22 PM PDT 24 Jun 26 04:23:23 PM PDT 24 11594265 ps
T7 /workspace/coverage/default/0.prim_async_alert.3664502547 Jun 26 04:23:17 PM PDT 24 Jun 26 04:23:18 PM PDT 24 10382345 ps
T14 /workspace/coverage/default/2.prim_async_alert.3632959975 Jun 26 04:23:33 PM PDT 24 Jun 26 04:23:35 PM PDT 24 11534258 ps
T19 /workspace/coverage/default/10.prim_async_alert.597520733 Jun 26 04:23:54 PM PDT 24 Jun 26 04:23:55 PM PDT 24 10860652 ps
T20 /workspace/coverage/default/5.prim_async_alert.1981979221 Jun 26 04:23:39 PM PDT 24 Jun 26 04:23:41 PM PDT 24 11154336 ps
T21 /workspace/coverage/default/3.prim_async_alert.1906922897 Jun 26 04:19:30 PM PDT 24 Jun 26 04:19:31 PM PDT 24 10792479 ps
T17 /workspace/coverage/default/8.prim_async_alert.1130009651 Jun 26 04:23:33 PM PDT 24 Jun 26 04:23:34 PM PDT 24 11876724 ps
T46 /workspace/coverage/default/17.prim_async_alert.2898409350 Jun 26 04:23:59 PM PDT 24 Jun 26 04:24:00 PM PDT 24 11456109 ps
T47 /workspace/coverage/default/12.prim_async_alert.2574072191 Jun 26 04:23:43 PM PDT 24 Jun 26 04:23:45 PM PDT 24 10543023 ps
T22 /workspace/coverage/default/9.prim_async_alert.191666087 Jun 26 04:23:55 PM PDT 24 Jun 26 04:23:57 PM PDT 24 10033020 ps
T15 /workspace/coverage/default/16.prim_async_alert.2372872229 Jun 26 04:17:52 PM PDT 24 Jun 26 04:17:53 PM PDT 24 11045226 ps
T16 /workspace/coverage/default/18.prim_async_alert.3219564973 Jun 26 04:18:58 PM PDT 24 Jun 26 04:19:00 PM PDT 24 11257555 ps
T48 /workspace/coverage/default/1.prim_async_alert.2847312099 Jun 26 04:23:33 PM PDT 24 Jun 26 04:23:34 PM PDT 24 10977830 ps
T49 /workspace/coverage/default/15.prim_async_alert.848169674 Jun 26 04:19:09 PM PDT 24 Jun 26 04:19:10 PM PDT 24 11249522 ps
T11 /workspace/coverage/default/7.prim_async_alert.1095711511 Jun 26 04:23:55 PM PDT 24 Jun 26 04:23:57 PM PDT 24 11964256 ps
T42 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1306015952 Jun 26 04:17:56 PM PDT 24 Jun 26 04:17:58 PM PDT 24 28992033 ps
T18 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4219491726 Jun 26 04:18:58 PM PDT 24 Jun 26 04:19:00 PM PDT 24 30602899 ps
T12 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3433644685 Jun 26 04:21:11 PM PDT 24 Jun 26 04:21:12 PM PDT 24 32131127 ps
T13 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1453638205 Jun 26 04:23:52 PM PDT 24 Jun 26 04:23:53 PM PDT 24 30556470 ps
T23 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3973331101 Jun 26 04:18:47 PM PDT 24 Jun 26 04:18:48 PM PDT 24 31614832 ps
T24 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3241176851 Jun 26 04:24:11 PM PDT 24 Jun 26 04:24:13 PM PDT 24 29265791 ps
T43 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2749819004 Jun 26 04:22:57 PM PDT 24 Jun 26 04:22:58 PM PDT 24 29455942 ps
T44 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4062292429 Jun 26 04:23:55 PM PDT 24 Jun 26 04:23:57 PM PDT 24 31530624 ps
T40 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4059093497 Jun 26 04:17:56 PM PDT 24 Jun 26 04:17:57 PM PDT 24 28480643 ps
T45 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1944980993 Jun 26 04:23:47 PM PDT 24 Jun 26 04:23:48 PM PDT 24 30461661 ps
T50 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.760083081 Jun 26 04:17:56 PM PDT 24 Jun 26 04:17:57 PM PDT 24 28680906 ps
T51 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1294394983 Jun 26 04:17:58 PM PDT 24 Jun 26 04:18:00 PM PDT 24 31089657 ps
T4 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.722877686 Jun 26 04:23:38 PM PDT 24 Jun 26 04:23:39 PM PDT 24 29403945 ps
T52 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1825972154 Jun 26 04:19:08 PM PDT 24 Jun 26 04:19:09 PM PDT 24 30043808 ps
T53 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2468447934 Jun 26 04:23:58 PM PDT 24 Jun 26 04:23:59 PM PDT 24 31315564 ps
T54 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1665631423 Jun 26 04:23:12 PM PDT 24 Jun 26 04:23:14 PM PDT 24 32694776 ps
T55 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.495742947 Jun 26 04:21:14 PM PDT 24 Jun 26 04:21:15 PM PDT 24 32183212 ps
T41 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3943629832 Jun 26 04:19:11 PM PDT 24 Jun 26 04:19:12 PM PDT 24 30105794 ps
T56 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1858908855 Jun 26 04:19:06 PM PDT 24 Jun 26 04:19:08 PM PDT 24 31791280 ps
T25 /workspace/coverage/sync_alert/10.prim_sync_alert.761148221 Jun 26 04:19:16 PM PDT 24 Jun 26 04:19:17 PM PDT 24 8631724 ps
T26 /workspace/coverage/sync_alert/14.prim_sync_alert.3949623455 Jun 26 04:20:18 PM PDT 24 Jun 26 04:20:19 PM PDT 24 9940081 ps
T35 /workspace/coverage/sync_alert/17.prim_sync_alert.3041292292 Jun 26 04:20:02 PM PDT 24 Jun 26 04:20:03 PM PDT 24 9259326 ps
T27 /workspace/coverage/sync_alert/5.prim_sync_alert.1996522429 Jun 26 04:23:29 PM PDT 24 Jun 26 04:23:30 PM PDT 24 9130070 ps
T28 /workspace/coverage/sync_alert/0.prim_sync_alert.2578608687 Jun 26 04:18:17 PM PDT 24 Jun 26 04:18:19 PM PDT 24 8631113 ps
T36 /workspace/coverage/sync_alert/4.prim_sync_alert.836422514 Jun 26 04:23:14 PM PDT 24 Jun 26 04:23:16 PM PDT 24 8995025 ps
T37 /workspace/coverage/sync_alert/19.prim_sync_alert.3422845451 Jun 26 04:18:45 PM PDT 24 Jun 26 04:18:47 PM PDT 24 9275691 ps
T38 /workspace/coverage/sync_alert/1.prim_sync_alert.2403465255 Jun 26 04:23:42 PM PDT 24 Jun 26 04:23:44 PM PDT 24 9215111 ps
T29 /workspace/coverage/sync_alert/8.prim_sync_alert.208550479 Jun 26 04:25:02 PM PDT 24 Jun 26 04:25:03 PM PDT 24 9500094 ps
T39 /workspace/coverage/sync_alert/6.prim_sync_alert.2133824129 Jun 26 04:19:38 PM PDT 24 Jun 26 04:19:39 PM PDT 24 9760320 ps
T57 /workspace/coverage/sync_alert/11.prim_sync_alert.422126488 Jun 26 04:23:47 PM PDT 24 Jun 26 04:23:48 PM PDT 24 8680618 ps
T30 /workspace/coverage/sync_alert/16.prim_sync_alert.2126309406 Jun 26 04:23:02 PM PDT 24 Jun 26 04:23:03 PM PDT 24 10376141 ps
T58 /workspace/coverage/sync_alert/13.prim_sync_alert.1743655299 Jun 26 04:20:31 PM PDT 24 Jun 26 04:20:32 PM PDT 24 8686546 ps
T59 /workspace/coverage/sync_alert/12.prim_sync_alert.737038122 Jun 26 04:23:12 PM PDT 24 Jun 26 04:23:13 PM PDT 24 9319126 ps
T60 /workspace/coverage/sync_alert/7.prim_sync_alert.1259830728 Jun 26 04:21:30 PM PDT 24 Jun 26 04:21:31 PM PDT 24 8084263 ps
T31 /workspace/coverage/sync_alert/3.prim_sync_alert.3165999718 Jun 26 04:23:15 PM PDT 24 Jun 26 04:23:17 PM PDT 24 9550920 ps
T32 /workspace/coverage/sync_alert/18.prim_sync_alert.983730730 Jun 26 04:18:56 PM PDT 24 Jun 26 04:18:58 PM PDT 24 9643104 ps
T61 /workspace/coverage/sync_alert/2.prim_sync_alert.264763632 Jun 26 04:23:14 PM PDT 24 Jun 26 04:23:16 PM PDT 24 9886082 ps
T33 /workspace/coverage/sync_alert/15.prim_sync_alert.3466578156 Jun 26 04:20:29 PM PDT 24 Jun 26 04:20:30 PM PDT 24 9188820 ps
T34 /workspace/coverage/sync_alert/9.prim_sync_alert.2319585136 Jun 26 04:23:28 PM PDT 24 Jun 26 04:23:29 PM PDT 24 9473936 ps
T62 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.575159974 Jun 26 04:18:46 PM PDT 24 Jun 26 04:18:47 PM PDT 24 27090244 ps
T63 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1329978996 Jun 26 04:20:35 PM PDT 24 Jun 26 04:20:36 PM PDT 24 28558609 ps
T64 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2588451498 Jun 26 04:20:32 PM PDT 24 Jun 26 04:20:33 PM PDT 24 26939574 ps
T65 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.576931172 Jun 26 04:23:55 PM PDT 24 Jun 26 04:23:57 PM PDT 24 26149171 ps
T66 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2058651033 Jun 26 04:21:03 PM PDT 24 Jun 26 04:21:05 PM PDT 24 28301639 ps
T67 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3666040998 Jun 26 04:19:44 PM PDT 24 Jun 26 04:19:45 PM PDT 24 26752273 ps
T68 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.656779895 Jun 26 04:23:23 PM PDT 24 Jun 26 04:23:25 PM PDT 24 27073063 ps
T69 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3757552077 Jun 26 04:21:58 PM PDT 24 Jun 26 04:21:59 PM PDT 24 25268143 ps
T5 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.413693594 Jun 26 04:21:36 PM PDT 24 Jun 26 04:21:38 PM PDT 24 26880450 ps
T70 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.988243378 Jun 26 04:21:40 PM PDT 24 Jun 26 04:21:41 PM PDT 24 26880311 ps
T10 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1033902240 Jun 26 04:23:10 PM PDT 24 Jun 26 04:23:12 PM PDT 24 27547003 ps
T71 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1333468481 Jun 26 04:21:13 PM PDT 24 Jun 26 04:21:14 PM PDT 24 27205713 ps
T72 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1543672265 Jun 26 04:20:25 PM PDT 24 Jun 26 04:20:27 PM PDT 24 26250504 ps
T6 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.959754757 Jun 26 04:18:46 PM PDT 24 Jun 26 04:18:48 PM PDT 24 26799512 ps
T73 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.427616303 Jun 26 04:23:27 PM PDT 24 Jun 26 04:23:29 PM PDT 24 28064136 ps
T74 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2198177881 Jun 26 04:23:54 PM PDT 24 Jun 26 04:23:56 PM PDT 24 26822791 ps
T75 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1990544677 Jun 26 04:23:23 PM PDT 24 Jun 26 04:23:24 PM PDT 24 27473016 ps
T76 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3920087405 Jun 26 04:23:11 PM PDT 24 Jun 26 04:23:13 PM PDT 24 27622760 ps
T77 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2019391733 Jun 26 04:18:44 PM PDT 24 Jun 26 04:18:45 PM PDT 24 28795830 ps
T78 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3098099213 Jun 26 04:19:11 PM PDT 24 Jun 26 04:19:12 PM PDT 24 26928994 ps

Test location /workspace/coverage/default/19.prim_async_alert.3377082101
Short name T8
Test name
Test status
Simulation time 12155929 ps
CPU time 0.4 seconds
Started Jun 26 04:18:01 PM PDT 24
Finished Jun 26 04:18:02 PM PDT 24
Peak memory 145904 kb
Host smart-cca5e2c9-e3a4-4233-b4de-b49beea95e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377082101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3377082101
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3949623455
Short name T26
Test name
Test status
Simulation time 9940081 ps
CPU time 0.39 seconds
Started Jun 26 04:20:18 PM PDT 24
Finished Jun 26 04:20:19 PM PDT 24
Peak memory 145300 kb
Host smart-fe5cda48-7eae-43ac-9d7a-165ae817dd2a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3949623455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3949623455
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1453638205
Short name T13
Test name
Test status
Simulation time 30556470 ps
CPU time 0.42 seconds
Started Jun 26 04:23:52 PM PDT 24
Finished Jun 26 04:23:53 PM PDT 24
Peak memory 144880 kb
Host smart-13ea173f-7ab0-4a9b-baee-162876af6010
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1453638205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1453638205
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3664502547
Short name T7
Test name
Test status
Simulation time 10382345 ps
CPU time 0.42 seconds
Started Jun 26 04:23:17 PM PDT 24
Finished Jun 26 04:23:18 PM PDT 24
Peak memory 145172 kb
Host smart-cc5eb1af-d94f-4127-aeb2-ad5ecf0050ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664502547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3664502547
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.722877686
Short name T4
Test name
Test status
Simulation time 29403945 ps
CPU time 0.43 seconds
Started Jun 26 04:23:38 PM PDT 24
Finished Jun 26 04:23:39 PM PDT 24
Peak memory 144544 kb
Host smart-dff0c4c0-554d-4fb0-9565-51eab8bf162a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=722877686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.722877686
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1033902240
Short name T10
Test name
Test status
Simulation time 27547003 ps
CPU time 0.41 seconds
Started Jun 26 04:23:10 PM PDT 24
Finished Jun 26 04:23:12 PM PDT 24
Peak memory 145848 kb
Host smart-26c9f386-f74a-43c5-89fe-b7f788d5654f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1033902240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1033902240
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2847312099
Short name T48
Test name
Test status
Simulation time 10977830 ps
CPU time 0.38 seconds
Started Jun 26 04:23:33 PM PDT 24
Finished Jun 26 04:23:34 PM PDT 24
Peak memory 145424 kb
Host smart-d444c817-f9d8-4161-8256-dc30738af913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847312099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2847312099
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.597520733
Short name T19
Test name
Test status
Simulation time 10860652 ps
CPU time 0.37 seconds
Started Jun 26 04:23:54 PM PDT 24
Finished Jun 26 04:23:55 PM PDT 24
Peak memory 145424 kb
Host smart-9c02a7f7-db07-445e-9104-8b29ac29d618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597520733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.597520733
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2574072191
Short name T47
Test name
Test status
Simulation time 10543023 ps
CPU time 0.42 seconds
Started Jun 26 04:23:43 PM PDT 24
Finished Jun 26 04:23:45 PM PDT 24
Peak memory 145768 kb
Host smart-26674677-0f5d-4800-b425-0a228ec5a9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574072191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2574072191
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1604813994
Short name T9
Test name
Test status
Simulation time 11594265 ps
CPU time 0.41 seconds
Started Jun 26 04:23:22 PM PDT 24
Finished Jun 26 04:23:23 PM PDT 24
Peak memory 145240 kb
Host smart-25cc41d0-940e-4b08-b047-67c72f6b1de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604813994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1604813994
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1685599924
Short name T1
Test name
Test status
Simulation time 10997971 ps
CPU time 0.49 seconds
Started Jun 26 04:17:49 PM PDT 24
Finished Jun 26 04:17:51 PM PDT 24
Peak memory 145228 kb
Host smart-6ff5c385-c4ed-473e-a4ab-e14ad408e942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685599924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1685599924
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.848169674
Short name T49
Test name
Test status
Simulation time 11249522 ps
CPU time 0.43 seconds
Started Jun 26 04:19:09 PM PDT 24
Finished Jun 26 04:19:10 PM PDT 24
Peak memory 145888 kb
Host smart-61a38bc1-3afc-467f-8af5-a52152438e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848169674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.848169674
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2372872229
Short name T15
Test name
Test status
Simulation time 11045226 ps
CPU time 0.41 seconds
Started Jun 26 04:17:52 PM PDT 24
Finished Jun 26 04:17:53 PM PDT 24
Peak memory 145436 kb
Host smart-48b0cb6f-1298-44b9-adea-de21e727bb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372872229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2372872229
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2898409350
Short name T46
Test name
Test status
Simulation time 11456109 ps
CPU time 0.38 seconds
Started Jun 26 04:23:59 PM PDT 24
Finished Jun 26 04:24:00 PM PDT 24
Peak memory 145536 kb
Host smart-45512de2-7ebd-48b6-ba6e-e1f2820ed0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898409350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2898409350
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3219564973
Short name T16
Test name
Test status
Simulation time 11257555 ps
CPU time 0.44 seconds
Started Jun 26 04:18:58 PM PDT 24
Finished Jun 26 04:19:00 PM PDT 24
Peak memory 144116 kb
Host smart-52977966-edc2-4fe0-bfa7-12cc2f761434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219564973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3219564973
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3632959975
Short name T14
Test name
Test status
Simulation time 11534258 ps
CPU time 0.39 seconds
Started Jun 26 04:23:33 PM PDT 24
Finished Jun 26 04:23:35 PM PDT 24
Peak memory 145472 kb
Host smart-d6916a55-7cbe-48e0-877a-b6b267a69830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632959975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3632959975
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1906922897
Short name T21
Test name
Test status
Simulation time 10792479 ps
CPU time 0.39 seconds
Started Jun 26 04:19:30 PM PDT 24
Finished Jun 26 04:19:31 PM PDT 24
Peak memory 145512 kb
Host smart-066a87c8-feda-4273-b277-a32491015282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906922897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1906922897
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1980807777
Short name T3
Test name
Test status
Simulation time 11614598 ps
CPU time 0.39 seconds
Started Jun 26 04:23:55 PM PDT 24
Finished Jun 26 04:23:57 PM PDT 24
Peak memory 145480 kb
Host smart-b8b35b0b-09fa-4ba4-b025-f46121bfe9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980807777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1980807777
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1981979221
Short name T20
Test name
Test status
Simulation time 11154336 ps
CPU time 0.47 seconds
Started Jun 26 04:23:39 PM PDT 24
Finished Jun 26 04:23:41 PM PDT 24
Peak memory 145172 kb
Host smart-95e6f187-f4d8-4d88-b195-e9eddc5621b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981979221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1981979221
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.60586664
Short name T2
Test name
Test status
Simulation time 11098007 ps
CPU time 0.39 seconds
Started Jun 26 04:23:33 PM PDT 24
Finished Jun 26 04:23:35 PM PDT 24
Peak memory 145424 kb
Host smart-cfb7c033-4b94-4f83-bcfc-95a3a01951a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60586664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.60586664
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1095711511
Short name T11
Test name
Test status
Simulation time 11964256 ps
CPU time 0.42 seconds
Started Jun 26 04:23:55 PM PDT 24
Finished Jun 26 04:23:57 PM PDT 24
Peak memory 145424 kb
Host smart-2d8409ab-d779-4ec5-818e-9ec4aed731ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095711511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1095711511
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1130009651
Short name T17
Test name
Test status
Simulation time 11876724 ps
CPU time 0.39 seconds
Started Jun 26 04:23:33 PM PDT 24
Finished Jun 26 04:23:34 PM PDT 24
Peak memory 145424 kb
Host smart-02dff101-90f9-4cf1-826e-ce70edce0f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130009651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1130009651
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.191666087
Short name T22
Test name
Test status
Simulation time 10033020 ps
CPU time 0.39 seconds
Started Jun 26 04:23:55 PM PDT 24
Finished Jun 26 04:23:57 PM PDT 24
Peak memory 145424 kb
Host smart-3f6c9b9c-b559-4afc-ab52-026566582bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191666087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.191666087
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.760083081
Short name T50
Test name
Test status
Simulation time 28680906 ps
CPU time 0.4 seconds
Started Jun 26 04:17:56 PM PDT 24
Finished Jun 26 04:17:57 PM PDT 24
Peak memory 144404 kb
Host smart-f12523d1-0443-410a-a7ff-89a29464af5e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=760083081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.760083081
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2468447934
Short name T53
Test name
Test status
Simulation time 31315564 ps
CPU time 0.39 seconds
Started Jun 26 04:23:58 PM PDT 24
Finished Jun 26 04:23:59 PM PDT 24
Peak memory 145096 kb
Host smart-a27fe833-76d0-4548-8d40-46b8a8084b2d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2468447934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2468447934
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3241176851
Short name T24
Test name
Test status
Simulation time 29265791 ps
CPU time 0.4 seconds
Started Jun 26 04:24:11 PM PDT 24
Finished Jun 26 04:24:13 PM PDT 24
Peak memory 145104 kb
Host smart-d75d25c3-3da7-476d-bfae-307ccbc1b324
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3241176851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3241176851
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4062292429
Short name T44
Test name
Test status
Simulation time 31530624 ps
CPU time 0.43 seconds
Started Jun 26 04:23:55 PM PDT 24
Finished Jun 26 04:23:57 PM PDT 24
Peak memory 144880 kb
Host smart-318ceac3-296c-4558-967d-15eaa25d4ebb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4062292429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.4062292429
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1665631423
Short name T54
Test name
Test status
Simulation time 32694776 ps
CPU time 0.43 seconds
Started Jun 26 04:23:12 PM PDT 24
Finished Jun 26 04:23:14 PM PDT 24
Peak memory 144880 kb
Host smart-cd2f7c8e-5512-499e-b850-e965a103666f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1665631423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1665631423
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1944980993
Short name T45
Test name
Test status
Simulation time 30461661 ps
CPU time 0.43 seconds
Started Jun 26 04:23:47 PM PDT 24
Finished Jun 26 04:23:48 PM PDT 24
Peak memory 144856 kb
Host smart-7968bd4d-d52b-4065-bd4c-477f8ddf9295
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1944980993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1944980993
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.495742947
Short name T55
Test name
Test status
Simulation time 32183212 ps
CPU time 0.41 seconds
Started Jun 26 04:21:14 PM PDT 24
Finished Jun 26 04:21:15 PM PDT 24
Peak memory 145116 kb
Host smart-e762cc6d-3b6a-4843-8fc2-5a8860eaac72
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=495742947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.495742947
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3433644685
Short name T12
Test name
Test status
Simulation time 32131127 ps
CPU time 0.41 seconds
Started Jun 26 04:21:11 PM PDT 24
Finished Jun 26 04:21:12 PM PDT 24
Peak memory 145404 kb
Host smart-ee5f2983-3542-40bc-853a-b50de94a5f40
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3433644685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3433644685
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1825972154
Short name T52
Test name
Test status
Simulation time 30043808 ps
CPU time 0.41 seconds
Started Jun 26 04:19:08 PM PDT 24
Finished Jun 26 04:19:09 PM PDT 24
Peak memory 145028 kb
Host smart-2a9d1788-2940-4809-a621-583fb2856fbc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1825972154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1825972154
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1294394983
Short name T51
Test name
Test status
Simulation time 31089657 ps
CPU time 0.4 seconds
Started Jun 26 04:17:58 PM PDT 24
Finished Jun 26 04:18:00 PM PDT 24
Peak memory 145428 kb
Host smart-f804dad8-8adf-40a3-a953-51a7bafbef20
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1294394983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1294394983
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3943629832
Short name T41
Test name
Test status
Simulation time 30105794 ps
CPU time 0.39 seconds
Started Jun 26 04:19:11 PM PDT 24
Finished Jun 26 04:19:12 PM PDT 24
Peak memory 145072 kb
Host smart-c06b4e80-159d-4605-a0ab-de0de7a4d8aa
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3943629832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3943629832
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3973331101
Short name T23
Test name
Test status
Simulation time 31614832 ps
CPU time 0.41 seconds
Started Jun 26 04:18:47 PM PDT 24
Finished Jun 26 04:18:48 PM PDT 24
Peak memory 145400 kb
Host smart-352decfd-1e18-4bfd-8524-b590114de48d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3973331101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3973331101
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1306015952
Short name T42
Test name
Test status
Simulation time 28992033 ps
CPU time 0.39 seconds
Started Jun 26 04:17:56 PM PDT 24
Finished Jun 26 04:17:58 PM PDT 24
Peak memory 144792 kb
Host smart-38254a34-5950-4f70-a236-acbb9622a171
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1306015952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1306015952
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4219491726
Short name T18
Test name
Test status
Simulation time 30602899 ps
CPU time 0.42 seconds
Started Jun 26 04:18:58 PM PDT 24
Finished Jun 26 04:19:00 PM PDT 24
Peak memory 144388 kb
Host smart-d75bc150-bc25-4ea3-8323-7b8ae6858e10
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4219491726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.4219491726
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4059093497
Short name T40
Test name
Test status
Simulation time 28480643 ps
CPU time 0.41 seconds
Started Jun 26 04:17:56 PM PDT 24
Finished Jun 26 04:17:57 PM PDT 24
Peak memory 145428 kb
Host smart-66ac26de-4bd8-46b6-985d-0eb0ac983e87
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4059093497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.4059093497
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2749819004
Short name T43
Test name
Test status
Simulation time 29455942 ps
CPU time 0.41 seconds
Started Jun 26 04:22:57 PM PDT 24
Finished Jun 26 04:22:58 PM PDT 24
Peak memory 144588 kb
Host smart-538be4dd-253f-4278-b4d0-7561a92a175f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2749819004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2749819004
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1858908855
Short name T56
Test name
Test status
Simulation time 31791280 ps
CPU time 0.43 seconds
Started Jun 26 04:19:06 PM PDT 24
Finished Jun 26 04:19:08 PM PDT 24
Peak memory 145076 kb
Host smart-f54dcdec-105e-427f-828e-285be39b2df2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1858908855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1858908855
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2578608687
Short name T28
Test name
Test status
Simulation time 8631113 ps
CPU time 0.42 seconds
Started Jun 26 04:18:17 PM PDT 24
Finished Jun 26 04:18:19 PM PDT 24
Peak memory 146312 kb
Host smart-cb52f9c1-4530-495b-bf7a-461980c62758
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2578608687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2578608687
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2403465255
Short name T38
Test name
Test status
Simulation time 9215111 ps
CPU time 0.41 seconds
Started Jun 26 04:23:42 PM PDT 24
Finished Jun 26 04:23:44 PM PDT 24
Peak memory 145836 kb
Host smart-13a327f7-6411-49a4-a9a5-39694556ec90
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2403465255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2403465255
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.761148221
Short name T25
Test name
Test status
Simulation time 8631724 ps
CPU time 0.42 seconds
Started Jun 26 04:19:16 PM PDT 24
Finished Jun 26 04:19:17 PM PDT 24
Peak memory 145292 kb
Host smart-522445d8-e42e-4f2d-beb2-7fd6409b188b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=761148221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.761148221
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.422126488
Short name T57
Test name
Test status
Simulation time 8680618 ps
CPU time 0.37 seconds
Started Jun 26 04:23:47 PM PDT 24
Finished Jun 26 04:23:48 PM PDT 24
Peak memory 145084 kb
Host smart-f49e268d-4084-45d9-8c04-a30c474c487d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=422126488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.422126488
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.737038122
Short name T59
Test name
Test status
Simulation time 9319126 ps
CPU time 0.37 seconds
Started Jun 26 04:23:12 PM PDT 24
Finished Jun 26 04:23:13 PM PDT 24
Peak memory 144964 kb
Host smart-8c124e01-3ae7-4231-bbe3-3845fda4763b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=737038122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.737038122
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1743655299
Short name T58
Test name
Test status
Simulation time 8686546 ps
CPU time 0.37 seconds
Started Jun 26 04:20:31 PM PDT 24
Finished Jun 26 04:20:32 PM PDT 24
Peak memory 145332 kb
Host smart-c2c74258-f1d4-4025-a9f0-50bc32981be3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1743655299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1743655299
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3466578156
Short name T33
Test name
Test status
Simulation time 9188820 ps
CPU time 0.41 seconds
Started Jun 26 04:20:29 PM PDT 24
Finished Jun 26 04:20:30 PM PDT 24
Peak memory 145692 kb
Host smart-0033d5c6-a455-48fb-810a-26eac4c5498f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3466578156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3466578156
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2126309406
Short name T30
Test name
Test status
Simulation time 10376141 ps
CPU time 0.4 seconds
Started Jun 26 04:23:02 PM PDT 24
Finished Jun 26 04:23:03 PM PDT 24
Peak memory 145820 kb
Host smart-0bc8bb46-adea-433d-9b99-11dc8a58c030
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2126309406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2126309406
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3041292292
Short name T35
Test name
Test status
Simulation time 9259326 ps
CPU time 0.4 seconds
Started Jun 26 04:20:02 PM PDT 24
Finished Jun 26 04:20:03 PM PDT 24
Peak memory 145288 kb
Host smart-32505b84-8a90-43a3-b5ca-3f649e3abd1b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3041292292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3041292292
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.983730730
Short name T32
Test name
Test status
Simulation time 9643104 ps
CPU time 0.43 seconds
Started Jun 26 04:18:56 PM PDT 24
Finished Jun 26 04:18:58 PM PDT 24
Peak memory 145300 kb
Host smart-12dd86e5-f5d6-484a-92a2-483e2487ef09
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=983730730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.983730730
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3422845451
Short name T37
Test name
Test status
Simulation time 9275691 ps
CPU time 0.38 seconds
Started Jun 26 04:18:45 PM PDT 24
Finished Jun 26 04:18:47 PM PDT 24
Peak memory 145252 kb
Host smart-854ec0ab-ef97-457d-b9c1-0edb357ff6bb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3422845451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3422845451
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.264763632
Short name T61
Test name
Test status
Simulation time 9886082 ps
CPU time 0.37 seconds
Started Jun 26 04:23:14 PM PDT 24
Finished Jun 26 04:23:16 PM PDT 24
Peak memory 145940 kb
Host smart-9aab3be2-0577-4e75-94bb-b871b83fc517
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=264763632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.264763632
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3165999718
Short name T31
Test name
Test status
Simulation time 9550920 ps
CPU time 0.37 seconds
Started Jun 26 04:23:15 PM PDT 24
Finished Jun 26 04:23:17 PM PDT 24
Peak memory 145012 kb
Host smart-296ffd55-5c47-4feb-a034-e71f13c85c66
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3165999718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3165999718
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.836422514
Short name T36
Test name
Test status
Simulation time 8995025 ps
CPU time 0.36 seconds
Started Jun 26 04:23:14 PM PDT 24
Finished Jun 26 04:23:16 PM PDT 24
Peak memory 145992 kb
Host smart-c4f36453-c78a-48bc-865d-a0f761fb7aab
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=836422514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.836422514
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1996522429
Short name T27
Test name
Test status
Simulation time 9130070 ps
CPU time 0.37 seconds
Started Jun 26 04:23:29 PM PDT 24
Finished Jun 26 04:23:30 PM PDT 24
Peak memory 145040 kb
Host smart-ff55c1df-5a2c-47f6-a7bd-d8341a3e2044
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1996522429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1996522429
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2133824129
Short name T39
Test name
Test status
Simulation time 9760320 ps
CPU time 0.39 seconds
Started Jun 26 04:19:38 PM PDT 24
Finished Jun 26 04:19:39 PM PDT 24
Peak memory 145680 kb
Host smart-d20db787-1f7b-4854-96cf-1671cc672130
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2133824129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2133824129
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1259830728
Short name T60
Test name
Test status
Simulation time 8084263 ps
CPU time 0.39 seconds
Started Jun 26 04:21:30 PM PDT 24
Finished Jun 26 04:21:31 PM PDT 24
Peak memory 145288 kb
Host smart-a7d24a62-20e0-4dee-9785-34f1def9a6d1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1259830728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1259830728
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.208550479
Short name T29
Test name
Test status
Simulation time 9500094 ps
CPU time 0.38 seconds
Started Jun 26 04:25:02 PM PDT 24
Finished Jun 26 04:25:03 PM PDT 24
Peak memory 145216 kb
Host smart-cfb6d5c7-5951-4f81-b2e4-cd23063b6b91
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=208550479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.208550479
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2319585136
Short name T34
Test name
Test status
Simulation time 9473936 ps
CPU time 0.36 seconds
Started Jun 26 04:23:28 PM PDT 24
Finished Jun 26 04:23:29 PM PDT 24
Peak memory 144984 kb
Host smart-4ba6a5d6-2f99-4c45-ab91-7a614d27093d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2319585136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2319585136
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2198177881
Short name T74
Test name
Test status
Simulation time 26822791 ps
CPU time 0.42 seconds
Started Jun 26 04:23:54 PM PDT 24
Finished Jun 26 04:23:56 PM PDT 24
Peak memory 145836 kb
Host smart-29c6cc32-b7f1-4478-b470-19dc351b96c7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2198177881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2198177881
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.988243378
Short name T70
Test name
Test status
Simulation time 26880311 ps
CPU time 0.42 seconds
Started Jun 26 04:21:40 PM PDT 24
Finished Jun 26 04:21:41 PM PDT 24
Peak memory 145720 kb
Host smart-1887d8e0-e9ef-45da-869b-a1572d5b549c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=988243378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.988243378
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3920087405
Short name T76
Test name
Test status
Simulation time 27622760 ps
CPU time 0.44 seconds
Started Jun 26 04:23:11 PM PDT 24
Finished Jun 26 04:23:13 PM PDT 24
Peak memory 145848 kb
Host smart-ce928f73-cfeb-4c86-8d74-fd8185310f4a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3920087405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3920087405
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.413693594
Short name T5
Test name
Test status
Simulation time 26880450 ps
CPU time 0.4 seconds
Started Jun 26 04:21:36 PM PDT 24
Finished Jun 26 04:21:38 PM PDT 24
Peak memory 145304 kb
Host smart-902c60b4-9058-4e67-af00-aa135b7ce8b1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=413693594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.413693594
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1329978996
Short name T63
Test name
Test status
Simulation time 28558609 ps
CPU time 0.43 seconds
Started Jun 26 04:20:35 PM PDT 24
Finished Jun 26 04:20:36 PM PDT 24
Peak memory 145300 kb
Host smart-ef81abf5-8f0e-47fd-bdfd-2be32316e820
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1329978996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1329978996
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1333468481
Short name T71
Test name
Test status
Simulation time 27205713 ps
CPU time 0.42 seconds
Started Jun 26 04:21:13 PM PDT 24
Finished Jun 26 04:21:14 PM PDT 24
Peak memory 145316 kb
Host smart-4320d650-9913-4f9b-b658-9b2ddc61f1a6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1333468481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1333468481
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.656779895
Short name T68
Test name
Test status
Simulation time 27073063 ps
CPU time 0.39 seconds
Started Jun 26 04:23:23 PM PDT 24
Finished Jun 26 04:23:25 PM PDT 24
Peak memory 145184 kb
Host smart-8f0ee6a2-e7a8-4890-8f98-0fd839a832f1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=656779895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.656779895
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2588451498
Short name T64
Test name
Test status
Simulation time 26939574 ps
CPU time 0.4 seconds
Started Jun 26 04:20:32 PM PDT 24
Finished Jun 26 04:20:33 PM PDT 24
Peak memory 145296 kb
Host smart-90a068e7-4b19-48fb-9c6c-71b13947dcb6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2588451498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2588451498
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1990544677
Short name T75
Test name
Test status
Simulation time 27473016 ps
CPU time 0.46 seconds
Started Jun 26 04:23:23 PM PDT 24
Finished Jun 26 04:23:24 PM PDT 24
Peak memory 145848 kb
Host smart-8c2761a2-5b71-4eaf-ba2a-6741c9ad2952
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1990544677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1990544677
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3098099213
Short name T78
Test name
Test status
Simulation time 26928994 ps
CPU time 0.41 seconds
Started Jun 26 04:19:11 PM PDT 24
Finished Jun 26 04:19:12 PM PDT 24
Peak memory 145296 kb
Host smart-43fa7bea-8826-44ea-ae15-713149c7e4eb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3098099213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3098099213
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2058651033
Short name T66
Test name
Test status
Simulation time 28301639 ps
CPU time 0.41 seconds
Started Jun 26 04:21:03 PM PDT 24
Finished Jun 26 04:21:05 PM PDT 24
Peak memory 145304 kb
Host smart-ace0a386-5935-4a6c-90f8-6fec277fa6ac
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2058651033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2058651033
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.959754757
Short name T6
Test name
Test status
Simulation time 26799512 ps
CPU time 0.4 seconds
Started Jun 26 04:18:46 PM PDT 24
Finished Jun 26 04:18:48 PM PDT 24
Peak memory 145688 kb
Host smart-58303c02-a33a-4602-b1f2-a7b265fee1d3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=959754757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.959754757
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2019391733
Short name T77
Test name
Test status
Simulation time 28795830 ps
CPU time 0.4 seconds
Started Jun 26 04:18:44 PM PDT 24
Finished Jun 26 04:18:45 PM PDT 24
Peak memory 145156 kb
Host smart-a43cec5a-3561-45f5-bf53-1e2be9c4829c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2019391733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2019391733
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1543672265
Short name T72
Test name
Test status
Simulation time 26250504 ps
CPU time 0.42 seconds
Started Jun 26 04:20:25 PM PDT 24
Finished Jun 26 04:20:27 PM PDT 24
Peak memory 145228 kb
Host smart-991f051b-e2f4-47ec-81b2-ab7895cc9471
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1543672265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1543672265
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.427616303
Short name T73
Test name
Test status
Simulation time 28064136 ps
CPU time 0.44 seconds
Started Jun 26 04:23:27 PM PDT 24
Finished Jun 26 04:23:29 PM PDT 24
Peak memory 145836 kb
Host smart-4ec02ecf-b505-479a-999e-157b904eac2f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=427616303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.427616303
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3757552077
Short name T69
Test name
Test status
Simulation time 25268143 ps
CPU time 0.39 seconds
Started Jun 26 04:21:58 PM PDT 24
Finished Jun 26 04:21:59 PM PDT 24
Peak memory 145304 kb
Host smart-26f9783a-6118-4bdc-b944-23fd9946578b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3757552077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3757552077
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.575159974
Short name T62
Test name
Test status
Simulation time 27090244 ps
CPU time 0.42 seconds
Started Jun 26 04:18:46 PM PDT 24
Finished Jun 26 04:18:47 PM PDT 24
Peak memory 145688 kb
Host smart-b83b41c5-04d4-43e4-888c-0cfba066d571
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=575159974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.575159974
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3666040998
Short name T67
Test name
Test status
Simulation time 26752273 ps
CPU time 0.43 seconds
Started Jun 26 04:19:44 PM PDT 24
Finished Jun 26 04:19:45 PM PDT 24
Peak memory 145228 kb
Host smart-559ce861-30a2-4a2a-81c1-159352b03f80
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3666040998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3666040998
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.576931172
Short name T65
Test name
Test status
Simulation time 26149171 ps
CPU time 0.41 seconds
Started Jun 26 04:23:55 PM PDT 24
Finished Jun 26 04:23:57 PM PDT 24
Peak memory 145200 kb
Host smart-acf45d80-9d1a-4d04-b040-14b0e7894411
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=576931172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.576931172
Directory /workspace/9.prim_sync_fatal_alert/latest
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