Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.61 89.61 100.00 100.00 95.83 95.83 100.00 100.00 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/11.prim_async_alert.761669788
92.74 3.13 100.00 0.00 95.83 0.00 100.00 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/0.prim_sync_alert.3749929822
94.85 2.11 100.00 0.00 97.92 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1333907061

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3139145509
/workspace/coverage/default/1.prim_async_alert.4146714108
/workspace/coverage/default/10.prim_async_alert.2258432743
/workspace/coverage/default/12.prim_async_alert.556866919
/workspace/coverage/default/13.prim_async_alert.823049468
/workspace/coverage/default/14.prim_async_alert.207694029
/workspace/coverage/default/15.prim_async_alert.655259966
/workspace/coverage/default/16.prim_async_alert.823025307
/workspace/coverage/default/17.prim_async_alert.1474695420
/workspace/coverage/default/18.prim_async_alert.2084131028
/workspace/coverage/default/19.prim_async_alert.596594988
/workspace/coverage/default/2.prim_async_alert.485680811
/workspace/coverage/default/3.prim_async_alert.1912206361
/workspace/coverage/default/4.prim_async_alert.2092942018
/workspace/coverage/default/5.prim_async_alert.2152861922
/workspace/coverage/default/6.prim_async_alert.1250020167
/workspace/coverage/default/7.prim_async_alert.2565481088
/workspace/coverage/default/8.prim_async_alert.2582377547
/workspace/coverage/default/9.prim_async_alert.1688857010
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2868649897
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.382474066
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1246319317
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2628317503
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3763341294
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4244313075
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1795533522
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4054564934
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3905312845
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2990976272
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1570551979
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2824134481
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2833565162
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1722487105
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.143486254
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4243782753
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2596727910
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3131934891
/workspace/coverage/sync_alert/1.prim_sync_alert.3394094399
/workspace/coverage/sync_alert/10.prim_sync_alert.2949296258
/workspace/coverage/sync_alert/11.prim_sync_alert.892470806
/workspace/coverage/sync_alert/12.prim_sync_alert.3234008165
/workspace/coverage/sync_alert/13.prim_sync_alert.2388233467
/workspace/coverage/sync_alert/14.prim_sync_alert.3246661834
/workspace/coverage/sync_alert/15.prim_sync_alert.4272186931
/workspace/coverage/sync_alert/16.prim_sync_alert.2270117439
/workspace/coverage/sync_alert/17.prim_sync_alert.1246659498
/workspace/coverage/sync_alert/18.prim_sync_alert.3499987656
/workspace/coverage/sync_alert/19.prim_sync_alert.3411263960
/workspace/coverage/sync_alert/2.prim_sync_alert.2947171642
/workspace/coverage/sync_alert/3.prim_sync_alert.1615687504
/workspace/coverage/sync_alert/4.prim_sync_alert.127703142
/workspace/coverage/sync_alert/5.prim_sync_alert.1995082588
/workspace/coverage/sync_alert/6.prim_sync_alert.2752822325
/workspace/coverage/sync_alert/7.prim_sync_alert.1853387046
/workspace/coverage/sync_alert/8.prim_sync_alert.1555271525
/workspace/coverage/sync_alert/9.prim_sync_alert.2724732444
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2737441927
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1113491123
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.481388777
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2106735446
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1441062216
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3292221518
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2130864535
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4080800917
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2909683412
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.372301053
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2768238798
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1848096801
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2852417683
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2817049257
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2855546309
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1198682407
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3878591775
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.506822689
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2887732680
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1716865776



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/10.prim_async_alert.2258432743 Jun 27 04:23:21 PM PDT 24 Jun 27 04:23:32 PM PDT 24 13103996 ps
T2 /workspace/coverage/default/13.prim_async_alert.823049468 Jun 27 04:23:04 PM PDT 24 Jun 27 04:23:07 PM PDT 24 11420701 ps
T3 /workspace/coverage/default/19.prim_async_alert.596594988 Jun 27 04:20:44 PM PDT 24 Jun 27 04:20:46 PM PDT 24 12111343 ps
T12 /workspace/coverage/default/0.prim_async_alert.3139145509 Jun 27 04:20:00 PM PDT 24 Jun 27 04:20:02 PM PDT 24 10937258 ps
T7 /workspace/coverage/default/11.prim_async_alert.761669788 Jun 27 04:22:39 PM PDT 24 Jun 27 04:22:41 PM PDT 24 12172982 ps
T13 /workspace/coverage/default/4.prim_async_alert.2092942018 Jun 27 04:19:56 PM PDT 24 Jun 27 04:19:58 PM PDT 24 10993488 ps
T14 /workspace/coverage/default/6.prim_async_alert.1250020167 Jun 27 04:22:25 PM PDT 24 Jun 27 04:22:27 PM PDT 24 10933008 ps
T15 /workspace/coverage/default/3.prim_async_alert.1912206361 Jun 27 04:20:21 PM PDT 24 Jun 27 04:20:23 PM PDT 24 11190185 ps
T16 /workspace/coverage/default/5.prim_async_alert.2152861922 Jun 27 04:22:25 PM PDT 24 Jun 27 04:22:27 PM PDT 24 12212177 ps
T8 /workspace/coverage/default/9.prim_async_alert.1688857010 Jun 27 04:18:47 PM PDT 24 Jun 27 04:18:48 PM PDT 24 10331278 ps
T17 /workspace/coverage/default/16.prim_async_alert.823025307 Jun 27 04:21:25 PM PDT 24 Jun 27 04:21:26 PM PDT 24 10984466 ps
T18 /workspace/coverage/default/14.prim_async_alert.207694029 Jun 27 04:19:06 PM PDT 24 Jun 27 04:19:07 PM PDT 24 11200564 ps
T11 /workspace/coverage/default/2.prim_async_alert.485680811 Jun 27 04:23:07 PM PDT 24 Jun 27 04:23:12 PM PDT 24 11344372 ps
T23 /workspace/coverage/default/7.prim_async_alert.2565481088 Jun 27 04:23:07 PM PDT 24 Jun 27 04:23:12 PM PDT 24 11527319 ps
T9 /workspace/coverage/default/12.prim_async_alert.556866919 Jun 27 04:20:09 PM PDT 24 Jun 27 04:20:11 PM PDT 24 10521692 ps
T10 /workspace/coverage/default/8.prim_async_alert.2582377547 Jun 27 04:23:36 PM PDT 24 Jun 27 04:23:51 PM PDT 24 11895505 ps
T47 /workspace/coverage/default/1.prim_async_alert.4146714108 Jun 27 04:23:21 PM PDT 24 Jun 27 04:23:32 PM PDT 24 10665918 ps
T19 /workspace/coverage/default/15.prim_async_alert.655259966 Jun 27 04:21:16 PM PDT 24 Jun 27 04:21:17 PM PDT 24 11967230 ps
T48 /workspace/coverage/default/17.prim_async_alert.1474695420 Jun 27 04:23:34 PM PDT 24 Jun 27 04:23:50 PM PDT 24 10702347 ps
T49 /workspace/coverage/default/18.prim_async_alert.2084131028 Jun 27 04:22:49 PM PDT 24 Jun 27 04:22:52 PM PDT 24 11213235 ps
T20 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4243782753 Jun 27 04:22:56 PM PDT 24 Jun 27 04:22:57 PM PDT 24 29224029 ps
T21 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.382474066 Jun 27 04:19:52 PM PDT 24 Jun 27 04:19:53 PM PDT 24 32017474 ps
T41 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2990976272 Jun 27 04:17:44 PM PDT 24 Jun 27 04:17:45 PM PDT 24 31141469 ps
T4 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1333907061 Jun 27 04:17:26 PM PDT 24 Jun 27 04:17:28 PM PDT 24 30549567 ps
T22 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2868649897 Jun 27 04:23:35 PM PDT 24 Jun 27 04:23:50 PM PDT 24 30365276 ps
T42 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2833565162 Jun 27 04:22:49 PM PDT 24 Jun 27 04:22:52 PM PDT 24 26964112 ps
T43 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3131934891 Jun 27 04:21:51 PM PDT 24 Jun 27 04:21:53 PM PDT 24 30797194 ps
T44 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3763341294 Jun 27 04:17:34 PM PDT 24 Jun 27 04:17:38 PM PDT 24 30812605 ps
T45 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4244313075 Jun 27 04:23:03 PM PDT 24 Jun 27 04:23:07 PM PDT 24 31974033 ps
T46 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2596727910 Jun 27 04:22:41 PM PDT 24 Jun 27 04:22:45 PM PDT 24 29196244 ps
T5 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2824134481 Jun 27 04:17:37 PM PDT 24 Jun 27 04:17:41 PM PDT 24 29156995 ps
T50 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2628317503 Jun 27 04:17:47 PM PDT 24 Jun 27 04:17:49 PM PDT 24 30142009 ps
T51 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.143486254 Jun 27 04:22:33 PM PDT 24 Jun 27 04:22:35 PM PDT 24 29331436 ps
T40 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1570551979 Jun 27 04:20:28 PM PDT 24 Jun 27 04:20:30 PM PDT 24 31044156 ps
T52 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1795533522 Jun 27 04:21:15 PM PDT 24 Jun 27 04:21:16 PM PDT 24 30852875 ps
T53 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4054564934 Jun 27 04:19:40 PM PDT 24 Jun 27 04:19:42 PM PDT 24 31736268 ps
T54 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3905312845 Jun 27 04:19:40 PM PDT 24 Jun 27 04:19:42 PM PDT 24 30459459 ps
T55 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1246319317 Jun 27 04:21:53 PM PDT 24 Jun 27 04:21:55 PM PDT 24 27341814 ps
T56 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1722487105 Jun 27 04:22:33 PM PDT 24 Jun 27 04:22:35 PM PDT 24 29627410 ps
T33 /workspace/coverage/sync_alert/14.prim_sync_alert.3246661834 Jun 27 04:18:47 PM PDT 24 Jun 27 04:18:48 PM PDT 24 8970306 ps
T34 /workspace/coverage/sync_alert/15.prim_sync_alert.4272186931 Jun 27 04:20:04 PM PDT 24 Jun 27 04:20:06 PM PDT 24 9862181 ps
T35 /workspace/coverage/sync_alert/7.prim_sync_alert.1853387046 Jun 27 04:23:07 PM PDT 24 Jun 27 04:23:12 PM PDT 24 8944616 ps
T36 /workspace/coverage/sync_alert/5.prim_sync_alert.1995082588 Jun 27 04:23:07 PM PDT 24 Jun 27 04:23:12 PM PDT 24 9182884 ps
T24 /workspace/coverage/sync_alert/1.prim_sync_alert.3394094399 Jun 27 04:17:35 PM PDT 24 Jun 27 04:17:39 PM PDT 24 8932663 ps
T37 /workspace/coverage/sync_alert/6.prim_sync_alert.2752822325 Jun 27 04:19:23 PM PDT 24 Jun 27 04:19:24 PM PDT 24 8672189 ps
T38 /workspace/coverage/sync_alert/12.prim_sync_alert.3234008165 Jun 27 04:19:57 PM PDT 24 Jun 27 04:19:59 PM PDT 24 10564134 ps
T39 /workspace/coverage/sync_alert/3.prim_sync_alert.1615687504 Jun 27 04:18:53 PM PDT 24 Jun 27 04:18:54 PM PDT 24 8891475 ps
T25 /workspace/coverage/sync_alert/0.prim_sync_alert.3749929822 Jun 27 04:17:35 PM PDT 24 Jun 27 04:17:39 PM PDT 24 10354958 ps
T26 /workspace/coverage/sync_alert/13.prim_sync_alert.2388233467 Jun 27 04:23:08 PM PDT 24 Jun 27 04:23:12 PM PDT 24 9882546 ps
T27 /workspace/coverage/sync_alert/17.prim_sync_alert.1246659498 Jun 27 04:18:12 PM PDT 24 Jun 27 04:18:13 PM PDT 24 9343935 ps
T28 /workspace/coverage/sync_alert/4.prim_sync_alert.127703142 Jun 27 04:21:12 PM PDT 24 Jun 27 04:21:13 PM PDT 24 9349382 ps
T29 /workspace/coverage/sync_alert/16.prim_sync_alert.2270117439 Jun 27 04:23:21 PM PDT 24 Jun 27 04:23:32 PM PDT 24 10023159 ps
T57 /workspace/coverage/sync_alert/2.prim_sync_alert.2947171642 Jun 27 04:23:08 PM PDT 24 Jun 27 04:23:13 PM PDT 24 9641446 ps
T58 /workspace/coverage/sync_alert/19.prim_sync_alert.3411263960 Jun 27 04:19:43 PM PDT 24 Jun 27 04:19:44 PM PDT 24 10333818 ps
T59 /workspace/coverage/sync_alert/9.prim_sync_alert.2724732444 Jun 27 04:20:00 PM PDT 24 Jun 27 04:20:02 PM PDT 24 9578278 ps
T60 /workspace/coverage/sync_alert/18.prim_sync_alert.3499987656 Jun 27 04:19:53 PM PDT 24 Jun 27 04:19:54 PM PDT 24 8576907 ps
T61 /workspace/coverage/sync_alert/10.prim_sync_alert.2949296258 Jun 27 04:18:28 PM PDT 24 Jun 27 04:18:30 PM PDT 24 8871492 ps
T30 /workspace/coverage/sync_alert/11.prim_sync_alert.892470806 Jun 27 04:20:14 PM PDT 24 Jun 27 04:20:15 PM PDT 24 9318959 ps
T31 /workspace/coverage/sync_alert/8.prim_sync_alert.1555271525 Jun 27 04:19:22 PM PDT 24 Jun 27 04:19:24 PM PDT 24 8447911 ps
T62 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.506822689 Jun 27 04:20:28 PM PDT 24 Jun 27 04:20:29 PM PDT 24 27038510 ps
T32 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3292221518 Jun 27 04:22:42 PM PDT 24 Jun 27 04:22:46 PM PDT 24 27345982 ps
T63 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2887732680 Jun 27 04:22:49 PM PDT 24 Jun 27 04:22:51 PM PDT 24 27417933 ps
T64 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2817049257 Jun 27 04:18:30 PM PDT 24 Jun 27 04:18:32 PM PDT 24 27163459 ps
T6 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2909683412 Jun 27 04:21:23 PM PDT 24 Jun 27 04:21:25 PM PDT 24 25596226 ps
T65 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1441062216 Jun 27 04:22:38 PM PDT 24 Jun 27 04:22:40 PM PDT 24 27736849 ps
T66 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.372301053 Jun 27 04:21:50 PM PDT 24 Jun 27 04:21:52 PM PDT 24 27629764 ps
T67 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2852417683 Jun 27 04:23:20 PM PDT 24 Jun 27 04:23:31 PM PDT 24 29897154 ps
T68 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1716865776 Jun 27 04:22:49 PM PDT 24 Jun 27 04:22:52 PM PDT 24 26865811 ps
T69 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2737441927 Jun 27 04:23:04 PM PDT 24 Jun 27 04:23:07 PM PDT 24 28482692 ps
T70 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2855546309 Jun 27 04:20:43 PM PDT 24 Jun 27 04:20:45 PM PDT 24 27199138 ps
T71 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2768238798 Jun 27 04:21:50 PM PDT 24 Jun 27 04:21:52 PM PDT 24 28053853 ps
T72 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1848096801 Jun 27 04:21:35 PM PDT 24 Jun 27 04:21:36 PM PDT 24 29507094 ps
T73 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4080800917 Jun 27 04:19:17 PM PDT 24 Jun 27 04:19:19 PM PDT 24 28033284 ps
T74 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3878591775 Jun 27 04:20:23 PM PDT 24 Jun 27 04:20:25 PM PDT 24 26799328 ps
T75 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1113491123 Jun 27 04:23:04 PM PDT 24 Jun 27 04:23:07 PM PDT 24 28611684 ps
T76 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2130864535 Jun 27 04:19:12 PM PDT 24 Jun 27 04:19:13 PM PDT 24 27998637 ps
T77 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.481388777 Jun 27 04:22:41 PM PDT 24 Jun 27 04:22:45 PM PDT 24 28946732 ps
T78 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2106735446 Jun 27 04:22:40 PM PDT 24 Jun 27 04:22:42 PM PDT 24 27988413 ps
T79 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1198682407 Jun 27 04:18:30 PM PDT 24 Jun 27 04:18:32 PM PDT 24 27375899 ps

Test location /workspace/coverage/default/11.prim_async_alert.761669788
Short name T7
Test name
Test status
Simulation time 12172982 ps
CPU time 0.38 seconds
Started Jun 27 04:22:39 PM PDT 24
Finished Jun 27 04:22:41 PM PDT 24
Peak memory 145640 kb
Host smart-b2a15cfe-183a-4d47-b15e-deac8b3b93c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761669788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.761669788
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3749929822
Short name T25
Test name
Test status
Simulation time 10354958 ps
CPU time 0.37 seconds
Started Jun 27 04:17:35 PM PDT 24
Finished Jun 27 04:17:39 PM PDT 24
Peak memory 145488 kb
Host smart-c3fda3ee-ced3-40aa-a360-ad3033619db5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3749929822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3749929822
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1333907061
Short name T4
Test name
Test status
Simulation time 30549567 ps
CPU time 0.48 seconds
Started Jun 27 04:17:26 PM PDT 24
Finished Jun 27 04:17:28 PM PDT 24
Peak memory 144216 kb
Host smart-7bd2c146-acaf-4ca7-9146-640408e7308b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1333907061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1333907061
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3139145509
Short name T12
Test name
Test status
Simulation time 10937258 ps
CPU time 0.4 seconds
Started Jun 27 04:20:00 PM PDT 24
Finished Jun 27 04:20:02 PM PDT 24
Peak memory 145636 kb
Host smart-cd4182b6-cf9c-4db6-954d-9404c54ce8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139145509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3139145509
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.4146714108
Short name T47
Test name
Test status
Simulation time 10665918 ps
CPU time 0.37 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:32 PM PDT 24
Peak memory 145596 kb
Host smart-ba9bfc20-646d-46db-b4b5-076ecf7b6ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146714108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.4146714108
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2258432743
Short name T1
Test name
Test status
Simulation time 13103996 ps
CPU time 0.38 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:32 PM PDT 24
Peak memory 145420 kb
Host smart-194f0cc0-4fb4-4147-a0e9-86d4ba0e2a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258432743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2258432743
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.556866919
Short name T9
Test name
Test status
Simulation time 10521692 ps
CPU time 0.38 seconds
Started Jun 27 04:20:09 PM PDT 24
Finished Jun 27 04:20:11 PM PDT 24
Peak memory 145728 kb
Host smart-4cbe80ab-e747-4bdc-a7c8-2a396777462d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556866919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.556866919
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.823049468
Short name T2
Test name
Test status
Simulation time 11420701 ps
CPU time 0.43 seconds
Started Jun 27 04:23:04 PM PDT 24
Finished Jun 27 04:23:07 PM PDT 24
Peak memory 145636 kb
Host smart-4df3df9a-ee1f-4a9c-91ee-16186e47d2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823049468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.823049468
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.207694029
Short name T18
Test name
Test status
Simulation time 11200564 ps
CPU time 0.42 seconds
Started Jun 27 04:19:06 PM PDT 24
Finished Jun 27 04:19:07 PM PDT 24
Peak memory 145648 kb
Host smart-6961c124-c7f8-466f-b340-2a53c1299785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207694029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.207694029
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.655259966
Short name T19
Test name
Test status
Simulation time 11967230 ps
CPU time 0.4 seconds
Started Jun 27 04:21:16 PM PDT 24
Finished Jun 27 04:21:17 PM PDT 24
Peak memory 145884 kb
Host smart-588bd332-3fea-462a-b321-ed73077d3fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655259966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.655259966
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.823025307
Short name T17
Test name
Test status
Simulation time 10984466 ps
CPU time 0.42 seconds
Started Jun 27 04:21:25 PM PDT 24
Finished Jun 27 04:21:26 PM PDT 24
Peak memory 145628 kb
Host smart-4dd3d282-60e2-44dd-a302-a335ae474f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823025307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.823025307
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1474695420
Short name T48
Test name
Test status
Simulation time 10702347 ps
CPU time 0.37 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 145348 kb
Host smart-e43bc544-d147-4471-b2f2-26674f66b835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474695420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1474695420
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2084131028
Short name T49
Test name
Test status
Simulation time 11213235 ps
CPU time 0.39 seconds
Started Jun 27 04:22:49 PM PDT 24
Finished Jun 27 04:22:52 PM PDT 24
Peak memory 145432 kb
Host smart-a6933509-a878-441d-9705-58a7ba9f499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084131028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2084131028
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.596594988
Short name T3
Test name
Test status
Simulation time 12111343 ps
CPU time 0.4 seconds
Started Jun 27 04:20:44 PM PDT 24
Finished Jun 27 04:20:46 PM PDT 24
Peak memory 145644 kb
Host smart-bad3e760-21fc-4414-a228-6a83703bf6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596594988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.596594988
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.485680811
Short name T11
Test name
Test status
Simulation time 11344372 ps
CPU time 0.37 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 144832 kb
Host smart-528b2720-8874-44cf-9a62-dc8493a085cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485680811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.485680811
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1912206361
Short name T15
Test name
Test status
Simulation time 11190185 ps
CPU time 0.39 seconds
Started Jun 27 04:20:21 PM PDT 24
Finished Jun 27 04:20:23 PM PDT 24
Peak memory 145644 kb
Host smart-c3388405-4411-4d61-93b3-5257d604dee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912206361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1912206361
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2092942018
Short name T13
Test name
Test status
Simulation time 10993488 ps
CPU time 0.4 seconds
Started Jun 27 04:19:56 PM PDT 24
Finished Jun 27 04:19:58 PM PDT 24
Peak memory 145612 kb
Host smart-a7784bde-1837-4b7b-8350-a832011cace2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092942018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2092942018
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2152861922
Short name T16
Test name
Test status
Simulation time 12212177 ps
CPU time 0.41 seconds
Started Jun 27 04:22:25 PM PDT 24
Finished Jun 27 04:22:27 PM PDT 24
Peak memory 143468 kb
Host smart-1bf051eb-0d00-48f5-ae6c-a54ff4312329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152861922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2152861922
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1250020167
Short name T14
Test name
Test status
Simulation time 10933008 ps
CPU time 0.43 seconds
Started Jun 27 04:22:25 PM PDT 24
Finished Jun 27 04:22:27 PM PDT 24
Peak memory 143516 kb
Host smart-4755750c-d91e-4d70-b310-3e6bab32216d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250020167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1250020167
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2565481088
Short name T23
Test name
Test status
Simulation time 11527319 ps
CPU time 0.37 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 145300 kb
Host smart-b12902b6-83f3-41d0-aef0-f1808f80fb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565481088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2565481088
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2582377547
Short name T10
Test name
Test status
Simulation time 11895505 ps
CPU time 0.37 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:23:51 PM PDT 24
Peak memory 145340 kb
Host smart-5f33c14c-ac94-42e2-8512-bea04f06d273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582377547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2582377547
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1688857010
Short name T8
Test name
Test status
Simulation time 10331278 ps
CPU time 0.39 seconds
Started Jun 27 04:18:47 PM PDT 24
Finished Jun 27 04:18:48 PM PDT 24
Peak memory 145636 kb
Host smart-bdbbdd54-5689-496e-b1d7-0e76b3332621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688857010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1688857010
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2868649897
Short name T22
Test name
Test status
Simulation time 30365276 ps
CPU time 0.38 seconds
Started Jun 27 04:23:35 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 144932 kb
Host smart-af8f8e48-074d-4da4-842f-dfaa13478a86
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2868649897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2868649897
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.382474066
Short name T21
Test name
Test status
Simulation time 32017474 ps
CPU time 0.45 seconds
Started Jun 27 04:19:52 PM PDT 24
Finished Jun 27 04:19:53 PM PDT 24
Peak memory 145224 kb
Host smart-22143bf3-8e7b-46c5-921a-e7c879f94009
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=382474066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.382474066
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1246319317
Short name T55
Test name
Test status
Simulation time 27341814 ps
CPU time 0.4 seconds
Started Jun 27 04:21:53 PM PDT 24
Finished Jun 27 04:21:55 PM PDT 24
Peak memory 145204 kb
Host smart-68430695-506e-4510-9cd2-834d31de9184
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1246319317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1246319317
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2628317503
Short name T50
Test name
Test status
Simulation time 30142009 ps
CPU time 0.38 seconds
Started Jun 27 04:17:47 PM PDT 24
Finished Jun 27 04:17:49 PM PDT 24
Peak memory 145204 kb
Host smart-ff4f36fc-d3fb-45c0-84a6-e1bc3c16d87c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2628317503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2628317503
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3763341294
Short name T44
Test name
Test status
Simulation time 30812605 ps
CPU time 0.4 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:17:38 PM PDT 24
Peak memory 145256 kb
Host smart-8a594a57-e91c-4bb8-abb8-eb6f097165be
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3763341294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3763341294
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4244313075
Short name T45
Test name
Test status
Simulation time 31974033 ps
CPU time 0.45 seconds
Started Jun 27 04:23:03 PM PDT 24
Finished Jun 27 04:23:07 PM PDT 24
Peak memory 143880 kb
Host smart-61e10e1a-19bd-4aac-a3ab-578ca0222e9b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4244313075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.4244313075
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1795533522
Short name T52
Test name
Test status
Simulation time 30852875 ps
CPU time 0.4 seconds
Started Jun 27 04:21:15 PM PDT 24
Finished Jun 27 04:21:16 PM PDT 24
Peak memory 145260 kb
Host smart-3ac9290c-62ff-4180-8c3c-0e1ce8a53678
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1795533522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1795533522
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4054564934
Short name T53
Test name
Test status
Simulation time 31736268 ps
CPU time 0.41 seconds
Started Jun 27 04:19:40 PM PDT 24
Finished Jun 27 04:19:42 PM PDT 24
Peak memory 145204 kb
Host smart-0edc683b-0c91-4f3c-b705-c3f8f4aa7d4d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4054564934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.4054564934
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3905312845
Short name T54
Test name
Test status
Simulation time 30459459 ps
CPU time 0.42 seconds
Started Jun 27 04:19:40 PM PDT 24
Finished Jun 27 04:19:42 PM PDT 24
Peak memory 145204 kb
Host smart-81e2e99d-15f6-442b-9773-4813e1127586
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3905312845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3905312845
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2990976272
Short name T41
Test name
Test status
Simulation time 31141469 ps
CPU time 0.4 seconds
Started Jun 27 04:17:44 PM PDT 24
Finished Jun 27 04:17:45 PM PDT 24
Peak memory 145204 kb
Host smart-7aa6c6e7-acde-4a5b-97a1-694068184b66
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2990976272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2990976272
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1570551979
Short name T40
Test name
Test status
Simulation time 31044156 ps
CPU time 0.4 seconds
Started Jun 27 04:20:28 PM PDT 24
Finished Jun 27 04:20:30 PM PDT 24
Peak memory 145192 kb
Host smart-d8b4eec8-9869-42eb-917f-e5cab1314c13
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1570551979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1570551979
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2824134481
Short name T5
Test name
Test status
Simulation time 29156995 ps
CPU time 0.4 seconds
Started Jun 27 04:17:37 PM PDT 24
Finished Jun 27 04:17:41 PM PDT 24
Peak memory 145192 kb
Host smart-b62b07c1-ee39-43a0-83b8-8f9d7f540452
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2824134481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2824134481
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2833565162
Short name T42
Test name
Test status
Simulation time 26964112 ps
CPU time 0.4 seconds
Started Jun 27 04:22:49 PM PDT 24
Finished Jun 27 04:22:52 PM PDT 24
Peak memory 145000 kb
Host smart-58ffd01b-64f7-4257-9209-f976b4bbf3d3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2833565162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2833565162
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1722487105
Short name T56
Test name
Test status
Simulation time 29627410 ps
CPU time 0.42 seconds
Started Jun 27 04:22:33 PM PDT 24
Finished Jun 27 04:22:35 PM PDT 24
Peak memory 144524 kb
Host smart-bc3ad9c1-931f-4930-8f1c-bf78f3352b4f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1722487105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1722487105
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.143486254
Short name T51
Test name
Test status
Simulation time 29331436 ps
CPU time 0.48 seconds
Started Jun 27 04:22:33 PM PDT 24
Finished Jun 27 04:22:35 PM PDT 24
Peak memory 145476 kb
Host smart-d8507bdd-96a7-4c7b-b469-10fc221146d0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=143486254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.143486254
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4243782753
Short name T20
Test name
Test status
Simulation time 29224029 ps
CPU time 0.38 seconds
Started Jun 27 04:22:56 PM PDT 24
Finished Jun 27 04:22:57 PM PDT 24
Peak memory 145212 kb
Host smart-6c22ba69-8d31-4f50-9d3d-520bf33f4e0b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4243782753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.4243782753
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2596727910
Short name T46
Test name
Test status
Simulation time 29196244 ps
CPU time 0.45 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:45 PM PDT 24
Peak memory 144008 kb
Host smart-498f8992-299b-4ded-af78-5f3a9c353a8e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2596727910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2596727910
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3131934891
Short name T43
Test name
Test status
Simulation time 30797194 ps
CPU time 0.43 seconds
Started Jun 27 04:21:51 PM PDT 24
Finished Jun 27 04:21:53 PM PDT 24
Peak memory 145224 kb
Host smart-d4b8142e-3f61-4b30-b9d3-ac94e0da3d3c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3131934891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3131934891
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3394094399
Short name T24
Test name
Test status
Simulation time 8932663 ps
CPU time 0.37 seconds
Started Jun 27 04:17:35 PM PDT 24
Finished Jun 27 04:17:39 PM PDT 24
Peak memory 145488 kb
Host smart-c12aec45-24b5-484e-90f4-b43789a57cdb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3394094399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3394094399
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2949296258
Short name T61
Test name
Test status
Simulation time 8871492 ps
CPU time 0.38 seconds
Started Jun 27 04:18:28 PM PDT 24
Finished Jun 27 04:18:30 PM PDT 24
Peak memory 145512 kb
Host smart-46567c6d-f5d9-4276-8582-08f8682c4c05
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2949296258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2949296258
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.892470806
Short name T30
Test name
Test status
Simulation time 9318959 ps
CPU time 0.4 seconds
Started Jun 27 04:20:14 PM PDT 24
Finished Jun 27 04:20:15 PM PDT 24
Peak memory 145456 kb
Host smart-0c03114f-c7e1-4bb9-bf92-8ceb61540984
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=892470806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.892470806
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3234008165
Short name T38
Test name
Test status
Simulation time 10564134 ps
CPU time 0.38 seconds
Started Jun 27 04:19:57 PM PDT 24
Finished Jun 27 04:19:59 PM PDT 24
Peak memory 145448 kb
Host smart-9f49186a-6698-4b59-b04f-7ee4066b5523
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3234008165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3234008165
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2388233467
Short name T26
Test name
Test status
Simulation time 9882546 ps
CPU time 0.36 seconds
Started Jun 27 04:23:08 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 145140 kb
Host smart-338c8cb1-daa0-42c8-bf84-210dbd6ec43e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2388233467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2388233467
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3246661834
Short name T33
Test name
Test status
Simulation time 8970306 ps
CPU time 0.4 seconds
Started Jun 27 04:18:47 PM PDT 24
Finished Jun 27 04:18:48 PM PDT 24
Peak memory 145444 kb
Host smart-e4bdd0c9-3844-4f50-b8a8-c7e013ba173c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3246661834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3246661834
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.4272186931
Short name T34
Test name
Test status
Simulation time 9862181 ps
CPU time 0.41 seconds
Started Jun 27 04:20:04 PM PDT 24
Finished Jun 27 04:20:06 PM PDT 24
Peak memory 145444 kb
Host smart-92ca6de0-0a96-47a4-a4c4-a3d3cb731dd7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4272186931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.4272186931
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2270117439
Short name T29
Test name
Test status
Simulation time 10023159 ps
CPU time 0.37 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:32 PM PDT 24
Peak memory 145168 kb
Host smart-67b9b23b-d3ca-4aa2-9d91-0752805076f3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2270117439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2270117439
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1246659498
Short name T27
Test name
Test status
Simulation time 9343935 ps
CPU time 0.41 seconds
Started Jun 27 04:18:12 PM PDT 24
Finished Jun 27 04:18:13 PM PDT 24
Peak memory 145432 kb
Host smart-60cd2c84-4bd7-4bfe-b9de-70ceeb94238c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1246659498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1246659498
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3499987656
Short name T60
Test name
Test status
Simulation time 8576907 ps
CPU time 0.38 seconds
Started Jun 27 04:19:53 PM PDT 24
Finished Jun 27 04:19:54 PM PDT 24
Peak memory 145444 kb
Host smart-86c02e79-9703-4e7f-af67-e2a0a0762d72
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3499987656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3499987656
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3411263960
Short name T58
Test name
Test status
Simulation time 10333818 ps
CPU time 0.4 seconds
Started Jun 27 04:19:43 PM PDT 24
Finished Jun 27 04:19:44 PM PDT 24
Peak memory 145444 kb
Host smart-210fecff-f9e4-4c8f-8ffb-d379b875348b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3411263960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3411263960
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2947171642
Short name T57
Test name
Test status
Simulation time 9641446 ps
CPU time 0.37 seconds
Started Jun 27 04:23:08 PM PDT 24
Finished Jun 27 04:23:13 PM PDT 24
Peak memory 145180 kb
Host smart-94517e15-28d1-441e-b7f1-67d248d07773
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2947171642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2947171642
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1615687504
Short name T39
Test name
Test status
Simulation time 8891475 ps
CPU time 0.39 seconds
Started Jun 27 04:18:53 PM PDT 24
Finished Jun 27 04:18:54 PM PDT 24
Peak memory 145448 kb
Host smart-76321201-04c7-4806-a83a-dde8dc356aa6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1615687504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1615687504
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.127703142
Short name T28
Test name
Test status
Simulation time 9349382 ps
CPU time 0.39 seconds
Started Jun 27 04:21:12 PM PDT 24
Finished Jun 27 04:21:13 PM PDT 24
Peak memory 145444 kb
Host smart-4eddb4fe-dfd0-4a2e-854a-5858363af110
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=127703142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.127703142
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1995082588
Short name T36
Test name
Test status
Simulation time 9182884 ps
CPU time 0.42 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 143892 kb
Host smart-da433e58-5632-4d19-bb36-be635a0679ce
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1995082588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1995082588
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2752822325
Short name T37
Test name
Test status
Simulation time 8672189 ps
CPU time 0.41 seconds
Started Jun 27 04:19:23 PM PDT 24
Finished Jun 27 04:19:24 PM PDT 24
Peak memory 145684 kb
Host smart-94120691-2559-4e38-bd79-736f1e3b9244
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2752822325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2752822325
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1853387046
Short name T35
Test name
Test status
Simulation time 8944616 ps
CPU time 0.45 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 144044 kb
Host smart-08a42d9d-efb8-4a98-a429-438c9fbab0dd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1853387046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1853387046
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1555271525
Short name T31
Test name
Test status
Simulation time 8447911 ps
CPU time 0.4 seconds
Started Jun 27 04:19:22 PM PDT 24
Finished Jun 27 04:19:24 PM PDT 24
Peak memory 145684 kb
Host smart-895681c2-a8eb-406f-bd11-31c9724d18a2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1555271525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1555271525
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2724732444
Short name T59
Test name
Test status
Simulation time 9578278 ps
CPU time 0.39 seconds
Started Jun 27 04:20:00 PM PDT 24
Finished Jun 27 04:20:02 PM PDT 24
Peak memory 145448 kb
Host smart-6ad8f874-02e5-4e8f-9198-48b628006a46
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2724732444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2724732444
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2737441927
Short name T69
Test name
Test status
Simulation time 28482692 ps
CPU time 0.44 seconds
Started Jun 27 04:23:04 PM PDT 24
Finished Jun 27 04:23:07 PM PDT 24
Peak memory 144716 kb
Host smart-c22a6264-0dd0-4587-a87b-2500eb3420fe
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2737441927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2737441927
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1113491123
Short name T75
Test name
Test status
Simulation time 28611684 ps
CPU time 0.41 seconds
Started Jun 27 04:23:04 PM PDT 24
Finished Jun 27 04:23:07 PM PDT 24
Peak memory 145732 kb
Host smart-3c79e7cd-537a-4ab8-bb6b-57bcda58a1b6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1113491123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1113491123
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.481388777
Short name T77
Test name
Test status
Simulation time 28946732 ps
CPU time 0.38 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:45 PM PDT 24
Peak memory 145220 kb
Host smart-5fd2e89b-1963-482b-8e13-d5b796e4927d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=481388777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.481388777
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2106735446
Short name T78
Test name
Test status
Simulation time 27988413 ps
CPU time 0.41 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:22:42 PM PDT 24
Peak memory 144352 kb
Host smart-c0b271f9-d0a9-48ff-868b-5a29fa4872f5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2106735446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2106735446
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1441062216
Short name T65
Test name
Test status
Simulation time 27736849 ps
CPU time 0.41 seconds
Started Jun 27 04:22:38 PM PDT 24
Finished Jun 27 04:22:40 PM PDT 24
Peak memory 144372 kb
Host smart-cac93b93-872c-433e-9c34-41c873a87847
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1441062216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1441062216
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3292221518
Short name T32
Test name
Test status
Simulation time 27345982 ps
CPU time 0.39 seconds
Started Jun 27 04:22:42 PM PDT 24
Finished Jun 27 04:22:46 PM PDT 24
Peak memory 145188 kb
Host smart-292a8353-1cc1-4206-a359-69dad2c23a80
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3292221518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3292221518
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2130864535
Short name T76
Test name
Test status
Simulation time 27998637 ps
CPU time 0.41 seconds
Started Jun 27 04:19:12 PM PDT 24
Finished Jun 27 04:19:13 PM PDT 24
Peak memory 145456 kb
Host smart-56926e3d-dd1a-4f3b-849c-e723a3bba12f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2130864535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2130864535
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4080800917
Short name T73
Test name
Test status
Simulation time 28033284 ps
CPU time 0.4 seconds
Started Jun 27 04:19:17 PM PDT 24
Finished Jun 27 04:19:19 PM PDT 24
Peak memory 145464 kb
Host smart-cbf49607-b139-4d95-9f3c-6fd672c72119
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4080800917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.4080800917
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2909683412
Short name T6
Test name
Test status
Simulation time 25596226 ps
CPU time 0.42 seconds
Started Jun 27 04:21:23 PM PDT 24
Finished Jun 27 04:21:25 PM PDT 24
Peak memory 145688 kb
Host smart-27159f8e-37f1-46ae-bd8f-1b7dd8c049da
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2909683412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2909683412
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.372301053
Short name T66
Test name
Test status
Simulation time 27629764 ps
CPU time 0.5 seconds
Started Jun 27 04:21:50 PM PDT 24
Finished Jun 27 04:21:52 PM PDT 24
Peak memory 145684 kb
Host smart-add40e86-5d26-4d10-8a77-3abb1a709cd6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=372301053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.372301053
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2768238798
Short name T71
Test name
Test status
Simulation time 28053853 ps
CPU time 0.44 seconds
Started Jun 27 04:21:50 PM PDT 24
Finished Jun 27 04:21:52 PM PDT 24
Peak memory 145688 kb
Host smart-2ea52b16-6540-40b1-b9b6-757760ad21a9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2768238798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2768238798
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1848096801
Short name T72
Test name
Test status
Simulation time 29507094 ps
CPU time 0.43 seconds
Started Jun 27 04:21:35 PM PDT 24
Finished Jun 27 04:21:36 PM PDT 24
Peak memory 145448 kb
Host smart-6cf7835f-afd1-448a-b0dc-c4f6d5080486
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1848096801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1848096801
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2852417683
Short name T67
Test name
Test status
Simulation time 29897154 ps
CPU time 0.37 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:31 PM PDT 24
Peak memory 145172 kb
Host smart-b8d79f64-1078-441c-b3cf-31d9b7211b06
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2852417683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2852417683
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2817049257
Short name T64
Test name
Test status
Simulation time 27163459 ps
CPU time 0.41 seconds
Started Jun 27 04:18:30 PM PDT 24
Finished Jun 27 04:18:32 PM PDT 24
Peak memory 145436 kb
Host smart-0a2b1265-ac10-4252-bd15-2077b54bf376
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2817049257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2817049257
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2855546309
Short name T70
Test name
Test status
Simulation time 27199138 ps
CPU time 0.41 seconds
Started Jun 27 04:20:43 PM PDT 24
Finished Jun 27 04:20:45 PM PDT 24
Peak memory 145452 kb
Host smart-6fa0c230-9000-4ed3-8f3c-4a7150a15032
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2855546309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2855546309
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1198682407
Short name T79
Test name
Test status
Simulation time 27375899 ps
CPU time 0.39 seconds
Started Jun 27 04:18:30 PM PDT 24
Finished Jun 27 04:18:32 PM PDT 24
Peak memory 145528 kb
Host smart-f068b498-7f19-4f79-b442-eefe911dd50b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1198682407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1198682407
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3878591775
Short name T74
Test name
Test status
Simulation time 26799328 ps
CPU time 0.43 seconds
Started Jun 27 04:20:23 PM PDT 24
Finished Jun 27 04:20:25 PM PDT 24
Peak memory 145696 kb
Host smart-09e274ff-3184-4bb3-9e06-64681c230eea
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3878591775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3878591775
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.506822689
Short name T62
Test name
Test status
Simulation time 27038510 ps
CPU time 0.4 seconds
Started Jun 27 04:20:28 PM PDT 24
Finished Jun 27 04:20:29 PM PDT 24
Peak memory 145456 kb
Host smart-3788e37c-0418-4307-a29c-706b913cb47a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=506822689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.506822689
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2887732680
Short name T63
Test name
Test status
Simulation time 27417933 ps
CPU time 0.39 seconds
Started Jun 27 04:22:49 PM PDT 24
Finished Jun 27 04:22:51 PM PDT 24
Peak memory 145172 kb
Host smart-45bfa8f7-4d8f-4c61-9e36-b9fd6e14e570
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2887732680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2887732680
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1716865776
Short name T68
Test name
Test status
Simulation time 26865811 ps
CPU time 0.39 seconds
Started Jun 27 04:22:49 PM PDT 24
Finished Jun 27 04:22:52 PM PDT 24
Peak memory 145172 kb
Host smart-851b9a58-96af-4808-a0f2-5fec997a17e2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1716865776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1716865776
Directory /workspace/9.prim_sync_fatal_alert/latest
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