Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.47 89.47 100.00 100.00 93.75 93.75 100.00 100.00 82.14 82.14 95.83 95.83 65.12 65.12 /workspace/coverage/default/1.prim_async_alert.4014850949
92.01 2.53 100.00 0.00 93.75 0.00 100.00 0.00 85.71 3.57 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/16.prim_sync_alert.2635235222
93.76 1.76 100.00 0.00 93.75 0.00 100.00 0.00 89.29 3.57 95.83 0.00 83.72 6.98 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4094068357
94.50 0.73 100.00 0.00 95.83 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 2.33 /workspace/coverage/default/10.prim_async_alert.532266226
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3353846453
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/0.prim_sync_alert.2896267899

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3853052300
/workspace/coverage/default/11.prim_async_alert.3868330356
/workspace/coverage/default/12.prim_async_alert.392289888
/workspace/coverage/default/13.prim_async_alert.2966662123
/workspace/coverage/default/14.prim_async_alert.33204058
/workspace/coverage/default/15.prim_async_alert.1554535245
/workspace/coverage/default/16.prim_async_alert.757853597
/workspace/coverage/default/17.prim_async_alert.1649697402
/workspace/coverage/default/18.prim_async_alert.1607087465
/workspace/coverage/default/19.prim_async_alert.2913637667
/workspace/coverage/default/2.prim_async_alert.4138990572
/workspace/coverage/default/3.prim_async_alert.1107987926
/workspace/coverage/default/4.prim_async_alert.3570322765
/workspace/coverage/default/5.prim_async_alert.3041721299
/workspace/coverage/default/6.prim_async_alert.2545597881
/workspace/coverage/default/7.prim_async_alert.2928550779
/workspace/coverage/default/8.prim_async_alert.3191009093
/workspace/coverage/default/9.prim_async_alert.1143347467
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3367227907
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3460328392
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.754149231
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2972824801
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.616508681
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3470713690
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1377773717
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3434447619
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1198892984
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2971938124
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.372496523
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3746499587
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1947268623
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1158874927
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2595086377
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4105329233
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1080094072
/workspace/coverage/sync_alert/1.prim_sync_alert.2026986552
/workspace/coverage/sync_alert/10.prim_sync_alert.4175793929
/workspace/coverage/sync_alert/11.prim_sync_alert.2792645650
/workspace/coverage/sync_alert/12.prim_sync_alert.4120839803
/workspace/coverage/sync_alert/13.prim_sync_alert.1371111415
/workspace/coverage/sync_alert/14.prim_sync_alert.494179277
/workspace/coverage/sync_alert/15.prim_sync_alert.3501025996
/workspace/coverage/sync_alert/17.prim_sync_alert.4146160200
/workspace/coverage/sync_alert/18.prim_sync_alert.1250964230
/workspace/coverage/sync_alert/19.prim_sync_alert.3398576968
/workspace/coverage/sync_alert/2.prim_sync_alert.3714999499
/workspace/coverage/sync_alert/3.prim_sync_alert.3385216104
/workspace/coverage/sync_alert/4.prim_sync_alert.1757547920
/workspace/coverage/sync_alert/5.prim_sync_alert.958857129
/workspace/coverage/sync_alert/6.prim_sync_alert.1772359438
/workspace/coverage/sync_alert/7.prim_sync_alert.910916735
/workspace/coverage/sync_alert/8.prim_sync_alert.2887550557
/workspace/coverage/sync_alert/9.prim_sync_alert.492011811
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1669588668
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2531890477
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1785133855
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2182827199
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2482012817
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1989174887
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1025837795
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3444954845
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2460679917
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2484543623
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2184945601
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.990407764
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1700093839
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3238784483
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2406899812
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2844629050
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2852556658
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.898755415
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.619909340
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2222497858



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/10.prim_async_alert.532266226 Jun 28 04:17:34 PM PDT 24 Jun 28 04:17:36 PM PDT 24 10669848 ps
T2 /workspace/coverage/default/4.prim_async_alert.3570322765 Jun 28 04:17:34 PM PDT 24 Jun 28 04:17:36 PM PDT 24 11557638 ps
T3 /workspace/coverage/default/19.prim_async_alert.2913637667 Jun 28 04:17:41 PM PDT 24 Jun 28 04:17:42 PM PDT 24 11725396 ps
T15 /workspace/coverage/default/5.prim_async_alert.3041721299 Jun 28 04:17:34 PM PDT 24 Jun 28 04:17:37 PM PDT 24 10416284 ps
T13 /workspace/coverage/default/8.prim_async_alert.3191009093 Jun 28 04:17:34 PM PDT 24 Jun 28 04:17:38 PM PDT 24 11465473 ps
T9 /workspace/coverage/default/11.prim_async_alert.3868330356 Jun 28 04:17:31 PM PDT 24 Jun 28 04:17:32 PM PDT 24 12107533 ps
T7 /workspace/coverage/default/16.prim_async_alert.757853597 Jun 28 04:17:31 PM PDT 24 Jun 28 04:17:34 PM PDT 24 11362726 ps
T19 /workspace/coverage/default/9.prim_async_alert.1143347467 Jun 28 04:17:31 PM PDT 24 Jun 28 04:17:32 PM PDT 24 10420650 ps
T8 /workspace/coverage/default/1.prim_async_alert.4014850949 Jun 28 04:17:35 PM PDT 24 Jun 28 04:17:38 PM PDT 24 12586587 ps
T20 /workspace/coverage/default/3.prim_async_alert.1107987926 Jun 28 04:22:28 PM PDT 24 Jun 28 04:22:29 PM PDT 24 11328059 ps
T18 /workspace/coverage/default/15.prim_async_alert.1554535245 Jun 28 04:17:25 PM PDT 24 Jun 28 04:17:26 PM PDT 24 11481794 ps
T14 /workspace/coverage/default/12.prim_async_alert.392289888 Jun 28 04:17:44 PM PDT 24 Jun 28 04:17:45 PM PDT 24 11373541 ps
T21 /workspace/coverage/default/14.prim_async_alert.33204058 Jun 28 04:17:34 PM PDT 24 Jun 28 04:17:36 PM PDT 24 10578319 ps
T16 /workspace/coverage/default/13.prim_async_alert.2966662123 Jun 28 04:22:56 PM PDT 24 Jun 28 04:22:57 PM PDT 24 11802244 ps
T17 /workspace/coverage/default/7.prim_async_alert.2928550779 Jun 28 04:17:34 PM PDT 24 Jun 28 04:17:36 PM PDT 24 11625580 ps
T45 /workspace/coverage/default/17.prim_async_alert.1649697402 Jun 28 04:18:46 PM PDT 24 Jun 28 04:18:47 PM PDT 24 11979552 ps
T46 /workspace/coverage/default/6.prim_async_alert.2545597881 Jun 28 04:17:32 PM PDT 24 Jun 28 04:17:34 PM PDT 24 11655403 ps
T47 /workspace/coverage/default/2.prim_async_alert.4138990572 Jun 28 04:17:35 PM PDT 24 Jun 28 04:17:38 PM PDT 24 12731288 ps
T48 /workspace/coverage/default/0.prim_async_alert.3853052300 Jun 28 04:20:12 PM PDT 24 Jun 28 04:20:12 PM PDT 24 11813102 ps
T49 /workspace/coverage/default/18.prim_async_alert.1607087465 Jun 28 04:22:15 PM PDT 24 Jun 28 04:22:16 PM PDT 24 11705400 ps
T35 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.616508681 Jun 28 04:22:47 PM PDT 24 Jun 28 04:22:48 PM PDT 24 29939125 ps
T36 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1080094072 Jun 28 04:18:18 PM PDT 24 Jun 28 04:18:19 PM PDT 24 29440845 ps
T37 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1198892984 Jun 28 04:20:15 PM PDT 24 Jun 28 04:20:15 PM PDT 24 31259312 ps
T38 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.372496523 Jun 28 04:19:48 PM PDT 24 Jun 28 04:19:49 PM PDT 24 29667517 ps
T39 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2971938124 Jun 28 04:20:58 PM PDT 24 Jun 28 04:20:58 PM PDT 24 32688966 ps
T40 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2595086377 Jun 28 04:19:01 PM PDT 24 Jun 28 04:19:02 PM PDT 24 30387434 ps
T41 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4094068357 Jun 28 04:21:03 PM PDT 24 Jun 28 04:21:04 PM PDT 24 30431193 ps
T42 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3434447619 Jun 28 04:20:17 PM PDT 24 Jun 28 04:20:18 PM PDT 24 31363032 ps
T43 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1377773717 Jun 28 04:20:17 PM PDT 24 Jun 28 04:20:18 PM PDT 24 27956501 ps
T44 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3367227907 Jun 28 04:18:32 PM PDT 24 Jun 28 04:18:34 PM PDT 24 30432858 ps
T50 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.754149231 Jun 28 04:19:14 PM PDT 24 Jun 28 04:19:15 PM PDT 24 29871871 ps
T4 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3353846453 Jun 28 04:18:32 PM PDT 24 Jun 28 04:18:34 PM PDT 24 29436685 ps
T51 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3746499587 Jun 28 04:18:01 PM PDT 24 Jun 28 04:18:02 PM PDT 24 29438120 ps
T52 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3460328392 Jun 28 04:22:31 PM PDT 24 Jun 28 04:22:32 PM PDT 24 31027452 ps
T53 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4105329233 Jun 28 04:22:15 PM PDT 24 Jun 28 04:22:16 PM PDT 24 28958269 ps
T54 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3470713690 Jun 28 04:21:47 PM PDT 24 Jun 28 04:21:48 PM PDT 24 30542265 ps
T55 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2972824801 Jun 28 04:17:35 PM PDT 24 Jun 28 04:17:38 PM PDT 24 31106900 ps
T56 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1947268623 Jun 28 04:18:32 PM PDT 24 Jun 28 04:18:34 PM PDT 24 31619526 ps
T57 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1158874927 Jun 28 04:19:15 PM PDT 24 Jun 28 04:19:15 PM PDT 24 28804476 ps
T30 /workspace/coverage/sync_alert/18.prim_sync_alert.1250964230 Jun 28 04:17:32 PM PDT 24 Jun 28 04:17:34 PM PDT 24 9498030 ps
T22 /workspace/coverage/sync_alert/16.prim_sync_alert.2635235222 Jun 28 04:17:34 PM PDT 24 Jun 28 04:17:37 PM PDT 24 9076641 ps
T31 /workspace/coverage/sync_alert/7.prim_sync_alert.910916735 Jun 28 04:21:02 PM PDT 24 Jun 28 04:21:03 PM PDT 24 8819517 ps
T32 /workspace/coverage/sync_alert/10.prim_sync_alert.4175793929 Jun 28 04:22:17 PM PDT 24 Jun 28 04:22:18 PM PDT 24 10198442 ps
T23 /workspace/coverage/sync_alert/9.prim_sync_alert.492011811 Jun 28 04:18:01 PM PDT 24 Jun 28 04:18:02 PM PDT 24 10137568 ps
T24 /workspace/coverage/sync_alert/6.prim_sync_alert.1772359438 Jun 28 04:22:28 PM PDT 24 Jun 28 04:22:29 PM PDT 24 8940150 ps
T33 /workspace/coverage/sync_alert/11.prim_sync_alert.2792645650 Jun 28 04:20:22 PM PDT 24 Jun 28 04:20:23 PM PDT 24 9877389 ps
T34 /workspace/coverage/sync_alert/17.prim_sync_alert.4146160200 Jun 28 04:17:33 PM PDT 24 Jun 28 04:17:35 PM PDT 24 9751979 ps
T25 /workspace/coverage/sync_alert/8.prim_sync_alert.2887550557 Jun 28 04:21:03 PM PDT 24 Jun 28 04:21:04 PM PDT 24 8841761 ps
T26 /workspace/coverage/sync_alert/5.prim_sync_alert.958857129 Jun 28 04:21:27 PM PDT 24 Jun 28 04:21:28 PM PDT 24 7914545 ps
T27 /workspace/coverage/sync_alert/12.prim_sync_alert.4120839803 Jun 28 04:20:18 PM PDT 24 Jun 28 04:20:19 PM PDT 24 8893520 ps
T58 /workspace/coverage/sync_alert/19.prim_sync_alert.3398576968 Jun 28 04:17:44 PM PDT 24 Jun 28 04:17:46 PM PDT 24 8482275 ps
T28 /workspace/coverage/sync_alert/13.prim_sync_alert.1371111415 Jun 28 04:23:11 PM PDT 24 Jun 28 04:23:12 PM PDT 24 9314687 ps
T29 /workspace/coverage/sync_alert/14.prim_sync_alert.494179277 Jun 28 04:19:10 PM PDT 24 Jun 28 04:19:10 PM PDT 24 8998907 ps
T59 /workspace/coverage/sync_alert/15.prim_sync_alert.3501025996 Jun 28 04:17:35 PM PDT 24 Jun 28 04:17:38 PM PDT 24 9243085 ps
T10 /workspace/coverage/sync_alert/1.prim_sync_alert.2026986552 Jun 28 04:18:17 PM PDT 24 Jun 28 04:18:18 PM PDT 24 9318355 ps
T11 /workspace/coverage/sync_alert/0.prim_sync_alert.2896267899 Jun 28 04:21:27 PM PDT 24 Jun 28 04:21:28 PM PDT 24 8440303 ps
T12 /workspace/coverage/sync_alert/3.prim_sync_alert.3385216104 Jun 28 04:23:15 PM PDT 24 Jun 28 04:23:16 PM PDT 24 8941823 ps
T60 /workspace/coverage/sync_alert/2.prim_sync_alert.3714999499 Jun 28 04:18:26 PM PDT 24 Jun 28 04:18:27 PM PDT 24 8920973 ps
T61 /workspace/coverage/sync_alert/4.prim_sync_alert.1757547920 Jun 28 04:21:27 PM PDT 24 Jun 28 04:21:28 PM PDT 24 9376559 ps
T62 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1785133855 Jun 28 04:18:17 PM PDT 24 Jun 28 04:18:18 PM PDT 24 27901978 ps
T63 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2531890477 Jun 28 04:22:56 PM PDT 24 Jun 28 04:22:57 PM PDT 24 27318919 ps
T64 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1700093839 Jun 28 04:17:33 PM PDT 24 Jun 28 04:17:34 PM PDT 24 29365728 ps
T65 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2482012817 Jun 28 04:18:32 PM PDT 24 Jun 28 04:18:34 PM PDT 24 27469253 ps
T66 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2852556658 Jun 28 04:17:42 PM PDT 24 Jun 28 04:17:43 PM PDT 24 29111439 ps
T67 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3444954845 Jun 28 04:18:17 PM PDT 24 Jun 28 04:18:18 PM PDT 24 26527369 ps
T68 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.990407764 Jun 28 04:22:47 PM PDT 24 Jun 28 04:22:48 PM PDT 24 26594182 ps
T69 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2460679917 Jun 28 04:17:26 PM PDT 24 Jun 28 04:17:28 PM PDT 24 28756200 ps
T5 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2222497858 Jun 28 04:18:18 PM PDT 24 Jun 28 04:18:19 PM PDT 24 28238347 ps
T70 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.898755415 Jun 28 04:18:17 PM PDT 24 Jun 28 04:18:18 PM PDT 24 26967601 ps
T71 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1669588668 Jun 28 04:17:44 PM PDT 24 Jun 28 04:17:46 PM PDT 24 26762348 ps
T6 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1025837795 Jun 28 04:22:15 PM PDT 24 Jun 28 04:22:16 PM PDT 24 29718544 ps
T72 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2406899812 Jun 28 04:20:12 PM PDT 24 Jun 28 04:20:12 PM PDT 24 27795254 ps
T73 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2484543623 Jun 28 04:22:56 PM PDT 24 Jun 28 04:22:56 PM PDT 24 26295870 ps
T74 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.619909340 Jun 28 04:18:47 PM PDT 24 Jun 28 04:18:48 PM PDT 24 27152250 ps
T75 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2844629050 Jun 28 04:18:47 PM PDT 24 Jun 28 04:18:48 PM PDT 24 28080878 ps
T76 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1989174887 Jun 28 04:18:29 PM PDT 24 Jun 28 04:18:30 PM PDT 24 28216515 ps
T77 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2184945601 Jun 28 04:19:03 PM PDT 24 Jun 28 04:19:04 PM PDT 24 26406383 ps
T78 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2182827199 Jun 28 04:18:33 PM PDT 24 Jun 28 04:18:34 PM PDT 24 28357258 ps
T79 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3238784483 Jun 28 04:17:34 PM PDT 24 Jun 28 04:17:36 PM PDT 24 26359006 ps

Test location /workspace/coverage/default/1.prim_async_alert.4014850949
Short name T8
Test name
Test status
Simulation time 12586587 ps
CPU time 0.4 seconds
Started Jun 28 04:17:35 PM PDT 24
Finished Jun 28 04:17:38 PM PDT 24
Peak memory 145732 kb
Host smart-4eb15751-4757-435a-88cb-cbf2d3365869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014850949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.4014850949
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2635235222
Short name T22
Test name
Test status
Simulation time 9076641 ps
CPU time 0.38 seconds
Started Jun 28 04:17:34 PM PDT 24
Finished Jun 28 04:17:37 PM PDT 24
Peak memory 145544 kb
Host smart-1d67919f-9893-45e4-ab31-834cb6089fd0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2635235222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2635235222
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4094068357
Short name T41
Test name
Test status
Simulation time 30431193 ps
CPU time 0.41 seconds
Started Jun 28 04:21:03 PM PDT 24
Finished Jun 28 04:21:04 PM PDT 24
Peak memory 145036 kb
Host smart-6ba504a1-7299-4bc3-984c-af7072b905f0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4094068357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.4094068357
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.532266226
Short name T1
Test name
Test status
Simulation time 10669848 ps
CPU time 0.4 seconds
Started Jun 28 04:17:34 PM PDT 24
Finished Jun 28 04:17:36 PM PDT 24
Peak memory 145872 kb
Host smart-bec612f6-acf8-4ba9-9506-d87cfebf0315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532266226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.532266226
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3353846453
Short name T4
Test name
Test status
Simulation time 29436685 ps
CPU time 0.43 seconds
Started Jun 28 04:18:32 PM PDT 24
Finished Jun 28 04:18:34 PM PDT 24
Peak memory 143712 kb
Host smart-7ceae0c5-a6cc-4201-911c-b8edef2d30c2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3353846453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3353846453
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2896267899
Short name T11
Test name
Test status
Simulation time 8440303 ps
CPU time 0.38 seconds
Started Jun 28 04:21:27 PM PDT 24
Finished Jun 28 04:21:28 PM PDT 24
Peak memory 144948 kb
Host smart-62acdf38-5fb7-4b75-bc3b-ee9a14577c8e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2896267899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2896267899
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3853052300
Short name T48
Test name
Test status
Simulation time 11813102 ps
CPU time 0.39 seconds
Started Jun 28 04:20:12 PM PDT 24
Finished Jun 28 04:20:12 PM PDT 24
Peak memory 145520 kb
Host smart-c3759391-f5df-401b-87b0-3062828c7da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853052300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3853052300
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3868330356
Short name T9
Test name
Test status
Simulation time 12107533 ps
CPU time 0.4 seconds
Started Jun 28 04:17:31 PM PDT 24
Finished Jun 28 04:17:32 PM PDT 24
Peak memory 145308 kb
Host smart-5b4458b6-0e6e-4c1e-afb0-dfa9fbfb6fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868330356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3868330356
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.392289888
Short name T14
Test name
Test status
Simulation time 11373541 ps
CPU time 0.37 seconds
Started Jun 28 04:17:44 PM PDT 24
Finished Jun 28 04:17:45 PM PDT 24
Peak memory 145640 kb
Host smart-a8aba868-25db-4414-9c78-e5472ba89632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392289888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.392289888
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2966662123
Short name T16
Test name
Test status
Simulation time 11802244 ps
CPU time 0.38 seconds
Started Jun 28 04:22:56 PM PDT 24
Finished Jun 28 04:22:57 PM PDT 24
Peak memory 145392 kb
Host smart-13e81341-8935-442c-9ccf-5d22d5bb1560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966662123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2966662123
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.33204058
Short name T21
Test name
Test status
Simulation time 10578319 ps
CPU time 0.39 seconds
Started Jun 28 04:17:34 PM PDT 24
Finished Jun 28 04:17:36 PM PDT 24
Peak memory 145848 kb
Host smart-7ff94eee-a76d-4def-8a03-6267aa58ecd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33204058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.33204058
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1554535245
Short name T18
Test name
Test status
Simulation time 11481794 ps
CPU time 0.52 seconds
Started Jun 28 04:17:25 PM PDT 24
Finished Jun 28 04:17:26 PM PDT 24
Peak memory 145272 kb
Host smart-91c894bc-57d8-43d9-99ca-e39a79a328b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554535245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1554535245
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.757853597
Short name T7
Test name
Test status
Simulation time 11362726 ps
CPU time 0.45 seconds
Started Jun 28 04:17:31 PM PDT 24
Finished Jun 28 04:17:34 PM PDT 24
Peak memory 145208 kb
Host smart-bf5d5ea1-fee5-4a36-b505-fa2edd8a88c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757853597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.757853597
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1649697402
Short name T45
Test name
Test status
Simulation time 11979552 ps
CPU time 0.39 seconds
Started Jun 28 04:18:46 PM PDT 24
Finished Jun 28 04:18:47 PM PDT 24
Peak memory 145456 kb
Host smart-4f140d4b-ff77-427a-ab50-59f682ab5425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649697402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1649697402
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1607087465
Short name T49
Test name
Test status
Simulation time 11705400 ps
CPU time 0.53 seconds
Started Jun 28 04:22:15 PM PDT 24
Finished Jun 28 04:22:16 PM PDT 24
Peak memory 144688 kb
Host smart-ce71cdaf-c57f-4ff7-9e09-a20fc8d2d5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607087465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1607087465
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2913637667
Short name T3
Test name
Test status
Simulation time 11725396 ps
CPU time 0.38 seconds
Started Jun 28 04:17:41 PM PDT 24
Finished Jun 28 04:17:42 PM PDT 24
Peak memory 145436 kb
Host smart-7e296180-8e6a-4836-a0cf-e390d31fa63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913637667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2913637667
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.4138990572
Short name T47
Test name
Test status
Simulation time 12731288 ps
CPU time 0.4 seconds
Started Jun 28 04:17:35 PM PDT 24
Finished Jun 28 04:17:38 PM PDT 24
Peak memory 145640 kb
Host smart-f48d6956-9b5d-46bf-a2c6-c94c4b80765a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138990572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.4138990572
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1107987926
Short name T20
Test name
Test status
Simulation time 11328059 ps
CPU time 0.44 seconds
Started Jun 28 04:22:28 PM PDT 24
Finished Jun 28 04:22:29 PM PDT 24
Peak memory 144424 kb
Host smart-d72bc6ce-91c5-40a5-9072-44a840850dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107987926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1107987926
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3570322765
Short name T2
Test name
Test status
Simulation time 11557638 ps
CPU time 0.38 seconds
Started Jun 28 04:17:34 PM PDT 24
Finished Jun 28 04:17:36 PM PDT 24
Peak memory 145708 kb
Host smart-1b364db2-860f-4ebc-89c3-4f5df4190c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570322765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3570322765
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3041721299
Short name T15
Test name
Test status
Simulation time 10416284 ps
CPU time 0.4 seconds
Started Jun 28 04:17:34 PM PDT 24
Finished Jun 28 04:17:37 PM PDT 24
Peak memory 145848 kb
Host smart-45235674-c1e5-454e-a13c-cbad10f4ccba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041721299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3041721299
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.2545597881
Short name T46
Test name
Test status
Simulation time 11655403 ps
CPU time 0.38 seconds
Started Jun 28 04:17:32 PM PDT 24
Finished Jun 28 04:17:34 PM PDT 24
Peak memory 145336 kb
Host smart-1ce6fbd0-ed00-4f17-b85a-d9efe678a9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545597881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2545597881
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2928550779
Short name T17
Test name
Test status
Simulation time 11625580 ps
CPU time 0.4 seconds
Started Jun 28 04:17:34 PM PDT 24
Finished Jun 28 04:17:36 PM PDT 24
Peak memory 145844 kb
Host smart-67743126-3584-486e-bc42-002d84407540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928550779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2928550779
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3191009093
Short name T13
Test name
Test status
Simulation time 11465473 ps
CPU time 0.4 seconds
Started Jun 28 04:17:34 PM PDT 24
Finished Jun 28 04:17:38 PM PDT 24
Peak memory 145872 kb
Host smart-0a26a711-44b9-4525-8604-ac1db34b1505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191009093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3191009093
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1143347467
Short name T19
Test name
Test status
Simulation time 10420650 ps
CPU time 0.38 seconds
Started Jun 28 04:17:31 PM PDT 24
Finished Jun 28 04:17:32 PM PDT 24
Peak memory 145508 kb
Host smart-9340c058-0425-44c7-a486-ea6e7d368fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143347467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1143347467
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3367227907
Short name T44
Test name
Test status
Simulation time 30432858 ps
CPU time 0.42 seconds
Started Jun 28 04:18:32 PM PDT 24
Finished Jun 28 04:18:34 PM PDT 24
Peak memory 143672 kb
Host smart-6253fbb5-1015-43df-8b03-ea73357680a0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3367227907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3367227907
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3460328392
Short name T52
Test name
Test status
Simulation time 31027452 ps
CPU time 0.44 seconds
Started Jun 28 04:22:31 PM PDT 24
Finished Jun 28 04:22:32 PM PDT 24
Peak memory 144860 kb
Host smart-7df30be6-ad8a-437b-b069-39850cd4ebd1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3460328392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3460328392
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.754149231
Short name T50
Test name
Test status
Simulation time 29871871 ps
CPU time 0.39 seconds
Started Jun 28 04:19:14 PM PDT 24
Finished Jun 28 04:19:15 PM PDT 24
Peak memory 145044 kb
Host smart-94ed4c6c-d62b-4968-abc1-7a668aaa4765
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=754149231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.754149231
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2972824801
Short name T55
Test name
Test status
Simulation time 31106900 ps
CPU time 0.4 seconds
Started Jun 28 04:17:35 PM PDT 24
Finished Jun 28 04:17:38 PM PDT 24
Peak memory 144996 kb
Host smart-012a1a60-243b-4e27-9ab8-c31d3bedc514
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2972824801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2972824801
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.616508681
Short name T35
Test name
Test status
Simulation time 29939125 ps
CPU time 0.41 seconds
Started Jun 28 04:22:47 PM PDT 24
Finished Jun 28 04:22:48 PM PDT 24
Peak memory 145112 kb
Host smart-5b140a02-b8ba-4e90-b651-8e074b9a36cf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=616508681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.616508681
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3470713690
Short name T54
Test name
Test status
Simulation time 30542265 ps
CPU time 0.41 seconds
Started Jun 28 04:21:47 PM PDT 24
Finished Jun 28 04:21:48 PM PDT 24
Peak memory 145068 kb
Host smart-4342215e-6693-477a-88c3-3cec61881a00
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3470713690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3470713690
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1377773717
Short name T43
Test name
Test status
Simulation time 27956501 ps
CPU time 0.41 seconds
Started Jun 28 04:20:17 PM PDT 24
Finished Jun 28 04:20:18 PM PDT 24
Peak memory 145096 kb
Host smart-f8b174a9-3ff1-4cdb-8785-6fc7e0749fad
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1377773717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1377773717
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3434447619
Short name T42
Test name
Test status
Simulation time 31363032 ps
CPU time 0.42 seconds
Started Jun 28 04:20:17 PM PDT 24
Finished Jun 28 04:20:18 PM PDT 24
Peak memory 145096 kb
Host smart-b9f7f145-4163-4076-ab85-9069dd25986a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3434447619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3434447619
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1198892984
Short name T37
Test name
Test status
Simulation time 31259312 ps
CPU time 0.46 seconds
Started Jun 28 04:20:15 PM PDT 24
Finished Jun 28 04:20:15 PM PDT 24
Peak memory 145036 kb
Host smart-924abf2d-f2fd-4f69-913e-33d54f72e171
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1198892984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1198892984
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2971938124
Short name T39
Test name
Test status
Simulation time 32688966 ps
CPU time 0.42 seconds
Started Jun 28 04:20:58 PM PDT 24
Finished Jun 28 04:20:58 PM PDT 24
Peak memory 145068 kb
Host smart-bf47453d-d33e-4502-adf7-28c93423692a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2971938124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2971938124
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.372496523
Short name T38
Test name
Test status
Simulation time 29667517 ps
CPU time 0.41 seconds
Started Jun 28 04:19:48 PM PDT 24
Finished Jun 28 04:19:49 PM PDT 24
Peak memory 145280 kb
Host smart-402f7e3d-0700-4271-bdf3-c78d86b15a46
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=372496523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.372496523
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3746499587
Short name T51
Test name
Test status
Simulation time 29438120 ps
CPU time 0.42 seconds
Started Jun 28 04:18:01 PM PDT 24
Finished Jun 28 04:18:02 PM PDT 24
Peak memory 144996 kb
Host smart-40ad3af6-7305-4052-b782-b8ce264ce0df
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3746499587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3746499587
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1947268623
Short name T56
Test name
Test status
Simulation time 31619526 ps
CPU time 0.42 seconds
Started Jun 28 04:18:32 PM PDT 24
Finished Jun 28 04:18:34 PM PDT 24
Peak memory 143636 kb
Host smart-4b269731-b437-45d4-8749-38ae555e2dcd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1947268623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1947268623
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1158874927
Short name T57
Test name
Test status
Simulation time 28804476 ps
CPU time 0.43 seconds
Started Jun 28 04:19:15 PM PDT 24
Finished Jun 28 04:19:15 PM PDT 24
Peak memory 145272 kb
Host smart-2f009929-592a-4ee5-bcf7-13a2c1b030e0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1158874927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1158874927
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2595086377
Short name T40
Test name
Test status
Simulation time 30387434 ps
CPU time 0.42 seconds
Started Jun 28 04:19:01 PM PDT 24
Finished Jun 28 04:19:02 PM PDT 24
Peak memory 145272 kb
Host smart-266348dc-4f37-4339-8f42-6eb1db435b22
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2595086377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2595086377
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4105329233
Short name T53
Test name
Test status
Simulation time 28958269 ps
CPU time 0.42 seconds
Started Jun 28 04:22:15 PM PDT 24
Finished Jun 28 04:22:16 PM PDT 24
Peak memory 145064 kb
Host smart-95bb2a39-7558-4c0d-b543-fae8ab01e101
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4105329233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.4105329233
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1080094072
Short name T36
Test name
Test status
Simulation time 29440845 ps
CPU time 0.45 seconds
Started Jun 28 04:18:18 PM PDT 24
Finished Jun 28 04:18:19 PM PDT 24
Peak memory 145356 kb
Host smart-9352b189-96a4-4e69-8d05-04043b4d1f7e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1080094072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1080094072
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2026986552
Short name T10
Test name
Test status
Simulation time 9318355 ps
CPU time 0.4 seconds
Started Jun 28 04:18:17 PM PDT 24
Finished Jun 28 04:18:18 PM PDT 24
Peak memory 145568 kb
Host smart-8b8ee31d-f0c8-47c0-b6b8-69e0b70120f2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2026986552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2026986552
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.4175793929
Short name T32
Test name
Test status
Simulation time 10198442 ps
CPU time 0.42 seconds
Started Jun 28 04:22:17 PM PDT 24
Finished Jun 28 04:22:18 PM PDT 24
Peak memory 145820 kb
Host smart-2d5c8c10-6127-462e-a269-3dc5403bd2ab
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4175793929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.4175793929
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2792645650
Short name T33
Test name
Test status
Simulation time 9877389 ps
CPU time 0.4 seconds
Started Jun 28 04:20:22 PM PDT 24
Finished Jun 28 04:20:23 PM PDT 24
Peak memory 145544 kb
Host smart-5dffca05-69b8-4086-b988-6cadd2a2b8ae
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2792645650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2792645650
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.4120839803
Short name T27
Test name
Test status
Simulation time 8893520 ps
CPU time 0.4 seconds
Started Jun 28 04:20:18 PM PDT 24
Finished Jun 28 04:20:19 PM PDT 24
Peak memory 145216 kb
Host smart-49297cf1-0cb0-41ad-b58d-01581edf8263
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4120839803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.4120839803
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1371111415
Short name T28
Test name
Test status
Simulation time 9314687 ps
CPU time 0.45 seconds
Started Jun 28 04:23:11 PM PDT 24
Finished Jun 28 04:23:12 PM PDT 24
Peak memory 145820 kb
Host smart-45c457a7-e1cb-41da-911f-f215e6f2aafa
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1371111415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1371111415
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.494179277
Short name T29
Test name
Test status
Simulation time 8998907 ps
CPU time 0.43 seconds
Started Jun 28 04:19:10 PM PDT 24
Finished Jun 28 04:19:10 PM PDT 24
Peak memory 145228 kb
Host smart-97fa9c76-9e19-49e1-b251-5dd90b607eb2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=494179277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.494179277
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3501025996
Short name T59
Test name
Test status
Simulation time 9243085 ps
CPU time 0.4 seconds
Started Jun 28 04:17:35 PM PDT 24
Finished Jun 28 04:17:38 PM PDT 24
Peak memory 145568 kb
Host smart-7d0a6144-a573-4727-95ac-13b4059bee3d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3501025996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3501025996
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.4146160200
Short name T34
Test name
Test status
Simulation time 9751979 ps
CPU time 0.39 seconds
Started Jun 28 04:17:33 PM PDT 24
Finished Jun 28 04:17:35 PM PDT 24
Peak memory 145644 kb
Host smart-9f4833ed-6992-4d68-a1a8-c5472b65e63f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4146160200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.4146160200
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1250964230
Short name T30
Test name
Test status
Simulation time 9498030 ps
CPU time 0.38 seconds
Started Jun 28 04:17:32 PM PDT 24
Finished Jun 28 04:17:34 PM PDT 24
Peak memory 145036 kb
Host smart-ff8a273d-fc9e-412e-9be3-eb87f1b96f86
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1250964230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1250964230
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3398576968
Short name T58
Test name
Test status
Simulation time 8482275 ps
CPU time 0.37 seconds
Started Jun 28 04:17:44 PM PDT 24
Finished Jun 28 04:17:46 PM PDT 24
Peak memory 145040 kb
Host smart-f20a60c6-cc54-4d3e-8101-5ab69d7dfe17
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3398576968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3398576968
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3714999499
Short name T60
Test name
Test status
Simulation time 8920973 ps
CPU time 0.38 seconds
Started Jun 28 04:18:26 PM PDT 24
Finished Jun 28 04:18:27 PM PDT 24
Peak memory 145172 kb
Host smart-d79322d3-d03a-46da-b780-5e0d32c1e24f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3714999499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3714999499
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3385216104
Short name T12
Test name
Test status
Simulation time 8941823 ps
CPU time 0.41 seconds
Started Jun 28 04:23:15 PM PDT 24
Finished Jun 28 04:23:16 PM PDT 24
Peak memory 145836 kb
Host smart-918edbaa-675b-4185-900e-09b052e6e235
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3385216104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3385216104
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1757547920
Short name T61
Test name
Test status
Simulation time 9376559 ps
CPU time 0.38 seconds
Started Jun 28 04:21:27 PM PDT 24
Finished Jun 28 04:21:28 PM PDT 24
Peak memory 144800 kb
Host smart-aa33ced8-d0df-4560-8fcb-e72436ffc3ae
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1757547920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1757547920
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.958857129
Short name T26
Test name
Test status
Simulation time 7914545 ps
CPU time 0.39 seconds
Started Jun 28 04:21:27 PM PDT 24
Finished Jun 28 04:21:28 PM PDT 24
Peak memory 145020 kb
Host smart-859ddadf-f2f1-404c-bb74-5081136eb830
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=958857129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.958857129
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1772359438
Short name T24
Test name
Test status
Simulation time 8940150 ps
CPU time 0.45 seconds
Started Jun 28 04:22:28 PM PDT 24
Finished Jun 28 04:22:29 PM PDT 24
Peak memory 144692 kb
Host smart-3dc9e3e4-ff8d-4179-ab70-7499a971ef05
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1772359438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1772359438
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.910916735
Short name T31
Test name
Test status
Simulation time 8819517 ps
CPU time 0.4 seconds
Started Jun 28 04:21:02 PM PDT 24
Finished Jun 28 04:21:03 PM PDT 24
Peak memory 145224 kb
Host smart-1525f995-8ae8-4c9d-bd44-7edd4991bcea
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=910916735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.910916735
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2887550557
Short name T25
Test name
Test status
Simulation time 8841761 ps
CPU time 0.41 seconds
Started Jun 28 04:21:03 PM PDT 24
Finished Jun 28 04:21:04 PM PDT 24
Peak memory 145220 kb
Host smart-09c37451-f8fd-43ee-ac0d-aaacb5f01ed7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2887550557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2887550557
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.492011811
Short name T23
Test name
Test status
Simulation time 10137568 ps
CPU time 0.4 seconds
Started Jun 28 04:18:01 PM PDT 24
Finished Jun 28 04:18:02 PM PDT 24
Peak memory 145176 kb
Host smart-46dadf2a-a52e-437a-8c92-76fccc5694f9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=492011811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.492011811
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1669588668
Short name T71
Test name
Test status
Simulation time 26762348 ps
CPU time 0.39 seconds
Started Jun 28 04:17:44 PM PDT 24
Finished Jun 28 04:17:46 PM PDT 24
Peak memory 145028 kb
Host smart-404e47a8-f762-4645-8243-c52238a44fd9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1669588668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1669588668
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2531890477
Short name T63
Test name
Test status
Simulation time 27318919 ps
CPU time 0.39 seconds
Started Jun 28 04:22:56 PM PDT 24
Finished Jun 28 04:22:57 PM PDT 24
Peak memory 145096 kb
Host smart-a25991f0-9cba-4c19-8e51-63ebd0f7c9f8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2531890477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2531890477
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1785133855
Short name T62
Test name
Test status
Simulation time 27901978 ps
CPU time 0.45 seconds
Started Jun 28 04:18:17 PM PDT 24
Finished Jun 28 04:18:18 PM PDT 24
Peak memory 145700 kb
Host smart-db15c716-181d-4a52-a811-619b6645c84f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1785133855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1785133855
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2182827199
Short name T78
Test name
Test status
Simulation time 28357258 ps
CPU time 0.37 seconds
Started Jun 28 04:18:33 PM PDT 24
Finished Jun 28 04:18:34 PM PDT 24
Peak memory 144956 kb
Host smart-56e1e702-cc08-4942-bd13-a877bdb58246
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2182827199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2182827199
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2482012817
Short name T65
Test name
Test status
Simulation time 27469253 ps
CPU time 0.49 seconds
Started Jun 28 04:18:32 PM PDT 24
Finished Jun 28 04:18:34 PM PDT 24
Peak memory 144436 kb
Host smart-dec30e3c-2140-4007-a9a1-3e6402840af5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2482012817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2482012817
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1989174887
Short name T76
Test name
Test status
Simulation time 28216515 ps
CPU time 0.41 seconds
Started Jun 28 04:18:29 PM PDT 24
Finished Jun 28 04:18:30 PM PDT 24
Peak memory 145184 kb
Host smart-ec8b3613-8383-4ea0-857c-f7b471d22ac6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1989174887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1989174887
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1025837795
Short name T6
Test name
Test status
Simulation time 29718544 ps
CPU time 0.41 seconds
Started Jun 28 04:22:15 PM PDT 24
Finished Jun 28 04:22:16 PM PDT 24
Peak memory 145184 kb
Host smart-aaef9c49-4868-4ce2-a0a1-4aec6cbb9b56
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1025837795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1025837795
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3444954845
Short name T67
Test name
Test status
Simulation time 26527369 ps
CPU time 0.41 seconds
Started Jun 28 04:18:17 PM PDT 24
Finished Jun 28 04:18:18 PM PDT 24
Peak memory 145184 kb
Host smart-60dba28a-9ea8-4403-86b0-cf40a24634ec
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3444954845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3444954845
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2460679917
Short name T69
Test name
Test status
Simulation time 28756200 ps
CPU time 0.46 seconds
Started Jun 28 04:17:26 PM PDT 24
Finished Jun 28 04:17:28 PM PDT 24
Peak memory 145856 kb
Host smart-ba971c47-358a-471d-8aef-9846025a306a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2460679917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2460679917
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2484543623
Short name T73
Test name
Test status
Simulation time 26295870 ps
CPU time 0.39 seconds
Started Jun 28 04:22:56 PM PDT 24
Finished Jun 28 04:22:56 PM PDT 24
Peak memory 146344 kb
Host smart-5527ef2d-ddb2-4e07-bf64-04126b2fee02
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2484543623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2484543623
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2184945601
Short name T77
Test name
Test status
Simulation time 26406383 ps
CPU time 0.4 seconds
Started Jun 28 04:19:03 PM PDT 24
Finished Jun 28 04:19:04 PM PDT 24
Peak memory 145184 kb
Host smart-fd55c2d6-1919-45d9-b112-625d3a282731
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2184945601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2184945601
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.990407764
Short name T68
Test name
Test status
Simulation time 26594182 ps
CPU time 0.39 seconds
Started Jun 28 04:22:47 PM PDT 24
Finished Jun 28 04:22:48 PM PDT 24
Peak memory 145216 kb
Host smart-cb6f9289-d80f-459d-8e25-e0603e98bc41
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=990407764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.990407764
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1700093839
Short name T64
Test name
Test status
Simulation time 29365728 ps
CPU time 0.39 seconds
Started Jun 28 04:17:33 PM PDT 24
Finished Jun 28 04:17:34 PM PDT 24
Peak memory 145448 kb
Host smart-6f2a3dd8-7a73-4f3f-8e19-2fafba3547ed
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1700093839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1700093839
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3238784483
Short name T79
Test name
Test status
Simulation time 26359006 ps
CPU time 0.39 seconds
Started Jun 28 04:17:34 PM PDT 24
Finished Jun 28 04:17:36 PM PDT 24
Peak memory 145428 kb
Host smart-e216f3a4-afd1-4774-8248-49e8561fe371
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3238784483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3238784483
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2406899812
Short name T72
Test name
Test status
Simulation time 27795254 ps
CPU time 0.4 seconds
Started Jun 28 04:20:12 PM PDT 24
Finished Jun 28 04:20:12 PM PDT 24
Peak memory 145220 kb
Host smart-36a06ebc-e30f-4142-b79e-3b6150ef262d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2406899812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2406899812
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2844629050
Short name T75
Test name
Test status
Simulation time 28080878 ps
CPU time 0.42 seconds
Started Jun 28 04:18:47 PM PDT 24
Finished Jun 28 04:18:48 PM PDT 24
Peak memory 145180 kb
Host smart-435b68eb-7c45-4529-a6a5-270ec18a9a3d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2844629050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2844629050
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2852556658
Short name T66
Test name
Test status
Simulation time 29111439 ps
CPU time 0.39 seconds
Started Jun 28 04:17:42 PM PDT 24
Finished Jun 28 04:17:43 PM PDT 24
Peak memory 145168 kb
Host smart-5e71050a-1abf-4c80-bc5f-99d877e93ec2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2852556658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2852556658
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.898755415
Short name T70
Test name
Test status
Simulation time 26967601 ps
CPU time 0.41 seconds
Started Jun 28 04:18:17 PM PDT 24
Finished Jun 28 04:18:18 PM PDT 24
Peak memory 145540 kb
Host smart-4344cb18-ac60-4949-969c-6a3bd739d85a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=898755415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.898755415
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.619909340
Short name T74
Test name
Test status
Simulation time 27152250 ps
CPU time 0.4 seconds
Started Jun 28 04:18:47 PM PDT 24
Finished Jun 28 04:18:48 PM PDT 24
Peak memory 145200 kb
Host smart-64bb3c7d-2bdf-4ddd-9df4-bdfd8b6eb4ed
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=619909340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.619909340
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2222497858
Short name T5
Test name
Test status
Simulation time 28238347 ps
CPU time 0.41 seconds
Started Jun 28 04:18:18 PM PDT 24
Finished Jun 28 04:18:19 PM PDT 24
Peak memory 145448 kb
Host smart-88be3839-f675-4734-ba37-f64cef0c829e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2222497858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2222497858
Directory /workspace/9.prim_sync_fatal_alert/latest
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