Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.27 89.27 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/7.prim_async_alert.1758040094
92.99 3.72 100.00 0.00 93.75 0.00 100.00 0.00 89.29 10.71 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/19.prim_sync_alert.190786258
94.50 1.51 100.00 0.00 95.83 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.206600967
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4038566743
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2804554886


Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1326882519
/workspace/coverage/default/1.prim_async_alert.2205393114
/workspace/coverage/default/10.prim_async_alert.2523212160
/workspace/coverage/default/11.prim_async_alert.2284645557
/workspace/coverage/default/12.prim_async_alert.170463506
/workspace/coverage/default/13.prim_async_alert.2284545396
/workspace/coverage/default/14.prim_async_alert.1613443957
/workspace/coverage/default/15.prim_async_alert.1904815934
/workspace/coverage/default/16.prim_async_alert.529476892
/workspace/coverage/default/17.prim_async_alert.2448937468
/workspace/coverage/default/18.prim_async_alert.721294630
/workspace/coverage/default/19.prim_async_alert.1102845775
/workspace/coverage/default/2.prim_async_alert.421988737
/workspace/coverage/default/3.prim_async_alert.2806325670
/workspace/coverage/default/4.prim_async_alert.2882498354
/workspace/coverage/default/5.prim_async_alert.4040293140
/workspace/coverage/default/6.prim_async_alert.1014716499
/workspace/coverage/default/8.prim_async_alert.1634157169
/workspace/coverage/default/9.prim_async_alert.232492253
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.971082888
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1802835286
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.943852678
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1871258045
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3373528529
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4150897910
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2978519803
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4136808087
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2462559928
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4117950187
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2479970211
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.971568107
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1166630569
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1772902553
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2131536392
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1538109151
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.938262432
/workspace/coverage/sync_alert/0.prim_sync_alert.1841679172
/workspace/coverage/sync_alert/1.prim_sync_alert.3634143275
/workspace/coverage/sync_alert/10.prim_sync_alert.1655149522
/workspace/coverage/sync_alert/11.prim_sync_alert.216656575
/workspace/coverage/sync_alert/12.prim_sync_alert.3667359989
/workspace/coverage/sync_alert/13.prim_sync_alert.3464953179
/workspace/coverage/sync_alert/14.prim_sync_alert.3748451267
/workspace/coverage/sync_alert/15.prim_sync_alert.4181096110
/workspace/coverage/sync_alert/16.prim_sync_alert.353863979
/workspace/coverage/sync_alert/17.prim_sync_alert.2920237776
/workspace/coverage/sync_alert/18.prim_sync_alert.880688186
/workspace/coverage/sync_alert/2.prim_sync_alert.164158172
/workspace/coverage/sync_alert/3.prim_sync_alert.2328566746
/workspace/coverage/sync_alert/4.prim_sync_alert.4185187238
/workspace/coverage/sync_alert/5.prim_sync_alert.2004010566
/workspace/coverage/sync_alert/6.prim_sync_alert.2370706344
/workspace/coverage/sync_alert/7.prim_sync_alert.2310445693
/workspace/coverage/sync_alert/8.prim_sync_alert.1984094290
/workspace/coverage/sync_alert/9.prim_sync_alert.1817553672
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3847587480
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1315557937
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3281491516
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4017999239
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.800391901
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1504449603
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2633622659
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1783043769
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2705992671
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3110351707
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2364870826
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3259934689
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3008808480
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.976235651
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2481793207
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2558516035
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.292054689
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.970437866
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1544732261




Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/18.prim_async_alert.721294630 Jun 29 04:33:55 PM PDT 24 Jun 29 04:33:56 PM PDT 24 10804832 ps
T2 /workspace/coverage/default/7.prim_async_alert.1758040094 Jun 29 04:34:05 PM PDT 24 Jun 29 04:34:05 PM PDT 24 12115297 ps
T3 /workspace/coverage/default/13.prim_async_alert.2284545396 Jun 29 04:34:05 PM PDT 24 Jun 29 04:34:06 PM PDT 24 11163589 ps
T10 /workspace/coverage/default/4.prim_async_alert.2882498354 Jun 29 04:33:58 PM PDT 24 Jun 29 04:33:59 PM PDT 24 11020085 ps
T11 /workspace/coverage/default/1.prim_async_alert.2205393114 Jun 29 04:34:05 PM PDT 24 Jun 29 04:34:06 PM PDT 24 11268921 ps
T18 /workspace/coverage/default/17.prim_async_alert.2448937468 Jun 29 04:34:02 PM PDT 24 Jun 29 04:34:03 PM PDT 24 11204639 ps
T19 /workspace/coverage/default/0.prim_async_alert.1326882519 Jun 29 04:33:52 PM PDT 24 Jun 29 04:33:53 PM PDT 24 10648623 ps
T7 /workspace/coverage/default/2.prim_async_alert.421988737 Jun 29 04:33:57 PM PDT 24 Jun 29 04:33:58 PM PDT 24 11456618 ps
T20 /workspace/coverage/default/8.prim_async_alert.1634157169 Jun 29 04:33:54 PM PDT 24 Jun 29 04:33:55 PM PDT 24 11118381 ps
T8 /workspace/coverage/default/11.prim_async_alert.2284645557 Jun 29 04:34:07 PM PDT 24 Jun 29 04:34:08 PM PDT 24 11060297 ps
T9 /workspace/coverage/default/9.prim_async_alert.232492253 Jun 29 04:34:03 PM PDT 24 Jun 29 04:34:04 PM PDT 24 10660522 ps
T21 /workspace/coverage/default/5.prim_async_alert.4040293140 Jun 29 04:33:58 PM PDT 24 Jun 29 04:33:58 PM PDT 24 10891782 ps
T52 /workspace/coverage/default/6.prim_async_alert.1014716499 Jun 29 04:33:59 PM PDT 24 Jun 29 04:34:00 PM PDT 24 11525821 ps
T14 /workspace/coverage/default/3.prim_async_alert.2806325670 Jun 29 04:33:56 PM PDT 24 Jun 29 04:33:56 PM PDT 24 11669715 ps
T13 /workspace/coverage/default/15.prim_async_alert.1904815934 Jun 29 04:34:02 PM PDT 24 Jun 29 04:34:03 PM PDT 24 12001161 ps
T53 /workspace/coverage/default/14.prim_async_alert.1613443957 Jun 29 04:34:03 PM PDT 24 Jun 29 04:34:04 PM PDT 24 10850825 ps
T15 /workspace/coverage/default/12.prim_async_alert.170463506 Jun 29 04:33:55 PM PDT 24 Jun 29 04:33:56 PM PDT 24 11787133 ps
T16 /workspace/coverage/default/10.prim_async_alert.2523212160 Jun 29 04:34:04 PM PDT 24 Jun 29 04:34:05 PM PDT 24 11839476 ps
T22 /workspace/coverage/default/19.prim_async_alert.1102845775 Jun 29 04:34:12 PM PDT 24 Jun 29 04:34:13 PM PDT 24 10981166 ps
T23 /workspace/coverage/default/16.prim_async_alert.529476892 Jun 29 04:33:51 PM PDT 24 Jun 29 04:33:51 PM PDT 24 11617314 ps
T17 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4150897910 Jun 29 04:17:43 PM PDT 24 Jun 29 04:17:45 PM PDT 24 30631049 ps
T45 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.943852678 Jun 29 04:17:46 PM PDT 24 Jun 29 04:17:47 PM PDT 24 29822377 ps
T46 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1166630569 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 31948726 ps
T47 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4136808087 Jun 29 04:17:48 PM PDT 24 Jun 29 04:17:49 PM PDT 24 30560576 ps
T48 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2479970211 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 30762291 ps
T24 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2978519803 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 28552232 ps
T49 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1772902553 Jun 29 04:17:54 PM PDT 24 Jun 29 04:17:57 PM PDT 24 28995618 ps
T4 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.938262432 Jun 29 04:17:59 PM PDT 24 Jun 29 04:18:00 PM PDT 24 30857500 ps
T50 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4117950187 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 29138326 ps
T51 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.206600967 Jun 29 04:17:59 PM PDT 24 Jun 29 04:18:00 PM PDT 24 31066277 ps
T54 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1538109151 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 31003322 ps
T5 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4038566743 Jun 29 04:17:54 PM PDT 24 Jun 29 04:17:57 PM PDT 24 31089166 ps
T55 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2131536392 Jun 29 04:18:27 PM PDT 24 Jun 29 04:18:28 PM PDT 24 31290069 ps
T56 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1871258045 Jun 29 04:22:50 PM PDT 24 Jun 29 04:22:51 PM PDT 24 31093056 ps
T57 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3373528529 Jun 29 04:18:27 PM PDT 24 Jun 29 04:18:28 PM PDT 24 29394827 ps
T58 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.971082888 Jun 29 04:17:54 PM PDT 24 Jun 29 04:17:56 PM PDT 24 31199356 ps
T59 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2462559928 Jun 29 04:17:59 PM PDT 24 Jun 29 04:18:00 PM PDT 24 30200817 ps
T44 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1802835286 Jun 29 04:17:52 PM PDT 24 Jun 29 04:17:54 PM PDT 24 28904661 ps
T60 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.971568107 Jun 29 04:17:46 PM PDT 24 Jun 29 04:17:47 PM PDT 24 31598297 ps
T25 /workspace/coverage/sync_alert/3.prim_sync_alert.2328566746 Jun 29 04:17:48 PM PDT 24 Jun 29 04:17:49 PM PDT 24 8742196 ps
T35 /workspace/coverage/sync_alert/19.prim_sync_alert.190786258 Jun 29 04:17:54 PM PDT 24 Jun 29 04:17:57 PM PDT 24 10277086 ps
T36 /workspace/coverage/sync_alert/18.prim_sync_alert.880688186 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:56 PM PDT 24 9511187 ps
T37 /workspace/coverage/sync_alert/10.prim_sync_alert.1655149522 Jun 29 04:17:52 PM PDT 24 Jun 29 04:17:54 PM PDT 24 9021937 ps
T38 /workspace/coverage/sync_alert/8.prim_sync_alert.1984094290 Jun 29 04:17:54 PM PDT 24 Jun 29 04:17:56 PM PDT 24 8326905 ps
T39 /workspace/coverage/sync_alert/4.prim_sync_alert.4185187238 Jun 29 04:17:52 PM PDT 24 Jun 29 04:17:53 PM PDT 24 8915971 ps
T40 /workspace/coverage/sync_alert/1.prim_sync_alert.3634143275 Jun 29 04:17:52 PM PDT 24 Jun 29 04:17:54 PM PDT 24 9973923 ps
T41 /workspace/coverage/sync_alert/2.prim_sync_alert.164158172 Jun 29 04:17:59 PM PDT 24 Jun 29 04:18:00 PM PDT 24 9427094 ps
T42 /workspace/coverage/sync_alert/14.prim_sync_alert.3748451267 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 9094167 ps
T26 /workspace/coverage/sync_alert/12.prim_sync_alert.3667359989 Jun 29 04:17:43 PM PDT 24 Jun 29 04:17:44 PM PDT 24 9333754 ps
T27 /workspace/coverage/sync_alert/15.prim_sync_alert.4181096110 Jun 29 04:17:54 PM PDT 24 Jun 29 04:17:57 PM PDT 24 10304621 ps
T61 /workspace/coverage/sync_alert/11.prim_sync_alert.216656575 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 8685821 ps
T43 /workspace/coverage/sync_alert/16.prim_sync_alert.353863979 Jun 29 04:17:52 PM PDT 24 Jun 29 04:17:53 PM PDT 24 10609959 ps
T28 /workspace/coverage/sync_alert/6.prim_sync_alert.2370706344 Jun 29 04:17:54 PM PDT 24 Jun 29 04:17:57 PM PDT 24 9644766 ps
T62 /workspace/coverage/sync_alert/0.prim_sync_alert.1841679172 Jun 29 04:17:46 PM PDT 24 Jun 29 04:17:47 PM PDT 24 9283929 ps
T29 /workspace/coverage/sync_alert/7.prim_sync_alert.2310445693 Jun 29 04:21:35 PM PDT 24 Jun 29 04:21:36 PM PDT 24 9859009 ps
T63 /workspace/coverage/sync_alert/17.prim_sync_alert.2920237776 Jun 29 04:17:42 PM PDT 24 Jun 29 04:17:44 PM PDT 24 8295354 ps
T30 /workspace/coverage/sync_alert/5.prim_sync_alert.2004010566 Jun 29 04:22:34 PM PDT 24 Jun 29 04:22:35 PM PDT 24 8059683 ps
T64 /workspace/coverage/sync_alert/9.prim_sync_alert.1817553672 Jun 29 04:17:54 PM PDT 24 Jun 29 04:17:57 PM PDT 24 10292856 ps
T65 /workspace/coverage/sync_alert/13.prim_sync_alert.3464953179 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:56 PM PDT 24 9600509 ps
T66 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2481793207 Jun 29 04:17:54 PM PDT 24 Jun 29 04:17:57 PM PDT 24 28322610 ps
T31 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3259934689 Jun 29 04:17:48 PM PDT 24 Jun 29 04:17:49 PM PDT 24 27078705 ps
T6 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2705992671 Jun 29 04:18:48 PM PDT 24 Jun 29 04:18:49 PM PDT 24 28879737 ps
T32 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3110351707 Jun 29 04:17:52 PM PDT 24 Jun 29 04:17:53 PM PDT 24 26607693 ps
T67 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2364870826 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 27692236 ps
T68 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3281491516 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 28324361 ps
T69 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3847587480 Jun 29 04:22:34 PM PDT 24 Jun 29 04:22:35 PM PDT 24 27503355 ps
T33 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1783043769 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 27365483 ps
T70 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.976235651 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 28965797 ps
T34 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.800391901 Jun 29 04:17:43 PM PDT 24 Jun 29 04:17:44 PM PDT 24 27306293 ps
T71 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.292054689 Jun 29 04:17:52 PM PDT 24 Jun 29 04:17:54 PM PDT 24 28611189 ps
T72 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1504449603 Jun 29 04:17:52 PM PDT 24 Jun 29 04:17:53 PM PDT 24 27360488 ps
T73 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3008808480 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 28961920 ps
T74 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2633622659 Jun 29 04:17:54 PM PDT 24 Jun 29 04:17:57 PM PDT 24 28387061 ps
T75 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1315557937 Jun 29 04:24:51 PM PDT 24 Jun 29 04:24:52 PM PDT 24 28684208 ps
T76 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2558516035 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 29464664 ps
T12 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2804554886 Jun 29 04:17:53 PM PDT 24 Jun 29 04:17:55 PM PDT 24 25699203 ps
T77 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4017999239 Jun 29 04:17:54 PM PDT 24 Jun 29 04:17:57 PM PDT 24 28573111 ps
T78 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.970437866 Jun 29 04:17:59 PM PDT 24 Jun 29 04:18:00 PM PDT 24 28353016 ps
T79 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1544732261 Jun 29 04:17:52 PM PDT 24 Jun 29 04:17:54 PM PDT 24 26546081 ps


Test location /workspace/coverage/default/7.prim_async_alert.1758040094
Short name T2
Test name
Test status
Simulation time 12115297 ps
CPU time 0.39 seconds
Started Jun 29 04:34:05 PM PDT 24
Finished Jun 29 04:34:05 PM PDT 24
Peak memory 145664 kb
Host smart-86dd9333-6144-4a68-a0e0-e50f55966ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758040094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1758040094
Directory /workspace/7.prim_async_alert/latest


Test location /workspace/coverage/sync_alert/19.prim_sync_alert.190786258
Short name T35
Test name
Test status
Simulation time 10277086 ps
CPU time 0.38 seconds
Started Jun 29 04:17:54 PM PDT 24
Finished Jun 29 04:17:57 PM PDT 24
Peak memory 145028 kb
Host smart-b638d025-7cea-492f-990f-12413b54ee32
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=190786258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.190786258
Directory /workspace/19.prim_sync_alert/latest


Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.206600967
Short name T51
Test name
Test status
Simulation time 31066277 ps
CPU time 0.4 seconds
Started Jun 29 04:17:59 PM PDT 24
Finished Jun 29 04:18:00 PM PDT 24
Peak memory 145388 kb
Host smart-19ae58c7-f27f-4165-bd47-99a14856b7aa
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=206600967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.206600967
Directory /workspace/0.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4038566743
Short name T5
Test name
Test status
Simulation time 31089166 ps
CPU time 0.39 seconds
Started Jun 29 04:17:54 PM PDT 24
Finished Jun 29 04:17:57 PM PDT 24
Peak memory 144780 kb
Host smart-2dee7024-55df-41e9-909d-415c948d8c5e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4038566743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.4038566743
Directory /workspace/17.prim_async_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2804554886
Short name T12
Test name
Test status
Simulation time 25699203 ps
CPU time 0.39 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 144708 kb
Host smart-35c930f8-1cbc-4ea6-82ed-dd3892124cbc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2804554886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2804554886
Directory /workspace/5.prim_sync_fatal_alert/latest


Test location /workspace/coverage/default/0.prim_async_alert.1326882519
Short name T19
Test name
Test status
Simulation time 10648623 ps
CPU time 0.43 seconds
Started Jun 29 04:33:52 PM PDT 24
Finished Jun 29 04:33:53 PM PDT 24
Peak memory 145168 kb
Host smart-21e54d36-856f-4867-bdd1-f3abaed28681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326882519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1326882519
Directory /workspace/0.prim_async_alert/latest


Test location /workspace/coverage/default/1.prim_async_alert.2205393114
Short name T11
Test name
Test status
Simulation time 11268921 ps
CPU time 0.39 seconds
Started Jun 29 04:34:05 PM PDT 24
Finished Jun 29 04:34:06 PM PDT 24
Peak memory 145628 kb
Host smart-647592dc-5cdb-41c4-ab4a-ec3393ad386e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205393114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2205393114
Directory /workspace/1.prim_async_alert/latest


Test location /workspace/coverage/default/10.prim_async_alert.2523212160
Short name T16
Test name
Test status
Simulation time 11839476 ps
CPU time 0.38 seconds
Started Jun 29 04:34:04 PM PDT 24
Finished Jun 29 04:34:05 PM PDT 24
Peak memory 145660 kb
Host smart-b6976968-c629-4399-9a5f-b372714998ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523212160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2523212160
Directory /workspace/10.prim_async_alert/latest


Test location /workspace/coverage/default/11.prim_async_alert.2284645557
Short name T8
Test name
Test status
Simulation time 11060297 ps
CPU time 0.4 seconds
Started Jun 29 04:34:07 PM PDT 24
Finished Jun 29 04:34:08 PM PDT 24
Peak memory 145672 kb
Host smart-01eeda53-d3f4-4fd6-b8bc-941c05c914b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284645557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2284645557
Directory /workspace/11.prim_async_alert/latest


Test location /workspace/coverage/default/12.prim_async_alert.170463506
Short name T15
Test name
Test status
Simulation time 11787133 ps
CPU time 0.37 seconds
Started Jun 29 04:33:55 PM PDT 24
Finished Jun 29 04:33:56 PM PDT 24
Peak memory 145636 kb
Host smart-7473f3b5-95b0-4773-9122-0b16b7dfed8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170463506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.170463506
Directory /workspace/12.prim_async_alert/latest


Test location /workspace/coverage/default/13.prim_async_alert.2284545396
Short name T3
Test name
Test status
Simulation time 11163589 ps
CPU time 0.4 seconds
Started Jun 29 04:34:05 PM PDT 24
Finished Jun 29 04:34:06 PM PDT 24
Peak memory 145772 kb
Host smart-8f11e594-dbee-4bf1-ad70-340084e0d03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284545396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2284545396
Directory /workspace/13.prim_async_alert/latest


Test location /workspace/coverage/default/14.prim_async_alert.1613443957
Short name T53
Test name
Test status
Simulation time 10850825 ps
CPU time 0.44 seconds
Started Jun 29 04:34:03 PM PDT 24
Finished Jun 29 04:34:04 PM PDT 24
Peak memory 145652 kb
Host smart-23d0f153-ed64-40ec-95c0-c8c9b85b2193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613443957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1613443957
Directory /workspace/14.prim_async_alert/latest


Test location /workspace/coverage/default/15.prim_async_alert.1904815934
Short name T13
Test name
Test status
Simulation time 12001161 ps
CPU time 0.4 seconds
Started Jun 29 04:34:02 PM PDT 24
Finished Jun 29 04:34:03 PM PDT 24
Peak memory 145648 kb
Host smart-26a11670-59d4-426a-b671-aefef85579b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904815934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1904815934
Directory /workspace/15.prim_async_alert/latest


Test location /workspace/coverage/default/16.prim_async_alert.529476892
Short name T23
Test name
Test status
Simulation time 11617314 ps
CPU time 0.38 seconds
Started Jun 29 04:33:51 PM PDT 24
Finished Jun 29 04:33:51 PM PDT 24
Peak memory 145640 kb
Host smart-05a1136d-41c9-483c-81e3-5ab4f27d792a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529476892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.529476892
Directory /workspace/16.prim_async_alert/latest


Test location /workspace/coverage/default/17.prim_async_alert.2448937468
Short name T18
Test name
Test status
Simulation time 11204639 ps
CPU time 0.4 seconds
Started Jun 29 04:34:02 PM PDT 24
Finished Jun 29 04:34:03 PM PDT 24
Peak memory 145672 kb
Host smart-9995dcf8-6ed4-4d86-ae87-663f3661f2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448937468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2448937468
Directory /workspace/17.prim_async_alert/latest


Test location /workspace/coverage/default/18.prim_async_alert.721294630
Short name T1
Test name
Test status
Simulation time 10804832 ps
CPU time 0.41 seconds
Started Jun 29 04:33:55 PM PDT 24
Finished Jun 29 04:33:56 PM PDT 24
Peak memory 145644 kb
Host smart-2db12305-83f5-49ae-883d-64ad1fcfea69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721294630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.721294630
Directory /workspace/18.prim_async_alert/latest


Test location /workspace/coverage/default/19.prim_async_alert.1102845775
Short name T22
Test name
Test status
Simulation time 10981166 ps
CPU time 0.4 seconds
Started Jun 29 04:34:12 PM PDT 24
Finished Jun 29 04:34:13 PM PDT 24
Peak memory 145648 kb
Host smart-f9867180-4003-4430-a0ec-10ce6a779dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102845775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1102845775
Directory /workspace/19.prim_async_alert/latest


Test location /workspace/coverage/default/2.prim_async_alert.421988737
Short name T7
Test name
Test status
Simulation time 11456618 ps
CPU time 0.42 seconds
Started Jun 29 04:33:57 PM PDT 24
Finished Jun 29 04:33:58 PM PDT 24
Peak memory 145648 kb
Host smart-c860b0ea-0cad-4308-a318-7c4e47de6f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421988737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.421988737
Directory /workspace/2.prim_async_alert/latest


Test location /workspace/coverage/default/3.prim_async_alert.2806325670
Short name T14
Test name
Test status
Simulation time 11669715 ps
CPU time 0.46 seconds
Started Jun 29 04:33:56 PM PDT 24
Finished Jun 29 04:33:56 PM PDT 24
Peak memory 145628 kb
Host smart-ce862ace-d368-44c6-a09c-3c383ae5f1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806325670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2806325670
Directory /workspace/3.prim_async_alert/latest


Test location /workspace/coverage/default/4.prim_async_alert.2882498354
Short name T10
Test name
Test status
Simulation time 11020085 ps
CPU time 0.4 seconds
Started Jun 29 04:33:58 PM PDT 24
Finished Jun 29 04:33:59 PM PDT 24
Peak memory 145648 kb
Host smart-0e8517a3-6ff8-4fb9-b12b-46c0ba84cdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882498354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2882498354
Directory /workspace/4.prim_async_alert/latest


Test location /workspace/coverage/default/5.prim_async_alert.4040293140
Short name T21
Test name
Test status
Simulation time 10891782 ps
CPU time 0.42 seconds
Started Jun 29 04:33:58 PM PDT 24
Finished Jun 29 04:33:58 PM PDT 24
Peak memory 145628 kb
Host smart-7556eabd-52eb-4079-af05-85b27dbeaf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040293140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.4040293140
Directory /workspace/5.prim_async_alert/latest


Test location /workspace/coverage/default/6.prim_async_alert.1014716499
Short name T52
Test name
Test status
Simulation time 11525821 ps
CPU time 0.41 seconds
Started Jun 29 04:33:59 PM PDT 24
Finished Jun 29 04:34:00 PM PDT 24
Peak memory 145648 kb
Host smart-108e3542-3469-4053-a00f-39644897e68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014716499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1014716499
Directory /workspace/6.prim_async_alert/latest


Test location /workspace/coverage/default/8.prim_async_alert.1634157169
Short name T20
Test name
Test status
Simulation time 11118381 ps
CPU time 0.39 seconds
Started Jun 29 04:33:54 PM PDT 24
Finished Jun 29 04:33:55 PM PDT 24
Peak memory 145644 kb
Host smart-44dc0847-d6bf-44a0-8cec-f5927e7459e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634157169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1634157169
Directory /workspace/8.prim_async_alert/latest


Test location /workspace/coverage/default/9.prim_async_alert.232492253
Short name T9
Test name
Test status
Simulation time 10660522 ps
CPU time 0.39 seconds
Started Jun 29 04:34:03 PM PDT 24
Finished Jun 29 04:34:04 PM PDT 24
Peak memory 145656 kb
Host smart-b32d02e5-016d-40bd-be1d-bf6252832d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232492253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.232492253
Directory /workspace/9.prim_async_alert/latest


Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.971082888
Short name T58
Test name
Test status
Simulation time 31199356 ps
CPU time 0.38 seconds
Started Jun 29 04:17:54 PM PDT 24
Finished Jun 29 04:17:56 PM PDT 24
Peak memory 144780 kb
Host smart-d38c3e49-c26d-4c59-8537-c76020b84de0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=971082888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.971082888
Directory /workspace/1.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1802835286
Short name T44
Test name
Test status
Simulation time 28904661 ps
CPU time 0.4 seconds
Started Jun 29 04:17:52 PM PDT 24
Finished Jun 29 04:17:54 PM PDT 24
Peak memory 144600 kb
Host smart-40ef9847-94a8-4b75-a3df-255b5ac485d6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1802835286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1802835286
Directory /workspace/10.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.943852678
Short name T45
Test name
Test status
Simulation time 29822377 ps
CPU time 0.47 seconds
Started Jun 29 04:17:46 PM PDT 24
Finished Jun 29 04:17:47 PM PDT 24
Peak memory 144036 kb
Host smart-cb288c40-9733-4a01-92c7-d6f168b4b594
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=943852678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.943852678
Directory /workspace/11.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1871258045
Short name T56
Test name
Test status
Simulation time 31093056 ps
CPU time 0.41 seconds
Started Jun 29 04:22:50 PM PDT 24
Finished Jun 29 04:22:51 PM PDT 24
Peak memory 145112 kb
Host smart-9e25a2f7-f161-446d-a40d-99c471736221
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1871258045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1871258045
Directory /workspace/12.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3373528529
Short name T57
Test name
Test status
Simulation time 29394827 ps
CPU time 0.41 seconds
Started Jun 29 04:18:27 PM PDT 24
Finished Jun 29 04:18:28 PM PDT 24
Peak memory 144984 kb
Host smart-835bd674-e318-4330-bc89-82bb7ac50544
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3373528529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3373528529
Directory /workspace/13.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4150897910
Short name T17
Test name
Test status
Simulation time 30631049 ps
CPU time 0.46 seconds
Started Jun 29 04:17:43 PM PDT 24
Finished Jun 29 04:17:45 PM PDT 24
Peak memory 144664 kb
Host smart-26b8f278-cd60-4258-b8f1-39f1be87f9c2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4150897910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.4150897910
Directory /workspace/14.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2978519803
Short name T24
Test name
Test status
Simulation time 28552232 ps
CPU time 0.4 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 145416 kb
Host smart-fe2be7a9-fc49-4ec0-9aaa-2834b1acfe25
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2978519803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2978519803
Directory /workspace/15.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4136808087
Short name T47
Test name
Test status
Simulation time 30560576 ps
CPU time 0.49 seconds
Started Jun 29 04:17:48 PM PDT 24
Finished Jun 29 04:17:49 PM PDT 24
Peak memory 144204 kb
Host smart-87e36473-4b86-4478-9c3e-58bfe86ce8df
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4136808087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.4136808087
Directory /workspace/16.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2462559928
Short name T59
Test name
Test status
Simulation time 30200817 ps
CPU time 0.41 seconds
Started Jun 29 04:17:59 PM PDT 24
Finished Jun 29 04:18:00 PM PDT 24
Peak memory 145416 kb
Host smart-aedf775b-53d5-4de1-87a8-f7c64516438c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2462559928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2462559928
Directory /workspace/18.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4117950187
Short name T50
Test name
Test status
Simulation time 29138326 ps
CPU time 0.42 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 144836 kb
Host smart-704e1aa7-282a-4b7b-9075-0331fdcf5640
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4117950187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.4117950187
Directory /workspace/19.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2479970211
Short name T48
Test name
Test status
Simulation time 30762291 ps
CPU time 0.39 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 145384 kb
Host smart-8c74f82c-4a90-422b-8113-3e7b3310fcf4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2479970211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2479970211
Directory /workspace/2.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.971568107
Short name T60
Test name
Test status
Simulation time 31598297 ps
CPU time 0.46 seconds
Started Jun 29 04:17:46 PM PDT 24
Finished Jun 29 04:17:47 PM PDT 24
Peak memory 145108 kb
Host smart-d13f82d5-0a9c-49f0-9fff-7ad8c21b1e03
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=971568107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.971568107
Directory /workspace/3.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1166630569
Short name T46
Test name
Test status
Simulation time 31948726 ps
CPU time 0.41 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 143904 kb
Host smart-38a3d018-2cb2-49fa-ada9-e6bc9c21dcdc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1166630569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1166630569
Directory /workspace/4.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1772902553
Short name T49
Test name
Test status
Simulation time 28995618 ps
CPU time 0.39 seconds
Started Jun 29 04:17:54 PM PDT 24
Finished Jun 29 04:17:57 PM PDT 24
Peak memory 144724 kb
Host smart-8a5e471d-4c6b-4dcc-8135-c3c3b5059eb2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1772902553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1772902553
Directory /workspace/5.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2131536392
Short name T55
Test name
Test status
Simulation time 31290069 ps
CPU time 0.41 seconds
Started Jun 29 04:18:27 PM PDT 24
Finished Jun 29 04:18:28 PM PDT 24
Peak memory 144980 kb
Host smart-a1c70fac-908f-4e55-ac31-ab6c8f8cbd64
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2131536392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2131536392
Directory /workspace/7.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1538109151
Short name T54
Test name
Test status
Simulation time 31003322 ps
CPU time 0.39 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 144888 kb
Host smart-87977929-f886-45e7-aa1b-d74d93a01391
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1538109151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1538109151
Directory /workspace/8.prim_async_fatal_alert/latest


Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.938262432
Short name T4
Test name
Test status
Simulation time 30857500 ps
CPU time 0.42 seconds
Started Jun 29 04:17:59 PM PDT 24
Finished Jun 29 04:18:00 PM PDT 24
Peak memory 145392 kb
Host smart-ef84dd0a-f570-4abb-a2d6-447622533af6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=938262432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.938262432
Directory /workspace/9.prim_async_fatal_alert/latest


Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1841679172
Short name T62
Test name
Test status
Simulation time 9283929 ps
CPU time 0.43 seconds
Started Jun 29 04:17:46 PM PDT 24
Finished Jun 29 04:17:47 PM PDT 24
Peak memory 144496 kb
Host smart-7bb683b0-792b-4281-97dc-395dfdf4cb04
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1841679172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1841679172
Directory /workspace/0.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3634143275
Short name T40
Test name
Test status
Simulation time 9973923 ps
CPU time 0.39 seconds
Started Jun 29 04:17:52 PM PDT 24
Finished Jun 29 04:17:54 PM PDT 24
Peak memory 144944 kb
Host smart-9a0848d2-3ec7-442b-920a-6f8bd1bb9714
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3634143275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3634143275
Directory /workspace/1.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1655149522
Short name T37
Test name
Test status
Simulation time 9021937 ps
CPU time 0.4 seconds
Started Jun 29 04:17:52 PM PDT 24
Finished Jun 29 04:17:54 PM PDT 24
Peak memory 145684 kb
Host smart-539cddc1-c895-48cc-9c9f-eeca55cc39c5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1655149522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1655149522
Directory /workspace/10.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/11.prim_sync_alert.216656575
Short name T61
Test name
Test status
Simulation time 8685821 ps
CPU time 0.41 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 145600 kb
Host smart-5bd00d50-3279-4b59-a2c0-77f49f3dc7dc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=216656575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.216656575
Directory /workspace/11.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3667359989
Short name T26
Test name
Test status
Simulation time 9333754 ps
CPU time 0.37 seconds
Started Jun 29 04:17:43 PM PDT 24
Finished Jun 29 04:17:44 PM PDT 24
Peak memory 144988 kb
Host smart-922fb665-13d5-4b0f-92b6-2783698646d5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3667359989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3667359989
Directory /workspace/12.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3464953179
Short name T65
Test name
Test status
Simulation time 9600509 ps
CPU time 0.38 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:56 PM PDT 24
Peak memory 145020 kb
Host smart-5e2cba87-2d78-4f93-a340-99a9b4c0215b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3464953179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3464953179
Directory /workspace/13.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3748451267
Short name T42
Test name
Test status
Simulation time 9094167 ps
CPU time 0.37 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 144844 kb
Host smart-26dd5dc4-6caa-4a60-917f-2e27813a5220
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3748451267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3748451267
Directory /workspace/14.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/15.prim_sync_alert.4181096110
Short name T27
Test name
Test status
Simulation time 10304621 ps
CPU time 0.38 seconds
Started Jun 29 04:17:54 PM PDT 24
Finished Jun 29 04:17:57 PM PDT 24
Peak memory 145024 kb
Host smart-e629ca2d-af80-46dc-9e9c-1c567151655b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4181096110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.4181096110
Directory /workspace/15.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/16.prim_sync_alert.353863979
Short name T43
Test name
Test status
Simulation time 10609959 ps
CPU time 0.41 seconds
Started Jun 29 04:17:52 PM PDT 24
Finished Jun 29 04:17:53 PM PDT 24
Peak memory 143712 kb
Host smart-826bbb28-41f4-4278-8002-29ad8aa377ef
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=353863979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.353863979
Directory /workspace/16.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2920237776
Short name T63
Test name
Test status
Simulation time 8295354 ps
CPU time 0.45 seconds
Started Jun 29 04:17:42 PM PDT 24
Finished Jun 29 04:17:44 PM PDT 24
Peak memory 145832 kb
Host smart-a3c73f37-6a0b-4be8-9b23-037625816ae0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2920237776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2920237776
Directory /workspace/17.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/18.prim_sync_alert.880688186
Short name T36
Test name
Test status
Simulation time 9511187 ps
CPU time 0.38 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:56 PM PDT 24
Peak memory 145024 kb
Host smart-0264055e-e32c-47df-b1cd-46c351fa8ee5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=880688186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.880688186
Directory /workspace/18.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/2.prim_sync_alert.164158172
Short name T41
Test name
Test status
Simulation time 9427094 ps
CPU time 0.39 seconds
Started Jun 29 04:17:59 PM PDT 24
Finished Jun 29 04:18:00 PM PDT 24
Peak memory 145700 kb
Host smart-f88d5497-0d47-4ea6-8239-22b446b86ec6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=164158172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.164158172
Directory /workspace/2.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2328566746
Short name T25
Test name
Test status
Simulation time 8742196 ps
CPU time 0.43 seconds
Started Jun 29 04:17:48 PM PDT 24
Finished Jun 29 04:17:49 PM PDT 24
Peak memory 144788 kb
Host smart-27316a8f-0742-4cca-a808-b45b678c6055
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2328566746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2328566746
Directory /workspace/3.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/4.prim_sync_alert.4185187238
Short name T39
Test name
Test status
Simulation time 8915971 ps
CPU time 0.39 seconds
Started Jun 29 04:17:52 PM PDT 24
Finished Jun 29 04:17:53 PM PDT 24
Peak memory 145688 kb
Host smart-dd6a023c-c643-4dd8-9cf0-5664abb349e9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4185187238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.4185187238
Directory /workspace/4.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2004010566
Short name T30
Test name
Test status
Simulation time 8059683 ps
CPU time 0.39 seconds
Started Jun 29 04:22:34 PM PDT 24
Finished Jun 29 04:22:35 PM PDT 24
Peak memory 143948 kb
Host smart-938e48db-81f1-4f2f-991c-ae98b7d48bf6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2004010566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2004010566
Directory /workspace/5.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2370706344
Short name T28
Test name
Test status
Simulation time 9644766 ps
CPU time 0.37 seconds
Started Jun 29 04:17:54 PM PDT 24
Finished Jun 29 04:17:57 PM PDT 24
Peak memory 145036 kb
Host smart-aa42c947-0505-4891-82fa-f7aea13c70d7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2370706344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2370706344
Directory /workspace/6.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2310445693
Short name T29
Test name
Test status
Simulation time 9859009 ps
CPU time 0.38 seconds
Started Jun 29 04:21:35 PM PDT 24
Finished Jun 29 04:21:36 PM PDT 24
Peak memory 145276 kb
Host smart-84555746-8a87-4db5-850a-9b6edaa1579b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2310445693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2310445693
Directory /workspace/7.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1984094290
Short name T38
Test name
Test status
Simulation time 8326905 ps
CPU time 0.38 seconds
Started Jun 29 04:17:54 PM PDT 24
Finished Jun 29 04:17:56 PM PDT 24
Peak memory 145024 kb
Host smart-d98f4468-d67c-4f7d-969b-37e8815a91d0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1984094290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1984094290
Directory /workspace/8.prim_sync_alert/latest


Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1817553672
Short name T64
Test name
Test status
Simulation time 10292856 ps
CPU time 0.37 seconds
Started Jun 29 04:17:54 PM PDT 24
Finished Jun 29 04:17:57 PM PDT 24
Peak memory 145024 kb
Host smart-2c91b50a-a5ee-42ed-aa9c-e92c237918c2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1817553672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1817553672
Directory /workspace/9.prim_sync_alert/latest


Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3847587480
Short name T69
Test name
Test status
Simulation time 27503355 ps
CPU time 0.44 seconds
Started Jun 29 04:22:34 PM PDT 24
Finished Jun 29 04:22:35 PM PDT 24
Peak memory 143916 kb
Host smart-7490f48b-c821-4208-9868-e40696034571
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3847587480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3847587480
Directory /workspace/0.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1315557937
Short name T75
Test name
Test status
Simulation time 28684208 ps
CPU time 0.42 seconds
Started Jun 29 04:24:51 PM PDT 24
Finished Jun 29 04:24:52 PM PDT 24
Peak memory 145844 kb
Host smart-507a9e8d-51a0-4377-af55-28b8ae1d74d6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1315557937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1315557937
Directory /workspace/1.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3281491516
Short name T68
Test name
Test status
Simulation time 28324361 ps
CPU time 0.42 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 144688 kb
Host smart-46883687-c063-4367-a634-028fce388ff6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3281491516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3281491516
Directory /workspace/10.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4017999239
Short name T77
Test name
Test status
Simulation time 28573111 ps
CPU time 0.4 seconds
Started Jun 29 04:17:54 PM PDT 24
Finished Jun 29 04:17:57 PM PDT 24
Peak memory 145036 kb
Host smart-3dbac92c-b556-4275-9a99-3418c8d37183
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4017999239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.4017999239
Directory /workspace/11.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.800391901
Short name T34
Test name
Test status
Simulation time 27306293 ps
CPU time 0.42 seconds
Started Jun 29 04:17:43 PM PDT 24
Finished Jun 29 04:17:44 PM PDT 24
Peak memory 144836 kb
Host smart-5f2bf858-c23b-45e7-9a3c-a77b6020df5d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=800391901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.800391901
Directory /workspace/12.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1504449603
Short name T72
Test name
Test status
Simulation time 27360488 ps
CPU time 0.44 seconds
Started Jun 29 04:17:52 PM PDT 24
Finished Jun 29 04:17:53 PM PDT 24
Peak memory 144356 kb
Host smart-38323276-3120-4df3-b9ef-812daf1e639b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1504449603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1504449603
Directory /workspace/13.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2633622659
Short name T74
Test name
Test status
Simulation time 28387061 ps
CPU time 0.4 seconds
Started Jun 29 04:17:54 PM PDT 24
Finished Jun 29 04:17:57 PM PDT 24
Peak memory 145044 kb
Host smart-148af049-d779-4c82-abc1-8878db47323e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2633622659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2633622659
Directory /workspace/14.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1783043769
Short name T33
Test name
Test status
Simulation time 27365483 ps
CPU time 0.41 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 145068 kb
Host smart-3fa099fe-4af9-4218-af43-aac3de87a8c4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1783043769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1783043769
Directory /workspace/15.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2705992671
Short name T6
Test name
Test status
Simulation time 28879737 ps
CPU time 0.42 seconds
Started Jun 29 04:18:48 PM PDT 24
Finished Jun 29 04:18:49 PM PDT 24
Peak memory 145316 kb
Host smart-721e0359-75c1-483f-8559-bbd6ea660280
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2705992671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2705992671
Directory /workspace/16.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3110351707
Short name T32
Test name
Test status
Simulation time 26607693 ps
CPU time 0.42 seconds
Started Jun 29 04:17:52 PM PDT 24
Finished Jun 29 04:17:53 PM PDT 24
Peak memory 144504 kb
Host smart-0c97e314-c36f-4eb2-a37d-7dda377eccc5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3110351707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3110351707
Directory /workspace/17.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2364870826
Short name T67
Test name
Test status
Simulation time 27692236 ps
CPU time 0.38 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 145200 kb
Host smart-4bb39e66-017e-469c-9f29-660a70cb080c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2364870826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2364870826
Directory /workspace/18.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3259934689
Short name T31
Test name
Test status
Simulation time 27078705 ps
CPU time 0.44 seconds
Started Jun 29 04:17:48 PM PDT 24
Finished Jun 29 04:17:49 PM PDT 24
Peak memory 145356 kb
Host smart-d2e16534-a3f0-43c7-bc40-b4177ef9c89c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3259934689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3259934689
Directory /workspace/19.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3008808480
Short name T73
Test name
Test status
Simulation time 28961920 ps
CPU time 0.4 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 145128 kb
Host smart-6aee29e7-5cc2-4d19-8c8e-45463cd180f0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3008808480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3008808480
Directory /workspace/2.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.976235651
Short name T70
Test name
Test status
Simulation time 28965797 ps
CPU time 0.39 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 145024 kb
Host smart-7fb13ded-9c87-421a-ba87-d397f18da4f6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=976235651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.976235651
Directory /workspace/3.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2481793207
Short name T66
Test name
Test status
Simulation time 28322610 ps
CPU time 0.4 seconds
Started Jun 29 04:17:54 PM PDT 24
Finished Jun 29 04:17:57 PM PDT 24
Peak memory 145036 kb
Host smart-8cfacba4-360a-44c5-97ba-1af3a1b44a39
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2481793207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2481793207
Directory /workspace/4.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2558516035
Short name T76
Test name
Test status
Simulation time 29464664 ps
CPU time 0.42 seconds
Started Jun 29 04:17:53 PM PDT 24
Finished Jun 29 04:17:55 PM PDT 24
Peak memory 145620 kb
Host smart-0602474e-78d1-4260-a634-c8b24df2789c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2558516035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2558516035
Directory /workspace/6.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.292054689
Short name T71
Test name
Test status
Simulation time 28611189 ps
CPU time 0.4 seconds
Started Jun 29 04:17:52 PM PDT 24
Finished Jun 29 04:17:54 PM PDT 24
Peak memory 144976 kb
Host smart-7b515640-5f55-44b4-af91-0322c4e2ae0b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=292054689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.292054689
Directory /workspace/7.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.970437866
Short name T78
Test name
Test status
Simulation time 28353016 ps
CPU time 0.41 seconds
Started Jun 29 04:17:59 PM PDT 24
Finished Jun 29 04:18:00 PM PDT 24
Peak memory 145696 kb
Host smart-15cfefe2-bc28-4244-91ad-0c8609141e32
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=970437866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.970437866
Directory /workspace/8.prim_sync_fatal_alert/latest


Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1544732261
Short name T79
Test name
Test status
Simulation time 26546081 ps
CPU time 0.4 seconds
Started Jun 29 04:17:52 PM PDT 24
Finished Jun 29 04:17:54 PM PDT 24
Peak memory 144980 kb
Host smart-c55935ab-1ea8-4119-a0cf-a9697ab8a31a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1544732261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1544732261
Directory /workspace/9.prim_sync_fatal_alert/latest
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