| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.88 | 88.88 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/11.prim_async_alert.2311878210 |
| 91.62 | 2.74 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 74.42 | 9.30 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1460420282 |
| 94.15 | 2.53 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 11.63 | /workspace/coverage/sync_alert/13.prim_sync_alert.3198129214 |
| 94.85 | 0.69 | 100.00 | 0.00 | 97.92 | 4.17 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.886180709 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/16.prim_sync_alert.3521888617 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.355143521 |
| /workspace/coverage/default/1.prim_async_alert.1353366544 |
| /workspace/coverage/default/10.prim_async_alert.522591435 |
| /workspace/coverage/default/12.prim_async_alert.643038792 |
| /workspace/coverage/default/13.prim_async_alert.2789217287 |
| /workspace/coverage/default/14.prim_async_alert.4127863977 |
| /workspace/coverage/default/15.prim_async_alert.1435144955 |
| /workspace/coverage/default/16.prim_async_alert.4097565747 |
| /workspace/coverage/default/17.prim_async_alert.2536617179 |
| /workspace/coverage/default/18.prim_async_alert.3361102206 |
| /workspace/coverage/default/19.prim_async_alert.1520030030 |
| /workspace/coverage/default/2.prim_async_alert.443318550 |
| /workspace/coverage/default/3.prim_async_alert.83220024 |
| /workspace/coverage/default/4.prim_async_alert.2854209509 |
| /workspace/coverage/default/5.prim_async_alert.1458706404 |
| /workspace/coverage/default/6.prim_async_alert.2280272327 |
| /workspace/coverage/default/7.prim_async_alert.1413343361 |
| /workspace/coverage/default/8.prim_async_alert.2933623386 |
| /workspace/coverage/default/9.prim_async_alert.1355480026 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3480416733 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3991950758 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3579989895 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1017447770 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1847379412 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3846159321 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.764778895 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.963886060 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.905865549 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1674905499 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3974138597 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1424166309 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.803336249 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4219993178 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3268275363 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.309573642 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1495007255 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.212454093 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.2461465621 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.2739896994 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.933724163 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.2289191300 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.137242635 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.4123910168 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.2367159510 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.3378847190 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.6546669 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.3195084263 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.2720456382 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.1821989735 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.1306249764 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.3502771947 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.854153324 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.3792623488 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.231136833 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2814117611 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1406326419 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3627351178 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2409623158 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3661875479 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3713984651 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3947424030 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2280462952 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1964776013 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3411025632 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3582745897 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.184659293 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1941963175 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2472334976 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1083561213 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.584126114 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.604027564 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.819445470 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3385529091 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1419449333 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/5.prim_async_alert.1458706404 | Jun 30 04:17:11 PM PDT 24 | Jun 30 04:17:11 PM PDT 24 | 11136064 ps | ||
| T2 | /workspace/coverage/default/1.prim_async_alert.1353366544 | Jun 30 04:17:11 PM PDT 24 | Jun 30 04:17:12 PM PDT 24 | 11264609 ps | ||
| T3 | /workspace/coverage/default/4.prim_async_alert.2854209509 | Jun 30 04:17:00 PM PDT 24 | Jun 30 04:17:01 PM PDT 24 | 11375516 ps | ||
| T15 | /workspace/coverage/default/13.prim_async_alert.2789217287 | Jun 30 04:17:11 PM PDT 24 | Jun 30 04:17:12 PM PDT 24 | 11241897 ps | ||
| T7 | /workspace/coverage/default/17.prim_async_alert.2536617179 | Jun 30 04:17:16 PM PDT 24 | Jun 30 04:17:17 PM PDT 24 | 11064537 ps | ||
| T20 | /workspace/coverage/default/7.prim_async_alert.1413343361 | Jun 30 04:17:00 PM PDT 24 | Jun 30 04:17:01 PM PDT 24 | 10619892 ps | ||
| T8 | /workspace/coverage/default/16.prim_async_alert.4097565747 | Jun 30 04:18:16 PM PDT 24 | Jun 30 04:18:17 PM PDT 24 | 10642537 ps | ||
| T13 | /workspace/coverage/default/11.prim_async_alert.2311878210 | Jun 30 04:17:11 PM PDT 24 | Jun 30 04:17:12 PM PDT 24 | 11623854 ps | ||
| T17 | /workspace/coverage/default/18.prim_async_alert.3361102206 | Jun 30 04:17:11 PM PDT 24 | Jun 30 04:17:12 PM PDT 24 | 11563156 ps | ||
| T21 | /workspace/coverage/default/6.prim_async_alert.2280272327 | Jun 30 04:17:01 PM PDT 24 | Jun 30 04:17:01 PM PDT 24 | 10222531 ps | ||
| T22 | /workspace/coverage/default/3.prim_async_alert.83220024 | Jun 30 04:16:52 PM PDT 24 | Jun 30 04:16:53 PM PDT 24 | 10518885 ps | ||
| T26 | /workspace/coverage/default/0.prim_async_alert.355143521 | Jun 30 04:17:01 PM PDT 24 | Jun 30 04:17:02 PM PDT 24 | 11261975 ps | ||
| T16 | /workspace/coverage/default/9.prim_async_alert.1355480026 | Jun 30 04:17:11 PM PDT 24 | Jun 30 04:17:12 PM PDT 24 | 11170059 ps | ||
| T40 | /workspace/coverage/default/2.prim_async_alert.443318550 | Jun 30 04:17:03 PM PDT 24 | Jun 30 04:17:03 PM PDT 24 | 11063548 ps | ||
| T9 | /workspace/coverage/default/10.prim_async_alert.522591435 | Jun 30 04:17:02 PM PDT 24 | Jun 30 04:17:03 PM PDT 24 | 11061083 ps | ||
| T10 | /workspace/coverage/default/14.prim_async_alert.4127863977 | Jun 30 04:17:11 PM PDT 24 | Jun 30 04:17:12 PM PDT 24 | 11427992 ps | ||
| T14 | /workspace/coverage/default/8.prim_async_alert.2933623386 | Jun 30 04:17:01 PM PDT 24 | Jun 30 04:17:02 PM PDT 24 | 12618739 ps | ||
| T23 | /workspace/coverage/default/15.prim_async_alert.1435144955 | Jun 30 04:17:09 PM PDT 24 | Jun 30 04:17:10 PM PDT 24 | 10831959 ps | ||
| T18 | /workspace/coverage/default/19.prim_async_alert.1520030030 | Jun 30 04:18:17 PM PDT 24 | Jun 30 04:18:19 PM PDT 24 | 10566767 ps | ||
| T48 | /workspace/coverage/default/12.prim_async_alert.643038792 | Jun 30 04:17:10 PM PDT 24 | Jun 30 04:17:11 PM PDT 24 | 10895552 ps | ||
| T19 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1674905499 | Jun 30 04:43:05 PM PDT 24 | Jun 30 04:43:06 PM PDT 24 | 29417260 ps | ||
| T24 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1460420282 | Jun 30 04:42:59 PM PDT 24 | Jun 30 04:43:00 PM PDT 24 | 30504150 ps | ||
| T42 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3480416733 | Jun 30 04:42:58 PM PDT 24 | Jun 30 04:42:59 PM PDT 24 | 29189086 ps | ||
| T43 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3846159321 | Jun 30 04:43:04 PM PDT 24 | Jun 30 04:43:05 PM PDT 24 | 31993448 ps | ||
| T25 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.764778895 | Jun 30 04:43:05 PM PDT 24 | Jun 30 04:43:06 PM PDT 24 | 29295801 ps | ||
| T4 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.886180709 | Jun 30 04:43:08 PM PDT 24 | Jun 30 04:43:09 PM PDT 24 | 30960059 ps | ||
| T44 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3268275363 | Jun 30 04:42:58 PM PDT 24 | Jun 30 04:42:59 PM PDT 24 | 29213135 ps | ||
| T45 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.963886060 | Jun 30 04:43:10 PM PDT 24 | Jun 30 04:43:11 PM PDT 24 | 29961595 ps | ||
| T46 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1017447770 | Jun 30 04:43:04 PM PDT 24 | Jun 30 04:43:05 PM PDT 24 | 29283637 ps | ||
| T47 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3991950758 | Jun 30 04:42:56 PM PDT 24 | Jun 30 04:42:56 PM PDT 24 | 29191403 ps | ||
| T49 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1424166309 | Jun 30 04:42:54 PM PDT 24 | Jun 30 04:42:55 PM PDT 24 | 29040028 ps | ||
| T50 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3579989895 | Jun 30 04:43:04 PM PDT 24 | Jun 30 04:43:05 PM PDT 24 | 30546575 ps | ||
| T5 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.905865549 | Jun 30 04:43:07 PM PDT 24 | Jun 30 04:43:08 PM PDT 24 | 27907623 ps | ||
| T51 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1847379412 | Jun 30 04:43:04 PM PDT 24 | Jun 30 04:43:05 PM PDT 24 | 29772132 ps | ||
| T52 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.309573642 | Jun 30 04:42:55 PM PDT 24 | Jun 30 04:42:56 PM PDT 24 | 29584780 ps | ||
| T53 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3974138597 | Jun 30 04:42:57 PM PDT 24 | Jun 30 04:42:58 PM PDT 24 | 29488608 ps | ||
| T54 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1495007255 | Jun 30 04:42:58 PM PDT 24 | Jun 30 04:42:59 PM PDT 24 | 30614079 ps | ||
| T55 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.803336249 | Jun 30 04:42:57 PM PDT 24 | Jun 30 04:42:58 PM PDT 24 | 30975321 ps | ||
| T56 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4219993178 | Jun 30 04:42:57 PM PDT 24 | Jun 30 04:42:58 PM PDT 24 | 31095206 ps | ||
| T35 | /workspace/coverage/sync_alert/0.prim_sync_alert.212454093 | Jun 30 04:17:52 PM PDT 24 | Jun 30 04:17:53 PM PDT 24 | 8747520 ps | ||
| T27 | /workspace/coverage/sync_alert/13.prim_sync_alert.3198129214 | Jun 30 04:20:38 PM PDT 24 | Jun 30 04:20:39 PM PDT 24 | 9110529 ps | ||
| T36 | /workspace/coverage/sync_alert/11.prim_sync_alert.933724163 | Jun 30 04:22:41 PM PDT 24 | Jun 30 04:22:44 PM PDT 24 | 9117535 ps | ||
| T37 | /workspace/coverage/sync_alert/6.prim_sync_alert.3502771947 | Jun 30 04:17:55 PM PDT 24 | Jun 30 04:17:56 PM PDT 24 | 9056508 ps | ||
| T28 | /workspace/coverage/sync_alert/2.prim_sync_alert.3195084263 | Jun 30 04:18:20 PM PDT 24 | Jun 30 04:18:20 PM PDT 24 | 9195236 ps | ||
| T38 | /workspace/coverage/sync_alert/12.prim_sync_alert.2289191300 | Jun 30 04:22:40 PM PDT 24 | Jun 30 04:22:43 PM PDT 24 | 10272212 ps | ||
| T39 | /workspace/coverage/sync_alert/1.prim_sync_alert.2461465621 | Jun 30 04:19:09 PM PDT 24 | Jun 30 04:19:10 PM PDT 24 | 9084390 ps | ||
| T11 | /workspace/coverage/sync_alert/16.prim_sync_alert.3521888617 | Jun 30 04:23:11 PM PDT 24 | Jun 30 04:23:12 PM PDT 24 | 8974043 ps | ||
| T29 | /workspace/coverage/sync_alert/19.prim_sync_alert.6546669 | Jun 30 04:22:41 PM PDT 24 | Jun 30 04:22:45 PM PDT 24 | 10297835 ps | ||
| T12 | /workspace/coverage/sync_alert/8.prim_sync_alert.3792623488 | Jun 30 04:18:20 PM PDT 24 | Jun 30 04:18:21 PM PDT 24 | 8062330 ps | ||
| T57 | /workspace/coverage/sync_alert/9.prim_sync_alert.231136833 | Jun 30 04:18:03 PM PDT 24 | Jun 30 04:18:04 PM PDT 24 | 9108447 ps | ||
| T30 | /workspace/coverage/sync_alert/4.prim_sync_alert.1821989735 | Jun 30 04:19:03 PM PDT 24 | Jun 30 04:19:04 PM PDT 24 | 9376634 ps | ||
| T58 | /workspace/coverage/sync_alert/15.prim_sync_alert.4123910168 | Jun 30 04:23:12 PM PDT 24 | Jun 30 04:23:13 PM PDT 24 | 7690804 ps | ||
| T59 | /workspace/coverage/sync_alert/7.prim_sync_alert.854153324 | Jun 30 04:18:24 PM PDT 24 | Jun 30 04:18:25 PM PDT 24 | 9319646 ps | ||
| T41 | /workspace/coverage/sync_alert/5.prim_sync_alert.1306249764 | Jun 30 04:18:07 PM PDT 24 | Jun 30 04:18:08 PM PDT 24 | 8953450 ps | ||
| T31 | /workspace/coverage/sync_alert/17.prim_sync_alert.2367159510 | Jun 30 04:22:40 PM PDT 24 | Jun 30 04:22:43 PM PDT 24 | 9263294 ps | ||
| T32 | /workspace/coverage/sync_alert/18.prim_sync_alert.3378847190 | Jun 30 04:23:00 PM PDT 24 | Jun 30 04:23:02 PM PDT 24 | 9410924 ps | ||
| T33 | /workspace/coverage/sync_alert/3.prim_sync_alert.2720456382 | Jun 30 04:17:54 PM PDT 24 | Jun 30 04:17:54 PM PDT 24 | 9309738 ps | ||
| T60 | /workspace/coverage/sync_alert/14.prim_sync_alert.137242635 | Jun 30 04:22:40 PM PDT 24 | Jun 30 04:22:43 PM PDT 24 | 9279274 ps | ||
| T61 | /workspace/coverage/sync_alert/10.prim_sync_alert.2739896994 | Jun 30 04:22:47 PM PDT 24 | Jun 30 04:22:50 PM PDT 24 | 8224360 ps | ||
| T34 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2280462952 | Jun 30 04:43:07 PM PDT 24 | Jun 30 04:43:08 PM PDT 24 | 26626698 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1964776013 | Jun 30 04:43:05 PM PDT 24 | Jun 30 04:43:06 PM PDT 24 | 27073644 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.819445470 | Jun 30 04:43:11 PM PDT 24 | Jun 30 04:43:12 PM PDT 24 | 27281197 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.184659293 | Jun 30 04:43:06 PM PDT 24 | Jun 30 04:43:06 PM PDT 24 | 24958107 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.584126114 | Jun 30 04:43:08 PM PDT 24 | Jun 30 04:43:09 PM PDT 24 | 26756774 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2409623158 | Jun 30 04:43:05 PM PDT 24 | Jun 30 04:43:06 PM PDT 24 | 25731035 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3713984651 | Jun 30 04:43:05 PM PDT 24 | Jun 30 04:43:06 PM PDT 24 | 27068735 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1419449333 | Jun 30 04:43:08 PM PDT 24 | Jun 30 04:43:09 PM PDT 24 | 27822921 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3661875479 | Jun 30 04:43:07 PM PDT 24 | Jun 30 04:43:08 PM PDT 24 | 28076756 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3582745897 | Jun 30 04:43:08 PM PDT 24 | Jun 30 04:43:09 PM PDT 24 | 27208921 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1406326419 | Jun 30 04:43:06 PM PDT 24 | Jun 30 04:43:07 PM PDT 24 | 30097572 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3411025632 | Jun 30 04:43:07 PM PDT 24 | Jun 30 04:43:09 PM PDT 24 | 27631350 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2472334976 | Jun 30 04:43:11 PM PDT 24 | Jun 30 04:43:12 PM PDT 24 | 27453076 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3947424030 | Jun 30 04:43:07 PM PDT 24 | Jun 30 04:43:08 PM PDT 24 | 27925368 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3385529091 | Jun 30 04:43:04 PM PDT 24 | Jun 30 04:43:05 PM PDT 24 | 27183302 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1941963175 | Jun 30 04:43:07 PM PDT 24 | Jun 30 04:43:08 PM PDT 24 | 25732295 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.604027564 | Jun 30 04:43:08 PM PDT 24 | Jun 30 04:43:10 PM PDT 24 | 28229111 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1083561213 | Jun 30 04:43:06 PM PDT 24 | Jun 30 04:43:07 PM PDT 24 | 26871728 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2814117611 | Jun 30 04:43:05 PM PDT 24 | Jun 30 04:43:06 PM PDT 24 | 28307184 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3627351178 | Jun 30 04:43:05 PM PDT 24 | Jun 30 04:43:06 PM PDT 24 | 26892941 ps |
| Test location | /workspace/coverage/default/11.prim_async_alert.2311878210 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11623854 ps |
| CPU time | 0.38 seconds |
| Started | Jun 30 04:17:11 PM PDT 24 |
| Finished | Jun 30 04:17:12 PM PDT 24 |
| Peak memory | 145916 kb |
| Host | smart-4fc862ef-6009-4fc6-a1ac-3c21041961bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311878210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2311878210 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1460420282 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 30504150 ps |
| CPU time | 0.43 seconds |
| Started | Jun 30 04:42:59 PM PDT 24 |
| Finished | Jun 30 04:43:00 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-6dc2676a-4975-436c-8bc3-51c49eb81320 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1460420282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1460420282 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.3198129214 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9110529 ps |
| CPU time | 0.42 seconds |
| Started | Jun 30 04:20:38 PM PDT 24 |
| Finished | Jun 30 04:20:39 PM PDT 24 |
| Peak memory | 145420 kb |
| Host | smart-3fcc2c17-570a-41ff-8d51-77a37abf27ba |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3198129214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3198129214 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.886180709 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30960059 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:43:08 PM PDT 24 |
| Finished | Jun 30 04:43:09 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-03a1e1de-bed7-4143-9767-e87a223879e5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=886180709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.886180709 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.3521888617 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8974043 ps |
| CPU time | 0.38 seconds |
| Started | Jun 30 04:23:11 PM PDT 24 |
| Finished | Jun 30 04:23:12 PM PDT 24 |
| Peak memory | 146312 kb |
| Host | smart-bd31ab67-d274-400c-aa79-11931245fc7a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3521888617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3521888617 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.355143521 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11261975 ps |
| CPU time | 0.39 seconds |
| Started | Jun 30 04:17:01 PM PDT 24 |
| Finished | Jun 30 04:17:02 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-7b756d07-9aef-4dfd-b924-467221fcff17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355143521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.355143521 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1353366544 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11264609 ps |
| CPU time | 0.39 seconds |
| Started | Jun 30 04:17:11 PM PDT 24 |
| Finished | Jun 30 04:17:12 PM PDT 24 |
| Peak memory | 145924 kb |
| Host | smart-b5f1f924-5b48-48ca-bdee-3a7ac1fcbba4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1353366544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1353366544 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.522591435 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11061083 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:17:02 PM PDT 24 |
| Finished | Jun 30 04:17:03 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-fade6e3c-47b4-4a22-9d3c-435009b00937 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=522591435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.522591435 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.643038792 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10895552 ps |
| CPU time | 0.43 seconds |
| Started | Jun 30 04:17:10 PM PDT 24 |
| Finished | Jun 30 04:17:11 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-076671e1-32f9-407a-9d6f-81194159441a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=643038792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.643038792 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.2789217287 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11241897 ps |
| CPU time | 0.44 seconds |
| Started | Jun 30 04:17:11 PM PDT 24 |
| Finished | Jun 30 04:17:12 PM PDT 24 |
| Peak memory | 145916 kb |
| Host | smart-286c15f0-db2b-485f-8ee3-8432b0207f4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789217287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2789217287 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.4127863977 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11427992 ps |
| CPU time | 0.39 seconds |
| Started | Jun 30 04:17:11 PM PDT 24 |
| Finished | Jun 30 04:17:12 PM PDT 24 |
| Peak memory | 145916 kb |
| Host | smart-a38a3565-4a66-4398-a7e1-9884f3f90201 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4127863977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.4127863977 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1435144955 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10831959 ps |
| CPU time | 0.39 seconds |
| Started | Jun 30 04:17:09 PM PDT 24 |
| Finished | Jun 30 04:17:10 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-bb069b41-9a4b-4c34-9216-66de129bff21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435144955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1435144955 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.4097565747 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10642537 ps |
| CPU time | 0.43 seconds |
| Started | Jun 30 04:18:16 PM PDT 24 |
| Finished | Jun 30 04:18:17 PM PDT 24 |
| Peak memory | 144056 kb |
| Host | smart-512db1fe-bd1a-4a6e-976f-3917af7e4ba7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097565747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.4097565747 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.2536617179 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11064537 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:17:16 PM PDT 24 |
| Finished | Jun 30 04:17:17 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-37261789-1f4e-4ea4-aeb1-68e1c79fedf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2536617179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2536617179 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.3361102206 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11563156 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:17:11 PM PDT 24 |
| Finished | Jun 30 04:17:12 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-d43e46b9-355d-4244-9878-eaa7ddfcbfb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3361102206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3361102206 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.1520030030 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10566767 ps |
| CPU time | 0.42 seconds |
| Started | Jun 30 04:18:17 PM PDT 24 |
| Finished | Jun 30 04:18:19 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-c7c5775c-a569-46e1-b935-33522a7a0824 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1520030030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1520030030 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.443318550 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11063548 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:17:03 PM PDT 24 |
| Finished | Jun 30 04:17:03 PM PDT 24 |
| Peak memory | 145924 kb |
| Host | smart-ad24c30a-e49e-4138-9c76-7af983fd9d5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443318550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.443318550 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.83220024 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10518885 ps |
| CPU time | 0.44 seconds |
| Started | Jun 30 04:16:52 PM PDT 24 |
| Finished | Jun 30 04:16:53 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-98e2078f-8906-4187-9968-85d663eccff9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83220024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.83220024 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.2854209509 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11375516 ps |
| CPU time | 0.45 seconds |
| Started | Jun 30 04:17:00 PM PDT 24 |
| Finished | Jun 30 04:17:01 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-6618fb01-c7da-4d85-bd1d-5d47cca2a1b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854209509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2854209509 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.1458706404 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11136064 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:17:11 PM PDT 24 |
| Finished | Jun 30 04:17:11 PM PDT 24 |
| Peak memory | 145924 kb |
| Host | smart-b099b4a0-2b19-4709-9cb5-0a7a9f71ce4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1458706404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1458706404 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2280272327 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10222531 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:17:01 PM PDT 24 |
| Finished | Jun 30 04:17:01 PM PDT 24 |
| Peak memory | 145292 kb |
| Host | smart-956bbb90-859e-4052-a687-bce8d9fe49b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280272327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2280272327 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.1413343361 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10619892 ps |
| CPU time | 0.38 seconds |
| Started | Jun 30 04:17:00 PM PDT 24 |
| Finished | Jun 30 04:17:01 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-1a9f58ff-3316-48a8-84e2-7204e9143a52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413343361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1413343361 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.2933623386 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12618739 ps |
| CPU time | 0.45 seconds |
| Started | Jun 30 04:17:01 PM PDT 24 |
| Finished | Jun 30 04:17:02 PM PDT 24 |
| Peak memory | 145292 kb |
| Host | smart-c258729a-a328-4cec-9937-9938c9bc0674 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2933623386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2933623386 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.1355480026 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11170059 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:17:11 PM PDT 24 |
| Finished | Jun 30 04:17:12 PM PDT 24 |
| Peak memory | 145924 kb |
| Host | smart-cc55db24-3e38-4a39-80ee-7cdbcc31ac83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1355480026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1355480026 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3480416733 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29189086 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:42:58 PM PDT 24 |
| Finished | Jun 30 04:42:59 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-58942d9a-2869-4333-9552-25d09bb0019d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3480416733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3480416733 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3991950758 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 29191403 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:42:56 PM PDT 24 |
| Finished | Jun 30 04:42:56 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-9b765a5e-0abe-45b2-ad29-958c09f2b1a0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3991950758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3991950758 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3579989895 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30546575 ps |
| CPU time | 0.42 seconds |
| Started | Jun 30 04:43:04 PM PDT 24 |
| Finished | Jun 30 04:43:05 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-076c85d3-b417-4554-9563-15d5d41bc9a5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3579989895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3579989895 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1017447770 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29283637 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:43:04 PM PDT 24 |
| Finished | Jun 30 04:43:05 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-fd2b1eef-b2fd-46cd-a036-912c05243ac0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1017447770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1017447770 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1847379412 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29772132 ps |
| CPU time | 0.42 seconds |
| Started | Jun 30 04:43:04 PM PDT 24 |
| Finished | Jun 30 04:43:05 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-92ed3a74-e39e-40aa-8339-71221880a5b9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1847379412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1847379412 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3846159321 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 31993448 ps |
| CPU time | 0.43 seconds |
| Started | Jun 30 04:43:04 PM PDT 24 |
| Finished | Jun 30 04:43:05 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-321bd002-c0db-4422-913d-6e39b0dd4e13 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3846159321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3846159321 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.764778895 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 29295801 ps |
| CPU time | 0.44 seconds |
| Started | Jun 30 04:43:05 PM PDT 24 |
| Finished | Jun 30 04:43:06 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-4f011f53-3250-47cb-a31e-cc3fe96bc7e5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=764778895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.764778895 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.963886060 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29961595 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:43:10 PM PDT 24 |
| Finished | Jun 30 04:43:11 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-8a2b66bb-2623-4491-9c0e-c1cdf03987e9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=963886060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.963886060 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.905865549 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 27907623 ps |
| CPU time | 0.42 seconds |
| Started | Jun 30 04:43:07 PM PDT 24 |
| Finished | Jun 30 04:43:08 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-6209e7a6-6bf8-4601-b3a1-e46c32b00096 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=905865549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.905865549 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1674905499 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 29417260 ps |
| CPU time | 0.43 seconds |
| Started | Jun 30 04:43:05 PM PDT 24 |
| Finished | Jun 30 04:43:06 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-3b0506e8-0081-4b66-8c0a-e5aee295efab |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1674905499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1674905499 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3974138597 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 29488608 ps |
| CPU time | 0.45 seconds |
| Started | Jun 30 04:42:57 PM PDT 24 |
| Finished | Jun 30 04:42:58 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-d17cacff-79e0-4c95-ab82-bf29366675ab |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3974138597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3974138597 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1424166309 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29040028 ps |
| CPU time | 0.39 seconds |
| Started | Jun 30 04:42:54 PM PDT 24 |
| Finished | Jun 30 04:42:55 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-49cc5bb1-ca0a-44af-bad8-c2918ab811cc |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1424166309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1424166309 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.803336249 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 30975321 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:42:57 PM PDT 24 |
| Finished | Jun 30 04:42:58 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-29b65d11-a592-4d85-8294-04d439b16e8c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=803336249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.803336249 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4219993178 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 31095206 ps |
| CPU time | 0.44 seconds |
| Started | Jun 30 04:42:57 PM PDT 24 |
| Finished | Jun 30 04:42:58 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-75392f39-210c-4785-b554-1b52e21f757d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4219993178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.4219993178 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3268275363 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 29213135 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:42:58 PM PDT 24 |
| Finished | Jun 30 04:42:59 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-79500765-cf0b-47c3-bdf4-3030c8f4c34c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3268275363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3268275363 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.309573642 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 29584780 ps |
| CPU time | 0.39 seconds |
| Started | Jun 30 04:42:55 PM PDT 24 |
| Finished | Jun 30 04:42:56 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-90553eb1-8cc0-4b08-b31b-ff475eae626b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=309573642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.309573642 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1495007255 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30614079 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:42:58 PM PDT 24 |
| Finished | Jun 30 04:42:59 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-91cbc9cb-e208-48dd-b26e-d079cec362f3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1495007255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1495007255 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.212454093 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8747520 ps |
| CPU time | 0.45 seconds |
| Started | Jun 30 04:17:52 PM PDT 24 |
| Finished | Jun 30 04:17:53 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-05dce470-060a-4976-9195-812f3e728538 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=212454093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.212454093 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.2461465621 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9084390 ps |
| CPU time | 0.44 seconds |
| Started | Jun 30 04:19:09 PM PDT 24 |
| Finished | Jun 30 04:19:10 PM PDT 24 |
| Peak memory | 145488 kb |
| Host | smart-966ff68f-feab-4d58-9e3b-840396a9a21f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2461465621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2461465621 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.2739896994 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 8224360 ps |
| CPU time | 0.36 seconds |
| Started | Jun 30 04:22:47 PM PDT 24 |
| Finished | Jun 30 04:22:50 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-1b3b02ad-b37e-4327-ab3d-1e27e9f15144 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2739896994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2739896994 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.933724163 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9117535 ps |
| CPU time | 0.37 seconds |
| Started | Jun 30 04:22:41 PM PDT 24 |
| Finished | Jun 30 04:22:44 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-f8272949-9f41-431d-bb7f-975993f35b64 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=933724163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.933724163 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.2289191300 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10272212 ps |
| CPU time | 0.45 seconds |
| Started | Jun 30 04:22:40 PM PDT 24 |
| Finished | Jun 30 04:22:43 PM PDT 24 |
| Peak memory | 144116 kb |
| Host | smart-048725d4-b091-4300-aa3b-8a5ed31279fd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2289191300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2289191300 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.137242635 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9279274 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:22:40 PM PDT 24 |
| Finished | Jun 30 04:22:43 PM PDT 24 |
| Peak memory | 144324 kb |
| Host | smart-da7b3405-0749-448f-9fe5-c5d5a6b8d5d5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=137242635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.137242635 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.4123910168 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 7690804 ps |
| CPU time | 0.39 seconds |
| Started | Jun 30 04:23:12 PM PDT 24 |
| Finished | Jun 30 04:23:13 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-a1d80a19-d07b-4076-bdcd-2c7044757569 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4123910168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.4123910168 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.2367159510 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9263294 ps |
| CPU time | 0.38 seconds |
| Started | Jun 30 04:22:40 PM PDT 24 |
| Finished | Jun 30 04:22:43 PM PDT 24 |
| Peak memory | 144440 kb |
| Host | smart-3ec3a6ab-517b-42ea-9942-7c13275e84b6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2367159510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2367159510 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.3378847190 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9410924 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:23:00 PM PDT 24 |
| Finished | Jun 30 04:23:02 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-459eb85e-27a0-4ce3-9735-2f67fb1fa05c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3378847190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3378847190 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.6546669 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10297835 ps |
| CPU time | 0.37 seconds |
| Started | Jun 30 04:22:41 PM PDT 24 |
| Finished | Jun 30 04:22:45 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-143dc491-93b8-4c85-9c2f-c0bc97291cd0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=6546669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.6546669 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.3195084263 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9195236 ps |
| CPU time | 0.39 seconds |
| Started | Jun 30 04:18:20 PM PDT 24 |
| Finished | Jun 30 04:18:20 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-3fa4fe78-536a-4cfc-9fd0-1f8acff9ed93 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3195084263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3195084263 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.2720456382 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9309738 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:17:54 PM PDT 24 |
| Finished | Jun 30 04:17:54 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-3d31aa16-1699-4f1a-a4a5-e08146d56f82 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2720456382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2720456382 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.1821989735 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9376634 ps |
| CPU time | 0.39 seconds |
| Started | Jun 30 04:19:03 PM PDT 24 |
| Finished | Jun 30 04:19:04 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-f50914c7-febb-4d26-b1a0-7fb29922cace |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1821989735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1821989735 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1306249764 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8953450 ps |
| CPU time | 0.38 seconds |
| Started | Jun 30 04:18:07 PM PDT 24 |
| Finished | Jun 30 04:18:08 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-6a20a9c0-f43a-446f-a354-4a07b9dadd05 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1306249764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1306249764 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.3502771947 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9056508 ps |
| CPU time | 0.39 seconds |
| Started | Jun 30 04:17:55 PM PDT 24 |
| Finished | Jun 30 04:17:56 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-a57135d0-8391-4d5c-a567-e2bcd4f0a9d6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3502771947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3502771947 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.854153324 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9319646 ps |
| CPU time | 0.38 seconds |
| Started | Jun 30 04:18:24 PM PDT 24 |
| Finished | Jun 30 04:18:25 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-7f1550bc-38fa-41c9-8843-4719919dc7d5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=854153324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.854153324 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.3792623488 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8062330 ps |
| CPU time | 0.38 seconds |
| Started | Jun 30 04:18:20 PM PDT 24 |
| Finished | Jun 30 04:18:21 PM PDT 24 |
| Peak memory | 145456 kb |
| Host | smart-5b0dca61-422c-4c0a-ad80-0e46418b3a04 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3792623488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3792623488 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.231136833 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9108447 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:18:03 PM PDT 24 |
| Finished | Jun 30 04:18:04 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-8f68a5ec-0ac7-4e8f-a1c2-55252e0028b9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=231136833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.231136833 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2814117611 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 28307184 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:43:05 PM PDT 24 |
| Finished | Jun 30 04:43:06 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-7b15a9e4-84d4-4caa-b58a-fe94fa311921 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2814117611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2814117611 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1406326419 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 30097572 ps |
| CPU time | 0.42 seconds |
| Started | Jun 30 04:43:06 PM PDT 24 |
| Finished | Jun 30 04:43:07 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-c7658b56-84cf-4540-bd1a-d661586ae89d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1406326419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1406326419 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3627351178 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 26892941 ps |
| CPU time | 0.45 seconds |
| Started | Jun 30 04:43:05 PM PDT 24 |
| Finished | Jun 30 04:43:06 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-d82771da-83d3-40e8-9242-732061722147 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3627351178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3627351178 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2409623158 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 25731035 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:43:05 PM PDT 24 |
| Finished | Jun 30 04:43:06 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-73011d99-9bff-4998-aedd-2f791a1262c3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2409623158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2409623158 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3661875479 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28076756 ps |
| CPU time | 0.45 seconds |
| Started | Jun 30 04:43:07 PM PDT 24 |
| Finished | Jun 30 04:43:08 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-0999010a-f028-46f0-9144-6ceca3676c69 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3661875479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3661875479 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3713984651 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27068735 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:43:05 PM PDT 24 |
| Finished | Jun 30 04:43:06 PM PDT 24 |
| Peak memory | 145448 kb |
| Host | smart-0033b928-79b2-476d-b9d7-585d7ee5a0e1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3713984651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3713984651 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3947424030 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27925368 ps |
| CPU time | 0.45 seconds |
| Started | Jun 30 04:43:07 PM PDT 24 |
| Finished | Jun 30 04:43:08 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-c3e4d951-6ed3-439b-9a31-b31e989ed78f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3947424030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3947424030 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2280462952 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 26626698 ps |
| CPU time | 0.41 seconds |
| Started | Jun 30 04:43:07 PM PDT 24 |
| Finished | Jun 30 04:43:08 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-2e62deb9-0b4a-4f32-a0c0-811ef0b03687 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2280462952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2280462952 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1964776013 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27073644 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:43:05 PM PDT 24 |
| Finished | Jun 30 04:43:06 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-fd7abf9d-0bd6-4454-8d28-6f38a85917ae |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1964776013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1964776013 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3411025632 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27631350 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:43:07 PM PDT 24 |
| Finished | Jun 30 04:43:09 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-e53ae2bd-e7b7-4911-a2a5-6b5b42158586 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3411025632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3411025632 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3582745897 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27208921 ps |
| CPU time | 0.42 seconds |
| Started | Jun 30 04:43:08 PM PDT 24 |
| Finished | Jun 30 04:43:09 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-ba64489b-d487-49f2-977d-d02d6f02b780 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3582745897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3582745897 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.184659293 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 24958107 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:43:06 PM PDT 24 |
| Finished | Jun 30 04:43:06 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-f14c3483-0b42-4c86-9e9d-40b89987e890 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=184659293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.184659293 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1941963175 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 25732295 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:43:07 PM PDT 24 |
| Finished | Jun 30 04:43:08 PM PDT 24 |
| Peak memory | 145328 kb |
| Host | smart-578510bd-30b8-4ea7-89b7-f1bacbd79fad |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1941963175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1941963175 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2472334976 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27453076 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:43:11 PM PDT 24 |
| Finished | Jun 30 04:43:12 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-fea9f476-58c4-4b12-9b0b-6dcd97bc57ce |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2472334976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2472334976 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1083561213 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 26871728 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:43:06 PM PDT 24 |
| Finished | Jun 30 04:43:07 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-19bc2697-285a-41ad-b0bd-6cb10be1f47a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1083561213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1083561213 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.584126114 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 26756774 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:43:08 PM PDT 24 |
| Finished | Jun 30 04:43:09 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-c0aa452f-8acc-4c0a-aa3f-a9fb41fca325 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=584126114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.584126114 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.604027564 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 28229111 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:43:08 PM PDT 24 |
| Finished | Jun 30 04:43:10 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-5766da84-5927-4a58-a87f-3b1bf8c6eb81 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=604027564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.604027564 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.819445470 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27281197 ps |
| CPU time | 0.44 seconds |
| Started | Jun 30 04:43:11 PM PDT 24 |
| Finished | Jun 30 04:43:12 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-ae9ae305-fbf5-49ca-b22c-1993faeea4bf |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=819445470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.819445470 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3385529091 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27183302 ps |
| CPU time | 0.4 seconds |
| Started | Jun 30 04:43:04 PM PDT 24 |
| Finished | Jun 30 04:43:05 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-3a399b72-d965-4a97-99a8-2c0d94549866 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3385529091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3385529091 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1419449333 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27822921 ps |
| CPU time | 0.45 seconds |
| Started | Jun 30 04:43:08 PM PDT 24 |
| Finished | Jun 30 04:43:09 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-257444fd-baf7-42f8-9206-7827317784f7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1419449333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1419449333 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |