| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.42 | 88.42 | 100.00 | 100.00 | 95.83 | 95.83 | 96.43 | 96.43 | 75.00 | 75.00 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/10.prim_async_alert.1211728924 |
| 92.15 | 3.72 | 100.00 | 0.00 | 95.83 | 0.00 | 96.43 | 0.00 | 85.71 | 10.71 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/6.prim_sync_alert.1618636519 |
| 94.25 | 2.11 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 3.57 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1819915698 |
| 94.85 | 0.60 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/6.prim_async_alert.1882564463 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/4.prim_sync_alert.2405042861 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.2796351880 |
| /workspace/coverage/default/1.prim_async_alert.2936594560 |
| /workspace/coverage/default/11.prim_async_alert.2813728489 |
| /workspace/coverage/default/12.prim_async_alert.1014550809 |
| /workspace/coverage/default/13.prim_async_alert.3888548402 |
| /workspace/coverage/default/14.prim_async_alert.1201638394 |
| /workspace/coverage/default/15.prim_async_alert.1881180396 |
| /workspace/coverage/default/16.prim_async_alert.1513163454 |
| /workspace/coverage/default/17.prim_async_alert.1284938397 |
| /workspace/coverage/default/18.prim_async_alert.2038089914 |
| /workspace/coverage/default/19.prim_async_alert.84385402 |
| /workspace/coverage/default/2.prim_async_alert.1346647525 |
| /workspace/coverage/default/3.prim_async_alert.393327518 |
| /workspace/coverage/default/4.prim_async_alert.4185829101 |
| /workspace/coverage/default/5.prim_async_alert.3861584019 |
| /workspace/coverage/default/7.prim_async_alert.229487806 |
| /workspace/coverage/default/8.prim_async_alert.1094512769 |
| /workspace/coverage/default/9.prim_async_alert.1574482613 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1245928124 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2857961761 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3990308571 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3528995466 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2694702349 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4053457379 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1526944122 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2250248035 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3351650776 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2463940256 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.868214101 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2423049904 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3706094738 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1488000509 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3623920209 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2835279116 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.44189956 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1696900815 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.3300486359 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.2344051108 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.2263562641 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1065989256 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.1934833824 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1387131647 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.2719079673 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.1214716024 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.138374060 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.3885483125 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.3530787971 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.7611178 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.3660785357 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.4254854517 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.1500184328 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.2935180252 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.2819696124 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.1746293589 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.356976937 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.677920334 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3339148456 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1755169154 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4156664703 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3823655169 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1493804486 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.944740285 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4170088802 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1917920955 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1228617710 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2584697411 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2081264350 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3123078880 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3848339238 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3747830762 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.147848192 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2258202337 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2114531872 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2068918632 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/10.prim_async_alert.1211728924 | Jul 01 10:22:37 AM PDT 24 | Jul 01 10:22:38 AM PDT 24 | 10819347 ps | ||
| T2 | /workspace/coverage/default/14.prim_async_alert.1201638394 | Jul 01 10:22:41 AM PDT 24 | Jul 01 10:22:42 AM PDT 24 | 11900398 ps | ||
| T3 | /workspace/coverage/default/12.prim_async_alert.1014550809 | Jul 01 10:22:31 AM PDT 24 | Jul 01 10:22:32 AM PDT 24 | 10684761 ps | ||
| T19 | /workspace/coverage/default/3.prim_async_alert.393327518 | Jul 01 10:27:17 AM PDT 24 | Jul 01 10:27:18 AM PDT 24 | 10296414 ps | ||
| T12 | /workspace/coverage/default/1.prim_async_alert.2936594560 | Jul 01 10:22:40 AM PDT 24 | Jul 01 10:22:41 AM PDT 24 | 11684728 ps | ||
| T20 | /workspace/coverage/default/4.prim_async_alert.4185829101 | Jul 01 10:22:46 AM PDT 24 | Jul 01 10:22:46 AM PDT 24 | 11594488 ps | ||
| T7 | /workspace/coverage/default/6.prim_async_alert.1882564463 | Jul 01 10:27:17 AM PDT 24 | Jul 01 10:27:18 AM PDT 24 | 12255984 ps | ||
| T21 | /workspace/coverage/default/8.prim_async_alert.1094512769 | Jul 01 10:27:32 AM PDT 24 | Jul 01 10:27:33 AM PDT 24 | 10359523 ps | ||
| T16 | /workspace/coverage/default/5.prim_async_alert.3861584019 | Jul 01 10:22:20 AM PDT 24 | Jul 01 10:22:22 AM PDT 24 | 10898929 ps | ||
| T8 | /workspace/coverage/default/2.prim_async_alert.1346647525 | Jul 01 10:28:02 AM PDT 24 | Jul 01 10:28:04 AM PDT 24 | 11003009 ps | ||
| T22 | /workspace/coverage/default/7.prim_async_alert.229487806 | Jul 01 10:28:03 AM PDT 24 | Jul 01 10:28:04 AM PDT 24 | 11195799 ps | ||
| T23 | /workspace/coverage/default/11.prim_async_alert.2813728489 | Jul 01 10:22:24 AM PDT 24 | Jul 01 10:22:24 AM PDT 24 | 11317555 ps | ||
| T14 | /workspace/coverage/default/15.prim_async_alert.1881180396 | Jul 01 10:22:31 AM PDT 24 | Jul 01 10:22:32 AM PDT 24 | 11331479 ps | ||
| T9 | /workspace/coverage/default/0.prim_async_alert.2796351880 | Jul 01 10:29:30 AM PDT 24 | Jul 01 10:29:31 AM PDT 24 | 11673209 ps | ||
| T24 | /workspace/coverage/default/18.prim_async_alert.2038089914 | Jul 01 10:22:33 AM PDT 24 | Jul 01 10:22:34 AM PDT 24 | 11866377 ps | ||
| T17 | /workspace/coverage/default/16.prim_async_alert.1513163454 | Jul 01 10:26:19 AM PDT 24 | Jul 01 10:26:20 AM PDT 24 | 11485645 ps | ||
| T18 | /workspace/coverage/default/19.prim_async_alert.84385402 | Jul 01 10:23:14 AM PDT 24 | Jul 01 10:23:14 AM PDT 24 | 10349426 ps | ||
| T45 | /workspace/coverage/default/17.prim_async_alert.1284938397 | Jul 01 10:22:27 AM PDT 24 | Jul 01 10:22:28 AM PDT 24 | 11606207 ps | ||
| T46 | /workspace/coverage/default/13.prim_async_alert.3888548402 | Jul 01 10:22:39 AM PDT 24 | Jul 01 10:22:40 AM PDT 24 | 11600585 ps | ||
| T47 | /workspace/coverage/default/9.prim_async_alert.1574482613 | Jul 01 10:22:32 AM PDT 24 | Jul 01 10:22:33 AM PDT 24 | 12199660 ps | ||
| T39 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1696900815 | Jul 01 10:29:37 AM PDT 24 | Jul 01 10:29:38 AM PDT 24 | 28537117 ps | ||
| T4 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1819915698 | Jul 01 10:27:32 AM PDT 24 | Jul 01 10:27:33 AM PDT 24 | 29678280 ps | ||
| T40 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3706094738 | Jul 01 10:22:34 AM PDT 24 | Jul 01 10:22:35 AM PDT 24 | 30826406 ps | ||
| T5 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2835279116 | Jul 01 10:27:31 AM PDT 24 | Jul 01 10:27:31 AM PDT 24 | 31421499 ps | ||
| T41 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2463940256 | Jul 01 10:22:39 AM PDT 24 | Jul 01 10:22:40 AM PDT 24 | 30672772 ps | ||
| T15 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2694702349 | Jul 01 10:22:40 AM PDT 24 | Jul 01 10:22:41 AM PDT 24 | 31663006 ps | ||
| T42 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.44189956 | Jul 01 10:22:33 AM PDT 24 | Jul 01 10:22:34 AM PDT 24 | 30308020 ps | ||
| T13 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2250248035 | Jul 01 10:22:47 AM PDT 24 | Jul 01 10:22:47 AM PDT 24 | 30740133 ps | ||
| T43 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2857961761 | Jul 01 10:28:16 AM PDT 24 | Jul 01 10:28:18 AM PDT 24 | 29930915 ps | ||
| T44 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3351650776 | Jul 01 10:22:26 AM PDT 24 | Jul 01 10:22:26 AM PDT 24 | 29249330 ps | ||
| T48 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3990308571 | Jul 01 10:22:32 AM PDT 24 | Jul 01 10:22:33 AM PDT 24 | 31163172 ps | ||
| T49 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.868214101 | Jul 01 10:22:32 AM PDT 24 | Jul 01 10:22:33 AM PDT 24 | 31339085 ps | ||
| T50 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1245928124 | Jul 01 10:27:32 AM PDT 24 | Jul 01 10:27:33 AM PDT 24 | 31792160 ps | ||
| T51 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1488000509 | Jul 01 10:28:02 AM PDT 24 | Jul 01 10:28:04 AM PDT 24 | 29281668 ps | ||
| T52 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3528995466 | Jul 01 10:25:35 AM PDT 24 | Jul 01 10:25:36 AM PDT 24 | 31045381 ps | ||
| T53 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4053457379 | Jul 01 10:22:30 AM PDT 24 | Jul 01 10:22:31 AM PDT 24 | 30837339 ps | ||
| T54 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2423049904 | Jul 01 10:22:24 AM PDT 24 | Jul 01 10:22:25 AM PDT 24 | 31083682 ps | ||
| T55 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3623920209 | Jul 01 10:28:02 AM PDT 24 | Jul 01 10:28:03 AM PDT 24 | 30965128 ps | ||
| T56 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1526944122 | Jul 01 10:27:17 AM PDT 24 | Jul 01 10:27:18 AM PDT 24 | 32885314 ps | ||
| T25 | /workspace/coverage/sync_alert/15.prim_sync_alert.1214716024 | Jul 01 10:45:25 AM PDT 24 | Jul 01 10:45:26 AM PDT 24 | 8698639 ps | ||
| T34 | /workspace/coverage/sync_alert/2.prim_sync_alert.3660785357 | Jul 01 10:45:27 AM PDT 24 | Jul 01 10:45:28 AM PDT 24 | 9925026 ps | ||
| T35 | /workspace/coverage/sync_alert/0.prim_sync_alert.3300486359 | Jul 01 10:45:24 AM PDT 24 | Jul 01 10:45:25 AM PDT 24 | 8983879 ps | ||
| T36 | /workspace/coverage/sync_alert/6.prim_sync_alert.1618636519 | Jul 01 10:45:41 AM PDT 24 | Jul 01 10:45:43 AM PDT 24 | 10063857 ps | ||
| T26 | /workspace/coverage/sync_alert/11.prim_sync_alert.1065989256 | Jul 01 10:45:43 AM PDT 24 | Jul 01 10:45:48 AM PDT 24 | 9750641 ps | ||
| T27 | /workspace/coverage/sync_alert/17.prim_sync_alert.3885483125 | Jul 01 10:45:35 AM PDT 24 | Jul 01 10:45:36 AM PDT 24 | 8950324 ps | ||
| T28 | /workspace/coverage/sync_alert/5.prim_sync_alert.1500184328 | Jul 01 10:45:29 AM PDT 24 | Jul 01 10:45:30 AM PDT 24 | 8467977 ps | ||
| T37 | /workspace/coverage/sync_alert/12.prim_sync_alert.1934833824 | Jul 01 10:45:42 AM PDT 24 | Jul 01 10:45:46 AM PDT 24 | 8475317 ps | ||
| T29 | /workspace/coverage/sync_alert/13.prim_sync_alert.1387131647 | Jul 01 10:45:25 AM PDT 24 | Jul 01 10:45:26 AM PDT 24 | 9519435 ps | ||
| T38 | /workspace/coverage/sync_alert/16.prim_sync_alert.138374060 | Jul 01 10:45:25 AM PDT 24 | Jul 01 10:45:26 AM PDT 24 | 9544837 ps | ||
| T10 | /workspace/coverage/sync_alert/4.prim_sync_alert.2405042861 | Jul 01 10:45:41 AM PDT 24 | Jul 01 10:45:45 AM PDT 24 | 9175223 ps | ||
| T57 | /workspace/coverage/sync_alert/18.prim_sync_alert.3530787971 | Jul 01 10:45:27 AM PDT 24 | Jul 01 10:45:28 AM PDT 24 | 9630071 ps | ||
| T30 | /workspace/coverage/sync_alert/19.prim_sync_alert.7611178 | Jul 01 10:45:44 AM PDT 24 | Jul 01 10:45:48 AM PDT 24 | 8851029 ps | ||
| T58 | /workspace/coverage/sync_alert/7.prim_sync_alert.2935180252 | Jul 01 10:45:28 AM PDT 24 | Jul 01 10:45:29 AM PDT 24 | 8957455 ps | ||
| T31 | /workspace/coverage/sync_alert/1.prim_sync_alert.2344051108 | Jul 01 10:45:25 AM PDT 24 | Jul 01 10:45:26 AM PDT 24 | 9498101 ps | ||
| T32 | /workspace/coverage/sync_alert/3.prim_sync_alert.4254854517 | Jul 01 10:45:26 AM PDT 24 | Jul 01 10:45:27 AM PDT 24 | 9925891 ps | ||
| T59 | /workspace/coverage/sync_alert/14.prim_sync_alert.2719079673 | Jul 01 10:45:45 AM PDT 24 | Jul 01 10:45:49 AM PDT 24 | 9041919 ps | ||
| T60 | /workspace/coverage/sync_alert/9.prim_sync_alert.1746293589 | Jul 01 10:45:27 AM PDT 24 | Jul 01 10:45:28 AM PDT 24 | 9087079 ps | ||
| T33 | /workspace/coverage/sync_alert/10.prim_sync_alert.2263562641 | Jul 01 10:45:44 AM PDT 24 | Jul 01 10:45:49 AM PDT 24 | 8660027 ps | ||
| T61 | /workspace/coverage/sync_alert/8.prim_sync_alert.2819696124 | Jul 01 10:45:27 AM PDT 24 | Jul 01 10:45:28 AM PDT 24 | 10033100 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2584697411 | Jul 01 10:28:01 AM PDT 24 | Jul 01 10:28:03 AM PDT 24 | 26361799 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3339148456 | Jul 01 10:24:11 AM PDT 24 | Jul 01 10:24:12 AM PDT 24 | 26203273 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3823655169 | Jul 01 10:22:30 AM PDT 24 | Jul 01 10:22:31 AM PDT 24 | 28127400 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3747830762 | Jul 01 10:27:30 AM PDT 24 | Jul 01 10:27:31 AM PDT 24 | 27197385 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3123078880 | Jul 01 10:22:32 AM PDT 24 | Jul 01 10:22:33 AM PDT 24 | 29511313 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.944740285 | Jul 01 10:22:39 AM PDT 24 | Jul 01 10:22:40 AM PDT 24 | 27346156 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1493804486 | Jul 01 10:22:41 AM PDT 24 | Jul 01 10:22:42 AM PDT 24 | 24464573 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4170088802 | Jul 01 10:29:29 AM PDT 24 | Jul 01 10:29:31 AM PDT 24 | 26128068 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1755169154 | Jul 01 10:22:27 AM PDT 24 | Jul 01 10:22:28 AM PDT 24 | 26703606 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.147848192 | Jul 01 10:22:32 AM PDT 24 | Jul 01 10:22:33 AM PDT 24 | 28692515 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3848339238 | Jul 01 10:22:31 AM PDT 24 | Jul 01 10:22:32 AM PDT 24 | 28836903 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.356976937 | Jul 01 10:22:29 AM PDT 24 | Jul 01 10:22:31 AM PDT 24 | 25418306 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2081264350 | Jul 01 10:22:23 AM PDT 24 | Jul 01 10:22:24 AM PDT 24 | 27530975 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4156664703 | Jul 01 10:25:12 AM PDT 24 | Jul 01 10:25:13 AM PDT 24 | 26413942 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2068918632 | Jul 01 10:28:02 AM PDT 24 | Jul 01 10:28:03 AM PDT 24 | 28066432 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1228617710 | Jul 01 10:22:39 AM PDT 24 | Jul 01 10:22:40 AM PDT 24 | 28109473 ps | ||
| T11 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2114531872 | Jul 01 10:22:20 AM PDT 24 | Jul 01 10:22:22 AM PDT 24 | 28092697 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.677920334 | Jul 01 10:28:21 AM PDT 24 | Jul 01 10:28:22 AM PDT 24 | 27983323 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1917920955 | Jul 01 10:28:13 AM PDT 24 | Jul 01 10:28:14 AM PDT 24 | 26388577 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2258202337 | Jul 01 10:22:33 AM PDT 24 | Jul 01 10:22:34 AM PDT 24 | 29707120 ps |
| Test location | /workspace/coverage/default/10.prim_async_alert.1211728924 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10819347 ps |
| CPU time | 0.37 seconds |
| Started | Jul 01 10:22:37 AM PDT 24 |
| Finished | Jul 01 10:22:38 AM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-32f6fda5-7183-4331-b75b-3f582064d0f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1211728924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1211728924 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1618636519 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10063857 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:45:41 AM PDT 24 |
| Finished | Jul 01 10:45:43 AM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-27e988a5-edd9-41cc-a8ab-04be2cd632dd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1618636519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1618636519 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1819915698 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 29678280 ps |
| CPU time | 0.41 seconds |
| Started | Jul 01 10:27:32 AM PDT 24 |
| Finished | Jul 01 10:27:33 AM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-66b3fff9-45aa-4a1a-9848-f72fbadd2d91 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1819915698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1819915698 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.1882564463 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12255984 ps |
| CPU time | 0.43 seconds |
| Started | Jul 01 10:27:17 AM PDT 24 |
| Finished | Jul 01 10:27:18 AM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-8a6d25a9-2d60-4bb2-addd-4cb7dd38a07f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882564463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1882564463 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.2405042861 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9175223 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:45:41 AM PDT 24 |
| Finished | Jul 01 10:45:45 AM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-bec74ae1-5e3a-4d3a-9683-c7f3cce6eed8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2405042861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2405042861 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.2796351880 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11673209 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:29:30 AM PDT 24 |
| Finished | Jul 01 10:29:31 AM PDT 24 |
| Peak memory | 145344 kb |
| Host | smart-3551420d-4159-494a-b76a-206aa1f70c63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2796351880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2796351880 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.2936594560 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11684728 ps |
| CPU time | 0.43 seconds |
| Started | Jul 01 10:22:40 AM PDT 24 |
| Finished | Jul 01 10:22:41 AM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-18c4c146-f60c-4b46-9559-41a3d620f048 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2936594560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2936594560 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.2813728489 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11317555 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:22:24 AM PDT 24 |
| Finished | Jul 01 10:22:24 AM PDT 24 |
| Peak memory | 145880 kb |
| Host | smart-18dcc819-7216-4fa9-b1cb-4c926fc99a7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2813728489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2813728489 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.1014550809 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10684761 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:22:31 AM PDT 24 |
| Finished | Jul 01 10:22:32 AM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-923b99e1-fecd-4802-8cee-8d8eb01b783d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1014550809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1014550809 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3888548402 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11600585 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:22:39 AM PDT 24 |
| Finished | Jul 01 10:22:40 AM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-4c1138b8-f287-44e2-89f3-4245aafa364a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888548402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3888548402 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1201638394 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11900398 ps |
| CPU time | 0.44 seconds |
| Started | Jul 01 10:22:41 AM PDT 24 |
| Finished | Jul 01 10:22:42 AM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-4278a48f-2515-43b2-b0df-4f1eb8484925 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201638394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1201638394 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1881180396 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11331479 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:22:31 AM PDT 24 |
| Finished | Jul 01 10:22:32 AM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-36866e36-c3ca-49e1-a044-35668b7c6e66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1881180396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1881180396 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.1513163454 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11485645 ps |
| CPU time | 0.42 seconds |
| Started | Jul 01 10:26:19 AM PDT 24 |
| Finished | Jul 01 10:26:20 AM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-d9d89a3a-bcd2-41c8-942a-52c02ba668b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1513163454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1513163454 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.1284938397 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11606207 ps |
| CPU time | 0.55 seconds |
| Started | Jul 01 10:22:27 AM PDT 24 |
| Finished | Jul 01 10:22:28 AM PDT 24 |
| Peak memory | 144796 kb |
| Host | smart-3fe45f34-987f-4d0f-8210-3864b73e107d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284938397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1284938397 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.2038089914 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11866377 ps |
| CPU time | 0.37 seconds |
| Started | Jul 01 10:22:33 AM PDT 24 |
| Finished | Jul 01 10:22:34 AM PDT 24 |
| Peak memory | 145276 kb |
| Host | smart-d2a7d8c7-9f32-4c0a-83cb-a0beee1c3419 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038089914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2038089914 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.84385402 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10349426 ps |
| CPU time | 0.4 seconds |
| Started | Jul 01 10:23:14 AM PDT 24 |
| Finished | Jul 01 10:23:14 AM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-2e4090d0-4c2f-4e39-bd91-008b0bdd9f0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84385402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.84385402 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.1346647525 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11003009 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:28:02 AM PDT 24 |
| Finished | Jul 01 10:28:04 AM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-e30bd9e4-6c3b-42c3-9771-99993cfddc5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1346647525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1346647525 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.393327518 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10296414 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:27:17 AM PDT 24 |
| Finished | Jul 01 10:27:18 AM PDT 24 |
| Peak memory | 145412 kb |
| Host | smart-8be8c32a-a7e2-401b-9643-5eb36b8ed18e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393327518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.393327518 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.4185829101 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11594488 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:22:46 AM PDT 24 |
| Finished | Jul 01 10:22:46 AM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-c2353daf-aa49-4a13-b4e2-80f9f55b1089 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4185829101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.4185829101 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3861584019 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10898929 ps |
| CPU time | 0.45 seconds |
| Started | Jul 01 10:22:20 AM PDT 24 |
| Finished | Jul 01 10:22:22 AM PDT 24 |
| Peak memory | 144568 kb |
| Host | smart-e152806f-ce31-49b4-b450-2b32c25ca17d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861584019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3861584019 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.229487806 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11195799 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:28:03 AM PDT 24 |
| Finished | Jul 01 10:28:04 AM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-5d622979-d151-4881-860c-04e0eabc8ced |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=229487806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.229487806 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.1094512769 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10359523 ps |
| CPU time | 0.4 seconds |
| Started | Jul 01 10:27:32 AM PDT 24 |
| Finished | Jul 01 10:27:33 AM PDT 24 |
| Peak memory | 145376 kb |
| Host | smart-48e1787f-531a-4e03-8165-4ef1eaefafde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1094512769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1094512769 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.1574482613 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 12199660 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:22:32 AM PDT 24 |
| Finished | Jul 01 10:22:33 AM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-ce98419e-fb42-4502-990e-033791d2aa5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574482613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1574482613 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1245928124 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 31792160 ps |
| CPU time | 0.42 seconds |
| Started | Jul 01 10:27:32 AM PDT 24 |
| Finished | Jul 01 10:27:33 AM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-83e829ce-2642-4080-ac4c-d5f7b48693a3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1245928124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1245928124 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2857961761 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 29930915 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:28:16 AM PDT 24 |
| Finished | Jul 01 10:28:18 AM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-3500602d-19b7-4b1c-8e82-7505efba305b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2857961761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2857961761 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3990308571 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 31163172 ps |
| CPU time | 0.4 seconds |
| Started | Jul 01 10:22:32 AM PDT 24 |
| Finished | Jul 01 10:22:33 AM PDT 24 |
| Peak memory | 144520 kb |
| Host | smart-6de23f31-8eb5-4d26-ba4b-b3a19138cb06 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3990308571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3990308571 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3528995466 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 31045381 ps |
| CPU time | 0.47 seconds |
| Started | Jul 01 10:25:35 AM PDT 24 |
| Finished | Jul 01 10:25:36 AM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-ff5db9b7-dd7a-4512-b393-7ec650b773b1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3528995466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3528995466 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2694702349 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 31663006 ps |
| CPU time | 0.41 seconds |
| Started | Jul 01 10:22:40 AM PDT 24 |
| Finished | Jul 01 10:22:41 AM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-061c7e88-8793-4520-a36f-1855a6157e13 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2694702349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2694702349 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4053457379 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30837339 ps |
| CPU time | 0.4 seconds |
| Started | Jul 01 10:22:30 AM PDT 24 |
| Finished | Jul 01 10:22:31 AM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-7daeba33-947a-47ed-9baa-1e00b427e5db |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4053457379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.4053457379 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1526944122 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 32885314 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:27:17 AM PDT 24 |
| Finished | Jul 01 10:27:18 AM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-87a37731-ccae-4a65-93cc-f9cc571ebf20 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1526944122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1526944122 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2250248035 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 30740133 ps |
| CPU time | 0.42 seconds |
| Started | Jul 01 10:22:47 AM PDT 24 |
| Finished | Jul 01 10:22:47 AM PDT 24 |
| Peak memory | 145268 kb |
| Host | smart-b9b8abd3-af1c-4c32-b0ef-0874b07e1ad7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2250248035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2250248035 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3351650776 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 29249330 ps |
| CPU time | 0.41 seconds |
| Started | Jul 01 10:22:26 AM PDT 24 |
| Finished | Jul 01 10:22:26 AM PDT 24 |
| Peak memory | 145412 kb |
| Host | smart-27715612-cb0d-4e84-a2c4-57a4fcf152f2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3351650776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3351650776 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2463940256 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30672772 ps |
| CPU time | 0.4 seconds |
| Started | Jul 01 10:22:39 AM PDT 24 |
| Finished | Jul 01 10:22:40 AM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-2f6121ec-101f-48f3-b10c-b3832a874483 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2463940256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2463940256 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.868214101 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 31339085 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:22:32 AM PDT 24 |
| Finished | Jul 01 10:22:33 AM PDT 24 |
| Peak memory | 144648 kb |
| Host | smart-e6d4ac7e-7c8a-43df-8a55-b0686c798e2b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=868214101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.868214101 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2423049904 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 31083682 ps |
| CPU time | 0.41 seconds |
| Started | Jul 01 10:22:24 AM PDT 24 |
| Finished | Jul 01 10:22:25 AM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-a625a4c5-2d7a-433a-bca4-6b828e910ba7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2423049904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2423049904 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3706094738 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 30826406 ps |
| CPU time | 0.41 seconds |
| Started | Jul 01 10:22:34 AM PDT 24 |
| Finished | Jul 01 10:22:35 AM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-2a409fbb-1f2c-475e-9190-e4b5cc73a6cc |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3706094738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3706094738 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1488000509 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29281668 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:28:02 AM PDT 24 |
| Finished | Jul 01 10:28:04 AM PDT 24 |
| Peak memory | 144888 kb |
| Host | smart-6350a110-c728-4584-a0fe-634ce87193ea |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1488000509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1488000509 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3623920209 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 30965128 ps |
| CPU time | 0.44 seconds |
| Started | Jul 01 10:28:02 AM PDT 24 |
| Finished | Jul 01 10:28:03 AM PDT 24 |
| Peak memory | 143136 kb |
| Host | smart-f83c3f77-add7-4a4b-8026-da5b4c5232d3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3623920209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3623920209 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2835279116 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 31421499 ps |
| CPU time | 0.41 seconds |
| Started | Jul 01 10:27:31 AM PDT 24 |
| Finished | Jul 01 10:27:31 AM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-dc4b31aa-cef9-42a5-a6bf-e2926bfd208e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2835279116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2835279116 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.44189956 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30308020 ps |
| CPU time | 0.4 seconds |
| Started | Jul 01 10:22:33 AM PDT 24 |
| Finished | Jul 01 10:22:34 AM PDT 24 |
| Peak memory | 144860 kb |
| Host | smart-26d1c5d7-37ef-426d-ab02-c723d63c8372 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=44189956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.44189956 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1696900815 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 28537117 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:29:37 AM PDT 24 |
| Finished | Jul 01 10:29:38 AM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-ad537f38-4fe0-43bf-b9b1-42b46e26579b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1696900815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1696900815 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.3300486359 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8983879 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:45:24 AM PDT 24 |
| Finished | Jul 01 10:45:25 AM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-967e7a62-493b-4102-9003-8dcd67b294f8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3300486359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3300486359 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.2344051108 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9498101 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:45:25 AM PDT 24 |
| Finished | Jul 01 10:45:26 AM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-273299fb-6213-480e-9edc-e919678a7cc3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2344051108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2344051108 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.2263562641 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8660027 ps |
| CPU time | 0.37 seconds |
| Started | Jul 01 10:45:44 AM PDT 24 |
| Finished | Jul 01 10:45:49 AM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-6d6bd343-b141-4747-9816-53f954a7186a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2263562641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2263562641 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1065989256 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9750641 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:45:43 AM PDT 24 |
| Finished | Jul 01 10:45:48 AM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-5c6ab67a-cafd-4db2-a5c7-eb2985229513 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1065989256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1065989256 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.1934833824 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8475317 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:45:42 AM PDT 24 |
| Finished | Jul 01 10:45:46 AM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-5734c6f4-0d51-4da3-9968-47ecfee7ed75 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1934833824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1934833824 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1387131647 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9519435 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:45:25 AM PDT 24 |
| Finished | Jul 01 10:45:26 AM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-f10904d7-7634-43df-9315-429c39ceb457 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1387131647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1387131647 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.2719079673 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9041919 ps |
| CPU time | 0.37 seconds |
| Started | Jul 01 10:45:45 AM PDT 24 |
| Finished | Jul 01 10:45:49 AM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-1f6a3fa1-a5af-49af-b914-4977906a206c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2719079673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2719079673 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.1214716024 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8698639 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:45:25 AM PDT 24 |
| Finished | Jul 01 10:45:26 AM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-8b4c95ca-5bbc-4a25-a716-1dcbcb2c6fc9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1214716024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1214716024 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.138374060 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9544837 ps |
| CPU time | 0.4 seconds |
| Started | Jul 01 10:45:25 AM PDT 24 |
| Finished | Jul 01 10:45:26 AM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-9049e0e4-e671-430d-aa4a-e2f2a0ec3901 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=138374060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.138374060 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.3885483125 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8950324 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:45:35 AM PDT 24 |
| Finished | Jul 01 10:45:36 AM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-d97b1296-2cba-46df-bdf4-8b2f482154b2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3885483125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3885483125 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.3530787971 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9630071 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:45:27 AM PDT 24 |
| Finished | Jul 01 10:45:28 AM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-a4a41d9b-d3ed-43b1-b68a-7c7476980cb0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3530787971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3530787971 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.7611178 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8851029 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:45:44 AM PDT 24 |
| Finished | Jul 01 10:45:48 AM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-930ea5f5-d608-4d2d-bd46-d3ae3a0cf1ec |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=7611178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.7611178 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.3660785357 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9925026 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:45:27 AM PDT 24 |
| Finished | Jul 01 10:45:28 AM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-a72ce1a9-994b-48a7-8457-229f062cf6a7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3660785357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3660785357 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.4254854517 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9925891 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:45:26 AM PDT 24 |
| Finished | Jul 01 10:45:27 AM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-6041d013-43a2-4cba-85df-b49bbde5bfc4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4254854517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.4254854517 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1500184328 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8467977 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:45:29 AM PDT 24 |
| Finished | Jul 01 10:45:30 AM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-ea25b50d-1e0d-45ee-879d-5d147b8f374b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1500184328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1500184328 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.2935180252 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8957455 ps |
| CPU time | 0.41 seconds |
| Started | Jul 01 10:45:28 AM PDT 24 |
| Finished | Jul 01 10:45:29 AM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-3820d60d-bbfa-41ab-af62-f4fe123c1bb3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2935180252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2935180252 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.2819696124 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 10033100 ps |
| CPU time | 0.41 seconds |
| Started | Jul 01 10:45:27 AM PDT 24 |
| Finished | Jul 01 10:45:28 AM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-e516e6b3-4778-471a-8a83-d47cb2a1571a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2819696124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2819696124 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.1746293589 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9087079 ps |
| CPU time | 0.41 seconds |
| Started | Jul 01 10:45:27 AM PDT 24 |
| Finished | Jul 01 10:45:28 AM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-fa7acbcf-478c-4c93-8161-9252c118fa77 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1746293589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1746293589 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.356976937 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 25418306 ps |
| CPU time | 0.43 seconds |
| Started | Jul 01 10:22:29 AM PDT 24 |
| Finished | Jul 01 10:22:31 AM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-2e18b4df-62e6-4f79-b0f8-995b66583eb7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=356976937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.356976937 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.677920334 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27983323 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:28:21 AM PDT 24 |
| Finished | Jul 01 10:28:22 AM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-346ece17-a668-4d64-bee0-0e74ff720f53 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=677920334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.677920334 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3339148456 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 26203273 ps |
| CPU time | 0.44 seconds |
| Started | Jul 01 10:24:11 AM PDT 24 |
| Finished | Jul 01 10:24:12 AM PDT 24 |
| Peak memory | 145404 kb |
| Host | smart-3e38c304-1d11-44a2-8a87-d9133dbeb191 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3339148456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3339148456 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1755169154 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 26703606 ps |
| CPU time | 0.41 seconds |
| Started | Jul 01 10:22:27 AM PDT 24 |
| Finished | Jul 01 10:22:28 AM PDT 24 |
| Peak memory | 145700 kb |
| Host | smart-7f65f9e0-eae3-48b9-ae7f-df67f819026e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1755169154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1755169154 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4156664703 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26413942 ps |
| CPU time | 0.43 seconds |
| Started | Jul 01 10:25:12 AM PDT 24 |
| Finished | Jul 01 10:25:13 AM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-678ea944-226a-40cf-8c4a-a873d48d2ebd |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4156664703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.4156664703 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3823655169 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 28127400 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:22:30 AM PDT 24 |
| Finished | Jul 01 10:22:31 AM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-d7ac74a6-5b85-4473-b28a-23de51bf6c3c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3823655169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3823655169 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1493804486 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 24464573 ps |
| CPU time | 0.4 seconds |
| Started | Jul 01 10:22:41 AM PDT 24 |
| Finished | Jul 01 10:22:42 AM PDT 24 |
| Peak memory | 145524 kb |
| Host | smart-9471afae-25eb-4e20-a0b4-020d85461d50 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1493804486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1493804486 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.944740285 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27346156 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:22:39 AM PDT 24 |
| Finished | Jul 01 10:22:40 AM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-cd91015f-e132-48b6-a95d-564cf4889a49 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=944740285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.944740285 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4170088802 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26128068 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:29:29 AM PDT 24 |
| Finished | Jul 01 10:29:31 AM PDT 24 |
| Peak memory | 146332 kb |
| Host | smart-14bb13e3-9dfc-4dda-959f-741f45f2ac33 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4170088802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.4170088802 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1917920955 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26388577 ps |
| CPU time | 0.38 seconds |
| Started | Jul 01 10:28:13 AM PDT 24 |
| Finished | Jul 01 10:28:14 AM PDT 24 |
| Peak memory | 145392 kb |
| Host | smart-b9269876-ac1b-44d0-84db-2afcd9815cfc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1917920955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1917920955 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1228617710 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 28109473 ps |
| CPU time | 0.41 seconds |
| Started | Jul 01 10:22:39 AM PDT 24 |
| Finished | Jul 01 10:22:40 AM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-298a991a-3680-41c5-b537-696f23e6ec0b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1228617710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1228617710 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2584697411 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 26361799 ps |
| CPU time | 0.44 seconds |
| Started | Jul 01 10:28:01 AM PDT 24 |
| Finished | Jul 01 10:28:03 AM PDT 24 |
| Peak memory | 142740 kb |
| Host | smart-1d55dc7c-9db8-4213-931b-2c9adcca85c1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2584697411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2584697411 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2081264350 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27530975 ps |
| CPU time | 0.41 seconds |
| Started | Jul 01 10:22:23 AM PDT 24 |
| Finished | Jul 01 10:22:24 AM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-22c423c3-b5b6-413f-a48e-72170d70e684 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2081264350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2081264350 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3123078880 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 29511313 ps |
| CPU time | 0.43 seconds |
| Started | Jul 01 10:22:32 AM PDT 24 |
| Finished | Jul 01 10:22:33 AM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-2944a033-0b9f-4c68-a0f1-7188bf739d16 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3123078880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3123078880 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3848339238 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 28836903 ps |
| CPU time | 0.4 seconds |
| Started | Jul 01 10:22:31 AM PDT 24 |
| Finished | Jul 01 10:22:32 AM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-816c06c4-7eef-4fc3-a495-ca9f2784fcbe |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3848339238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3848339238 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3747830762 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27197385 ps |
| CPU time | 0.39 seconds |
| Started | Jul 01 10:27:30 AM PDT 24 |
| Finished | Jul 01 10:27:31 AM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-053cfeb4-e7eb-4e1c-8b16-92668e76de28 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3747830762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3747830762 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.147848192 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28692515 ps |
| CPU time | 0.42 seconds |
| Started | Jul 01 10:22:32 AM PDT 24 |
| Finished | Jul 01 10:22:33 AM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-b07afe4d-9f80-4bd3-87c9-6c315184a329 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=147848192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.147848192 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2258202337 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 29707120 ps |
| CPU time | 0.4 seconds |
| Started | Jul 01 10:22:33 AM PDT 24 |
| Finished | Jul 01 10:22:34 AM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-9ca10ab3-d8f1-4993-9593-5f7b70863c61 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2258202337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2258202337 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2114531872 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 28092697 ps |
| CPU time | 0.42 seconds |
| Started | Jul 01 10:22:20 AM PDT 24 |
| Finished | Jul 01 10:22:22 AM PDT 24 |
| Peak memory | 144420 kb |
| Host | smart-ae9835b1-6403-4bdf-aa3f-545a759b6b2c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2114531872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2114531872 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2068918632 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 28066432 ps |
| CPU time | 0.44 seconds |
| Started | Jul 01 10:28:02 AM PDT 24 |
| Finished | Jul 01 10:28:03 AM PDT 24 |
| Peak memory | 143180 kb |
| Host | smart-06b27ac4-bf51-4a66-baf6-c71d27c85755 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2068918632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2068918632 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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