Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.63 88.63 100.00 100.00 95.83 95.83 96.43 96.43 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/3.prim_async_alert.2235305021
91.37 2.74 100.00 0.00 95.83 0.00 100.00 3.57 82.14 3.57 95.83 0.00 74.42 9.30 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.600494309
93.90 2.53 100.00 0.00 95.83 0.00 100.00 0.00 85.71 3.57 95.83 0.00 86.05 11.63 /workspace/coverage/sync_alert/12.prim_sync_alert.1918707352
94.85 0.94 100.00 0.00 97.92 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3613643656

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3832647849
/workspace/coverage/default/1.prim_async_alert.584274485
/workspace/coverage/default/10.prim_async_alert.3775001549
/workspace/coverage/default/11.prim_async_alert.2295038040
/workspace/coverage/default/12.prim_async_alert.2656574093
/workspace/coverage/default/13.prim_async_alert.3704417225
/workspace/coverage/default/14.prim_async_alert.1957856989
/workspace/coverage/default/15.prim_async_alert.1674883342
/workspace/coverage/default/16.prim_async_alert.1603015635
/workspace/coverage/default/17.prim_async_alert.4130017197
/workspace/coverage/default/18.prim_async_alert.3189673158
/workspace/coverage/default/19.prim_async_alert.3956518366
/workspace/coverage/default/2.prim_async_alert.3020266931
/workspace/coverage/default/4.prim_async_alert.2458209154
/workspace/coverage/default/5.prim_async_alert.2254864306
/workspace/coverage/default/6.prim_async_alert.862445120
/workspace/coverage/default/7.prim_async_alert.591775646
/workspace/coverage/default/8.prim_async_alert.2654233421
/workspace/coverage/default/9.prim_async_alert.2740294091
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.692668928
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.797061767
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3952740583
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1456296327
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3874176672
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2018137739
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1879656624
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3700452616
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.655084957
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3421714591
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2973078826
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1048682490
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3910032302
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.675629014
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1340570365
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3231276170
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3390445566
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2604098118
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1777256995
/workspace/coverage/sync_alert/0.prim_sync_alert.2456845026
/workspace/coverage/sync_alert/1.prim_sync_alert.2453919027
/workspace/coverage/sync_alert/10.prim_sync_alert.3456615171
/workspace/coverage/sync_alert/11.prim_sync_alert.307856084
/workspace/coverage/sync_alert/13.prim_sync_alert.888623415
/workspace/coverage/sync_alert/14.prim_sync_alert.3229846488
/workspace/coverage/sync_alert/15.prim_sync_alert.2370896151
/workspace/coverage/sync_alert/16.prim_sync_alert.336097028
/workspace/coverage/sync_alert/17.prim_sync_alert.2456163826
/workspace/coverage/sync_alert/18.prim_sync_alert.2293119469
/workspace/coverage/sync_alert/19.prim_sync_alert.2612236487
/workspace/coverage/sync_alert/2.prim_sync_alert.1728244245
/workspace/coverage/sync_alert/3.prim_sync_alert.1797182007
/workspace/coverage/sync_alert/4.prim_sync_alert.1023447663
/workspace/coverage/sync_alert/5.prim_sync_alert.372419233
/workspace/coverage/sync_alert/6.prim_sync_alert.1332815503
/workspace/coverage/sync_alert/7.prim_sync_alert.3483069845
/workspace/coverage/sync_alert/8.prim_sync_alert.3989711257
/workspace/coverage/sync_alert/9.prim_sync_alert.981743337
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1498302832
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2474875636
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3950631014
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3120014949
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4124044742
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2399605433
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.411119534
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2358472768
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1938310831
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1756928474
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3131568117
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.229092527
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1248246543
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3274416691
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1927877353
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3921008034
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2450608784
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2345556825
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3153511127



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/16.prim_async_alert.1603015635 Jul 01 04:15:49 PM PDT 24 Jul 01 04:15:50 PM PDT 24 11048546 ps
T2 /workspace/coverage/default/1.prim_async_alert.584274485 Jul 01 04:15:50 PM PDT 24 Jul 01 04:15:53 PM PDT 24 11744402 ps
T3 /workspace/coverage/default/7.prim_async_alert.591775646 Jul 01 04:15:52 PM PDT 24 Jul 01 04:15:56 PM PDT 24 11621070 ps
T7 /workspace/coverage/default/3.prim_async_alert.2235305021 Jul 01 04:15:51 PM PDT 24 Jul 01 04:15:55 PM PDT 24 11400147 ps
T13 /workspace/coverage/default/17.prim_async_alert.4130017197 Jul 01 04:15:53 PM PDT 24 Jul 01 04:15:59 PM PDT 24 11156450 ps
T10 /workspace/coverage/default/15.prim_async_alert.1674883342 Jul 01 04:15:55 PM PDT 24 Jul 01 04:16:04 PM PDT 24 12753984 ps
T8 /workspace/coverage/default/12.prim_async_alert.2656574093 Jul 01 04:15:53 PM PDT 24 Jul 01 04:15:59 PM PDT 24 11580537 ps
T17 /workspace/coverage/default/14.prim_async_alert.1957856989 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 11594171 ps
T18 /workspace/coverage/default/13.prim_async_alert.3704417225 Jul 01 04:15:53 PM PDT 24 Jul 01 04:15:59 PM PDT 24 10925738 ps
T19 /workspace/coverage/default/11.prim_async_alert.2295038040 Jul 01 04:15:50 PM PDT 24 Jul 01 04:15:52 PM PDT 24 11161745 ps
T11 /workspace/coverage/default/6.prim_async_alert.862445120 Jul 01 04:15:53 PM PDT 24 Jul 01 04:15:59 PM PDT 24 11973950 ps
T24 /workspace/coverage/default/0.prim_async_alert.3832647849 Jul 01 04:15:55 PM PDT 24 Jul 01 04:16:03 PM PDT 24 11897861 ps
T20 /workspace/coverage/default/10.prim_async_alert.3775001549 Jul 01 04:15:51 PM PDT 24 Jul 01 04:15:55 PM PDT 24 11865173 ps
T16 /workspace/coverage/default/2.prim_async_alert.3020266931 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 11902918 ps
T12 /workspace/coverage/default/5.prim_async_alert.2254864306 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 12250968 ps
T21 /workspace/coverage/default/8.prim_async_alert.2654233421 Jul 01 04:15:50 PM PDT 24 Jul 01 04:15:51 PM PDT 24 10857512 ps
T22 /workspace/coverage/default/19.prim_async_alert.3956518366 Jul 01 04:15:50 PM PDT 24 Jul 01 04:15:51 PM PDT 24 11537199 ps
T14 /workspace/coverage/default/9.prim_async_alert.2740294091 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 11769160 ps
T46 /workspace/coverage/default/4.prim_async_alert.2458209154 Jul 01 04:15:51 PM PDT 24 Jul 01 04:15:55 PM PDT 24 10689626 ps
T47 /workspace/coverage/default/18.prim_async_alert.3189673158 Jul 01 04:15:53 PM PDT 24 Jul 01 04:15:59 PM PDT 24 11289283 ps
T9 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3952740583 Jul 01 04:15:53 PM PDT 24 Jul 01 04:15:59 PM PDT 24 29012127 ps
T23 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3874176672 Jul 01 04:15:52 PM PDT 24 Jul 01 04:15:57 PM PDT 24 29961233 ps
T15 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.600494309 Jul 01 04:15:50 PM PDT 24 Jul 01 04:15:53 PM PDT 24 30910091 ps
T40 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.675629014 Jul 01 04:15:51 PM PDT 24 Jul 01 04:15:53 PM PDT 24 32802702 ps
T4 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2604098118 Jul 01 04:15:55 PM PDT 24 Jul 01 04:16:04 PM PDT 24 30096084 ps
T41 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2018137739 Jul 01 04:15:50 PM PDT 24 Jul 01 04:15:51 PM PDT 24 30801358 ps
T42 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.692668928 Jul 01 04:15:49 PM PDT 24 Jul 01 04:15:51 PM PDT 24 27767246 ps
T43 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2973078826 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 31477980 ps
T44 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1048682490 Jul 01 04:15:53 PM PDT 24 Jul 01 04:15:59 PM PDT 24 33448006 ps
T45 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3910032302 Jul 01 04:15:53 PM PDT 24 Jul 01 04:16:00 PM PDT 24 31232565 ps
T48 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3231276170 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:01 PM PDT 24 28308218 ps
T49 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.655084957 Jul 01 04:15:52 PM PDT 24 Jul 01 04:15:58 PM PDT 24 29055001 ps
T50 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.797061767 Jul 01 04:15:53 PM PDT 24 Jul 01 04:15:59 PM PDT 24 31312618 ps
T51 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1456296327 Jul 01 04:15:50 PM PDT 24 Jul 01 04:15:53 PM PDT 24 32373038 ps
T52 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1777256995 Jul 01 04:15:55 PM PDT 24 Jul 01 04:16:03 PM PDT 24 30269729 ps
T53 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1879656624 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:01 PM PDT 24 29680318 ps
T54 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3390445566 Jul 01 04:15:53 PM PDT 24 Jul 01 04:16:00 PM PDT 24 29186799 ps
T55 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1340570365 Jul 01 04:15:52 PM PDT 24 Jul 01 04:15:57 PM PDT 24 29921152 ps
T56 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3421714591 Jul 01 04:15:51 PM PDT 24 Jul 01 04:15:55 PM PDT 24 28803129 ps
T57 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3700452616 Jul 01 04:15:52 PM PDT 24 Jul 01 04:15:57 PM PDT 24 32619655 ps
T34 /workspace/coverage/sync_alert/5.prim_sync_alert.372419233 Jul 01 04:15:51 PM PDT 24 Jul 01 04:15:53 PM PDT 24 9033376 ps
T35 /workspace/coverage/sync_alert/16.prim_sync_alert.336097028 Jul 01 04:15:53 PM PDT 24 Jul 01 04:15:59 PM PDT 24 9700352 ps
T36 /workspace/coverage/sync_alert/14.prim_sync_alert.3229846488 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:01 PM PDT 24 9159653 ps
T25 /workspace/coverage/sync_alert/17.prim_sync_alert.2456163826 Jul 01 04:15:52 PM PDT 24 Jul 01 04:15:58 PM PDT 24 8864740 ps
T26 /workspace/coverage/sync_alert/19.prim_sync_alert.2612236487 Jul 01 04:15:53 PM PDT 24 Jul 01 04:15:58 PM PDT 24 9549128 ps
T27 /workspace/coverage/sync_alert/10.prim_sync_alert.3456615171 Jul 01 04:15:52 PM PDT 24 Jul 01 04:15:58 PM PDT 24 9116311 ps
T28 /workspace/coverage/sync_alert/18.prim_sync_alert.2293119469 Jul 01 04:15:50 PM PDT 24 Jul 01 04:15:51 PM PDT 24 8397069 ps
T29 /workspace/coverage/sync_alert/12.prim_sync_alert.1918707352 Jul 01 04:15:50 PM PDT 24 Jul 01 04:15:53 PM PDT 24 8227314 ps
T30 /workspace/coverage/sync_alert/1.prim_sync_alert.2453919027 Jul 01 04:15:51 PM PDT 24 Jul 01 04:15:54 PM PDT 24 9515591 ps
T37 /workspace/coverage/sync_alert/0.prim_sync_alert.2456845026 Jul 01 04:15:52 PM PDT 24 Jul 01 04:15:58 PM PDT 24 8524479 ps
T58 /workspace/coverage/sync_alert/9.prim_sync_alert.981743337 Jul 01 04:15:53 PM PDT 24 Jul 01 04:16:00 PM PDT 24 8761206 ps
T38 /workspace/coverage/sync_alert/3.prim_sync_alert.1797182007 Jul 01 04:15:53 PM PDT 24 Jul 01 04:16:00 PM PDT 24 9480699 ps
T31 /workspace/coverage/sync_alert/4.prim_sync_alert.1023447663 Jul 01 04:15:53 PM PDT 24 Jul 01 04:15:59 PM PDT 24 9776184 ps
T32 /workspace/coverage/sync_alert/13.prim_sync_alert.888623415 Jul 01 04:15:51 PM PDT 24 Jul 01 04:15:53 PM PDT 24 9180309 ps
T59 /workspace/coverage/sync_alert/8.prim_sync_alert.3989711257 Jul 01 04:15:53 PM PDT 24 Jul 01 04:16:00 PM PDT 24 8498981 ps
T60 /workspace/coverage/sync_alert/2.prim_sync_alert.1728244245 Jul 01 04:15:53 PM PDT 24 Jul 01 04:16:00 PM PDT 24 8937022 ps
T61 /workspace/coverage/sync_alert/15.prim_sync_alert.2370896151 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 8951782 ps
T33 /workspace/coverage/sync_alert/11.prim_sync_alert.307856084 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 9713691 ps
T62 /workspace/coverage/sync_alert/6.prim_sync_alert.1332815503 Jul 01 04:15:51 PM PDT 24 Jul 01 04:15:55 PM PDT 24 9276181 ps
T63 /workspace/coverage/sync_alert/7.prim_sync_alert.3483069845 Jul 01 04:15:50 PM PDT 24 Jul 01 04:15:52 PM PDT 24 8775583 ps
T39 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1756928474 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 27933781 ps
T64 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2450608784 Jul 01 04:15:51 PM PDT 24 Jul 01 04:15:55 PM PDT 24 28559963 ps
T65 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2474875636 Jul 01 04:15:52 PM PDT 24 Jul 01 04:15:58 PM PDT 24 28079523 ps
T66 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3120014949 Jul 01 04:15:53 PM PDT 24 Jul 01 04:16:00 PM PDT 24 29134230 ps
T67 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3274416691 Jul 01 04:15:53 PM PDT 24 Jul 01 04:15:59 PM PDT 24 28567042 ps
T5 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1248246543 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:01 PM PDT 24 27207292 ps
T68 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3950631014 Jul 01 04:15:52 PM PDT 24 Jul 01 04:15:57 PM PDT 24 27271815 ps
T69 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3131568117 Jul 01 04:15:53 PM PDT 24 Jul 01 04:15:59 PM PDT 24 26874681 ps
T70 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1938310831 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:01 PM PDT 24 26870896 ps
T6 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3153511127 Jul 01 04:15:51 PM PDT 24 Jul 01 04:15:55 PM PDT 24 27342290 ps
T71 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2358472768 Jul 01 04:15:55 PM PDT 24 Jul 01 04:16:03 PM PDT 24 27845657 ps
T72 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4124044742 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 26994131 ps
T73 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1498302832 Jul 01 04:15:50 PM PDT 24 Jul 01 04:15:52 PM PDT 24 28767756 ps
T74 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1927877353 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 26047455 ps
T75 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2399605433 Jul 01 04:15:55 PM PDT 24 Jul 01 04:16:03 PM PDT 24 28462960 ps
T76 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2345556825 Jul 01 04:15:52 PM PDT 24 Jul 01 04:15:56 PM PDT 24 27229862 ps
T77 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.411119534 Jul 01 04:15:54 PM PDT 24 Jul 01 04:16:02 PM PDT 24 27957776 ps
T78 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3921008034 Jul 01 04:15:50 PM PDT 24 Jul 01 04:15:52 PM PDT 24 29117184 ps
T79 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3613643656 Jul 01 04:15:51 PM PDT 24 Jul 01 04:15:54 PM PDT 24 27005146 ps
T80 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.229092527 Jul 01 04:15:52 PM PDT 24 Jul 01 04:15:56 PM PDT 24 26938246 ps

Test location /workspace/coverage/default/3.prim_async_alert.2235305021
Short name T7
Test name
Test status
Simulation time 11400147 ps
CPU time 0.4 seconds
Started Jul 01 04:15:51 PM PDT 24
Finished Jul 01 04:15:55 PM PDT 24
Peak memory 145872 kb
Host smart-4d75f986-26a6-45c2-b346-09b10c39ae56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235305021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2235305021
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.600494309
Short name T15
Test name
Test status
Simulation time 30910091 ps
CPU time 0.41 seconds
Started Jul 01 04:15:50 PM PDT 24
Finished Jul 01 04:15:53 PM PDT 24
Peak memory 145356 kb
Host smart-2076ddd1-7283-42f9-9dd5-4abe2979246a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=600494309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.600494309
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.1918707352
Short name T29
Test name
Test status
Simulation time 8227314 ps
CPU time 0.38 seconds
Started Jul 01 04:15:50 PM PDT 24
Finished Jul 01 04:15:53 PM PDT 24
Peak memory 145664 kb
Host smart-3d37282d-aa1b-4860-9f11-5943d16ce240
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1918707352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1918707352
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3613643656
Short name T79
Test name
Test status
Simulation time 27005146 ps
CPU time 0.39 seconds
Started Jul 01 04:15:51 PM PDT 24
Finished Jul 01 04:15:54 PM PDT 24
Peak memory 145680 kb
Host smart-6d0e7455-2462-4de6-9477-eb1a53d3280d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3613643656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3613643656
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3832647849
Short name T24
Test name
Test status
Simulation time 11897861 ps
CPU time 0.44 seconds
Started Jul 01 04:15:55 PM PDT 24
Finished Jul 01 04:16:03 PM PDT 24
Peak memory 145876 kb
Host smart-c6a1dd3b-4413-4daf-86b8-99cf57b21e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832647849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3832647849
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.584274485
Short name T2
Test name
Test status
Simulation time 11744402 ps
CPU time 0.4 seconds
Started Jul 01 04:15:50 PM PDT 24
Finished Jul 01 04:15:53 PM PDT 24
Peak memory 145872 kb
Host smart-9193b33c-3122-4cf9-ad51-c8d5b781e5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584274485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.584274485
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3775001549
Short name T20
Test name
Test status
Simulation time 11865173 ps
CPU time 0.39 seconds
Started Jul 01 04:15:51 PM PDT 24
Finished Jul 01 04:15:55 PM PDT 24
Peak memory 145832 kb
Host smart-2dd41a9a-466e-4fdd-ae4b-fa9e7bfa90b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775001549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3775001549
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2295038040
Short name T19
Test name
Test status
Simulation time 11161745 ps
CPU time 0.43 seconds
Started Jul 01 04:15:50 PM PDT 24
Finished Jul 01 04:15:52 PM PDT 24
Peak memory 145816 kb
Host smart-66a890f3-88f1-49f5-be6d-c10f7c1f2e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295038040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2295038040
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2656574093
Short name T8
Test name
Test status
Simulation time 11580537 ps
CPU time 0.38 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:15:59 PM PDT 24
Peak memory 145872 kb
Host smart-14e11ea7-3dbd-48db-a9fb-54a6c1dff783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656574093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2656574093
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3704417225
Short name T18
Test name
Test status
Simulation time 10925738 ps
CPU time 0.39 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:15:59 PM PDT 24
Peak memory 145840 kb
Host smart-9253c760-13cd-4a2d-a9e8-494b01e7b434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704417225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3704417225
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1957856989
Short name T17
Test name
Test status
Simulation time 11594171 ps
CPU time 0.39 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 145888 kb
Host smart-f4700d6d-95f4-4ae0-81cb-151933983ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957856989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1957856989
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1674883342
Short name T10
Test name
Test status
Simulation time 12753984 ps
CPU time 0.39 seconds
Started Jul 01 04:15:55 PM PDT 24
Finished Jul 01 04:16:04 PM PDT 24
Peak memory 145836 kb
Host smart-97f4bb91-afe3-43bc-a139-0e039544fcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674883342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1674883342
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1603015635
Short name T1
Test name
Test status
Simulation time 11048546 ps
CPU time 0.39 seconds
Started Jul 01 04:15:49 PM PDT 24
Finished Jul 01 04:15:50 PM PDT 24
Peak memory 145816 kb
Host smart-83de27bb-d98f-4772-b9d5-deebc6cc8429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603015635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1603015635
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.4130017197
Short name T13
Test name
Test status
Simulation time 11156450 ps
CPU time 0.39 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:15:59 PM PDT 24
Peak memory 145760 kb
Host smart-cee0ceae-d580-4c0e-a894-b0de7997986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130017197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.4130017197
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3189673158
Short name T47
Test name
Test status
Simulation time 11289283 ps
CPU time 0.43 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:15:59 PM PDT 24
Peak memory 145876 kb
Host smart-f77a6183-c98b-4fd1-a9a5-acfe3ec40c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189673158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3189673158
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3956518366
Short name T22
Test name
Test status
Simulation time 11537199 ps
CPU time 0.38 seconds
Started Jul 01 04:15:50 PM PDT 24
Finished Jul 01 04:15:51 PM PDT 24
Peak memory 145876 kb
Host smart-59e47f1e-93c6-4cb8-93e3-515167b1f605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956518366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3956518366
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3020266931
Short name T16
Test name
Test status
Simulation time 11902918 ps
CPU time 0.39 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 145836 kb
Host smart-68fcea37-d137-4291-9b36-fd04a52258d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020266931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3020266931
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2458209154
Short name T46
Test name
Test status
Simulation time 10689626 ps
CPU time 0.4 seconds
Started Jul 01 04:15:51 PM PDT 24
Finished Jul 01 04:15:55 PM PDT 24
Peak memory 145820 kb
Host smart-48ad5842-2927-4201-aa1e-ec02e29680a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458209154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2458209154
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2254864306
Short name T12
Test name
Test status
Simulation time 12250968 ps
CPU time 0.39 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 145868 kb
Host smart-fc6f6f02-37f8-4b4c-8568-adbbde771057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254864306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2254864306
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.862445120
Short name T11
Test name
Test status
Simulation time 11973950 ps
CPU time 0.39 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:15:59 PM PDT 24
Peak memory 145892 kb
Host smart-766cda98-bc51-4566-b472-617b7ec28ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862445120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.862445120
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.591775646
Short name T3
Test name
Test status
Simulation time 11621070 ps
CPU time 0.45 seconds
Started Jul 01 04:15:52 PM PDT 24
Finished Jul 01 04:15:56 PM PDT 24
Peak memory 145820 kb
Host smart-642b7d9f-2445-4db4-8ee0-6361e6b9f500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591775646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.591775646
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2654233421
Short name T21
Test name
Test status
Simulation time 10857512 ps
CPU time 0.39 seconds
Started Jul 01 04:15:50 PM PDT 24
Finished Jul 01 04:15:51 PM PDT 24
Peak memory 145848 kb
Host smart-f9a68c25-0147-4e34-ad9c-9707f54e5bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654233421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2654233421
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2740294091
Short name T14
Test name
Test status
Simulation time 11769160 ps
CPU time 0.39 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 145876 kb
Host smart-86d52141-33b7-4c23-a3ff-1f99e51ba95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740294091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2740294091
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.692668928
Short name T42
Test name
Test status
Simulation time 27767246 ps
CPU time 0.41 seconds
Started Jul 01 04:15:49 PM PDT 24
Finished Jul 01 04:15:51 PM PDT 24
Peak memory 145380 kb
Host smart-bdec7c5b-95e2-4787-aba7-720c83b86b68
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=692668928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.692668928
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.797061767
Short name T50
Test name
Test status
Simulation time 31312618 ps
CPU time 0.41 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:15:59 PM PDT 24
Peak memory 145388 kb
Host smart-b0bcaae7-d1f9-4f58-a44a-c051a18b085b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=797061767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.797061767
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3952740583
Short name T9
Test name
Test status
Simulation time 29012127 ps
CPU time 0.4 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:15:59 PM PDT 24
Peak memory 145392 kb
Host smart-ae0671f6-ba97-4d93-9220-582e51f3e3fd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3952740583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3952740583
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1456296327
Short name T51
Test name
Test status
Simulation time 32373038 ps
CPU time 0.39 seconds
Started Jul 01 04:15:50 PM PDT 24
Finished Jul 01 04:15:53 PM PDT 24
Peak memory 145376 kb
Host smart-7a608415-8977-4d0f-a12b-859b3dce42d0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1456296327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1456296327
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3874176672
Short name T23
Test name
Test status
Simulation time 29961233 ps
CPU time 0.4 seconds
Started Jul 01 04:15:52 PM PDT 24
Finished Jul 01 04:15:57 PM PDT 24
Peak memory 145408 kb
Host smart-51fc193f-68e7-4bce-905a-dabf97c9c50b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3874176672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3874176672
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2018137739
Short name T41
Test name
Test status
Simulation time 30801358 ps
CPU time 0.4 seconds
Started Jul 01 04:15:50 PM PDT 24
Finished Jul 01 04:15:51 PM PDT 24
Peak memory 145340 kb
Host smart-b14452a4-37b2-481f-99c3-499e5368dac8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2018137739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2018137739
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1879656624
Short name T53
Test name
Test status
Simulation time 29680318 ps
CPU time 0.43 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:01 PM PDT 24
Peak memory 145384 kb
Host smart-9631a70f-c590-4ea6-9223-111e38492dbf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1879656624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1879656624
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3700452616
Short name T57
Test name
Test status
Simulation time 32619655 ps
CPU time 0.42 seconds
Started Jul 01 04:15:52 PM PDT 24
Finished Jul 01 04:15:57 PM PDT 24
Peak memory 145376 kb
Host smart-3527d20d-69e6-4fd7-bf7b-7f9f02ce6443
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3700452616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3700452616
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.655084957
Short name T49
Test name
Test status
Simulation time 29055001 ps
CPU time 0.41 seconds
Started Jul 01 04:15:52 PM PDT 24
Finished Jul 01 04:15:58 PM PDT 24
Peak memory 145364 kb
Host smart-944b0b00-ed06-472c-a019-844bc6aa9344
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=655084957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.655084957
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3421714591
Short name T56
Test name
Test status
Simulation time 28803129 ps
CPU time 0.39 seconds
Started Jul 01 04:15:51 PM PDT 24
Finished Jul 01 04:15:55 PM PDT 24
Peak memory 145376 kb
Host smart-6eea8b7f-51f9-4350-8afd-6109ca07feb3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3421714591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3421714591
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2973078826
Short name T43
Test name
Test status
Simulation time 31477980 ps
CPU time 0.4 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 145396 kb
Host smart-fb14a60c-cf5e-4e93-a25a-07d9eebda269
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2973078826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2973078826
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1048682490
Short name T44
Test name
Test status
Simulation time 33448006 ps
CPU time 0.4 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:15:59 PM PDT 24
Peak memory 145320 kb
Host smart-caa46304-f049-403f-bade-34515206d923
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1048682490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1048682490
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3910032302
Short name T45
Test name
Test status
Simulation time 31232565 ps
CPU time 0.42 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:16:00 PM PDT 24
Peak memory 145364 kb
Host smart-be2013c9-34db-4952-915f-39c1166082bd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3910032302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3910032302
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.675629014
Short name T40
Test name
Test status
Simulation time 32802702 ps
CPU time 0.45 seconds
Started Jul 01 04:15:51 PM PDT 24
Finished Jul 01 04:15:53 PM PDT 24
Peak memory 145380 kb
Host smart-11a5d7f7-759e-451a-9a21-4be53d5d76a0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=675629014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.675629014
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1340570365
Short name T55
Test name
Test status
Simulation time 29921152 ps
CPU time 0.41 seconds
Started Jul 01 04:15:52 PM PDT 24
Finished Jul 01 04:15:57 PM PDT 24
Peak memory 145364 kb
Host smart-a6c4859b-8ac8-4668-bfbd-a36e0f3919e5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1340570365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1340570365
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3231276170
Short name T48
Test name
Test status
Simulation time 28308218 ps
CPU time 0.4 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:01 PM PDT 24
Peak memory 145384 kb
Host smart-db907db9-42f1-414b-b9ea-48686d3c6620
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3231276170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3231276170
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3390445566
Short name T54
Test name
Test status
Simulation time 29186799 ps
CPU time 0.4 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:16:00 PM PDT 24
Peak memory 145396 kb
Host smart-4f6ccb49-eb15-4697-bffa-00de94946d3d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3390445566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3390445566
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2604098118
Short name T4
Test name
Test status
Simulation time 30096084 ps
CPU time 0.39 seconds
Started Jul 01 04:15:55 PM PDT 24
Finished Jul 01 04:16:04 PM PDT 24
Peak memory 145336 kb
Host smart-b1d34619-fa06-44d9-b3f4-c1241ba1454d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2604098118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2604098118
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1777256995
Short name T52
Test name
Test status
Simulation time 30269729 ps
CPU time 0.4 seconds
Started Jul 01 04:15:55 PM PDT 24
Finished Jul 01 04:16:03 PM PDT 24
Peak memory 145384 kb
Host smart-96f2a9a1-8f91-49fa-855c-67e50e041d64
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1777256995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1777256995
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2456845026
Short name T37
Test name
Test status
Simulation time 8524479 ps
CPU time 0.39 seconds
Started Jul 01 04:15:52 PM PDT 24
Finished Jul 01 04:15:58 PM PDT 24
Peak memory 145652 kb
Host smart-1bfec2ff-da20-4ef5-98ec-137a97686b9d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2456845026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2456845026
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2453919027
Short name T30
Test name
Test status
Simulation time 9515591 ps
CPU time 0.38 seconds
Started Jul 01 04:15:51 PM PDT 24
Finished Jul 01 04:15:54 PM PDT 24
Peak memory 145620 kb
Host smart-f88e4ad5-efec-4fdb-96e7-40b0a8be382e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2453919027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2453919027
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3456615171
Short name T27
Test name
Test status
Simulation time 9116311 ps
CPU time 0.38 seconds
Started Jul 01 04:15:52 PM PDT 24
Finished Jul 01 04:15:58 PM PDT 24
Peak memory 145672 kb
Host smart-2f382289-cb16-42ce-ad82-d30fd06825d5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3456615171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3456615171
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.307856084
Short name T33
Test name
Test status
Simulation time 9713691 ps
CPU time 0.39 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 145592 kb
Host smart-ac46114d-6dda-49a0-a476-18ad6396aeaa
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=307856084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.307856084
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.888623415
Short name T32
Test name
Test status
Simulation time 9180309 ps
CPU time 0.37 seconds
Started Jul 01 04:15:51 PM PDT 24
Finished Jul 01 04:15:53 PM PDT 24
Peak memory 145696 kb
Host smart-68de6fe4-e5ac-4902-8f2c-7a3d8230279f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=888623415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.888623415
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3229846488
Short name T36
Test name
Test status
Simulation time 9159653 ps
CPU time 0.38 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:01 PM PDT 24
Peak memory 145608 kb
Host smart-55d4eabc-3dcf-48aa-969f-da795e77d168
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3229846488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3229846488
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2370896151
Short name T61
Test name
Test status
Simulation time 8951782 ps
CPU time 0.38 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 145676 kb
Host smart-9488dcb9-3467-41a6-a216-7aa40ff7f178
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2370896151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2370896151
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.336097028
Short name T35
Test name
Test status
Simulation time 9700352 ps
CPU time 0.38 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:15:59 PM PDT 24
Peak memory 145576 kb
Host smart-84cc0098-6750-416c-8284-fbf28f6217eb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=336097028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.336097028
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2456163826
Short name T25
Test name
Test status
Simulation time 8864740 ps
CPU time 0.38 seconds
Started Jul 01 04:15:52 PM PDT 24
Finished Jul 01 04:15:58 PM PDT 24
Peak memory 145648 kb
Host smart-6a9a1dc9-2541-4f49-8214-12610943bf7e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2456163826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2456163826
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2293119469
Short name T28
Test name
Test status
Simulation time 8397069 ps
CPU time 0.37 seconds
Started Jul 01 04:15:50 PM PDT 24
Finished Jul 01 04:15:51 PM PDT 24
Peak memory 145664 kb
Host smart-d1c121c9-0f28-4242-ae0d-c2a7c65a5598
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2293119469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2293119469
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2612236487
Short name T26
Test name
Test status
Simulation time 9549128 ps
CPU time 0.38 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:15:58 PM PDT 24
Peak memory 145672 kb
Host smart-78d93ba7-24d6-415d-9bf8-4abfa08cdeb6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2612236487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2612236487
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1728244245
Short name T60
Test name
Test status
Simulation time 8937022 ps
CPU time 0.37 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:16:00 PM PDT 24
Peak memory 145664 kb
Host smart-05c5431e-0c9d-4677-9d70-3b637b426d53
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1728244245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1728244245
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1797182007
Short name T38
Test name
Test status
Simulation time 9480699 ps
CPU time 0.39 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:16:00 PM PDT 24
Peak memory 145124 kb
Host smart-c887e35f-2ceb-4e86-bc98-0323aafb4361
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1797182007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1797182007
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1023447663
Short name T31
Test name
Test status
Simulation time 9776184 ps
CPU time 0.38 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:15:59 PM PDT 24
Peak memory 145636 kb
Host smart-07c7cb57-c7fb-43e5-ba6c-4ac42bb3af25
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1023447663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1023447663
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.372419233
Short name T34
Test name
Test status
Simulation time 9033376 ps
CPU time 0.38 seconds
Started Jul 01 04:15:51 PM PDT 24
Finished Jul 01 04:15:53 PM PDT 24
Peak memory 145696 kb
Host smart-197ad0bc-6291-4427-8dab-e07cf1e84ec1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=372419233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.372419233
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1332815503
Short name T62
Test name
Test status
Simulation time 9276181 ps
CPU time 0.39 seconds
Started Jul 01 04:15:51 PM PDT 24
Finished Jul 01 04:15:55 PM PDT 24
Peak memory 145624 kb
Host smart-bfd77078-c28a-46da-94ca-702bd7c2c5cf
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1332815503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1332815503
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3483069845
Short name T63
Test name
Test status
Simulation time 8775583 ps
CPU time 0.37 seconds
Started Jul 01 04:15:50 PM PDT 24
Finished Jul 01 04:15:52 PM PDT 24
Peak memory 145668 kb
Host smart-4502c115-187b-42e7-8aca-85c1699a80f8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3483069845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3483069845
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.3989711257
Short name T59
Test name
Test status
Simulation time 8498981 ps
CPU time 0.41 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:16:00 PM PDT 24
Peak memory 145004 kb
Host smart-2de10477-c799-4249-873f-cfee851fca6a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3989711257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3989711257
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.981743337
Short name T58
Test name
Test status
Simulation time 8761206 ps
CPU time 0.38 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:16:00 PM PDT 24
Peak memory 145660 kb
Host smart-7de47570-bb20-4123-92eb-9d3ddd33c14a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=981743337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.981743337
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1498302832
Short name T73
Test name
Test status
Simulation time 28767756 ps
CPU time 0.39 seconds
Started Jul 01 04:15:50 PM PDT 24
Finished Jul 01 04:15:52 PM PDT 24
Peak memory 145632 kb
Host smart-62c80284-e655-43cd-a6c3-c04865d24fb9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1498302832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1498302832
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2474875636
Short name T65
Test name
Test status
Simulation time 28079523 ps
CPU time 0.39 seconds
Started Jul 01 04:15:52 PM PDT 24
Finished Jul 01 04:15:58 PM PDT 24
Peak memory 145688 kb
Host smart-9931869c-e037-4bc8-9d17-84f1edcdc18b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2474875636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2474875636
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3950631014
Short name T68
Test name
Test status
Simulation time 27271815 ps
CPU time 0.39 seconds
Started Jul 01 04:15:52 PM PDT 24
Finished Jul 01 04:15:57 PM PDT 24
Peak memory 145684 kb
Host smart-025de79e-3b82-40f0-a846-72a325211663
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3950631014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3950631014
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3120014949
Short name T66
Test name
Test status
Simulation time 29134230 ps
CPU time 0.4 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:16:00 PM PDT 24
Peak memory 145664 kb
Host smart-9f2b44a0-ec8b-4e98-9ff2-120dcfc83ecb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3120014949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3120014949
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4124044742
Short name T72
Test name
Test status
Simulation time 26994131 ps
CPU time 0.4 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 145624 kb
Host smart-7bd75df7-d23a-4a62-9f43-cdcc3b305f94
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4124044742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.4124044742
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2399605433
Short name T75
Test name
Test status
Simulation time 28462960 ps
CPU time 0.39 seconds
Started Jul 01 04:15:55 PM PDT 24
Finished Jul 01 04:16:03 PM PDT 24
Peak memory 145676 kb
Host smart-69204e88-4ce1-4d2a-977e-98b650413071
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2399605433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2399605433
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.411119534
Short name T77
Test name
Test status
Simulation time 27957776 ps
CPU time 0.4 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 145692 kb
Host smart-59bb2325-9d5b-42b3-9d06-fb8a2906db63
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=411119534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.411119534
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2358472768
Short name T71
Test name
Test status
Simulation time 27845657 ps
CPU time 0.39 seconds
Started Jul 01 04:15:55 PM PDT 24
Finished Jul 01 04:16:03 PM PDT 24
Peak memory 145624 kb
Host smart-54bd4562-e194-4038-9094-53d8392eae6f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2358472768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2358472768
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1938310831
Short name T70
Test name
Test status
Simulation time 26870896 ps
CPU time 0.39 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:01 PM PDT 24
Peak memory 145692 kb
Host smart-5b6bf7f8-0acf-4a21-82e2-5fd365103748
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1938310831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1938310831
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1756928474
Short name T39
Test name
Test status
Simulation time 27933781 ps
CPU time 0.43 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 145624 kb
Host smart-e58d3cc1-f75e-4ee0-9e66-02c46b8b5eb5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1756928474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1756928474
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3131568117
Short name T69
Test name
Test status
Simulation time 26874681 ps
CPU time 0.39 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:15:59 PM PDT 24
Peak memory 145652 kb
Host smart-7bd675be-04cd-4d0a-8ac3-0f423ceaaccc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3131568117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3131568117
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.229092527
Short name T80
Test name
Test status
Simulation time 26938246 ps
CPU time 0.4 seconds
Started Jul 01 04:15:52 PM PDT 24
Finished Jul 01 04:15:56 PM PDT 24
Peak memory 145696 kb
Host smart-bd541680-3af5-4699-9f6e-935554f57e30
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=229092527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.229092527
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1248246543
Short name T5
Test name
Test status
Simulation time 27207292 ps
CPU time 0.4 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:01 PM PDT 24
Peak memory 145660 kb
Host smart-e21088c8-9e9c-415e-a9a5-f51b5952d7c6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1248246543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1248246543
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3274416691
Short name T67
Test name
Test status
Simulation time 28567042 ps
CPU time 0.4 seconds
Started Jul 01 04:15:53 PM PDT 24
Finished Jul 01 04:15:59 PM PDT 24
Peak memory 145664 kb
Host smart-2583f417-d3f7-49d1-8cdd-55d3a21aeeb1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3274416691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3274416691
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1927877353
Short name T74
Test name
Test status
Simulation time 26047455 ps
CPU time 0.4 seconds
Started Jul 01 04:15:54 PM PDT 24
Finished Jul 01 04:16:02 PM PDT 24
Peak memory 145620 kb
Host smart-99850124-1663-45e3-8311-8112543c7813
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1927877353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1927877353
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3921008034
Short name T78
Test name
Test status
Simulation time 29117184 ps
CPU time 0.39 seconds
Started Jul 01 04:15:50 PM PDT 24
Finished Jul 01 04:15:52 PM PDT 24
Peak memory 145680 kb
Host smart-71c4f661-14d3-441e-a01f-877984540425
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3921008034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3921008034
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2450608784
Short name T64
Test name
Test status
Simulation time 28559963 ps
CPU time 0.41 seconds
Started Jul 01 04:15:51 PM PDT 24
Finished Jul 01 04:15:55 PM PDT 24
Peak memory 145632 kb
Host smart-a00510b1-556d-4848-a190-dc0ac77620e6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2450608784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2450608784
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2345556825
Short name T76
Test name
Test status
Simulation time 27229862 ps
CPU time 0.42 seconds
Started Jul 01 04:15:52 PM PDT 24
Finished Jul 01 04:15:56 PM PDT 24
Peak memory 145688 kb
Host smart-9deb0aad-a0db-4d8f-910c-61d2bdba5747
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2345556825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2345556825
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3153511127
Short name T6
Test name
Test status
Simulation time 27342290 ps
CPU time 0.4 seconds
Started Jul 01 04:15:51 PM PDT 24
Finished Jul 01 04:15:55 PM PDT 24
Peak memory 145704 kb
Host smart-51fa15f3-51f3-414c-a07a-6dbb8715abd6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3153511127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3153511127
Directory /workspace/9.prim_sync_fatal_alert/latest
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