Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.27 89.27 100.00 100.00 93.75 93.75 96.43 96.43 82.14 82.14 95.83 95.83 67.44 67.44 /workspace/coverage/default/12.prim_async_alert.3632065934
91.80 2.53 100.00 0.00 93.75 0.00 96.43 0.00 85.71 3.57 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/12.prim_sync_alert.934073285
93.90 2.11 100.00 0.00 95.83 2.08 100.00 3.57 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.254008220
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/18.prim_async_alert.2198351683
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.237442281

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2293284279
/workspace/coverage/default/1.prim_async_alert.1764451409
/workspace/coverage/default/10.prim_async_alert.2836123328
/workspace/coverage/default/11.prim_async_alert.2300786204
/workspace/coverage/default/13.prim_async_alert.1978099329
/workspace/coverage/default/14.prim_async_alert.2040239158
/workspace/coverage/default/15.prim_async_alert.1797303774
/workspace/coverage/default/16.prim_async_alert.2052923609
/workspace/coverage/default/17.prim_async_alert.2187555595
/workspace/coverage/default/19.prim_async_alert.2935294903
/workspace/coverage/default/2.prim_async_alert.3984723298
/workspace/coverage/default/3.prim_async_alert.1013897009
/workspace/coverage/default/4.prim_async_alert.204891513
/workspace/coverage/default/5.prim_async_alert.1720397042
/workspace/coverage/default/6.prim_async_alert.696200402
/workspace/coverage/default/7.prim_async_alert.3358823823
/workspace/coverage/default/8.prim_async_alert.467659663
/workspace/coverage/default/9.prim_async_alert.1273268341
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3666745820
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1054167925
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3278638622
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.459328223
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2318738957
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3257557726
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1445195670
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3571370562
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2112116486
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2626725281
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3092186100
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1750911380
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.855235690
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.224256785
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.710555974
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1855471838
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1370372718
/workspace/coverage/sync_alert/0.prim_sync_alert.1345040640
/workspace/coverage/sync_alert/1.prim_sync_alert.3263575330
/workspace/coverage/sync_alert/10.prim_sync_alert.125162804
/workspace/coverage/sync_alert/11.prim_sync_alert.653261883
/workspace/coverage/sync_alert/13.prim_sync_alert.3935824882
/workspace/coverage/sync_alert/14.prim_sync_alert.2726394956
/workspace/coverage/sync_alert/15.prim_sync_alert.3153894304
/workspace/coverage/sync_alert/16.prim_sync_alert.3407405640
/workspace/coverage/sync_alert/17.prim_sync_alert.3703546020
/workspace/coverage/sync_alert/18.prim_sync_alert.390562180
/workspace/coverage/sync_alert/19.prim_sync_alert.1544900707
/workspace/coverage/sync_alert/2.prim_sync_alert.3706095867
/workspace/coverage/sync_alert/3.prim_sync_alert.797643872
/workspace/coverage/sync_alert/4.prim_sync_alert.3145930828
/workspace/coverage/sync_alert/5.prim_sync_alert.3488626753
/workspace/coverage/sync_alert/6.prim_sync_alert.1823847195
/workspace/coverage/sync_alert/7.prim_sync_alert.1994185802
/workspace/coverage/sync_alert/8.prim_sync_alert.48862132
/workspace/coverage/sync_alert/9.prim_sync_alert.3367150300
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2562526416
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2037106494
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1275047706
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3244209718
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2968631585
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2681218385
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1249614619
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1610858652
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.329407656
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4026248773
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3085786842
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3815248213
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3531882506
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3609932388
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1707535431
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3054803240
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1609489821
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4111591500
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1766707607
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.382723700



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/15.prim_async_alert.1797303774 Jul 02 07:31:34 AM PDT 24 Jul 02 07:31:35 AM PDT 24 10793287 ps
T2 /workspace/coverage/default/10.prim_async_alert.2836123328 Jul 02 07:31:40 AM PDT 24 Jul 02 07:31:42 AM PDT 24 10572846 ps
T3 /workspace/coverage/default/12.prim_async_alert.3632065934 Jul 02 07:31:53 AM PDT 24 Jul 02 07:31:55 AM PDT 24 11887943 ps
T12 /workspace/coverage/default/1.prim_async_alert.1764451409 Jul 02 07:33:06 AM PDT 24 Jul 02 07:33:07 AM PDT 24 11028914 ps
T7 /workspace/coverage/default/16.prim_async_alert.2052923609 Jul 02 07:31:33 AM PDT 24 Jul 02 07:31:34 AM PDT 24 11448759 ps
T8 /workspace/coverage/default/4.prim_async_alert.204891513 Jul 02 07:31:54 AM PDT 24 Jul 02 07:31:55 AM PDT 24 11685340 ps
T16 /workspace/coverage/default/6.prim_async_alert.696200402 Jul 02 07:31:34 AM PDT 24 Jul 02 07:31:36 AM PDT 24 11136758 ps
T11 /workspace/coverage/default/18.prim_async_alert.2198351683 Jul 02 07:31:37 AM PDT 24 Jul 02 07:31:39 AM PDT 24 11801125 ps
T17 /workspace/coverage/default/19.prim_async_alert.2935294903 Jul 02 07:31:34 AM PDT 24 Jul 02 07:31:35 AM PDT 24 11595932 ps
T9 /workspace/coverage/default/13.prim_async_alert.1978099329 Jul 02 07:31:53 AM PDT 24 Jul 02 07:31:55 AM PDT 24 11455136 ps
T10 /workspace/coverage/default/11.prim_async_alert.2300786204 Jul 02 07:31:40 AM PDT 24 Jul 02 07:31:43 AM PDT 24 10498757 ps
T14 /workspace/coverage/default/8.prim_async_alert.467659663 Jul 02 07:31:39 AM PDT 24 Jul 02 07:31:42 AM PDT 24 12486969 ps
T13 /workspace/coverage/default/9.prim_async_alert.1273268341 Jul 02 07:31:41 AM PDT 24 Jul 02 07:31:44 AM PDT 24 12449022 ps
T39 /workspace/coverage/default/2.prim_async_alert.3984723298 Jul 02 07:31:51 AM PDT 24 Jul 02 07:31:52 AM PDT 24 10948111 ps
T15 /workspace/coverage/default/0.prim_async_alert.2293284279 Jul 02 07:31:39 AM PDT 24 Jul 02 07:31:41 AM PDT 24 11509734 ps
T40 /workspace/coverage/default/7.prim_async_alert.3358823823 Jul 02 07:31:40 AM PDT 24 Jul 02 07:31:43 AM PDT 24 11846717 ps
T41 /workspace/coverage/default/14.prim_async_alert.2040239158 Jul 02 07:31:54 AM PDT 24 Jul 02 07:31:55 AM PDT 24 11572816 ps
T42 /workspace/coverage/default/3.prim_async_alert.1013897009 Jul 02 07:31:39 AM PDT 24 Jul 02 07:31:41 AM PDT 24 11046853 ps
T43 /workspace/coverage/default/5.prim_async_alert.1720397042 Jul 02 07:31:54 AM PDT 24 Jul 02 07:31:56 AM PDT 24 10891426 ps
T44 /workspace/coverage/default/17.prim_async_alert.2187555595 Jul 02 07:31:40 AM PDT 24 Jul 02 07:31:42 AM PDT 24 11380147 ps
T30 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.710555974 Jul 02 07:31:53 AM PDT 24 Jul 02 07:31:54 AM PDT 24 29443336 ps
T31 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.254008220 Jul 02 07:31:59 AM PDT 24 Jul 02 07:32:00 AM PDT 24 33166154 ps
T32 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1855471838 Jul 02 07:31:40 AM PDT 24 Jul 02 07:31:43 AM PDT 24 29231890 ps
T33 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2626725281 Jul 02 07:31:40 AM PDT 24 Jul 02 07:31:43 AM PDT 24 29064140 ps
T4 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2318738957 Jul 02 07:36:40 AM PDT 24 Jul 02 07:36:48 AM PDT 24 30747781 ps
T34 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1054167925 Jul 02 07:31:39 AM PDT 24 Jul 02 07:31:41 AM PDT 24 29977698 ps
T35 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3278638622 Jul 02 07:37:14 AM PDT 24 Jul 02 07:37:18 AM PDT 24 32789885 ps
T36 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3257557726 Jul 02 07:36:15 AM PDT 24 Jul 02 07:36:16 AM PDT 24 31484520 ps
T37 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1750911380 Jul 02 07:31:34 AM PDT 24 Jul 02 07:31:35 AM PDT 24 29279462 ps
T38 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.855235690 Jul 02 07:31:33 AM PDT 24 Jul 02 07:31:34 AM PDT 24 30197548 ps
T45 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2112116486 Jul 02 07:34:17 AM PDT 24 Jul 02 07:34:18 AM PDT 24 31673943 ps
T46 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3571370562 Jul 02 07:32:53 AM PDT 24 Jul 02 07:32:54 AM PDT 24 31124222 ps
T5 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.237442281 Jul 02 07:35:15 AM PDT 24 Jul 02 07:35:16 AM PDT 24 29144257 ps
T47 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1370372718 Jul 02 07:31:39 AM PDT 24 Jul 02 07:31:42 AM PDT 24 30103710 ps
T48 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.224256785 Jul 02 07:31:40 AM PDT 24 Jul 02 07:31:43 AM PDT 24 29404283 ps
T49 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3666745820 Jul 02 07:31:53 AM PDT 24 Jul 02 07:31:55 AM PDT 24 30153735 ps
T50 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.459328223 Jul 02 07:36:30 AM PDT 24 Jul 02 07:36:34 AM PDT 24 30062333 ps
T51 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1445195670 Jul 02 07:31:53 AM PDT 24 Jul 02 07:31:55 AM PDT 24 31243896 ps
T52 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3092186100 Jul 02 07:31:34 AM PDT 24 Jul 02 07:31:36 AM PDT 24 31811585 ps
T27 /workspace/coverage/sync_alert/4.prim_sync_alert.3145930828 Jul 02 07:31:54 AM PDT 24 Jul 02 07:31:56 AM PDT 24 10520694 ps
T18 /workspace/coverage/sync_alert/11.prim_sync_alert.653261883 Jul 02 07:31:55 AM PDT 24 Jul 02 07:31:56 AM PDT 24 8430661 ps
T19 /workspace/coverage/sync_alert/15.prim_sync_alert.3153894304 Jul 02 07:32:01 AM PDT 24 Jul 02 07:32:02 AM PDT 24 9025854 ps
T20 /workspace/coverage/sync_alert/9.prim_sync_alert.3367150300 Jul 02 07:31:39 AM PDT 24 Jul 02 07:31:41 AM PDT 24 7988359 ps
T21 /workspace/coverage/sync_alert/13.prim_sync_alert.3935824882 Jul 02 07:31:53 AM PDT 24 Jul 02 07:31:54 AM PDT 24 10541798 ps
T22 /workspace/coverage/sync_alert/5.prim_sync_alert.3488626753 Jul 02 07:31:39 AM PDT 24 Jul 02 07:31:41 AM PDT 24 8979384 ps
T28 /workspace/coverage/sync_alert/12.prim_sync_alert.934073285 Jul 02 07:36:43 AM PDT 24 Jul 02 07:36:51 AM PDT 24 8717930 ps
T23 /workspace/coverage/sync_alert/17.prim_sync_alert.3703546020 Jul 02 07:34:47 AM PDT 24 Jul 02 07:34:48 AM PDT 24 9749495 ps
T29 /workspace/coverage/sync_alert/2.prim_sync_alert.3706095867 Jul 02 07:31:34 AM PDT 24 Jul 02 07:31:35 AM PDT 24 10212018 ps
T24 /workspace/coverage/sync_alert/16.prim_sync_alert.3407405640 Jul 02 07:36:37 AM PDT 24 Jul 02 07:36:44 AM PDT 24 8699431 ps
T53 /workspace/coverage/sync_alert/14.prim_sync_alert.2726394956 Jul 02 07:36:13 AM PDT 24 Jul 02 07:36:15 AM PDT 24 9918279 ps
T25 /workspace/coverage/sync_alert/7.prim_sync_alert.1994185802 Jul 02 07:31:41 AM PDT 24 Jul 02 07:31:43 AM PDT 24 8915353 ps
T54 /workspace/coverage/sync_alert/6.prim_sync_alert.1823847195 Jul 02 07:31:51 AM PDT 24 Jul 02 07:31:52 AM PDT 24 8588987 ps
T55 /workspace/coverage/sync_alert/8.prim_sync_alert.48862132 Jul 02 07:31:33 AM PDT 24 Jul 02 07:31:34 AM PDT 24 9324277 ps
T26 /workspace/coverage/sync_alert/18.prim_sync_alert.390562180 Jul 02 07:37:13 AM PDT 24 Jul 02 07:37:17 AM PDT 24 9644871 ps
T56 /workspace/coverage/sync_alert/10.prim_sync_alert.125162804 Jul 02 07:33:20 AM PDT 24 Jul 02 07:33:21 AM PDT 24 8643707 ps
T57 /workspace/coverage/sync_alert/1.prim_sync_alert.3263575330 Jul 02 07:31:40 AM PDT 24 Jul 02 07:31:43 AM PDT 24 10021489 ps
T58 /workspace/coverage/sync_alert/19.prim_sync_alert.1544900707 Jul 02 07:36:29 AM PDT 24 Jul 02 07:36:33 AM PDT 24 8715400 ps
T59 /workspace/coverage/sync_alert/0.prim_sync_alert.1345040640 Jul 02 07:31:52 AM PDT 24 Jul 02 07:31:54 AM PDT 24 8501512 ps
T60 /workspace/coverage/sync_alert/3.prim_sync_alert.797643872 Jul 02 07:31:39 AM PDT 24 Jul 02 07:31:41 AM PDT 24 9480794 ps
T61 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1766707607 Jul 02 07:33:21 AM PDT 24 Jul 02 07:33:22 AM PDT 24 27792626 ps
T62 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2968631585 Jul 02 07:34:01 AM PDT 24 Jul 02 07:34:02 AM PDT 24 29589453 ps
T63 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3054803240 Jul 02 07:36:29 AM PDT 24 Jul 02 07:36:34 AM PDT 24 26545505 ps
T64 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3531882506 Jul 02 07:33:52 AM PDT 24 Jul 02 07:33:53 AM PDT 24 27114511 ps
T65 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.382723700 Jul 02 07:36:43 AM PDT 24 Jul 02 07:36:51 AM PDT 24 26842800 ps
T66 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1610858652 Jul 02 07:36:41 AM PDT 24 Jul 02 07:36:49 AM PDT 24 28740842 ps
T67 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.329407656 Jul 02 07:36:34 AM PDT 24 Jul 02 07:36:42 AM PDT 24 27546262 ps
T68 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2681218385 Jul 02 07:34:19 AM PDT 24 Jul 02 07:34:20 AM PDT 24 28714893 ps
T6 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4026248773 Jul 02 07:34:46 AM PDT 24 Jul 02 07:34:47 AM PDT 24 28416717 ps
T69 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2037106494 Jul 02 07:36:43 AM PDT 24 Jul 02 07:36:51 AM PDT 24 27981477 ps
T70 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3609932388 Jul 02 07:36:42 AM PDT 24 Jul 02 07:36:49 AM PDT 24 26576104 ps
T71 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4111591500 Jul 02 07:36:29 AM PDT 24 Jul 02 07:36:32 AM PDT 24 27335647 ps
T72 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3244209718 Jul 02 07:36:40 AM PDT 24 Jul 02 07:36:49 AM PDT 24 26759057 ps
T73 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1707535431 Jul 02 07:36:43 AM PDT 24 Jul 02 07:36:51 AM PDT 24 27765822 ps
T74 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3085786842 Jul 02 07:36:34 AM PDT 24 Jul 02 07:36:42 AM PDT 24 29008661 ps
T75 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1609489821 Jul 02 07:36:29 AM PDT 24 Jul 02 07:36:32 AM PDT 24 27835101 ps
T76 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1249614619 Jul 02 07:34:45 AM PDT 24 Jul 02 07:34:46 AM PDT 24 26904360 ps
T77 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2562526416 Jul 02 07:36:42 AM PDT 24 Jul 02 07:36:49 AM PDT 24 25446624 ps
T78 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3815248213 Jul 02 07:36:35 AM PDT 24 Jul 02 07:36:43 AM PDT 24 26915301 ps
T79 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1275047706 Jul 02 07:36:40 AM PDT 24 Jul 02 07:36:49 AM PDT 24 27428419 ps

Test location /workspace/coverage/default/12.prim_async_alert.3632065934
Short name T3
Test name
Test status
Simulation time 11887943 ps
CPU time 0.38 seconds
Started Jul 02 07:31:53 AM PDT 24
Finished Jul 02 07:31:55 AM PDT 24
Peak memory 145628 kb
Host smart-bef828da-d2ed-45ea-be93-bfa1ed5f1a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632065934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3632065934
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.934073285
Short name T28
Test name
Test status
Simulation time 8717930 ps
CPU time 0.36 seconds
Started Jul 02 07:36:43 AM PDT 24
Finished Jul 02 07:36:51 AM PDT 24
Peak memory 145072 kb
Host smart-bc666b38-8a07-4ea3-98fd-8ce0b340a0f2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=934073285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.934073285
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.254008220
Short name T31
Test name
Test status
Simulation time 33166154 ps
CPU time 0.43 seconds
Started Jul 02 07:31:59 AM PDT 24
Finished Jul 02 07:32:00 AM PDT 24
Peak memory 145552 kb
Host smart-dfa1b03a-2255-4697-aee5-d1371e4c07d3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=254008220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.254008220
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2198351683
Short name T11
Test name
Test status
Simulation time 11801125 ps
CPU time 0.45 seconds
Started Jul 02 07:31:37 AM PDT 24
Finished Jul 02 07:31:39 AM PDT 24
Peak memory 145172 kb
Host smart-2912225c-85e8-4653-b06e-9f75d79f590b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198351683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2198351683
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.237442281
Short name T5
Test name
Test status
Simulation time 29144257 ps
CPU time 0.42 seconds
Started Jul 02 07:35:15 AM PDT 24
Finished Jul 02 07:35:16 AM PDT 24
Peak memory 145176 kb
Host smart-f560133d-58cd-427a-83ef-a5327dcb38b3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=237442281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.237442281
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2293284279
Short name T15
Test name
Test status
Simulation time 11509734 ps
CPU time 0.4 seconds
Started Jul 02 07:31:39 AM PDT 24
Finished Jul 02 07:31:41 AM PDT 24
Peak memory 145864 kb
Host smart-2d60a218-6c7d-4961-9e46-8f023cbf6669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293284279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2293284279
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1764451409
Short name T12
Test name
Test status
Simulation time 11028914 ps
CPU time 0.41 seconds
Started Jul 02 07:33:06 AM PDT 24
Finished Jul 02 07:33:07 AM PDT 24
Peak memory 145628 kb
Host smart-7ea19703-3958-41a2-a71c-a2c6f2346df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764451409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1764451409
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2836123328
Short name T2
Test name
Test status
Simulation time 10572846 ps
CPU time 0.39 seconds
Started Jul 02 07:31:40 AM PDT 24
Finished Jul 02 07:31:42 AM PDT 24
Peak memory 145864 kb
Host smart-25e4e9f1-42a1-44ee-b290-401594b6c89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836123328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2836123328
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2300786204
Short name T10
Test name
Test status
Simulation time 10498757 ps
CPU time 0.36 seconds
Started Jul 02 07:31:40 AM PDT 24
Finished Jul 02 07:31:43 AM PDT 24
Peak memory 146552 kb
Host smart-f10e070a-6692-4e25-af37-6c5c1f94c832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300786204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2300786204
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1978099329
Short name T9
Test name
Test status
Simulation time 11455136 ps
CPU time 0.39 seconds
Started Jul 02 07:31:53 AM PDT 24
Finished Jul 02 07:31:55 AM PDT 24
Peak memory 145864 kb
Host smart-58eecb9e-502c-48cd-9589-5dd0af3215f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978099329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1978099329
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2040239158
Short name T41
Test name
Test status
Simulation time 11572816 ps
CPU time 0.39 seconds
Started Jul 02 07:31:54 AM PDT 24
Finished Jul 02 07:31:55 AM PDT 24
Peak memory 145700 kb
Host smart-7e53ce57-ae58-4d34-b691-cd474566e1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040239158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2040239158
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1797303774
Short name T1
Test name
Test status
Simulation time 10793287 ps
CPU time 0.41 seconds
Started Jul 02 07:31:34 AM PDT 24
Finished Jul 02 07:31:35 AM PDT 24
Peak memory 145912 kb
Host smart-61902cda-dbef-4f77-90d6-82675958ba80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797303774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1797303774
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2052923609
Short name T7
Test name
Test status
Simulation time 11448759 ps
CPU time 0.42 seconds
Started Jul 02 07:31:33 AM PDT 24
Finished Jul 02 07:31:34 AM PDT 24
Peak memory 145912 kb
Host smart-007dd986-d436-4fdf-95e8-f1c0b61d599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052923609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2052923609
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2187555595
Short name T44
Test name
Test status
Simulation time 11380147 ps
CPU time 0.37 seconds
Started Jul 02 07:31:40 AM PDT 24
Finished Jul 02 07:31:42 AM PDT 24
Peak memory 145184 kb
Host smart-c62f5cc6-8f6c-4939-a708-aaff5bbc309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187555595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2187555595
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2935294903
Short name T17
Test name
Test status
Simulation time 11595932 ps
CPU time 0.43 seconds
Started Jul 02 07:31:34 AM PDT 24
Finished Jul 02 07:31:35 AM PDT 24
Peak memory 145912 kb
Host smart-ac39dcfb-4deb-4b75-9c4a-d828c6f093f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935294903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2935294903
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3984723298
Short name T39
Test name
Test status
Simulation time 10948111 ps
CPU time 0.38 seconds
Started Jul 02 07:31:51 AM PDT 24
Finished Jul 02 07:31:52 AM PDT 24
Peak memory 145392 kb
Host smart-76d25c2b-e2af-4739-b914-d309ffe93759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984723298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3984723298
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1013897009
Short name T42
Test name
Test status
Simulation time 11046853 ps
CPU time 0.4 seconds
Started Jul 02 07:31:39 AM PDT 24
Finished Jul 02 07:31:41 AM PDT 24
Peak memory 145528 kb
Host smart-325afa62-07de-4741-8927-8b9e7ba1e850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013897009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1013897009
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.204891513
Short name T8
Test name
Test status
Simulation time 11685340 ps
CPU time 0.39 seconds
Started Jul 02 07:31:54 AM PDT 24
Finished Jul 02 07:31:55 AM PDT 24
Peak memory 145704 kb
Host smart-bed8be19-173b-416a-8269-2590756e86f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204891513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.204891513
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1720397042
Short name T43
Test name
Test status
Simulation time 10891426 ps
CPU time 0.39 seconds
Started Jul 02 07:31:54 AM PDT 24
Finished Jul 02 07:31:56 AM PDT 24
Peak memory 145704 kb
Host smart-23f9dfcd-9616-4af0-83cb-f0183ca42a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720397042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1720397042
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.696200402
Short name T16
Test name
Test status
Simulation time 11136758 ps
CPU time 0.4 seconds
Started Jul 02 07:31:34 AM PDT 24
Finished Jul 02 07:31:36 AM PDT 24
Peak memory 145904 kb
Host smart-a0e349df-ece4-4c8b-b688-a8e25437f94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696200402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.696200402
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3358823823
Short name T40
Test name
Test status
Simulation time 11846717 ps
CPU time 0.4 seconds
Started Jul 02 07:31:40 AM PDT 24
Finished Jul 02 07:31:43 AM PDT 24
Peak memory 145864 kb
Host smart-aba53dac-7245-4ce8-9156-e1f0c611e577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358823823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3358823823
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.467659663
Short name T14
Test name
Test status
Simulation time 12486969 ps
CPU time 0.39 seconds
Started Jul 02 07:31:39 AM PDT 24
Finished Jul 02 07:31:42 AM PDT 24
Peak memory 145860 kb
Host smart-9eed0771-a417-4192-8346-c55bf7648542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467659663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.467659663
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1273268341
Short name T13
Test name
Test status
Simulation time 12449022 ps
CPU time 0.39 seconds
Started Jul 02 07:31:41 AM PDT 24
Finished Jul 02 07:31:44 AM PDT 24
Peak memory 145864 kb
Host smart-8b0d7241-58df-47eb-a65b-b7dc243e0375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273268341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1273268341
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3666745820
Short name T49
Test name
Test status
Simulation time 30153735 ps
CPU time 0.43 seconds
Started Jul 02 07:31:53 AM PDT 24
Finished Jul 02 07:31:55 AM PDT 24
Peak memory 145240 kb
Host smart-defddc14-12ca-4b3c-83b5-67343782ccb7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3666745820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3666745820
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1054167925
Short name T34
Test name
Test status
Simulation time 29977698 ps
CPU time 0.41 seconds
Started Jul 02 07:31:39 AM PDT 24
Finished Jul 02 07:31:41 AM PDT 24
Peak memory 144032 kb
Host smart-ca15d34e-6424-4519-a6fc-4fd4f0770ab5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1054167925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1054167925
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3278638622
Short name T35
Test name
Test status
Simulation time 32789885 ps
CPU time 0.39 seconds
Started Jul 02 07:37:14 AM PDT 24
Finished Jul 02 07:37:18 AM PDT 24
Peak memory 144808 kb
Host smart-cdbe16d9-4e78-44d2-a6cf-51e5385f4482
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3278638622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3278638622
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.459328223
Short name T50
Test name
Test status
Simulation time 30062333 ps
CPU time 0.43 seconds
Started Jul 02 07:36:30 AM PDT 24
Finished Jul 02 07:36:34 AM PDT 24
Peak memory 145020 kb
Host smart-b35cfe4f-f3cd-44be-8e73-6c4e3cb39e75
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=459328223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.459328223
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2318738957
Short name T4
Test name
Test status
Simulation time 30747781 ps
CPU time 0.39 seconds
Started Jul 02 07:36:40 AM PDT 24
Finished Jul 02 07:36:48 AM PDT 24
Peak memory 145204 kb
Host smart-12867ef0-553c-4007-80b0-88a0daf2b121
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2318738957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2318738957
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3257557726
Short name T36
Test name
Test status
Simulation time 31484520 ps
CPU time 0.38 seconds
Started Jul 02 07:36:15 AM PDT 24
Finished Jul 02 07:36:16 AM PDT 24
Peak memory 144684 kb
Host smart-2b892bd8-1135-4acb-ac39-a012691e33df
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3257557726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3257557726
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1445195670
Short name T51
Test name
Test status
Simulation time 31243896 ps
CPU time 0.4 seconds
Started Jul 02 07:31:53 AM PDT 24
Finished Jul 02 07:31:55 AM PDT 24
Peak memory 145160 kb
Host smart-0dec75d4-c717-4acf-b360-ce64f0378ebd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1445195670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1445195670
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3571370562
Short name T46
Test name
Test status
Simulation time 31124222 ps
CPU time 0.43 seconds
Started Jul 02 07:32:53 AM PDT 24
Finished Jul 02 07:32:54 AM PDT 24
Peak memory 145164 kb
Host smart-137fbc8e-069d-4475-873e-78e6dd105220
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3571370562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3571370562
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2112116486
Short name T45
Test name
Test status
Simulation time 31673943 ps
CPU time 0.44 seconds
Started Jul 02 07:34:17 AM PDT 24
Finished Jul 02 07:34:18 AM PDT 24
Peak memory 145280 kb
Host smart-74fa2ef3-f50f-4c57-ba0f-097fe632eebc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2112116486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2112116486
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2626725281
Short name T33
Test name
Test status
Simulation time 29064140 ps
CPU time 0.43 seconds
Started Jul 02 07:31:40 AM PDT 24
Finished Jul 02 07:31:43 AM PDT 24
Peak memory 144716 kb
Host smart-7a4acc5b-80fb-4deb-ba2f-e08b53617d86
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2626725281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2626725281
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3092186100
Short name T52
Test name
Test status
Simulation time 31811585 ps
CPU time 0.46 seconds
Started Jul 02 07:31:34 AM PDT 24
Finished Jul 02 07:31:36 AM PDT 24
Peak memory 145436 kb
Host smart-7da6c70b-14e5-4aca-b7df-54a6a5285272
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3092186100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3092186100
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1750911380
Short name T37
Test name
Test status
Simulation time 29279462 ps
CPU time 0.41 seconds
Started Jul 02 07:31:34 AM PDT 24
Finished Jul 02 07:31:35 AM PDT 24
Peak memory 145436 kb
Host smart-b237a93d-06da-4902-9955-3e39652f4d2d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1750911380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1750911380
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.855235690
Short name T38
Test name
Test status
Simulation time 30197548 ps
CPU time 0.44 seconds
Started Jul 02 07:31:33 AM PDT 24
Finished Jul 02 07:31:34 AM PDT 24
Peak memory 144376 kb
Host smart-9a3440a0-242f-4736-bd2f-53a0689065cb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=855235690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.855235690
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.224256785
Short name T48
Test name
Test status
Simulation time 29404283 ps
CPU time 0.41 seconds
Started Jul 02 07:31:40 AM PDT 24
Finished Jul 02 07:31:43 AM PDT 24
Peak memory 145376 kb
Host smart-4345caca-d933-4750-86f2-36633a458414
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=224256785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.224256785
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.710555974
Short name T30
Test name
Test status
Simulation time 29443336 ps
CPU time 0.41 seconds
Started Jul 02 07:31:53 AM PDT 24
Finished Jul 02 07:31:54 AM PDT 24
Peak memory 145376 kb
Host smart-fe6067d1-2c00-483d-8f0b-30564200cd7a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=710555974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.710555974
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1855471838
Short name T32
Test name
Test status
Simulation time 29231890 ps
CPU time 0.42 seconds
Started Jul 02 07:31:40 AM PDT 24
Finished Jul 02 07:31:43 AM PDT 24
Peak memory 145376 kb
Host smart-2576b3fe-7113-4418-91b6-2375e7ee3d13
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1855471838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1855471838
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1370372718
Short name T47
Test name
Test status
Simulation time 30103710 ps
CPU time 0.41 seconds
Started Jul 02 07:31:39 AM PDT 24
Finished Jul 02 07:31:42 AM PDT 24
Peak memory 145376 kb
Host smart-2fad4017-03b6-47a7-959a-f98d15f64d6e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1370372718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1370372718
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1345040640
Short name T59
Test name
Test status
Simulation time 8501512 ps
CPU time 0.39 seconds
Started Jul 02 07:31:52 AM PDT 24
Finished Jul 02 07:31:54 AM PDT 24
Peak memory 145396 kb
Host smart-15b846cf-2a2f-4f3f-82de-59e88e5ed177
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1345040640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1345040640
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3263575330
Short name T57
Test name
Test status
Simulation time 10021489 ps
CPU time 0.37 seconds
Started Jul 02 07:31:40 AM PDT 24
Finished Jul 02 07:31:43 AM PDT 24
Peak memory 144884 kb
Host smart-5cc37024-9505-45e6-9cc3-875917296bc8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3263575330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3263575330
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.125162804
Short name T56
Test name
Test status
Simulation time 8643707 ps
CPU time 0.43 seconds
Started Jul 02 07:33:20 AM PDT 24
Finished Jul 02 07:33:21 AM PDT 24
Peak memory 145432 kb
Host smart-61731b28-3f4c-4fdc-8505-1ae5474312bb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=125162804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.125162804
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.653261883
Short name T18
Test name
Test status
Simulation time 8430661 ps
CPU time 0.39 seconds
Started Jul 02 07:31:55 AM PDT 24
Finished Jul 02 07:31:56 AM PDT 24
Peak memory 145480 kb
Host smart-e60831e1-91fc-42a6-a667-4a89c66a569a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=653261883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.653261883
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3935824882
Short name T21
Test name
Test status
Simulation time 10541798 ps
CPU time 0.38 seconds
Started Jul 02 07:31:53 AM PDT 24
Finished Jul 02 07:31:54 AM PDT 24
Peak memory 145448 kb
Host smart-15fa8b0e-74f0-4c59-a06a-a78457003275
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3935824882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3935824882
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2726394956
Short name T53
Test name
Test status
Simulation time 9918279 ps
CPU time 0.39 seconds
Started Jul 02 07:36:13 AM PDT 24
Finished Jul 02 07:36:15 AM PDT 24
Peak memory 145088 kb
Host smart-7b1ac202-f6f2-461a-bf16-a5b940964bdb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2726394956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2726394956
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3153894304
Short name T19
Test name
Test status
Simulation time 9025854 ps
CPU time 0.43 seconds
Started Jul 02 07:32:01 AM PDT 24
Finished Jul 02 07:32:02 AM PDT 24
Peak memory 145356 kb
Host smart-c0c62755-f4b8-4b30-9704-a405716cb8a0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3153894304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3153894304
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3407405640
Short name T24
Test name
Test status
Simulation time 8699431 ps
CPU time 0.38 seconds
Started Jul 02 07:36:37 AM PDT 24
Finished Jul 02 07:36:44 AM PDT 24
Peak memory 146320 kb
Host smart-b963f21a-5944-46c6-8ee0-8985d8f116a2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3407405640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3407405640
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3703546020
Short name T23
Test name
Test status
Simulation time 9749495 ps
CPU time 0.4 seconds
Started Jul 02 07:34:47 AM PDT 24
Finished Jul 02 07:34:48 AM PDT 24
Peak memory 145432 kb
Host smart-1f338b9c-d9c2-4c8e-9076-050fc2a688b7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3703546020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3703546020
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.390562180
Short name T26
Test name
Test status
Simulation time 9644871 ps
CPU time 0.36 seconds
Started Jul 02 07:37:13 AM PDT 24
Finished Jul 02 07:37:17 AM PDT 24
Peak memory 146256 kb
Host smart-04472ca8-f000-49f7-970c-145fecd78f53
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=390562180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.390562180
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1544900707
Short name T58
Test name
Test status
Simulation time 8715400 ps
CPU time 0.37 seconds
Started Jul 02 07:36:29 AM PDT 24
Finished Jul 02 07:36:33 AM PDT 24
Peak memory 145020 kb
Host smart-94ada43f-98a1-431a-868c-90cb99af3da4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1544900707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1544900707
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3706095867
Short name T29
Test name
Test status
Simulation time 10212018 ps
CPU time 0.42 seconds
Started Jul 02 07:31:34 AM PDT 24
Finished Jul 02 07:31:35 AM PDT 24
Peak memory 145700 kb
Host smart-8ee4f68c-a334-406c-a3a3-bba519779a09
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3706095867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3706095867
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.797643872
Short name T60
Test name
Test status
Simulation time 9480794 ps
CPU time 0.39 seconds
Started Jul 02 07:31:39 AM PDT 24
Finished Jul 02 07:31:41 AM PDT 24
Peak memory 145968 kb
Host smart-32df2313-7dee-4cb7-8f2f-db60e25105ba
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=797643872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.797643872
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3145930828
Short name T27
Test name
Test status
Simulation time 10520694 ps
CPU time 0.42 seconds
Started Jul 02 07:31:54 AM PDT 24
Finished Jul 02 07:31:56 AM PDT 24
Peak memory 145480 kb
Host smart-9b51b449-1fb6-4ff6-9ded-12022d63d591
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3145930828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3145930828
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3488626753
Short name T22
Test name
Test status
Simulation time 8979384 ps
CPU time 0.39 seconds
Started Jul 02 07:31:39 AM PDT 24
Finished Jul 02 07:31:41 AM PDT 24
Peak memory 144884 kb
Host smart-9e29087d-c0dc-4989-9b3b-ea128731898d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3488626753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3488626753
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1823847195
Short name T54
Test name
Test status
Simulation time 8588987 ps
CPU time 0.38 seconds
Started Jul 02 07:31:51 AM PDT 24
Finished Jul 02 07:31:52 AM PDT 24
Peak memory 145660 kb
Host smart-0fe0c78a-b436-4c60-8dc1-310ec721efd8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1823847195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1823847195
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1994185802
Short name T25
Test name
Test status
Simulation time 8915353 ps
CPU time 0.37 seconds
Started Jul 02 07:31:41 AM PDT 24
Finished Jul 02 07:31:43 AM PDT 24
Peak memory 144960 kb
Host smart-9f137924-55d9-4921-9718-f08f55f953f1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1994185802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1994185802
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.48862132
Short name T55
Test name
Test status
Simulation time 9324277 ps
CPU time 0.4 seconds
Started Jul 02 07:31:33 AM PDT 24
Finished Jul 02 07:31:34 AM PDT 24
Peak memory 144416 kb
Host smart-4ebea7ea-dadb-4f75-8a63-45ef52724881
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=48862132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.48862132
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3367150300
Short name T20
Test name
Test status
Simulation time 7988359 ps
CPU time 0.42 seconds
Started Jul 02 07:31:39 AM PDT 24
Finished Jul 02 07:31:41 AM PDT 24
Peak memory 144812 kb
Host smart-9bd6bdd8-cd63-4eaa-bb39-ae8d809b4634
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3367150300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3367150300
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2562526416
Short name T77
Test name
Test status
Simulation time 25446624 ps
CPU time 0.4 seconds
Started Jul 02 07:36:42 AM PDT 24
Finished Jul 02 07:36:49 AM PDT 24
Peak memory 145220 kb
Host smart-b2fad4f3-a361-4f9a-8fe6-aadafb33044d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2562526416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2562526416
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2037106494
Short name T69
Test name
Test status
Simulation time 27981477 ps
CPU time 0.4 seconds
Started Jul 02 07:36:43 AM PDT 24
Finished Jul 02 07:36:51 AM PDT 24
Peak memory 145068 kb
Host smart-c572f01c-1de9-4a3a-878d-060b2b344da4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2037106494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2037106494
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1275047706
Short name T79
Test name
Test status
Simulation time 27428419 ps
CPU time 0.38 seconds
Started Jul 02 07:36:40 AM PDT 24
Finished Jul 02 07:36:49 AM PDT 24
Peak memory 145252 kb
Host smart-48f5390b-98b1-4acb-b4d3-9f3a4d57b7a4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1275047706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1275047706
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3244209718
Short name T72
Test name
Test status
Simulation time 26759057 ps
CPU time 0.36 seconds
Started Jul 02 07:36:40 AM PDT 24
Finished Jul 02 07:36:49 AM PDT 24
Peak memory 145252 kb
Host smart-0a8e0bbd-da28-4814-83f7-d9d347a0b7ff
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3244209718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3244209718
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2968631585
Short name T62
Test name
Test status
Simulation time 29589453 ps
CPU time 0.41 seconds
Started Jul 02 07:34:01 AM PDT 24
Finished Jul 02 07:34:02 AM PDT 24
Peak memory 145724 kb
Host smart-d6b2ddee-1b53-43e4-b183-671e4eb284dd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2968631585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2968631585
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2681218385
Short name T68
Test name
Test status
Simulation time 28714893 ps
CPU time 0.41 seconds
Started Jul 02 07:34:19 AM PDT 24
Finished Jul 02 07:34:20 AM PDT 24
Peak memory 145408 kb
Host smart-c4d9dbe3-7829-4dbf-865e-a63e57c3ecc6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2681218385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2681218385
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1249614619
Short name T76
Test name
Test status
Simulation time 26904360 ps
CPU time 0.41 seconds
Started Jul 02 07:34:45 AM PDT 24
Finished Jul 02 07:34:46 AM PDT 24
Peak memory 145488 kb
Host smart-6d95a002-c864-47c6-b526-2775291aa683
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1249614619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1249614619
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1610858652
Short name T66
Test name
Test status
Simulation time 28740842 ps
CPU time 0.38 seconds
Started Jul 02 07:36:41 AM PDT 24
Finished Jul 02 07:36:49 AM PDT 24
Peak memory 145256 kb
Host smart-5647127e-bd2b-4859-99ad-b386f8a46195
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1610858652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1610858652
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.329407656
Short name T67
Test name
Test status
Simulation time 27546262 ps
CPU time 0.41 seconds
Started Jul 02 07:36:34 AM PDT 24
Finished Jul 02 07:36:42 AM PDT 24
Peak memory 144672 kb
Host smart-e177b2de-50f4-46ce-9034-d1207b86f6b9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=329407656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.329407656
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4026248773
Short name T6
Test name
Test status
Simulation time 28416717 ps
CPU time 0.42 seconds
Started Jul 02 07:34:46 AM PDT 24
Finished Jul 02 07:34:47 AM PDT 24
Peak memory 145528 kb
Host smart-b28527e8-5322-4c2a-a339-b9f566b4b8b0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4026248773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.4026248773
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3085786842
Short name T74
Test name
Test status
Simulation time 29008661 ps
CPU time 0.46 seconds
Started Jul 02 07:36:34 AM PDT 24
Finished Jul 02 07:36:42 AM PDT 24
Peak memory 143592 kb
Host smart-517f9d5a-cbdd-4b70-8212-7e41d5f427d3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3085786842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3085786842
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3815248213
Short name T78
Test name
Test status
Simulation time 26915301 ps
CPU time 0.38 seconds
Started Jul 02 07:36:35 AM PDT 24
Finished Jul 02 07:36:43 AM PDT 24
Peak memory 145004 kb
Host smart-435f2d18-6a17-49f7-8a75-735cb0d0e789
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3815248213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3815248213
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3531882506
Short name T64
Test name
Test status
Simulation time 27114511 ps
CPU time 0.43 seconds
Started Jul 02 07:33:52 AM PDT 24
Finished Jul 02 07:33:53 AM PDT 24
Peak memory 145432 kb
Host smart-b85b7b3b-f995-41eb-81c0-84a202bf91ed
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3531882506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3531882506
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3609932388
Short name T70
Test name
Test status
Simulation time 26576104 ps
CPU time 0.38 seconds
Started Jul 02 07:36:42 AM PDT 24
Finished Jul 02 07:36:49 AM PDT 24
Peak memory 146312 kb
Host smart-e3d24f8f-b60a-447c-b889-959aaa2c2a4a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3609932388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3609932388
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1707535431
Short name T73
Test name
Test status
Simulation time 27765822 ps
CPU time 0.38 seconds
Started Jul 02 07:36:43 AM PDT 24
Finished Jul 02 07:36:51 AM PDT 24
Peak memory 145076 kb
Host smart-e278aa8d-a8c8-4284-b3d2-9eaec6269016
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1707535431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1707535431
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3054803240
Short name T63
Test name
Test status
Simulation time 26545505 ps
CPU time 0.39 seconds
Started Jul 02 07:36:29 AM PDT 24
Finished Jul 02 07:36:34 AM PDT 24
Peak memory 145012 kb
Host smart-3f3adbb0-200f-4a01-afb8-f5bcfe078bfd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3054803240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3054803240
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1609489821
Short name T75
Test name
Test status
Simulation time 27835101 ps
CPU time 0.47 seconds
Started Jul 02 07:36:29 AM PDT 24
Finished Jul 02 07:36:32 AM PDT 24
Peak memory 144456 kb
Host smart-5ce7d477-e73f-4545-8c52-7681b6ee056c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1609489821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1609489821
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4111591500
Short name T71
Test name
Test status
Simulation time 27335647 ps
CPU time 0.44 seconds
Started Jul 02 07:36:29 AM PDT 24
Finished Jul 02 07:36:32 AM PDT 24
Peak memory 144384 kb
Host smart-b623f170-2c8f-4982-bacd-9c12f9e498a9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4111591500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.4111591500
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1766707607
Short name T61
Test name
Test status
Simulation time 27792626 ps
CPU time 0.42 seconds
Started Jul 02 07:33:21 AM PDT 24
Finished Jul 02 07:33:22 AM PDT 24
Peak memory 145672 kb
Host smart-8a626d82-d4d3-4750-b8db-b3af727eeb17
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1766707607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1766707607
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.382723700
Short name T65
Test name
Test status
Simulation time 26842800 ps
CPU time 0.39 seconds
Started Jul 02 07:36:43 AM PDT 24
Finished Jul 02 07:36:51 AM PDT 24
Peak memory 145084 kb
Host smart-8c3fbc88-64b9-49f5-9516-cbb8c7305e4d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=382723700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.382723700
Directory /workspace/9.prim_sync_fatal_alert/latest
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