Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.51 89.51 100.00 100.00 91.67 91.67 100.00 100.00 82.14 82.14 95.83 95.83 67.44 67.44 /workspace/coverage/default/4.prim_async_alert.1459682174
92.64 3.13 100.00 0.00 91.67 0.00 100.00 0.00 89.29 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/5.prim_sync_alert.3898565874
94.50 1.86 100.00 0.00 95.83 4.17 100.00 0.00 89.29 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3653034659
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/0.prim_async_alert.2116710832
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3059405265

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.2912938058
/workspace/coverage/default/10.prim_async_alert.1981728835
/workspace/coverage/default/11.prim_async_alert.2595404873
/workspace/coverage/default/12.prim_async_alert.4064795156
/workspace/coverage/default/13.prim_async_alert.1617236861
/workspace/coverage/default/14.prim_async_alert.4112943379
/workspace/coverage/default/16.prim_async_alert.4198260756
/workspace/coverage/default/17.prim_async_alert.2656529428
/workspace/coverage/default/18.prim_async_alert.2239843861
/workspace/coverage/default/19.prim_async_alert.1001995906
/workspace/coverage/default/2.prim_async_alert.1280509936
/workspace/coverage/default/3.prim_async_alert.110221139
/workspace/coverage/default/5.prim_async_alert.1664759675
/workspace/coverage/default/6.prim_async_alert.2534864817
/workspace/coverage/default/7.prim_async_alert.2417013295
/workspace/coverage/default/8.prim_async_alert.2257731280
/workspace/coverage/default/9.prim_async_alert.3527696434
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3635300694
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.707779007
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.914363919
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2044051984
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1395085789
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2010247861
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1463391914
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2157946012
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1583897193
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4203102945
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.465593982
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1013618683
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.958142032
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3056390821
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1250002605
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3477145073
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1402968887
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3344215721
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.199801046
/workspace/coverage/sync_alert/0.prim_sync_alert.954331958
/workspace/coverage/sync_alert/1.prim_sync_alert.791400954
/workspace/coverage/sync_alert/10.prim_sync_alert.596004761
/workspace/coverage/sync_alert/11.prim_sync_alert.606303659
/workspace/coverage/sync_alert/12.prim_sync_alert.1574565318
/workspace/coverage/sync_alert/13.prim_sync_alert.3094474945
/workspace/coverage/sync_alert/14.prim_sync_alert.2405256706
/workspace/coverage/sync_alert/15.prim_sync_alert.87012262
/workspace/coverage/sync_alert/16.prim_sync_alert.3397935806
/workspace/coverage/sync_alert/17.prim_sync_alert.2919886377
/workspace/coverage/sync_alert/18.prim_sync_alert.820729287
/workspace/coverage/sync_alert/19.prim_sync_alert.2798185289
/workspace/coverage/sync_alert/2.prim_sync_alert.38229897
/workspace/coverage/sync_alert/3.prim_sync_alert.988376407
/workspace/coverage/sync_alert/4.prim_sync_alert.3949060311
/workspace/coverage/sync_alert/6.prim_sync_alert.2424300579
/workspace/coverage/sync_alert/7.prim_sync_alert.3409896655
/workspace/coverage/sync_alert/8.prim_sync_alert.491445071
/workspace/coverage/sync_alert/9.prim_sync_alert.3718579325
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1427447606
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1872890028
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.445127632
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3834529064
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2446742609
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2672297278
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1214587734
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2224781765
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.869871242
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.29787346
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4178526978
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2725950836
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.270451272
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.393657908
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.699963150
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.438705886
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4257747070
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2543297699
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1163626027



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/11.prim_async_alert.2595404873 Jul 03 04:16:41 PM PDT 24 Jul 03 04:16:42 PM PDT 24 11795447 ps
T2 /workspace/coverage/default/3.prim_async_alert.110221139 Jul 03 04:15:36 PM PDT 24 Jul 03 04:15:38 PM PDT 24 11421366 ps
T3 /workspace/coverage/default/13.prim_async_alert.1617236861 Jul 03 04:16:15 PM PDT 24 Jul 03 04:16:16 PM PDT 24 12030364 ps
T12 /workspace/coverage/default/4.prim_async_alert.1459682174 Jul 03 04:16:08 PM PDT 24 Jul 03 04:16:09 PM PDT 24 11985094 ps
T18 /workspace/coverage/default/1.prim_async_alert.2912938058 Jul 03 04:19:27 PM PDT 24 Jul 03 04:19:28 PM PDT 24 10772149 ps
T19 /workspace/coverage/default/10.prim_async_alert.1981728835 Jul 03 04:21:25 PM PDT 24 Jul 03 04:21:26 PM PDT 24 10546415 ps
T20 /workspace/coverage/default/7.prim_async_alert.2417013295 Jul 03 04:21:16 PM PDT 24 Jul 03 04:21:17 PM PDT 24 10605750 ps
T9 /workspace/coverage/default/16.prim_async_alert.4198260756 Jul 03 04:22:00 PM PDT 24 Jul 03 04:22:01 PM PDT 24 11016441 ps
T21 /workspace/coverage/default/5.prim_async_alert.1664759675 Jul 03 04:21:39 PM PDT 24 Jul 03 04:21:40 PM PDT 24 11567950 ps
T16 /workspace/coverage/default/18.prim_async_alert.2239843861 Jul 03 04:21:25 PM PDT 24 Jul 03 04:21:26 PM PDT 24 10852273 ps
T14 /workspace/coverage/default/19.prim_async_alert.1001995906 Jul 03 04:15:36 PM PDT 24 Jul 03 04:15:36 PM PDT 24 10362237 ps
T7 /workspace/coverage/default/17.prim_async_alert.2656529428 Jul 03 04:21:26 PM PDT 24 Jul 03 04:21:27 PM PDT 24 10627796 ps
T10 /workspace/coverage/default/0.prim_async_alert.2116710832 Jul 03 04:15:37 PM PDT 24 Jul 03 04:15:38 PM PDT 24 11761161 ps
T13 /workspace/coverage/default/12.prim_async_alert.4064795156 Jul 03 04:21:30 PM PDT 24 Jul 03 04:21:30 PM PDT 24 11012322 ps
T48 /workspace/coverage/default/14.prim_async_alert.4112943379 Jul 03 04:15:41 PM PDT 24 Jul 03 04:15:42 PM PDT 24 12508687 ps
T15 /workspace/coverage/default/8.prim_async_alert.2257731280 Jul 03 04:21:17 PM PDT 24 Jul 03 04:21:18 PM PDT 24 11638972 ps
T17 /workspace/coverage/default/9.prim_async_alert.3527696434 Jul 03 04:15:36 PM PDT 24 Jul 03 04:15:36 PM PDT 24 12662235 ps
T22 /workspace/coverage/default/2.prim_async_alert.1280509936 Jul 03 04:16:18 PM PDT 24 Jul 03 04:16:18 PM PDT 24 10834221 ps
T23 /workspace/coverage/default/6.prim_async_alert.2534864817 Jul 03 04:15:37 PM PDT 24 Jul 03 04:15:38 PM PDT 24 10827244 ps
T41 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1395085789 Jul 03 04:22:35 PM PDT 24 Jul 03 04:22:36 PM PDT 24 29329184 ps
T8 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3477145073 Jul 03 04:17:35 PM PDT 24 Jul 03 04:17:36 PM PDT 24 30010950 ps
T4 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3653034659 Jul 03 04:18:37 PM PDT 24 Jul 03 04:18:38 PM PDT 24 31618053 ps
T42 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1013618683 Jul 03 04:20:30 PM PDT 24 Jul 03 04:20:31 PM PDT 24 29852782 ps
T43 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4203102945 Jul 03 04:20:23 PM PDT 24 Jul 03 04:20:24 PM PDT 24 30840152 ps
T44 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.199801046 Jul 03 04:20:28 PM PDT 24 Jul 03 04:20:29 PM PDT 24 28607892 ps
T45 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1583897193 Jul 03 04:20:07 PM PDT 24 Jul 03 04:20:08 PM PDT 24 29416586 ps
T5 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.958142032 Jul 03 04:17:35 PM PDT 24 Jul 03 04:17:36 PM PDT 24 30454612 ps
T46 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3056390821 Jul 03 04:20:23 PM PDT 24 Jul 03 04:20:24 PM PDT 24 30875160 ps
T47 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2010247861 Jul 03 04:21:12 PM PDT 24 Jul 03 04:21:13 PM PDT 24 29835850 ps
T49 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2044051984 Jul 03 04:20:55 PM PDT 24 Jul 03 04:20:56 PM PDT 24 30823847 ps
T50 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1402968887 Jul 03 04:17:35 PM PDT 24 Jul 03 04:17:36 PM PDT 24 29012130 ps
T51 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3344215721 Jul 03 04:22:39 PM PDT 24 Jul 03 04:22:40 PM PDT 24 31394144 ps
T52 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.914363919 Jul 03 04:20:23 PM PDT 24 Jul 03 04:20:24 PM PDT 24 29653122 ps
T53 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3635300694 Jul 03 04:21:55 PM PDT 24 Jul 03 04:21:56 PM PDT 24 30025527 ps
T54 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1463391914 Jul 03 04:21:16 PM PDT 24 Jul 03 04:21:17 PM PDT 24 29557785 ps
T55 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2157946012 Jul 03 04:22:32 PM PDT 24 Jul 03 04:22:33 PM PDT 24 30191844 ps
T56 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.707779007 Jul 03 04:21:00 PM PDT 24 Jul 03 04:21:01 PM PDT 24 30599214 ps
T57 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.465593982 Jul 03 04:17:31 PM PDT 24 Jul 03 04:17:31 PM PDT 24 30674827 ps
T58 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1250002605 Jul 03 04:19:08 PM PDT 24 Jul 03 04:19:08 PM PDT 24 29504326 ps
T32 /workspace/coverage/sync_alert/12.prim_sync_alert.1574565318 Jul 03 04:18:55 PM PDT 24 Jul 03 04:18:57 PM PDT 24 8030423 ps
T33 /workspace/coverage/sync_alert/5.prim_sync_alert.3898565874 Jul 03 04:16:01 PM PDT 24 Jul 03 04:16:02 PM PDT 24 8728114 ps
T34 /workspace/coverage/sync_alert/10.prim_sync_alert.596004761 Jul 03 04:23:11 PM PDT 24 Jul 03 04:23:12 PM PDT 24 10515012 ps
T24 /workspace/coverage/sync_alert/9.prim_sync_alert.3718579325 Jul 03 04:20:28 PM PDT 24 Jul 03 04:20:29 PM PDT 24 10626863 ps
T35 /workspace/coverage/sync_alert/3.prim_sync_alert.988376407 Jul 03 04:15:37 PM PDT 24 Jul 03 04:15:38 PM PDT 24 10936607 ps
T36 /workspace/coverage/sync_alert/8.prim_sync_alert.491445071 Jul 03 04:20:27 PM PDT 24 Jul 03 04:20:28 PM PDT 24 9813782 ps
T37 /workspace/coverage/sync_alert/7.prim_sync_alert.3409896655 Jul 03 04:18:55 PM PDT 24 Jul 03 04:18:57 PM PDT 24 8758501 ps
T38 /workspace/coverage/sync_alert/13.prim_sync_alert.3094474945 Jul 03 04:20:09 PM PDT 24 Jul 03 04:20:10 PM PDT 24 8891122 ps
T39 /workspace/coverage/sync_alert/14.prim_sync_alert.2405256706 Jul 03 04:21:14 PM PDT 24 Jul 03 04:21:15 PM PDT 24 8937645 ps
T40 /workspace/coverage/sync_alert/18.prim_sync_alert.820729287 Jul 03 04:18:27 PM PDT 24 Jul 03 04:18:28 PM PDT 24 8949014 ps
T59 /workspace/coverage/sync_alert/17.prim_sync_alert.2919886377 Jul 03 04:15:36 PM PDT 24 Jul 03 04:15:37 PM PDT 24 9187649 ps
T60 /workspace/coverage/sync_alert/16.prim_sync_alert.3397935806 Jul 03 04:16:09 PM PDT 24 Jul 03 04:16:10 PM PDT 24 7937445 ps
T25 /workspace/coverage/sync_alert/19.prim_sync_alert.2798185289 Jul 03 04:16:20 PM PDT 24 Jul 03 04:16:20 PM PDT 24 9119011 ps
T61 /workspace/coverage/sync_alert/2.prim_sync_alert.38229897 Jul 03 04:17:21 PM PDT 24 Jul 03 04:17:22 PM PDT 24 9267472 ps
T62 /workspace/coverage/sync_alert/15.prim_sync_alert.87012262 Jul 03 04:15:57 PM PDT 24 Jul 03 04:15:58 PM PDT 24 8793040 ps
T63 /workspace/coverage/sync_alert/6.prim_sync_alert.2424300579 Jul 03 04:15:35 PM PDT 24 Jul 03 04:15:37 PM PDT 24 10801691 ps
T26 /workspace/coverage/sync_alert/11.prim_sync_alert.606303659 Jul 03 04:20:18 PM PDT 24 Jul 03 04:20:19 PM PDT 24 9079787 ps
T64 /workspace/coverage/sync_alert/0.prim_sync_alert.954331958 Jul 03 04:21:14 PM PDT 24 Jul 03 04:21:15 PM PDT 24 9066662 ps
T65 /workspace/coverage/sync_alert/4.prim_sync_alert.3949060311 Jul 03 04:15:39 PM PDT 24 Jul 03 04:15:39 PM PDT 24 8996922 ps
T27 /workspace/coverage/sync_alert/1.prim_sync_alert.791400954 Jul 03 04:15:41 PM PDT 24 Jul 03 04:15:42 PM PDT 24 9551107 ps
T11 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3059405265 Jul 03 04:20:28 PM PDT 24 Jul 03 04:20:28 PM PDT 24 27470907 ps
T66 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.869871242 Jul 03 04:20:15 PM PDT 24 Jul 03 04:20:16 PM PDT 24 26907928 ps
T6 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2672297278 Jul 03 04:21:25 PM PDT 24 Jul 03 04:21:26 PM PDT 24 28549759 ps
T28 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4257747070 Jul 03 04:20:04 PM PDT 24 Jul 03 04:20:04 PM PDT 24 27029020 ps
T67 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2725950836 Jul 03 04:21:30 PM PDT 24 Jul 03 04:21:31 PM PDT 24 28003706 ps
T29 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4178526978 Jul 03 04:21:20 PM PDT 24 Jul 03 04:21:21 PM PDT 24 28705827 ps
T68 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1214587734 Jul 03 04:20:24 PM PDT 24 Jul 03 04:20:25 PM PDT 24 25895363 ps
T30 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1872890028 Jul 03 04:21:28 PM PDT 24 Jul 03 04:21:29 PM PDT 24 27364969 ps
T69 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2224781765 Jul 03 04:16:02 PM PDT 24 Jul 03 04:16:03 PM PDT 24 28799142 ps
T70 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.29787346 Jul 03 04:21:08 PM PDT 24 Jul 03 04:21:09 PM PDT 24 28636984 ps
T31 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3834529064 Jul 03 04:21:00 PM PDT 24 Jul 03 04:21:01 PM PDT 24 28338376 ps
T71 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2543297699 Jul 03 04:15:41 PM PDT 24 Jul 03 04:15:42 PM PDT 24 26962273 ps
T72 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1163626027 Jul 03 04:15:41 PM PDT 24 Jul 03 04:15:42 PM PDT 24 27197080 ps
T73 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.438705886 Jul 03 04:21:25 PM PDT 24 Jul 03 04:21:26 PM PDT 24 26053726 ps
T74 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.699963150 Jul 03 04:21:26 PM PDT 24 Jul 03 04:21:27 PM PDT 24 27564529 ps
T75 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2446742609 Jul 03 04:21:16 PM PDT 24 Jul 03 04:21:17 PM PDT 24 28798768 ps
T76 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.270451272 Jul 03 04:16:26 PM PDT 24 Jul 03 04:16:26 PM PDT 24 29486416 ps
T77 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.445127632 Jul 03 04:21:20 PM PDT 24 Jul 03 04:21:21 PM PDT 24 27762100 ps
T78 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1427447606 Jul 03 04:18:55 PM PDT 24 Jul 03 04:18:57 PM PDT 24 27792492 ps
T79 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.393657908 Jul 03 04:18:55 PM PDT 24 Jul 03 04:18:57 PM PDT 24 27615514 ps

Test location /workspace/coverage/default/4.prim_async_alert.1459682174
Short name T12
Test name
Test status
Simulation time 11985094 ps
CPU time 0.37 seconds
Started Jul 03 04:16:08 PM PDT 24
Finished Jul 03 04:16:09 PM PDT 24
Peak memory 145420 kb
Host smart-7c1788fb-9849-4c46-9b37-1e1393189cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459682174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1459682174
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3898565874
Short name T33
Test name
Test status
Simulation time 8728114 ps
CPU time 0.46 seconds
Started Jul 03 04:16:01 PM PDT 24
Finished Jul 03 04:16:02 PM PDT 24
Peak memory 145196 kb
Host smart-0031d50e-7d5a-4319-9087-9ed9228f70bb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3898565874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3898565874
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3653034659
Short name T4
Test name
Test status
Simulation time 31618053 ps
CPU time 0.42 seconds
Started Jul 03 04:18:37 PM PDT 24
Finished Jul 03 04:18:38 PM PDT 24
Peak memory 145200 kb
Host smart-618cecd0-fa1b-4c59-98e0-4d03e8034ca3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3653034659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3653034659
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2116710832
Short name T10
Test name
Test status
Simulation time 11761161 ps
CPU time 0.4 seconds
Started Jul 03 04:15:37 PM PDT 24
Finished Jul 03 04:15:38 PM PDT 24
Peak memory 145168 kb
Host smart-aa8a2f63-dc5a-47ce-a48c-8796743a81cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116710832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2116710832
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3059405265
Short name T11
Test name
Test status
Simulation time 27470907 ps
CPU time 0.42 seconds
Started Jul 03 04:20:28 PM PDT 24
Finished Jul 03 04:20:28 PM PDT 24
Peak memory 144916 kb
Host smart-27f72eeb-91c2-46b7-be54-32ddba5dbd9d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3059405265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3059405265
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2912938058
Short name T18
Test name
Test status
Simulation time 10772149 ps
CPU time 0.41 seconds
Started Jul 03 04:19:27 PM PDT 24
Finished Jul 03 04:19:28 PM PDT 24
Peak memory 145652 kb
Host smart-62e2b3e2-d9e1-4825-947c-6c15e1438a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912938058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2912938058
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1981728835
Short name T19
Test name
Test status
Simulation time 10546415 ps
CPU time 0.42 seconds
Started Jul 03 04:21:25 PM PDT 24
Finished Jul 03 04:21:26 PM PDT 24
Peak memory 144984 kb
Host smart-2462d8e5-0f34-42ec-980b-4b88ac8373ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981728835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1981728835
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2595404873
Short name T1
Test name
Test status
Simulation time 11795447 ps
CPU time 0.4 seconds
Started Jul 03 04:16:41 PM PDT 24
Finished Jul 03 04:16:42 PM PDT 24
Peak memory 145432 kb
Host smart-f6d03bd5-062b-4f3d-8f50-14acb6caa165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595404873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2595404873
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.4064795156
Short name T13
Test name
Test status
Simulation time 11012322 ps
CPU time 0.37 seconds
Started Jul 03 04:21:30 PM PDT 24
Finished Jul 03 04:21:30 PM PDT 24
Peak memory 145424 kb
Host smart-1bacb037-6cbc-4eb2-b3d3-c0617fbfca86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064795156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.4064795156
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1617236861
Short name T3
Test name
Test status
Simulation time 12030364 ps
CPU time 0.38 seconds
Started Jul 03 04:16:15 PM PDT 24
Finished Jul 03 04:16:16 PM PDT 24
Peak memory 145900 kb
Host smart-2ddf66a1-99ee-4454-861a-cfe667f95f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617236861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1617236861
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.4112943379
Short name T48
Test name
Test status
Simulation time 12508687 ps
CPU time 0.46 seconds
Started Jul 03 04:15:41 PM PDT 24
Finished Jul 03 04:15:42 PM PDT 24
Peak memory 145052 kb
Host smart-f09d117c-ead8-4a30-9bbe-1799dbbc10ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112943379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.4112943379
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.4198260756
Short name T9
Test name
Test status
Simulation time 11016441 ps
CPU time 0.38 seconds
Started Jul 03 04:22:00 PM PDT 24
Finished Jul 03 04:22:01 PM PDT 24
Peak memory 145484 kb
Host smart-76efd35e-de9f-4719-a28f-c5f219625632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198260756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.4198260756
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2656529428
Short name T7
Test name
Test status
Simulation time 10627796 ps
CPU time 0.37 seconds
Started Jul 03 04:21:26 PM PDT 24
Finished Jul 03 04:21:27 PM PDT 24
Peak memory 145108 kb
Host smart-56add45a-f6ab-4fc5-b961-49fc8a47bee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656529428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2656529428
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2239843861
Short name T16
Test name
Test status
Simulation time 10852273 ps
CPU time 0.4 seconds
Started Jul 03 04:21:25 PM PDT 24
Finished Jul 03 04:21:26 PM PDT 24
Peak memory 145124 kb
Host smart-29cb97f3-45ef-448f-9467-511d58b079c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239843861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2239843861
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1001995906
Short name T14
Test name
Test status
Simulation time 10362237 ps
CPU time 0.39 seconds
Started Jul 03 04:15:36 PM PDT 24
Finished Jul 03 04:15:36 PM PDT 24
Peak memory 145920 kb
Host smart-a91433b4-993c-499f-a762-6dd4ba924ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001995906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1001995906
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.1280509936
Short name T22
Test name
Test status
Simulation time 10834221 ps
CPU time 0.39 seconds
Started Jul 03 04:16:18 PM PDT 24
Finished Jul 03 04:16:18 PM PDT 24
Peak memory 145420 kb
Host smart-daaa6f4a-9125-46f6-97fd-7deb27bd0633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280509936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1280509936
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.110221139
Short name T2
Test name
Test status
Simulation time 11421366 ps
CPU time 0.47 seconds
Started Jul 03 04:15:36 PM PDT 24
Finished Jul 03 04:15:38 PM PDT 24
Peak memory 145228 kb
Host smart-11457b6b-4721-4677-9673-e7c64c3c1e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110221139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.110221139
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1664759675
Short name T21
Test name
Test status
Simulation time 11567950 ps
CPU time 0.44 seconds
Started Jul 03 04:21:39 PM PDT 24
Finished Jul 03 04:21:40 PM PDT 24
Peak memory 145668 kb
Host smart-c9dfeb58-ae33-4167-acea-e2cfc149f299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664759675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1664759675
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.2534864817
Short name T23
Test name
Test status
Simulation time 10827244 ps
CPU time 0.41 seconds
Started Jul 03 04:15:37 PM PDT 24
Finished Jul 03 04:15:38 PM PDT 24
Peak memory 145196 kb
Host smart-73a54688-54d3-40c9-ab2a-b2f778c2a6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534864817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2534864817
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2417013295
Short name T20
Test name
Test status
Simulation time 10605750 ps
CPU time 0.38 seconds
Started Jul 03 04:21:16 PM PDT 24
Finished Jul 03 04:21:17 PM PDT 24
Peak memory 145424 kb
Host smart-2c473fae-7a68-4805-8bc6-5bf4147bfc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417013295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2417013295
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2257731280
Short name T15
Test name
Test status
Simulation time 11638972 ps
CPU time 0.38 seconds
Started Jul 03 04:21:17 PM PDT 24
Finished Jul 03 04:21:18 PM PDT 24
Peak memory 145424 kb
Host smart-c12fe893-393e-4d05-9daa-0be94df53b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257731280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2257731280
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3527696434
Short name T17
Test name
Test status
Simulation time 12662235 ps
CPU time 0.4 seconds
Started Jul 03 04:15:36 PM PDT 24
Finished Jul 03 04:15:36 PM PDT 24
Peak memory 145920 kb
Host smart-501ee7e0-1430-48b9-90e4-c229f0739f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527696434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3527696434
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3635300694
Short name T53
Test name
Test status
Simulation time 30025527 ps
CPU time 0.39 seconds
Started Jul 03 04:21:55 PM PDT 24
Finished Jul 03 04:21:56 PM PDT 24
Peak memory 145188 kb
Host smart-15046acd-d10c-42a3-b375-9436dab44cd6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3635300694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3635300694
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.707779007
Short name T56
Test name
Test status
Simulation time 30599214 ps
CPU time 0.41 seconds
Started Jul 03 04:21:00 PM PDT 24
Finished Jul 03 04:21:01 PM PDT 24
Peak memory 145264 kb
Host smart-5cddeb98-cf72-4b35-bf52-f19e01d1abf7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=707779007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.707779007
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.914363919
Short name T52
Test name
Test status
Simulation time 29653122 ps
CPU time 0.41 seconds
Started Jul 03 04:20:23 PM PDT 24
Finished Jul 03 04:20:24 PM PDT 24
Peak memory 144224 kb
Host smart-af47f009-d53a-4e16-b3ad-715de36a6ba3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=914363919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.914363919
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2044051984
Short name T49
Test name
Test status
Simulation time 30823847 ps
CPU time 0.43 seconds
Started Jul 03 04:20:55 PM PDT 24
Finished Jul 03 04:20:56 PM PDT 24
Peak memory 144772 kb
Host smart-52d86ee2-2098-4b2b-8acc-af52e81c2fcf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2044051984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2044051984
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1395085789
Short name T41
Test name
Test status
Simulation time 29329184 ps
CPU time 0.39 seconds
Started Jul 03 04:22:35 PM PDT 24
Finished Jul 03 04:22:36 PM PDT 24
Peak memory 144980 kb
Host smart-1aeb5120-df37-4318-b630-59362920e5e1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1395085789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1395085789
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2010247861
Short name T47
Test name
Test status
Simulation time 29835850 ps
CPU time 0.43 seconds
Started Jul 03 04:21:12 PM PDT 24
Finished Jul 03 04:21:13 PM PDT 24
Peak memory 144204 kb
Host smart-e88d9bce-7fef-41e3-8544-591a010e2469
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2010247861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2010247861
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1463391914
Short name T54
Test name
Test status
Simulation time 29557785 ps
CPU time 0.48 seconds
Started Jul 03 04:21:16 PM PDT 24
Finished Jul 03 04:21:17 PM PDT 24
Peak memory 144980 kb
Host smart-560d13e7-9eb6-49ab-aa90-47e2113cf5c0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1463391914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1463391914
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2157946012
Short name T55
Test name
Test status
Simulation time 30191844 ps
CPU time 0.43 seconds
Started Jul 03 04:22:32 PM PDT 24
Finished Jul 03 04:22:33 PM PDT 24
Peak memory 144848 kb
Host smart-a9b58fbb-7978-4bb5-8b3f-67c23cab1516
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2157946012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2157946012
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1583897193
Short name T45
Test name
Test status
Simulation time 29416586 ps
CPU time 0.43 seconds
Started Jul 03 04:20:07 PM PDT 24
Finished Jul 03 04:20:08 PM PDT 24
Peak memory 144772 kb
Host smart-3793d8f6-e2a8-46ec-873a-d60964f388a1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1583897193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1583897193
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4203102945
Short name T43
Test name
Test status
Simulation time 30840152 ps
CPU time 0.41 seconds
Started Jul 03 04:20:23 PM PDT 24
Finished Jul 03 04:20:24 PM PDT 24
Peak memory 144980 kb
Host smart-d4164e7d-c4ad-4303-ad28-efcaccd4a104
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4203102945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.4203102945
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.465593982
Short name T57
Test name
Test status
Simulation time 30674827 ps
CPU time 0.41 seconds
Started Jul 03 04:17:31 PM PDT 24
Finished Jul 03 04:17:31 PM PDT 24
Peak memory 144988 kb
Host smart-ef6d9592-2b41-49b3-afbf-0639e91233b4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=465593982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.465593982
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1013618683
Short name T42
Test name
Test status
Simulation time 29852782 ps
CPU time 0.4 seconds
Started Jul 03 04:20:30 PM PDT 24
Finished Jul 03 04:20:31 PM PDT 24
Peak memory 145216 kb
Host smart-3922ebc3-af44-4ebc-8699-1e06fe8453ec
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1013618683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1013618683
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.958142032
Short name T5
Test name
Test status
Simulation time 30454612 ps
CPU time 0.46 seconds
Started Jul 03 04:17:35 PM PDT 24
Finished Jul 03 04:17:36 PM PDT 24
Peak memory 144964 kb
Host smart-5832c2ea-faba-4ced-a70e-5000cc6f892f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=958142032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.958142032
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3056390821
Short name T46
Test name
Test status
Simulation time 30875160 ps
CPU time 0.41 seconds
Started Jul 03 04:20:23 PM PDT 24
Finished Jul 03 04:20:24 PM PDT 24
Peak memory 144280 kb
Host smart-a2856524-69d1-4f23-b66a-9276e08e4052
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3056390821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3056390821
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1250002605
Short name T58
Test name
Test status
Simulation time 29504326 ps
CPU time 0.41 seconds
Started Jul 03 04:19:08 PM PDT 24
Finished Jul 03 04:19:08 PM PDT 24
Peak memory 145164 kb
Host smart-06f06b59-6c95-41e5-bd31-29967f7e19b9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1250002605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1250002605
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3477145073
Short name T8
Test name
Test status
Simulation time 30010950 ps
CPU time 0.4 seconds
Started Jul 03 04:17:35 PM PDT 24
Finished Jul 03 04:17:36 PM PDT 24
Peak memory 144964 kb
Host smart-342eb616-2c12-43d4-b4b9-1c5c09918bdb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3477145073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3477145073
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1402968887
Short name T50
Test name
Test status
Simulation time 29012130 ps
CPU time 0.41 seconds
Started Jul 03 04:17:35 PM PDT 24
Finished Jul 03 04:17:36 PM PDT 24
Peak memory 144964 kb
Host smart-00286860-6c79-4c01-a700-7bfafc5d534c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1402968887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1402968887
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3344215721
Short name T51
Test name
Test status
Simulation time 31394144 ps
CPU time 0.4 seconds
Started Jul 03 04:22:39 PM PDT 24
Finished Jul 03 04:22:40 PM PDT 24
Peak memory 144996 kb
Host smart-10891b17-d662-421b-bca3-749167cd86c7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3344215721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3344215721
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.199801046
Short name T44
Test name
Test status
Simulation time 28607892 ps
CPU time 0.4 seconds
Started Jul 03 04:20:28 PM PDT 24
Finished Jul 03 04:20:29 PM PDT 24
Peak memory 144480 kb
Host smart-04561ae8-d01c-4bed-bd2d-e7c9b64d7776
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=199801046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.199801046
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.954331958
Short name T64
Test name
Test status
Simulation time 9066662 ps
CPU time 0.4 seconds
Started Jul 03 04:21:14 PM PDT 24
Finished Jul 03 04:21:15 PM PDT 24
Peak memory 145452 kb
Host smart-6f1a5516-fc18-4da7-8440-97d70713448a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=954331958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.954331958
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.791400954
Short name T27
Test name
Test status
Simulation time 9551107 ps
CPU time 0.46 seconds
Started Jul 03 04:15:41 PM PDT 24
Finished Jul 03 04:15:42 PM PDT 24
Peak memory 142992 kb
Host smart-641ae617-176c-438d-adf9-7670b1fbccc6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=791400954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.791400954
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.596004761
Short name T34
Test name
Test status
Simulation time 10515012 ps
CPU time 0.37 seconds
Started Jul 03 04:23:11 PM PDT 24
Finished Jul 03 04:23:12 PM PDT 24
Peak memory 145336 kb
Host smart-0d91bc65-ca09-4d67-91f7-2ff26ea089ab
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=596004761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.596004761
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.606303659
Short name T26
Test name
Test status
Simulation time 9079787 ps
CPU time 0.41 seconds
Started Jul 03 04:20:18 PM PDT 24
Finished Jul 03 04:20:19 PM PDT 24
Peak memory 145432 kb
Host smart-54db7b89-6f07-40b8-ba2f-1ccffd577b2b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=606303659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.606303659
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.1574565318
Short name T32
Test name
Test status
Simulation time 8030423 ps
CPU time 0.49 seconds
Started Jul 03 04:18:55 PM PDT 24
Finished Jul 03 04:18:57 PM PDT 24
Peak memory 144488 kb
Host smart-4682bf06-0835-4ae2-b7f3-77bd1b26b45c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1574565318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1574565318
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3094474945
Short name T38
Test name
Test status
Simulation time 8891122 ps
CPU time 0.42 seconds
Started Jul 03 04:20:09 PM PDT 24
Finished Jul 03 04:20:10 PM PDT 24
Peak memory 145788 kb
Host smart-fe25a58b-48db-4f23-86d7-7bacdda1723d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3094474945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3094474945
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2405256706
Short name T39
Test name
Test status
Simulation time 8937645 ps
CPU time 0.43 seconds
Started Jul 03 04:21:14 PM PDT 24
Finished Jul 03 04:21:15 PM PDT 24
Peak memory 145464 kb
Host smart-827769ca-154a-4918-8e45-663fa53d90ca
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2405256706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2405256706
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.87012262
Short name T62
Test name
Test status
Simulation time 8793040 ps
CPU time 0.47 seconds
Started Jul 03 04:15:57 PM PDT 24
Finished Jul 03 04:15:58 PM PDT 24
Peak memory 145848 kb
Host smart-e1942058-dbfc-4c5c-90af-578194bce5dd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=87012262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.87012262
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3397935806
Short name T60
Test name
Test status
Simulation time 7937445 ps
CPU time 0.39 seconds
Started Jul 03 04:16:09 PM PDT 24
Finished Jul 03 04:16:10 PM PDT 24
Peak memory 145192 kb
Host smart-85268f0e-4af6-4aa5-b16f-bc96916611a1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3397935806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3397935806
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2919886377
Short name T59
Test name
Test status
Simulation time 9187649 ps
CPU time 0.38 seconds
Started Jul 03 04:15:36 PM PDT 24
Finished Jul 03 04:15:37 PM PDT 24
Peak memory 145712 kb
Host smart-0630e8a8-cea9-4f06-93ee-ae3e65a5462d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2919886377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2919886377
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.820729287
Short name T40
Test name
Test status
Simulation time 8949014 ps
CPU time 0.42 seconds
Started Jul 03 04:18:27 PM PDT 24
Finished Jul 03 04:18:28 PM PDT 24
Peak memory 145444 kb
Host smart-04ba7426-18ff-49ee-9d5b-dd4de0e8113b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=820729287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.820729287
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2798185289
Short name T25
Test name
Test status
Simulation time 9119011 ps
CPU time 0.38 seconds
Started Jul 03 04:16:20 PM PDT 24
Finished Jul 03 04:16:20 PM PDT 24
Peak memory 145212 kb
Host smart-d1d33a53-f85c-480f-a366-61552f3656ee
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2798185289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2798185289
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.38229897
Short name T61
Test name
Test status
Simulation time 9267472 ps
CPU time 0.38 seconds
Started Jul 03 04:17:21 PM PDT 24
Finished Jul 03 04:17:22 PM PDT 24
Peak memory 145164 kb
Host smart-49d7e58b-b28d-4c38-8cd5-c4c594410ad0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=38229897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.38229897
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.988376407
Short name T35
Test name
Test status
Simulation time 10936607 ps
CPU time 0.45 seconds
Started Jul 03 04:15:37 PM PDT 24
Finished Jul 03 04:15:38 PM PDT 24
Peak memory 145856 kb
Host smart-9a3dfe22-d32f-44e1-b976-42d63dc8c49c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=988376407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.988376407
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3949060311
Short name T65
Test name
Test status
Simulation time 8996922 ps
CPU time 0.39 seconds
Started Jul 03 04:15:39 PM PDT 24
Finished Jul 03 04:15:39 PM PDT 24
Peak memory 145204 kb
Host smart-b51f8ac3-e135-4f89-99a3-8cfef60ca5f5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3949060311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3949060311
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2424300579
Short name T63
Test name
Test status
Simulation time 10801691 ps
CPU time 0.45 seconds
Started Jul 03 04:15:35 PM PDT 24
Finished Jul 03 04:15:37 PM PDT 24
Peak memory 145848 kb
Host smart-79fe1210-4383-44ec-8ef3-27cb0d55d470
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2424300579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2424300579
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3409896655
Short name T37
Test name
Test status
Simulation time 8758501 ps
CPU time 0.49 seconds
Started Jul 03 04:18:55 PM PDT 24
Finished Jul 03 04:18:57 PM PDT 24
Peak memory 144436 kb
Host smart-7fc8c7ae-bd09-4f43-b3f4-20e3fa4da09e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3409896655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3409896655
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.491445071
Short name T36
Test name
Test status
Simulation time 9813782 ps
CPU time 0.43 seconds
Started Jul 03 04:20:27 PM PDT 24
Finished Jul 03 04:20:28 PM PDT 24
Peak memory 144092 kb
Host smart-0698784a-3869-40ae-ac28-1da185ad9533
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=491445071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.491445071
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3718579325
Short name T24
Test name
Test status
Simulation time 10626863 ps
CPU time 0.39 seconds
Started Jul 03 04:20:28 PM PDT 24
Finished Jul 03 04:20:29 PM PDT 24
Peak memory 144988 kb
Host smart-fb656661-665f-400c-919e-b751dcf5fced
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3718579325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3718579325
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1427447606
Short name T78
Test name
Test status
Simulation time 27792492 ps
CPU time 0.49 seconds
Started Jul 03 04:18:55 PM PDT 24
Finished Jul 03 04:18:57 PM PDT 24
Peak memory 144584 kb
Host smart-5c65339d-5ff1-4196-ae46-bb2a024bdbc3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1427447606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1427447606
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1872890028
Short name T30
Test name
Test status
Simulation time 27364969 ps
CPU time 0.42 seconds
Started Jul 03 04:21:28 PM PDT 24
Finished Jul 03 04:21:29 PM PDT 24
Peak memory 145856 kb
Host smart-68871532-7168-48b3-a540-6358e738fe7f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1872890028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1872890028
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.445127632
Short name T77
Test name
Test status
Simulation time 27762100 ps
CPU time 0.38 seconds
Started Jul 03 04:21:20 PM PDT 24
Finished Jul 03 04:21:21 PM PDT 24
Peak memory 145236 kb
Host smart-1615f369-ac19-4d46-9e1a-5486305cbd20
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=445127632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.445127632
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3834529064
Short name T31
Test name
Test status
Simulation time 28338376 ps
CPU time 0.42 seconds
Started Jul 03 04:21:00 PM PDT 24
Finished Jul 03 04:21:01 PM PDT 24
Peak memory 144712 kb
Host smart-4cb0fdae-59b8-4811-b316-36ea90117fe1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3834529064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3834529064
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2446742609
Short name T75
Test name
Test status
Simulation time 28798768 ps
CPU time 0.45 seconds
Started Jul 03 04:21:16 PM PDT 24
Finished Jul 03 04:21:17 PM PDT 24
Peak memory 144196 kb
Host smart-4d849331-2d61-4ac3-83bf-7547ff46a2e8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2446742609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2446742609
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2672297278
Short name T6
Test name
Test status
Simulation time 28549759 ps
CPU time 0.44 seconds
Started Jul 03 04:21:25 PM PDT 24
Finished Jul 03 04:21:26 PM PDT 24
Peak memory 144356 kb
Host smart-d76a90e6-20b7-4269-a5ab-de195f4e3e2a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2672297278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2672297278
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1214587734
Short name T68
Test name
Test status
Simulation time 25895363 ps
CPU time 0.4 seconds
Started Jul 03 04:20:24 PM PDT 24
Finished Jul 03 04:20:25 PM PDT 24
Peak memory 145460 kb
Host smart-9a4a3aa6-5e35-4823-a562-cfb4059f8d53
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1214587734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1214587734
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2224781765
Short name T69
Test name
Test status
Simulation time 28799142 ps
CPU time 0.43 seconds
Started Jul 03 04:16:02 PM PDT 24
Finished Jul 03 04:16:03 PM PDT 24
Peak memory 145204 kb
Host smart-7fbd4e6c-141c-4a71-bbaa-ece77d560319
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2224781765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2224781765
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.869871242
Short name T66
Test name
Test status
Simulation time 26907928 ps
CPU time 0.4 seconds
Started Jul 03 04:20:15 PM PDT 24
Finished Jul 03 04:20:16 PM PDT 24
Peak memory 145484 kb
Host smart-8262edb3-b1ef-41f0-9d74-41c38335830e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=869871242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.869871242
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.29787346
Short name T70
Test name
Test status
Simulation time 28636984 ps
CPU time 0.39 seconds
Started Jul 03 04:21:08 PM PDT 24
Finished Jul 03 04:21:09 PM PDT 24
Peak memory 145224 kb
Host smart-5fb3a384-df6e-43f9-8170-96fdaade2c08
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=29787346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.29787346
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4178526978
Short name T29
Test name
Test status
Simulation time 28705827 ps
CPU time 0.38 seconds
Started Jul 03 04:21:20 PM PDT 24
Finished Jul 03 04:21:21 PM PDT 24
Peak memory 145236 kb
Host smart-74579e8e-c189-4f2c-b73e-e526e7648536
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4178526978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.4178526978
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2725950836
Short name T67
Test name
Test status
Simulation time 28003706 ps
CPU time 0.4 seconds
Started Jul 03 04:21:30 PM PDT 24
Finished Jul 03 04:21:31 PM PDT 24
Peak memory 145196 kb
Host smart-6f4e6ce5-177f-46de-ab8e-6945a097c8a1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2725950836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2725950836
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.270451272
Short name T76
Test name
Test status
Simulation time 29486416 ps
CPU time 0.42 seconds
Started Jul 03 04:16:26 PM PDT 24
Finished Jul 03 04:16:26 PM PDT 24
Peak memory 145204 kb
Host smart-5c7b506f-029d-4878-93fa-fc02e1e5d735
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=270451272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.270451272
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.393657908
Short name T79
Test name
Test status
Simulation time 27615514 ps
CPU time 0.56 seconds
Started Jul 03 04:18:55 PM PDT 24
Finished Jul 03 04:18:57 PM PDT 24
Peak memory 144148 kb
Host smart-a3df9759-2477-490f-88ef-e7ac7cb5b32e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=393657908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.393657908
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.699963150
Short name T74
Test name
Test status
Simulation time 27564529 ps
CPU time 0.4 seconds
Started Jul 03 04:21:26 PM PDT 24
Finished Jul 03 04:21:27 PM PDT 24
Peak memory 144948 kb
Host smart-bb35e078-efc6-49e8-ae05-6c96d30797fa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=699963150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.699963150
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.438705886
Short name T73
Test name
Test status
Simulation time 26053726 ps
CPU time 0.45 seconds
Started Jul 03 04:21:25 PM PDT 24
Finished Jul 03 04:21:26 PM PDT 24
Peak memory 144412 kb
Host smart-355b3a7e-3977-40d3-aa51-d89168f32090
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=438705886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.438705886
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4257747070
Short name T28
Test name
Test status
Simulation time 27029020 ps
CPU time 0.41 seconds
Started Jul 03 04:20:04 PM PDT 24
Finished Jul 03 04:20:04 PM PDT 24
Peak memory 145452 kb
Host smart-6a785c40-1ba3-44d8-8d6e-5ff31b3946d2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4257747070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.4257747070
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2543297699
Short name T71
Test name
Test status
Simulation time 26962273 ps
CPU time 0.5 seconds
Started Jul 03 04:15:41 PM PDT 24
Finished Jul 03 04:15:42 PM PDT 24
Peak memory 144164 kb
Host smart-4486120f-b5ce-4b18-a9c3-1ddc2a479e97
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2543297699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2543297699
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1163626027
Short name T72
Test name
Test status
Simulation time 27197080 ps
CPU time 0.45 seconds
Started Jul 03 04:15:41 PM PDT 24
Finished Jul 03 04:15:42 PM PDT 24
Peak memory 144296 kb
Host smart-53cbdd64-9f10-483f-aa34-36fff26f9ae0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1163626027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1163626027
Directory /workspace/9.prim_sync_fatal_alert/latest
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