Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 78
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.42 88.42 100.00 100.00 95.83 95.83 96.43 96.43 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/8.prim_async_alert.2409956763
92.15 3.72 100.00 0.00 95.83 0.00 96.43 0.00 85.71 10.71 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/11.prim_sync_alert.3407425152
94.25 2.11 100.00 0.00 97.92 2.08 100.00 3.57 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3753190502
94.85 0.60 100.00 0.00 97.92 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/16.prim_async_alert.3139066835
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/0.prim_sync_alert.3487058669

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.325080236
/workspace/coverage/default/1.prim_async_alert.2494724508
/workspace/coverage/default/10.prim_async_alert.1525416470
/workspace/coverage/default/11.prim_async_alert.2708079367
/workspace/coverage/default/12.prim_async_alert.4126492746
/workspace/coverage/default/13.prim_async_alert.4113209737
/workspace/coverage/default/14.prim_async_alert.2381929255
/workspace/coverage/default/15.prim_async_alert.722355911
/workspace/coverage/default/17.prim_async_alert.4026650739
/workspace/coverage/default/18.prim_async_alert.38259651
/workspace/coverage/default/19.prim_async_alert.992238077
/workspace/coverage/default/2.prim_async_alert.2323257153
/workspace/coverage/default/3.prim_async_alert.3540107902
/workspace/coverage/default/4.prim_async_alert.1858779425
/workspace/coverage/default/5.prim_async_alert.3773064475
/workspace/coverage/default/6.prim_async_alert.602165582
/workspace/coverage/default/7.prim_async_alert.3646966474
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2006772486
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2029620600
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3237720149
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1884681005
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3590960052
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1928984494
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3260060151
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3285282157
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3548930973
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1720459824
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4237603475
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4097534195
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2465693524
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1947519152
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.171564353
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1316739724
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1968587669
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3942893289
/workspace/coverage/sync_alert/1.prim_sync_alert.1581794599
/workspace/coverage/sync_alert/10.prim_sync_alert.3930995246
/workspace/coverage/sync_alert/12.prim_sync_alert.4190935013
/workspace/coverage/sync_alert/13.prim_sync_alert.4029761204
/workspace/coverage/sync_alert/14.prim_sync_alert.973688951
/workspace/coverage/sync_alert/15.prim_sync_alert.2041710804
/workspace/coverage/sync_alert/16.prim_sync_alert.3692223706
/workspace/coverage/sync_alert/17.prim_sync_alert.3062268780
/workspace/coverage/sync_alert/18.prim_sync_alert.2536792924
/workspace/coverage/sync_alert/19.prim_sync_alert.508613789
/workspace/coverage/sync_alert/2.prim_sync_alert.1880546643
/workspace/coverage/sync_alert/3.prim_sync_alert.211310030
/workspace/coverage/sync_alert/4.prim_sync_alert.86979850
/workspace/coverage/sync_alert/5.prim_sync_alert.1053571263
/workspace/coverage/sync_alert/6.prim_sync_alert.3076878953
/workspace/coverage/sync_alert/7.prim_sync_alert.1645758465
/workspace/coverage/sync_alert/8.prim_sync_alert.1467466955
/workspace/coverage/sync_alert/9.prim_sync_alert.3534261597
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3169702027
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2947259023
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1994107225
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3049192906
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2350286927
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3045365268
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3994441326
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3685542895
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2677825867
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.613224577
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1230895460
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2643171634
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3348267692
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3993762886
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1887858803
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1109168069
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.963741019
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3601748158
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1590203721
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2488137438



Total test records in report: 78
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/10.prim_async_alert.1525416470 Jul 04 04:48:11 PM PDT 24 Jul 04 04:48:12 PM PDT 24 11386800 ps
T2 /workspace/coverage/default/18.prim_async_alert.38259651 Jul 04 04:48:08 PM PDT 24 Jul 04 04:48:08 PM PDT 24 11071680 ps
T3 /workspace/coverage/default/12.prim_async_alert.4126492746 Jul 04 04:48:16 PM PDT 24 Jul 04 04:48:18 PM PDT 24 11526054 ps
T7 /workspace/coverage/default/8.prim_async_alert.2409956763 Jul 04 04:48:03 PM PDT 24 Jul 04 04:48:04 PM PDT 24 11766592 ps
T8 /workspace/coverage/default/19.prim_async_alert.992238077 Jul 04 04:48:11 PM PDT 24 Jul 04 04:48:12 PM PDT 24 10747150 ps
T10 /workspace/coverage/default/11.prim_async_alert.2708079367 Jul 04 04:48:06 PM PDT 24 Jul 04 04:48:07 PM PDT 24 11883363 ps
T9 /workspace/coverage/default/6.prim_async_alert.602165582 Jul 04 04:48:06 PM PDT 24 Jul 04 04:48:06 PM PDT 24 11769908 ps
T14 /workspace/coverage/default/3.prim_async_alert.3540107902 Jul 04 04:48:14 PM PDT 24 Jul 04 04:48:15 PM PDT 24 11451124 ps
T19 /workspace/coverage/default/5.prim_async_alert.3773064475 Jul 04 04:48:03 PM PDT 24 Jul 04 04:48:04 PM PDT 24 11606680 ps
T20 /workspace/coverage/default/7.prim_async_alert.3646966474 Jul 04 04:48:10 PM PDT 24 Jul 04 04:48:11 PM PDT 24 10413991 ps
T15 /workspace/coverage/default/4.prim_async_alert.1858779425 Jul 04 04:48:12 PM PDT 24 Jul 04 04:48:13 PM PDT 24 12548490 ps
T21 /workspace/coverage/default/15.prim_async_alert.722355911 Jul 04 04:48:10 PM PDT 24 Jul 04 04:48:11 PM PDT 24 11202601 ps
T22 /workspace/coverage/default/1.prim_async_alert.2494724508 Jul 04 04:48:05 PM PDT 24 Jul 04 04:48:05 PM PDT 24 11021591 ps
T23 /workspace/coverage/default/0.prim_async_alert.325080236 Jul 04 04:48:10 PM PDT 24 Jul 04 04:48:11 PM PDT 24 10686496 ps
T17 /workspace/coverage/default/2.prim_async_alert.2323257153 Jul 04 04:48:04 PM PDT 24 Jul 04 04:48:04 PM PDT 24 12086642 ps
T24 /workspace/coverage/default/17.prim_async_alert.4026650739 Jul 04 04:48:15 PM PDT 24 Jul 04 04:48:16 PM PDT 24 11662124 ps
T16 /workspace/coverage/default/16.prim_async_alert.3139066835 Jul 04 04:48:16 PM PDT 24 Jul 04 04:48:17 PM PDT 24 11660308 ps
T49 /workspace/coverage/default/13.prim_async_alert.4113209737 Jul 04 04:48:08 PM PDT 24 Jul 04 04:48:09 PM PDT 24 11768344 ps
T50 /workspace/coverage/default/14.prim_async_alert.2381929255 Jul 04 04:48:15 PM PDT 24 Jul 04 04:48:16 PM PDT 24 10690394 ps
T18 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3942893289 Jul 04 04:48:10 PM PDT 24 Jul 04 04:48:10 PM PDT 24 30536554 ps
T44 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1720459824 Jul 04 04:48:25 PM PDT 24 Jul 04 04:48:25 PM PDT 24 29520488 ps
T25 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1316739724 Jul 04 04:48:11 PM PDT 24 Jul 04 04:48:12 PM PDT 24 31574933 ps
T4 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3753190502 Jul 04 04:48:11 PM PDT 24 Jul 04 04:48:12 PM PDT 24 30802873 ps
T5 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1884681005 Jul 04 04:48:13 PM PDT 24 Jul 04 04:48:14 PM PDT 24 29269734 ps
T45 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1968587669 Jul 04 04:48:15 PM PDT 24 Jul 04 04:48:16 PM PDT 24 30413366 ps
T6 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3590960052 Jul 04 04:48:07 PM PDT 24 Jul 04 04:48:08 PM PDT 24 29803486 ps
T46 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4237603475 Jul 04 04:48:19 PM PDT 24 Jul 04 04:48:20 PM PDT 24 28648522 ps
T47 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4097534195 Jul 04 04:48:13 PM PDT 24 Jul 04 04:48:14 PM PDT 24 30649651 ps
T48 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3285282157 Jul 04 04:48:17 PM PDT 24 Jul 04 04:48:19 PM PDT 24 29409824 ps
T51 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3260060151 Jul 04 04:48:23 PM PDT 24 Jul 04 04:48:23 PM PDT 24 30133895 ps
T52 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3237720149 Jul 04 04:48:19 PM PDT 24 Jul 04 04:48:20 PM PDT 24 29686608 ps
T53 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2465693524 Jul 04 04:48:13 PM PDT 24 Jul 04 04:48:14 PM PDT 24 30144238 ps
T54 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2006772486 Jul 04 04:48:19 PM PDT 24 Jul 04 04:48:20 PM PDT 24 32058050 ps
T55 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.171564353 Jul 04 04:48:16 PM PDT 24 Jul 04 04:48:17 PM PDT 24 30405194 ps
T56 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1947519152 Jul 04 04:48:20 PM PDT 24 Jul 04 04:48:21 PM PDT 24 30640992 ps
T57 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2029620600 Jul 04 04:48:12 PM PDT 24 Jul 04 04:48:13 PM PDT 24 31459425 ps
T58 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3548930973 Jul 04 04:48:07 PM PDT 24 Jul 04 04:48:08 PM PDT 24 29756745 ps
T59 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1928984494 Jul 04 04:48:20 PM PDT 24 Jul 04 04:48:21 PM PDT 24 30760859 ps
T26 /workspace/coverage/sync_alert/16.prim_sync_alert.3692223706 Jul 04 04:18:48 PM PDT 24 Jul 04 04:18:49 PM PDT 24 8128963 ps
T36 /workspace/coverage/sync_alert/1.prim_sync_alert.1581794599 Jul 04 04:18:46 PM PDT 24 Jul 04 04:18:47 PM PDT 24 8488316 ps
T37 /workspace/coverage/sync_alert/3.prim_sync_alert.211310030 Jul 04 04:18:48 PM PDT 24 Jul 04 04:18:49 PM PDT 24 9138806 ps
T38 /workspace/coverage/sync_alert/14.prim_sync_alert.973688951 Jul 04 04:18:48 PM PDT 24 Jul 04 04:18:49 PM PDT 24 10862729 ps
T39 /workspace/coverage/sync_alert/19.prim_sync_alert.508613789 Jul 04 04:19:22 PM PDT 24 Jul 04 04:19:23 PM PDT 24 8997857 ps
T27 /workspace/coverage/sync_alert/18.prim_sync_alert.2536792924 Jul 04 04:19:22 PM PDT 24 Jul 04 04:19:23 PM PDT 24 8856820 ps
T40 /workspace/coverage/sync_alert/2.prim_sync_alert.1880546643 Jul 04 04:18:49 PM PDT 24 Jul 04 04:18:50 PM PDT 24 8591129 ps
T41 /workspace/coverage/sync_alert/9.prim_sync_alert.3534261597 Jul 04 04:18:47 PM PDT 24 Jul 04 04:18:48 PM PDT 24 9133509 ps
T42 /workspace/coverage/sync_alert/4.prim_sync_alert.86979850 Jul 04 04:18:48 PM PDT 24 Jul 04 04:18:49 PM PDT 24 9664954 ps
T43 /workspace/coverage/sync_alert/11.prim_sync_alert.3407425152 Jul 04 04:18:47 PM PDT 24 Jul 04 04:18:48 PM PDT 24 9141927 ps
T28 /workspace/coverage/sync_alert/10.prim_sync_alert.3930995246 Jul 04 04:18:47 PM PDT 24 Jul 04 04:18:48 PM PDT 24 8550932 ps
T60 /workspace/coverage/sync_alert/13.prim_sync_alert.4029761204 Jul 04 04:18:49 PM PDT 24 Jul 04 04:18:50 PM PDT 24 9516838 ps
T61 /workspace/coverage/sync_alert/8.prim_sync_alert.1467466955 Jul 04 04:18:47 PM PDT 24 Jul 04 04:18:48 PM PDT 24 10280149 ps
T62 /workspace/coverage/sync_alert/12.prim_sync_alert.4190935013 Jul 04 04:18:48 PM PDT 24 Jul 04 04:18:49 PM PDT 24 9584620 ps
T63 /workspace/coverage/sync_alert/7.prim_sync_alert.1645758465 Jul 04 04:18:47 PM PDT 24 Jul 04 04:18:48 PM PDT 24 8371020 ps
T29 /workspace/coverage/sync_alert/17.prim_sync_alert.3062268780 Jul 04 04:18:47 PM PDT 24 Jul 04 04:18:48 PM PDT 24 9839274 ps
T64 /workspace/coverage/sync_alert/6.prim_sync_alert.3076878953 Jul 04 04:18:48 PM PDT 24 Jul 04 04:18:49 PM PDT 24 8663216 ps
T11 /workspace/coverage/sync_alert/0.prim_sync_alert.3487058669 Jul 04 04:18:46 PM PDT 24 Jul 04 04:18:47 PM PDT 24 9595689 ps
T12 /workspace/coverage/sync_alert/15.prim_sync_alert.2041710804 Jul 04 04:18:48 PM PDT 24 Jul 04 04:18:49 PM PDT 24 10253572 ps
T65 /workspace/coverage/sync_alert/5.prim_sync_alert.1053571263 Jul 04 04:18:48 PM PDT 24 Jul 04 04:18:49 PM PDT 24 9412709 ps
T30 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3601748158 Jul 04 04:48:22 PM PDT 24 Jul 04 04:48:23 PM PDT 24 27513469 ps
T31 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1230895460 Jul 04 04:48:15 PM PDT 24 Jul 04 04:48:16 PM PDT 24 27657469 ps
T32 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3169702027 Jul 04 04:48:16 PM PDT 24 Jul 04 04:48:17 PM PDT 24 27384674 ps
T13 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3348267692 Jul 04 04:48:07 PM PDT 24 Jul 04 04:48:08 PM PDT 24 26396086 ps
T33 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3993762886 Jul 04 04:48:21 PM PDT 24 Jul 04 04:48:22 PM PDT 24 27407343 ps
T66 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1590203721 Jul 04 04:48:22 PM PDT 24 Jul 04 04:48:23 PM PDT 24 27641898 ps
T67 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2677825867 Jul 04 04:48:18 PM PDT 24 Jul 04 04:48:19 PM PDT 24 27170189 ps
T34 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.963741019 Jul 04 04:48:16 PM PDT 24 Jul 04 04:48:17 PM PDT 24 26281195 ps
T35 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2350286927 Jul 04 04:48:22 PM PDT 24 Jul 04 04:48:23 PM PDT 24 28293093 ps
T68 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1994107225 Jul 04 04:48:19 PM PDT 24 Jul 04 04:48:19 PM PDT 24 29604503 ps
T69 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.613224577 Jul 04 04:48:11 PM PDT 24 Jul 04 04:48:12 PM PDT 24 26750043 ps
T70 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3049192906 Jul 04 04:48:21 PM PDT 24 Jul 04 04:48:22 PM PDT 24 28476278 ps
T71 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3685542895 Jul 04 04:48:18 PM PDT 24 Jul 04 04:48:19 PM PDT 24 27417984 ps
T72 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1887858803 Jul 04 04:48:23 PM PDT 24 Jul 04 04:48:23 PM PDT 24 28770284 ps
T73 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2643171634 Jul 04 04:48:11 PM PDT 24 Jul 04 04:48:12 PM PDT 24 25012977 ps
T74 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1109168069 Jul 04 04:48:21 PM PDT 24 Jul 04 04:48:21 PM PDT 24 25079273 ps
T75 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2488137438 Jul 04 04:48:07 PM PDT 24 Jul 04 04:48:08 PM PDT 24 26632786 ps
T76 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2947259023 Jul 04 04:48:13 PM PDT 24 Jul 04 04:48:14 PM PDT 24 25819496 ps
T77 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3994441326 Jul 04 04:48:23 PM PDT 24 Jul 04 04:48:23 PM PDT 24 28279111 ps
T78 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3045365268 Jul 04 04:48:13 PM PDT 24 Jul 04 04:48:14 PM PDT 24 27311167 ps

Test location /workspace/coverage/default/8.prim_async_alert.2409956763
Short name T7
Test name
Test status
Simulation time 11766592 ps
CPU time 0.43 seconds
Started Jul 04 04:48:03 PM PDT 24
Finished Jul 04 04:48:04 PM PDT 24
Peak memory 145628 kb
Host smart-4fc22e5e-0399-4450-9dac-114d75dab9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409956763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2409956763
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3407425152
Short name T43
Test name
Test status
Simulation time 9141927 ps
CPU time 0.37 seconds
Started Jul 04 04:18:47 PM PDT 24
Finished Jul 04 04:18:48 PM PDT 24
Peak memory 145976 kb
Host smart-782d3033-0dae-4f4e-ad7c-26111dd3d609
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3407425152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3407425152
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3753190502
Short name T4
Test name
Test status
Simulation time 30802873 ps
CPU time 0.39 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 145192 kb
Host smart-f53f3f01-e16a-449a-9429-e5cb3497c5eb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3753190502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3753190502
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3139066835
Short name T16
Test name
Test status
Simulation time 11660308 ps
CPU time 0.37 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:48:17 PM PDT 24
Peak memory 145652 kb
Host smart-01afe83d-5ead-412d-ab3a-ac5f842639c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139066835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3139066835
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3487058669
Short name T11
Test name
Test status
Simulation time 9595689 ps
CPU time 0.42 seconds
Started Jul 04 04:18:46 PM PDT 24
Finished Jul 04 04:18:47 PM PDT 24
Peak memory 144360 kb
Host smart-6cb76dff-8173-4696-8b92-2747dfa49a55
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3487058669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3487058669
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.325080236
Short name T23
Test name
Test status
Simulation time 10686496 ps
CPU time 0.38 seconds
Started Jul 04 04:48:10 PM PDT 24
Finished Jul 04 04:48:11 PM PDT 24
Peak memory 145668 kb
Host smart-032b6d13-8bba-4f43-8c1a-c998cbd1625d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325080236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.325080236
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2494724508
Short name T22
Test name
Test status
Simulation time 11021591 ps
CPU time 0.39 seconds
Started Jul 04 04:48:05 PM PDT 24
Finished Jul 04 04:48:05 PM PDT 24
Peak memory 145652 kb
Host smart-8fb93445-7c6f-4515-a539-bc700e20f5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494724508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2494724508
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1525416470
Short name T1
Test name
Test status
Simulation time 11386800 ps
CPU time 0.4 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 145648 kb
Host smart-0505edfa-7112-4174-a10d-bca96a4c3986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525416470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1525416470
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2708079367
Short name T10
Test name
Test status
Simulation time 11883363 ps
CPU time 0.37 seconds
Started Jul 04 04:48:06 PM PDT 24
Finished Jul 04 04:48:07 PM PDT 24
Peak memory 145684 kb
Host smart-d876fe67-e04b-40eb-b734-e0d09a984a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708079367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2708079367
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.4126492746
Short name T3
Test name
Test status
Simulation time 11526054 ps
CPU time 0.4 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:48:18 PM PDT 24
Peak memory 145648 kb
Host smart-bc7f0420-7e16-48b5-a72c-9cfc5876a4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126492746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.4126492746
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.4113209737
Short name T49
Test name
Test status
Simulation time 11768344 ps
CPU time 0.38 seconds
Started Jul 04 04:48:08 PM PDT 24
Finished Jul 04 04:48:09 PM PDT 24
Peak memory 145656 kb
Host smart-afa7c21a-e0a9-4e14-8f70-9f6956f95dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113209737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.4113209737
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2381929255
Short name T50
Test name
Test status
Simulation time 10690394 ps
CPU time 0.4 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:48:16 PM PDT 24
Peak memory 145624 kb
Host smart-039328e5-64a1-437f-b2a4-b4e0548e58b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381929255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2381929255
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.722355911
Short name T21
Test name
Test status
Simulation time 11202601 ps
CPU time 0.38 seconds
Started Jul 04 04:48:10 PM PDT 24
Finished Jul 04 04:48:11 PM PDT 24
Peak memory 145652 kb
Host smart-ef444a49-f800-4d0f-ae63-1c51d524d3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722355911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.722355911
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.4026650739
Short name T24
Test name
Test status
Simulation time 11662124 ps
CPU time 0.39 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:48:16 PM PDT 24
Peak memory 145640 kb
Host smart-36133296-7108-4a0b-b9b1-2c4bfb2ac435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026650739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.4026650739
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.38259651
Short name T2
Test name
Test status
Simulation time 11071680 ps
CPU time 0.4 seconds
Started Jul 04 04:48:08 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 145644 kb
Host smart-456a3a85-5786-47e6-bb8f-d5b0a6b89a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38259651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.38259651
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.992238077
Short name T8
Test name
Test status
Simulation time 10747150 ps
CPU time 0.38 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 145652 kb
Host smart-402d58ed-ff5b-4a61-97dc-c704c09013a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992238077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.992238077
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2323257153
Short name T17
Test name
Test status
Simulation time 12086642 ps
CPU time 0.44 seconds
Started Jul 04 04:48:04 PM PDT 24
Finished Jul 04 04:48:04 PM PDT 24
Peak memory 145668 kb
Host smart-86146abf-80b8-4e22-8aa4-f91e6a5740c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323257153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2323257153
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3540107902
Short name T14
Test name
Test status
Simulation time 11451124 ps
CPU time 0.39 seconds
Started Jul 04 04:48:14 PM PDT 24
Finished Jul 04 04:48:15 PM PDT 24
Peak memory 145628 kb
Host smart-2eb96caf-ea8e-47af-a8eb-9228cce7a5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540107902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3540107902
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1858779425
Short name T15
Test name
Test status
Simulation time 12548490 ps
CPU time 0.38 seconds
Started Jul 04 04:48:12 PM PDT 24
Finished Jul 04 04:48:13 PM PDT 24
Peak memory 145648 kb
Host smart-f6c2c04a-b536-4103-bdef-1aa933854603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858779425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1858779425
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3773064475
Short name T19
Test name
Test status
Simulation time 11606680 ps
CPU time 0.41 seconds
Started Jul 04 04:48:03 PM PDT 24
Finished Jul 04 04:48:04 PM PDT 24
Peak memory 145628 kb
Host smart-00ceeaaa-a956-4f24-9d0b-ccba3e961598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773064475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3773064475
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.602165582
Short name T9
Test name
Test status
Simulation time 11769908 ps
CPU time 0.38 seconds
Started Jul 04 04:48:06 PM PDT 24
Finished Jul 04 04:48:06 PM PDT 24
Peak memory 145636 kb
Host smart-d8fd6fb6-e8b5-4d91-892b-40eea0ee35c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602165582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.602165582
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3646966474
Short name T20
Test name
Test status
Simulation time 10413991 ps
CPU time 0.39 seconds
Started Jul 04 04:48:10 PM PDT 24
Finished Jul 04 04:48:11 PM PDT 24
Peak memory 145668 kb
Host smart-204fce58-341e-481a-bc60-5220642b8b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646966474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3646966474
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2006772486
Short name T54
Test name
Test status
Simulation time 32058050 ps
CPU time 0.4 seconds
Started Jul 04 04:48:19 PM PDT 24
Finished Jul 04 04:48:20 PM PDT 24
Peak memory 145188 kb
Host smart-240f3f93-2ae7-4d33-98b2-0d70f7df7721
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2006772486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2006772486
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2029620600
Short name T57
Test name
Test status
Simulation time 31459425 ps
CPU time 0.4 seconds
Started Jul 04 04:48:12 PM PDT 24
Finished Jul 04 04:48:13 PM PDT 24
Peak memory 145192 kb
Host smart-d504ca61-af20-47f0-8d2c-eac860e805e7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2029620600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2029620600
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3237720149
Short name T52
Test name
Test status
Simulation time 29686608 ps
CPU time 0.4 seconds
Started Jul 04 04:48:19 PM PDT 24
Finished Jul 04 04:48:20 PM PDT 24
Peak memory 145164 kb
Host smart-eab020ed-bb50-45ab-ae71-bfc3d4390a5e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3237720149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3237720149
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1884681005
Short name T5
Test name
Test status
Simulation time 29269734 ps
CPU time 0.38 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:14 PM PDT 24
Peak memory 145208 kb
Host smart-777a9788-af50-499b-86ec-d154ec0faa97
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1884681005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1884681005
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3590960052
Short name T6
Test name
Test status
Simulation time 29803486 ps
CPU time 0.39 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 145180 kb
Host smart-691041ed-bb5f-4f06-b27c-5b8063e515f4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3590960052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3590960052
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1928984494
Short name T59
Test name
Test status
Simulation time 30760859 ps
CPU time 0.45 seconds
Started Jul 04 04:48:20 PM PDT 24
Finished Jul 04 04:48:21 PM PDT 24
Peak memory 145200 kb
Host smart-49d65047-32a9-44ee-a2fd-4ce59e39a803
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1928984494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1928984494
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3260060151
Short name T51
Test name
Test status
Simulation time 30133895 ps
CPU time 0.41 seconds
Started Jul 04 04:48:23 PM PDT 24
Finished Jul 04 04:48:23 PM PDT 24
Peak memory 145188 kb
Host smart-38cf9434-aff5-4c1c-922e-fe5065bc831c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3260060151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3260060151
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3285282157
Short name T48
Test name
Test status
Simulation time 29409824 ps
CPU time 0.38 seconds
Started Jul 04 04:48:17 PM PDT 24
Finished Jul 04 04:48:19 PM PDT 24
Peak memory 145196 kb
Host smart-ff08f5b8-47ca-449a-afc3-b55adb65f425
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3285282157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3285282157
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3548930973
Short name T58
Test name
Test status
Simulation time 29756745 ps
CPU time 0.42 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 145196 kb
Host smart-77e7f9b7-3592-4bcd-9ae3-d75b47707f68
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3548930973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3548930973
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1720459824
Short name T44
Test name
Test status
Simulation time 29520488 ps
CPU time 0.4 seconds
Started Jul 04 04:48:25 PM PDT 24
Finished Jul 04 04:48:25 PM PDT 24
Peak memory 145212 kb
Host smart-429bf267-a196-4d80-912f-d93a7f28420a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1720459824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1720459824
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4237603475
Short name T46
Test name
Test status
Simulation time 28648522 ps
CPU time 0.39 seconds
Started Jul 04 04:48:19 PM PDT 24
Finished Jul 04 04:48:20 PM PDT 24
Peak memory 145204 kb
Host smart-cf36230f-f732-4493-8994-476e193e45a1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4237603475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4237603475
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4097534195
Short name T47
Test name
Test status
Simulation time 30649651 ps
CPU time 0.39 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:14 PM PDT 24
Peak memory 145236 kb
Host smart-98e5665f-de1e-484d-8575-47c83ad8f151
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4097534195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.4097534195
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2465693524
Short name T53
Test name
Test status
Simulation time 30144238 ps
CPU time 0.45 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:14 PM PDT 24
Peak memory 145200 kb
Host smart-2bd020ff-6329-455c-a3bc-afae5b0a0f02
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2465693524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2465693524
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1947519152
Short name T56
Test name
Test status
Simulation time 30640992 ps
CPU time 0.42 seconds
Started Jul 04 04:48:20 PM PDT 24
Finished Jul 04 04:48:21 PM PDT 24
Peak memory 145200 kb
Host smart-71f4700b-4ce5-4417-9885-42150313e6e1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1947519152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1947519152
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.171564353
Short name T55
Test name
Test status
Simulation time 30405194 ps
CPU time 0.41 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:48:17 PM PDT 24
Peak memory 145200 kb
Host smart-a0c92be2-104a-420f-91fd-4afc9354094a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=171564353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.171564353
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1316739724
Short name T25
Test name
Test status
Simulation time 31574933 ps
CPU time 0.4 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 145200 kb
Host smart-f347cc8b-c7ed-4ca4-95c8-d51ad9a71a73
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1316739724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1316739724
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1968587669
Short name T45
Test name
Test status
Simulation time 30413366 ps
CPU time 0.43 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:48:16 PM PDT 24
Peak memory 145188 kb
Host smart-af07de09-1ee6-4b05-b7a2-fdf92f6afb1c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1968587669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1968587669
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3942893289
Short name T18
Test name
Test status
Simulation time 30536554 ps
CPU time 0.4 seconds
Started Jul 04 04:48:10 PM PDT 24
Finished Jul 04 04:48:10 PM PDT 24
Peak memory 145200 kb
Host smart-1fe3b910-5633-4302-8df0-623cc6875194
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3942893289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3942893289
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1581794599
Short name T36
Test name
Test status
Simulation time 8488316 ps
CPU time 0.38 seconds
Started Jul 04 04:18:46 PM PDT 24
Finished Jul 04 04:18:47 PM PDT 24
Peak memory 144784 kb
Host smart-bd9034f7-574e-4372-a605-43b317fa836b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1581794599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1581794599
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3930995246
Short name T28
Test name
Test status
Simulation time 8550932 ps
CPU time 0.4 seconds
Started Jul 04 04:18:47 PM PDT 24
Finished Jul 04 04:18:48 PM PDT 24
Peak memory 144876 kb
Host smart-c1a3e23c-cc3a-42d3-9911-e7b1f1c243e2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3930995246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3930995246
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.4190935013
Short name T62
Test name
Test status
Simulation time 9584620 ps
CPU time 0.38 seconds
Started Jul 04 04:18:48 PM PDT 24
Finished Jul 04 04:18:49 PM PDT 24
Peak memory 144948 kb
Host smart-7cc13caa-57cb-4b6f-8cbe-d769a4253cd7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4190935013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.4190935013
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.4029761204
Short name T60
Test name
Test status
Simulation time 9516838 ps
CPU time 0.38 seconds
Started Jul 04 04:18:49 PM PDT 24
Finished Jul 04 04:18:50 PM PDT 24
Peak memory 145060 kb
Host smart-6a9dac6c-8709-484d-aa78-987c07fe99e7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4029761204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.4029761204
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.973688951
Short name T38
Test name
Test status
Simulation time 10862729 ps
CPU time 0.41 seconds
Started Jul 04 04:18:48 PM PDT 24
Finished Jul 04 04:18:49 PM PDT 24
Peak memory 145172 kb
Host smart-32c13a00-332d-4332-9e9d-372261d5844a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=973688951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.973688951
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2041710804
Short name T12
Test name
Test status
Simulation time 10253572 ps
CPU time 0.39 seconds
Started Jul 04 04:18:48 PM PDT 24
Finished Jul 04 04:18:49 PM PDT 24
Peak memory 145356 kb
Host smart-4830b8c3-29b0-4e62-beee-2ad60f54f0e0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2041710804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2041710804
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3692223706
Short name T26
Test name
Test status
Simulation time 8128963 ps
CPU time 0.38 seconds
Started Jul 04 04:18:48 PM PDT 24
Finished Jul 04 04:18:49 PM PDT 24
Peak memory 144924 kb
Host smart-7f48c2de-f5e8-4829-adc2-27a6e32c0a37
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3692223706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3692223706
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3062268780
Short name T29
Test name
Test status
Simulation time 9839274 ps
CPU time 0.4 seconds
Started Jul 04 04:18:47 PM PDT 24
Finished Jul 04 04:18:48 PM PDT 24
Peak memory 143968 kb
Host smart-a062f781-40a8-47f9-8196-45fc8247a806
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3062268780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3062268780
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2536792924
Short name T27
Test name
Test status
Simulation time 8856820 ps
CPU time 0.4 seconds
Started Jul 04 04:19:22 PM PDT 24
Finished Jul 04 04:19:23 PM PDT 24
Peak memory 145344 kb
Host smart-4ef8a043-adef-4ce8-aa9a-d796a3e5fb03
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2536792924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2536792924
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.508613789
Short name T39
Test name
Test status
Simulation time 8997857 ps
CPU time 0.4 seconds
Started Jul 04 04:19:22 PM PDT 24
Finished Jul 04 04:19:23 PM PDT 24
Peak memory 145352 kb
Host smart-885f3858-ed9f-4762-899e-842097edb2b4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=508613789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.508613789
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1880546643
Short name T40
Test name
Test status
Simulation time 8591129 ps
CPU time 0.38 seconds
Started Jul 04 04:18:49 PM PDT 24
Finished Jul 04 04:18:50 PM PDT 24
Peak memory 145028 kb
Host smart-afab6f13-94df-40fc-bd08-4716960e8ff8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1880546643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1880546643
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.211310030
Short name T37
Test name
Test status
Simulation time 9138806 ps
CPU time 0.41 seconds
Started Jul 04 04:18:48 PM PDT 24
Finished Jul 04 04:18:49 PM PDT 24
Peak memory 145036 kb
Host smart-531fce9d-bc30-4809-9898-95e07519c0a2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=211310030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.211310030
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.86979850
Short name T42
Test name
Test status
Simulation time 9664954 ps
CPU time 0.37 seconds
Started Jul 04 04:18:48 PM PDT 24
Finished Jul 04 04:18:49 PM PDT 24
Peak memory 145036 kb
Host smart-9f8b9747-c318-4c64-8249-9f1be3586061
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=86979850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.86979850
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1053571263
Short name T65
Test name
Test status
Simulation time 9412709 ps
CPU time 0.39 seconds
Started Jul 04 04:18:48 PM PDT 24
Finished Jul 04 04:18:49 PM PDT 24
Peak memory 145028 kb
Host smart-5028f5eb-b2bf-4484-b3fb-ade06c21f65e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1053571263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1053571263
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3076878953
Short name T64
Test name
Test status
Simulation time 8663216 ps
CPU time 0.37 seconds
Started Jul 04 04:18:48 PM PDT 24
Finished Jul 04 04:18:49 PM PDT 24
Peak memory 145016 kb
Host smart-e54e0971-cbc9-4cd8-ae58-80db6570e162
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3076878953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3076878953
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1645758465
Short name T63
Test name
Test status
Simulation time 8371020 ps
CPU time 0.39 seconds
Started Jul 04 04:18:47 PM PDT 24
Finished Jul 04 04:18:48 PM PDT 24
Peak memory 146068 kb
Host smart-c423cdf5-450e-4e38-b0c5-9d3f7994abbd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1645758465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1645758465
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1467466955
Short name T61
Test name
Test status
Simulation time 10280149 ps
CPU time 0.42 seconds
Started Jul 04 04:18:47 PM PDT 24
Finished Jul 04 04:18:48 PM PDT 24
Peak memory 144908 kb
Host smart-a680d539-b61e-4726-8d43-5522f85bd037
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1467466955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1467466955
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3534261597
Short name T41
Test name
Test status
Simulation time 9133509 ps
CPU time 0.37 seconds
Started Jul 04 04:18:47 PM PDT 24
Finished Jul 04 04:18:48 PM PDT 24
Peak memory 145908 kb
Host smart-7e6c1b96-3a5d-4c0e-afe2-89bdfa77356f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3534261597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3534261597
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3169702027
Short name T32
Test name
Test status
Simulation time 27384674 ps
CPU time 0.38 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:48:17 PM PDT 24
Peak memory 145228 kb
Host smart-68a4b69e-8c8a-42a7-87fa-e4214a78274e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3169702027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3169702027
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2947259023
Short name T76
Test name
Test status
Simulation time 25819496 ps
CPU time 0.43 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:14 PM PDT 24
Peak memory 145480 kb
Host smart-63792e11-f24c-4c0c-ad52-2b9e09377310
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2947259023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2947259023
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1994107225
Short name T68
Test name
Test status
Simulation time 29604503 ps
CPU time 0.4 seconds
Started Jul 04 04:48:19 PM PDT 24
Finished Jul 04 04:48:19 PM PDT 24
Peak memory 145488 kb
Host smart-42cf5844-af47-43fd-a085-c7da1c5ef518
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1994107225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1994107225
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3049192906
Short name T70
Test name
Test status
Simulation time 28476278 ps
CPU time 0.39 seconds
Started Jul 04 04:48:21 PM PDT 24
Finished Jul 04 04:48:22 PM PDT 24
Peak memory 145468 kb
Host smart-5ede3a63-177f-46bd-bac7-7717501af965
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3049192906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3049192906
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2350286927
Short name T35
Test name
Test status
Simulation time 28293093 ps
CPU time 0.41 seconds
Started Jul 04 04:48:22 PM PDT 24
Finished Jul 04 04:48:23 PM PDT 24
Peak memory 145472 kb
Host smart-ba5ed362-83fb-40de-98a9-465c9d303212
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2350286927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2350286927
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3045365268
Short name T78
Test name
Test status
Simulation time 27311167 ps
CPU time 0.42 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:14 PM PDT 24
Peak memory 145504 kb
Host smart-168e9109-a5a2-4a8d-a116-d0f0027395e2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3045365268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3045365268
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3994441326
Short name T77
Test name
Test status
Simulation time 28279111 ps
CPU time 0.4 seconds
Started Jul 04 04:48:23 PM PDT 24
Finished Jul 04 04:48:23 PM PDT 24
Peak memory 144804 kb
Host smart-f7e01508-dd30-40c7-8a50-2dc394b6e58e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3994441326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3994441326
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3685542895
Short name T71
Test name
Test status
Simulation time 27417984 ps
CPU time 0.4 seconds
Started Jul 04 04:48:18 PM PDT 24
Finished Jul 04 04:48:19 PM PDT 24
Peak memory 145484 kb
Host smart-59d444ea-eadd-4436-a3b7-39051f17a738
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3685542895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3685542895
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2677825867
Short name T67
Test name
Test status
Simulation time 27170189 ps
CPU time 0.44 seconds
Started Jul 04 04:48:18 PM PDT 24
Finished Jul 04 04:48:19 PM PDT 24
Peak memory 145440 kb
Host smart-b868743a-79e6-40a5-92f6-fd6c14cde3fc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2677825867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2677825867
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.613224577
Short name T69
Test name
Test status
Simulation time 26750043 ps
CPU time 0.4 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 145480 kb
Host smart-9e2fc23e-517b-4aa2-b40b-531b9d3ac8c3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=613224577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.613224577
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1230895460
Short name T31
Test name
Test status
Simulation time 27657469 ps
CPU time 0.39 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:48:16 PM PDT 24
Peak memory 145488 kb
Host smart-16cf74c9-81ce-46b0-b11a-fafaed624336
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1230895460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1230895460
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2643171634
Short name T73
Test name
Test status
Simulation time 25012977 ps
CPU time 0.39 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 145476 kb
Host smart-afa8bd02-c4ef-4605-9f50-4befe50bbfe6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2643171634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2643171634
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3348267692
Short name T13
Test name
Test status
Simulation time 26396086 ps
CPU time 0.4 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 145488 kb
Host smart-bfe90314-f347-4e23-ab59-302c454f46d4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3348267692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3348267692
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3993762886
Short name T33
Test name
Test status
Simulation time 27407343 ps
CPU time 0.4 seconds
Started Jul 04 04:48:21 PM PDT 24
Finished Jul 04 04:48:22 PM PDT 24
Peak memory 145452 kb
Host smart-ca6803c4-fa5f-470c-8675-758acc14d2fc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3993762886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3993762886
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1887858803
Short name T72
Test name
Test status
Simulation time 28770284 ps
CPU time 0.4 seconds
Started Jul 04 04:48:23 PM PDT 24
Finished Jul 04 04:48:23 PM PDT 24
Peak memory 144732 kb
Host smart-f6249f55-c95d-4794-87c7-a4c2306f0e22
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1887858803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1887858803
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1109168069
Short name T74
Test name
Test status
Simulation time 25079273 ps
CPU time 0.39 seconds
Started Jul 04 04:48:21 PM PDT 24
Finished Jul 04 04:48:21 PM PDT 24
Peak memory 145484 kb
Host smart-4221ccd5-8ec6-4724-9bd7-3728b1fe2daa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1109168069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1109168069
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.963741019
Short name T34
Test name
Test status
Simulation time 26281195 ps
CPU time 0.4 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:48:17 PM PDT 24
Peak memory 145484 kb
Host smart-f7ae099c-2add-499a-9635-0a493851fbb6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=963741019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.963741019
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3601748158
Short name T30
Test name
Test status
Simulation time 27513469 ps
CPU time 0.38 seconds
Started Jul 04 04:48:22 PM PDT 24
Finished Jul 04 04:48:23 PM PDT 24
Peak memory 145492 kb
Host smart-c379b4bb-bf73-4194-86c2-32ce939af971
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3601748158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3601748158
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1590203721
Short name T66
Test name
Test status
Simulation time 27641898 ps
CPU time 0.39 seconds
Started Jul 04 04:48:22 PM PDT 24
Finished Jul 04 04:48:23 PM PDT 24
Peak memory 145488 kb
Host smart-bd58ae3e-8bc7-4f9f-b36b-338d273bd018
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1590203721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1590203721
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2488137438
Short name T75
Test name
Test status
Simulation time 26632786 ps
CPU time 0.39 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 145468 kb
Host smart-4bad19c9-4e35-43ac-ae74-bf079efa25e1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2488137438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2488137438
Directory /workspace/9.prim_sync_fatal_alert/latest
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