Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.88 88.88 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/0.prim_async_alert.161935042
91.41 2.53 100.00 0.00 93.75 0.00 100.00 0.00 82.14 3.57 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/12.prim_sync_alert.3474686191
93.17 1.76 100.00 0.00 93.75 0.00 100.00 0.00 85.71 3.57 95.83 0.00 83.72 6.98 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2510963374
94.11 0.94 100.00 0.00 95.83 2.08 100.00 0.00 89.29 3.57 95.83 0.00 83.72 0.00 /workspace/coverage/sync_alert/3.prim_sync_alert.2415269558
94.50 0.39 100.00 0.00 95.83 0.00 100.00 0.00 89.29 0.00 95.83 0.00 86.05 2.33 /workspace/coverage/default/10.prim_async_alert.779622454
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3725168230
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/15.prim_sync_alert.25328652

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.3964137084
/workspace/coverage/default/11.prim_async_alert.668706274
/workspace/coverage/default/12.prim_async_alert.4083574266
/workspace/coverage/default/13.prim_async_alert.912069469
/workspace/coverage/default/14.prim_async_alert.670790980
/workspace/coverage/default/15.prim_async_alert.3139741080
/workspace/coverage/default/16.prim_async_alert.2685092525
/workspace/coverage/default/17.prim_async_alert.1329527559
/workspace/coverage/default/18.prim_async_alert.864106863
/workspace/coverage/default/19.prim_async_alert.1691424174
/workspace/coverage/default/2.prim_async_alert.460680160
/workspace/coverage/default/3.prim_async_alert.1062444755
/workspace/coverage/default/4.prim_async_alert.3199656261
/workspace/coverage/default/5.prim_async_alert.2799043916
/workspace/coverage/default/6.prim_async_alert.2323960889
/workspace/coverage/default/7.prim_async_alert.3620131081
/workspace/coverage/default/8.prim_async_alert.4089192686
/workspace/coverage/default/9.prim_async_alert.2325093510
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3245651275
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3575120459
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.289076519
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2395726053
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3925326850
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2608085678
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1641479384
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.82615158
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3852504376
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.131752113
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1308234483
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3308517918
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2495240529
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.216734170
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1999073722
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3242049740
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.52087580
/workspace/coverage/sync_alert/0.prim_sync_alert.3426435340
/workspace/coverage/sync_alert/1.prim_sync_alert.2489203096
/workspace/coverage/sync_alert/10.prim_sync_alert.868440121
/workspace/coverage/sync_alert/11.prim_sync_alert.3731981683
/workspace/coverage/sync_alert/13.prim_sync_alert.2850899192
/workspace/coverage/sync_alert/14.prim_sync_alert.2639075704
/workspace/coverage/sync_alert/16.prim_sync_alert.964233485
/workspace/coverage/sync_alert/17.prim_sync_alert.3847648468
/workspace/coverage/sync_alert/18.prim_sync_alert.1854122645
/workspace/coverage/sync_alert/19.prim_sync_alert.3391703079
/workspace/coverage/sync_alert/2.prim_sync_alert.3719225603
/workspace/coverage/sync_alert/4.prim_sync_alert.3998275872
/workspace/coverage/sync_alert/5.prim_sync_alert.477240275
/workspace/coverage/sync_alert/6.prim_sync_alert.148327614
/workspace/coverage/sync_alert/7.prim_sync_alert.3064976198
/workspace/coverage/sync_alert/8.prim_sync_alert.2353208536
/workspace/coverage/sync_alert/9.prim_sync_alert.80538639
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4184775717
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.807788353
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.620867169
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1705017061
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.574965385
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3426595342
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2465265667
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3841538377
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2273620592
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.384657377
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2936816033
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3897381694
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1447736313
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1986379581
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.43234653
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.641815317
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.893917239
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.360701789
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3767281826
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3710519661



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/7.prim_async_alert.3620131081 Jul 05 04:22:50 PM PDT 24 Jul 05 04:22:51 PM PDT 24 11346595 ps
T2 /workspace/coverage/default/12.prim_async_alert.4083574266 Jul 05 04:22:06 PM PDT 24 Jul 05 04:22:07 PM PDT 24 11191016 ps
T3 /workspace/coverage/default/9.prim_async_alert.2325093510 Jul 05 04:17:29 PM PDT 24 Jul 05 04:17:30 PM PDT 24 10924588 ps
T13 /workspace/coverage/default/19.prim_async_alert.1691424174 Jul 05 04:22:56 PM PDT 24 Jul 05 04:22:58 PM PDT 24 11390582 ps
T15 /workspace/coverage/default/3.prim_async_alert.1062444755 Jul 05 04:18:00 PM PDT 24 Jul 05 04:18:01 PM PDT 24 11053209 ps
T8 /workspace/coverage/default/17.prim_async_alert.1329527559 Jul 05 04:17:35 PM PDT 24 Jul 05 04:17:37 PM PDT 24 11753837 ps
T7 /workspace/coverage/default/0.prim_async_alert.161935042 Jul 05 04:17:29 PM PDT 24 Jul 05 04:17:30 PM PDT 24 11768160 ps
T20 /workspace/coverage/default/16.prim_async_alert.2685092525 Jul 05 04:22:56 PM PDT 24 Jul 05 04:22:57 PM PDT 24 11249022 ps
T21 /workspace/coverage/default/11.prim_async_alert.668706274 Jul 05 04:17:32 PM PDT 24 Jul 05 04:17:32 PM PDT 24 11170171 ps
T14 /workspace/coverage/default/10.prim_async_alert.779622454 Jul 05 04:17:35 PM PDT 24 Jul 05 04:17:36 PM PDT 24 12711224 ps
T22 /workspace/coverage/default/6.prim_async_alert.2323960889 Jul 05 04:17:35 PM PDT 24 Jul 05 04:17:37 PM PDT 24 11790542 ps
T9 /workspace/coverage/default/8.prim_async_alert.4089192686 Jul 05 04:20:00 PM PDT 24 Jul 05 04:20:01 PM PDT 24 11452412 ps
T10 /workspace/coverage/default/1.prim_async_alert.3964137084 Jul 05 04:17:39 PM PDT 24 Jul 05 04:17:40 PM PDT 24 10756278 ps
T16 /workspace/coverage/default/5.prim_async_alert.2799043916 Jul 05 04:17:30 PM PDT 24 Jul 05 04:17:31 PM PDT 24 11195713 ps
T18 /workspace/coverage/default/15.prim_async_alert.3139741080 Jul 05 04:17:50 PM PDT 24 Jul 05 04:17:51 PM PDT 24 11872651 ps
T47 /workspace/coverage/default/13.prim_async_alert.912069469 Jul 05 04:17:35 PM PDT 24 Jul 05 04:17:36 PM PDT 24 11548377 ps
T19 /workspace/coverage/default/2.prim_async_alert.460680160 Jul 05 04:18:49 PM PDT 24 Jul 05 04:18:50 PM PDT 24 11072846 ps
T23 /workspace/coverage/default/14.prim_async_alert.670790980 Jul 05 04:22:56 PM PDT 24 Jul 05 04:22:58 PM PDT 24 10891738 ps
T48 /workspace/coverage/default/4.prim_async_alert.3199656261 Jul 05 04:22:56 PM PDT 24 Jul 05 04:22:58 PM PDT 24 11649966 ps
T49 /workspace/coverage/default/18.prim_async_alert.864106863 Jul 05 04:22:20 PM PDT 24 Jul 05 04:22:21 PM PDT 24 11177290 ps
T4 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.216734170 Jul 05 04:17:35 PM PDT 24 Jul 05 04:17:37 PM PDT 24 30560535 ps
T40 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3852504376 Jul 05 04:22:46 PM PDT 24 Jul 05 04:22:46 PM PDT 24 31132703 ps
T5 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3725168230 Jul 05 04:23:19 PM PDT 24 Jul 05 04:23:20 PM PDT 24 28871499 ps
T41 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3308517918 Jul 05 04:17:35 PM PDT 24 Jul 05 04:17:37 PM PDT 24 28126214 ps
T42 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2495240529 Jul 05 04:17:36 PM PDT 24 Jul 05 04:17:37 PM PDT 24 28836788 ps
T43 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3575120459 Jul 05 04:17:35 PM PDT 24 Jul 05 04:17:36 PM PDT 24 32067222 ps
T44 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.82615158 Jul 05 04:17:38 PM PDT 24 Jul 05 04:17:38 PM PDT 24 30174184 ps
T45 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2395726053 Jul 05 04:22:56 PM PDT 24 Jul 05 04:22:58 PM PDT 24 30644894 ps
T46 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2608085678 Jul 05 04:22:56 PM PDT 24 Jul 05 04:22:58 PM PDT 24 30890358 ps
T17 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2510963374 Jul 05 04:22:32 PM PDT 24 Jul 05 04:22:33 PM PDT 24 30146804 ps
T39 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.289076519 Jul 05 04:17:21 PM PDT 24 Jul 05 04:17:22 PM PDT 24 29987155 ps
T50 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1999073722 Jul 05 04:17:30 PM PDT 24 Jul 05 04:17:31 PM PDT 24 28393443 ps
T51 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3245651275 Jul 05 04:17:35 PM PDT 24 Jul 05 04:17:37 PM PDT 24 28361944 ps
T52 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1308234483 Jul 05 04:17:26 PM PDT 24 Jul 05 04:17:28 PM PDT 24 30182045 ps
T53 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3242049740 Jul 05 04:17:35 PM PDT 24 Jul 05 04:17:36 PM PDT 24 29286523 ps
T54 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1641479384 Jul 05 04:22:06 PM PDT 24 Jul 05 04:22:07 PM PDT 24 29124125 ps
T55 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.52087580 Jul 05 04:18:28 PM PDT 24 Jul 05 04:18:29 PM PDT 24 30133442 ps
T56 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3925326850 Jul 05 04:17:23 PM PDT 24 Jul 05 04:17:23 PM PDT 24 31890329 ps
T57 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.131752113 Jul 05 04:22:45 PM PDT 24 Jul 05 04:22:46 PM PDT 24 30829792 ps
T24 /workspace/coverage/sync_alert/17.prim_sync_alert.3847648468 Jul 05 04:18:44 PM PDT 24 Jul 05 04:18:45 PM PDT 24 9836768 ps
T25 /workspace/coverage/sync_alert/16.prim_sync_alert.964233485 Jul 05 04:22:55 PM PDT 24 Jul 05 04:22:57 PM PDT 24 9124099 ps
T34 /workspace/coverage/sync_alert/14.prim_sync_alert.2639075704 Jul 05 04:22:32 PM PDT 24 Jul 05 04:22:33 PM PDT 24 8536257 ps
T26 /workspace/coverage/sync_alert/4.prim_sync_alert.3998275872 Jul 05 04:17:29 PM PDT 24 Jul 05 04:17:30 PM PDT 24 8837091 ps
T27 /workspace/coverage/sync_alert/9.prim_sync_alert.80538639 Jul 05 04:22:44 PM PDT 24 Jul 05 04:22:45 PM PDT 24 10581299 ps
T35 /workspace/coverage/sync_alert/5.prim_sync_alert.477240275 Jul 05 04:17:20 PM PDT 24 Jul 05 04:17:20 PM PDT 24 10088340 ps
T36 /workspace/coverage/sync_alert/12.prim_sync_alert.3474686191 Jul 05 04:22:05 PM PDT 24 Jul 05 04:22:06 PM PDT 24 9005336 ps
T28 /workspace/coverage/sync_alert/13.prim_sync_alert.2850899192 Jul 05 04:17:28 PM PDT 24 Jul 05 04:17:30 PM PDT 24 8995318 ps
T37 /workspace/coverage/sync_alert/10.prim_sync_alert.868440121 Jul 05 04:17:38 PM PDT 24 Jul 05 04:17:38 PM PDT 24 8888153 ps
T38 /workspace/coverage/sync_alert/2.prim_sync_alert.3719225603 Jul 05 04:20:54 PM PDT 24 Jul 05 04:20:55 PM PDT 24 8881778 ps
T29 /workspace/coverage/sync_alert/7.prim_sync_alert.3064976198 Jul 05 04:19:22 PM PDT 24 Jul 05 04:19:23 PM PDT 24 8397319 ps
T30 /workspace/coverage/sync_alert/3.prim_sync_alert.2415269558 Jul 05 04:18:17 PM PDT 24 Jul 05 04:18:18 PM PDT 24 9667482 ps
T31 /workspace/coverage/sync_alert/6.prim_sync_alert.148327614 Jul 05 04:17:38 PM PDT 24 Jul 05 04:17:38 PM PDT 24 9065090 ps
T32 /workspace/coverage/sync_alert/19.prim_sync_alert.3391703079 Jul 05 04:17:36 PM PDT 24 Jul 05 04:17:37 PM PDT 24 9933181 ps
T58 /workspace/coverage/sync_alert/8.prim_sync_alert.2353208536 Jul 05 04:22:32 PM PDT 24 Jul 05 04:22:33 PM PDT 24 9564286 ps
T33 /workspace/coverage/sync_alert/18.prim_sync_alert.1854122645 Jul 05 04:22:49 PM PDT 24 Jul 05 04:22:50 PM PDT 24 9499655 ps
T59 /workspace/coverage/sync_alert/1.prim_sync_alert.2489203096 Jul 05 04:20:19 PM PDT 24 Jul 05 04:20:22 PM PDT 24 8511124 ps
T60 /workspace/coverage/sync_alert/11.prim_sync_alert.3731981683 Jul 05 04:22:39 PM PDT 24 Jul 05 04:22:41 PM PDT 24 9857948 ps
T61 /workspace/coverage/sync_alert/0.prim_sync_alert.3426435340 Jul 05 04:22:49 PM PDT 24 Jul 05 04:22:51 PM PDT 24 8417592 ps
T11 /workspace/coverage/sync_alert/15.prim_sync_alert.25328652 Jul 05 04:20:20 PM PDT 24 Jul 05 04:20:22 PM PDT 24 9254833 ps
T62 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2273620592 Jul 05 04:20:05 PM PDT 24 Jul 05 04:20:07 PM PDT 24 29272492 ps
T63 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2936816033 Jul 05 04:20:05 PM PDT 24 Jul 05 04:20:07 PM PDT 24 27890976 ps
T64 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1986379581 Jul 05 04:22:54 PM PDT 24 Jul 05 04:22:55 PM PDT 24 25468673 ps
T65 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3841538377 Jul 05 04:20:05 PM PDT 24 Jul 05 04:20:07 PM PDT 24 29501697 ps
T66 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.43234653 Jul 05 04:22:39 PM PDT 24 Jul 05 04:22:41 PM PDT 24 26728780 ps
T67 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4184775717 Jul 05 04:17:36 PM PDT 24 Jul 05 04:17:37 PM PDT 24 26873748 ps
T68 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.384657377 Jul 05 04:22:39 PM PDT 24 Jul 05 04:22:40 PM PDT 24 26117835 ps
T6 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1705017061 Jul 05 04:20:18 PM PDT 24 Jul 05 04:20:21 PM PDT 24 28850331 ps
T69 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1447736313 Jul 05 04:18:42 PM PDT 24 Jul 05 04:18:44 PM PDT 24 26768601 ps
T70 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3897381694 Jul 05 04:22:39 PM PDT 24 Jul 05 04:22:40 PM PDT 24 27101405 ps
T71 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.893917239 Jul 05 04:22:54 PM PDT 24 Jul 05 04:22:55 PM PDT 24 28303806 ps
T72 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.360701789 Jul 05 04:23:04 PM PDT 24 Jul 05 04:23:05 PM PDT 24 25690891 ps
T73 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3426595342 Jul 05 04:20:18 PM PDT 24 Jul 05 04:20:21 PM PDT 24 28947863 ps
T74 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.641815317 Jul 05 04:18:28 PM PDT 24 Jul 05 04:18:29 PM PDT 24 26952588 ps
T75 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.807788353 Jul 05 04:18:37 PM PDT 24 Jul 05 04:18:38 PM PDT 24 27852920 ps
T12 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.620867169 Jul 05 04:19:28 PM PDT 24 Jul 05 04:19:29 PM PDT 24 26673000 ps
T76 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.574965385 Jul 05 04:22:54 PM PDT 24 Jul 05 04:22:56 PM PDT 24 25474645 ps
T77 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3710519661 Jul 05 04:18:00 PM PDT 24 Jul 05 04:18:01 PM PDT 24 28543559 ps
T78 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3767281826 Jul 05 04:22:56 PM PDT 24 Jul 05 04:22:58 PM PDT 24 26564803 ps
T79 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2465265667 Jul 05 04:19:30 PM PDT 24 Jul 05 04:19:31 PM PDT 24 29716177 ps

Test location /workspace/coverage/default/0.prim_async_alert.161935042
Short name T7
Test name
Test status
Simulation time 11768160 ps
CPU time 0.44 seconds
Started Jul 05 04:17:29 PM PDT 24
Finished Jul 05 04:17:30 PM PDT 24
Peak memory 145436 kb
Host smart-3912e392-a80d-4835-8310-6585bb45d167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161935042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.161935042
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3474686191
Short name T36
Test name
Test status
Simulation time 9005336 ps
CPU time 0.43 seconds
Started Jul 05 04:22:05 PM PDT 24
Finished Jul 05 04:22:06 PM PDT 24
Peak memory 145860 kb
Host smart-e5aec20e-bb84-4449-a0e5-eaf5ae053dc3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3474686191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3474686191
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2510963374
Short name T17
Test name
Test status
Simulation time 30146804 ps
CPU time 0.42 seconds
Started Jul 05 04:22:32 PM PDT 24
Finished Jul 05 04:22:33 PM PDT 24
Peak memory 144648 kb
Host smart-dbedb4e1-4dab-4ce2-a6e0-43da2873ddb7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2510963374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2510963374
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2415269558
Short name T30
Test name
Test status
Simulation time 9667482 ps
CPU time 0.4 seconds
Started Jul 05 04:18:17 PM PDT 24
Finished Jul 05 04:18:18 PM PDT 24
Peak memory 145544 kb
Host smart-dd5986df-8f0a-46b1-973b-ae4f24152846
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2415269558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2415269558
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.779622454
Short name T14
Test name
Test status
Simulation time 12711224 ps
CPU time 0.38 seconds
Started Jul 05 04:17:35 PM PDT 24
Finished Jul 05 04:17:36 PM PDT 24
Peak memory 145688 kb
Host smart-a9d1ea42-87e2-4e71-9887-55011551e675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779622454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.779622454
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3725168230
Short name T5
Test name
Test status
Simulation time 28871499 ps
CPU time 0.41 seconds
Started Jul 05 04:23:19 PM PDT 24
Finished Jul 05 04:23:20 PM PDT 24
Peak memory 144980 kb
Host smart-49719f5c-9878-4a99-ad3a-06dac4c4bde1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3725168230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3725168230
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.25328652
Short name T11
Test name
Test status
Simulation time 9254833 ps
CPU time 0.41 seconds
Started Jul 05 04:20:20 PM PDT 24
Finished Jul 05 04:20:22 PM PDT 24
Peak memory 145172 kb
Host smart-ed9cb658-d375-4184-a633-560294fdee68
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=25328652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.25328652
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3964137084
Short name T10
Test name
Test status
Simulation time 10756278 ps
CPU time 0.5 seconds
Started Jul 05 04:17:39 PM PDT 24
Finished Jul 05 04:17:40 PM PDT 24
Peak memory 145116 kb
Host smart-389756db-5f33-473b-8083-daf097dc0970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964137084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3964137084
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.668706274
Short name T21
Test name
Test status
Simulation time 11170171 ps
CPU time 0.41 seconds
Started Jul 05 04:17:32 PM PDT 24
Finished Jul 05 04:17:32 PM PDT 24
Peak memory 145436 kb
Host smart-d9408f23-05a7-45b5-99b8-ef8c94fceb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668706274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.668706274
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.4083574266
Short name T2
Test name
Test status
Simulation time 11191016 ps
CPU time 0.37 seconds
Started Jul 05 04:22:06 PM PDT 24
Finished Jul 05 04:22:07 PM PDT 24
Peak memory 145184 kb
Host smart-5460b610-2d59-4bdf-8c9b-db6f198a20ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083574266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.4083574266
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.912069469
Short name T47
Test name
Test status
Simulation time 11548377 ps
CPU time 0.38 seconds
Started Jul 05 04:17:35 PM PDT 24
Finished Jul 05 04:17:36 PM PDT 24
Peak memory 145632 kb
Host smart-5bfc804a-8c70-4e2f-82b3-4790ff7bebe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912069469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.912069469
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.670790980
Short name T23
Test name
Test status
Simulation time 10891738 ps
CPU time 0.4 seconds
Started Jul 05 04:22:56 PM PDT 24
Finished Jul 05 04:22:58 PM PDT 24
Peak memory 145408 kb
Host smart-308fb168-32b1-44a2-81a6-c6cf15cc77b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670790980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.670790980
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.3139741080
Short name T18
Test name
Test status
Simulation time 11872651 ps
CPU time 0.39 seconds
Started Jul 05 04:17:50 PM PDT 24
Finished Jul 05 04:17:51 PM PDT 24
Peak memory 145388 kb
Host smart-580f2031-036c-4f02-96d5-297b738a6c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139741080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3139741080
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2685092525
Short name T20
Test name
Test status
Simulation time 11249022 ps
CPU time 0.37 seconds
Started Jul 05 04:22:56 PM PDT 24
Finished Jul 05 04:22:57 PM PDT 24
Peak memory 145408 kb
Host smart-ee8c2b01-c6c4-4aad-8cb7-1f27f9214b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685092525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2685092525
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1329527559
Short name T8
Test name
Test status
Simulation time 11753837 ps
CPU time 0.5 seconds
Started Jul 05 04:17:35 PM PDT 24
Finished Jul 05 04:17:37 PM PDT 24
Peak memory 144784 kb
Host smart-6bddb126-ea32-4697-bc53-0f9ec687df8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329527559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1329527559
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.864106863
Short name T49
Test name
Test status
Simulation time 11177290 ps
CPU time 0.36 seconds
Started Jul 05 04:22:20 PM PDT 24
Finished Jul 05 04:22:21 PM PDT 24
Peak memory 145448 kb
Host smart-771592f3-a91a-473e-8bae-34d609e059b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864106863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.864106863
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1691424174
Short name T13
Test name
Test status
Simulation time 11390582 ps
CPU time 0.41 seconds
Started Jul 05 04:22:56 PM PDT 24
Finished Jul 05 04:22:58 PM PDT 24
Peak memory 145396 kb
Host smart-ece3a40a-db95-49af-a172-1ff5e1c81182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691424174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1691424174
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.460680160
Short name T19
Test name
Test status
Simulation time 11072846 ps
CPU time 0.42 seconds
Started Jul 05 04:18:49 PM PDT 24
Finished Jul 05 04:18:50 PM PDT 24
Peak memory 145748 kb
Host smart-1fee91ca-20f3-40d4-b8b8-5de3f153d229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460680160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.460680160
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1062444755
Short name T15
Test name
Test status
Simulation time 11053209 ps
CPU time 0.4 seconds
Started Jul 05 04:18:00 PM PDT 24
Finished Jul 05 04:18:01 PM PDT 24
Peak memory 145652 kb
Host smart-ceecff86-e2d9-4884-8703-6d3e4f6fd460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062444755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1062444755
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3199656261
Short name T48
Test name
Test status
Simulation time 11649966 ps
CPU time 0.39 seconds
Started Jul 05 04:22:56 PM PDT 24
Finished Jul 05 04:22:58 PM PDT 24
Peak memory 145340 kb
Host smart-b41bf470-82b2-484b-9365-e459f99bd592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199656261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3199656261
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2799043916
Short name T16
Test name
Test status
Simulation time 11195713 ps
CPU time 0.39 seconds
Started Jul 05 04:17:30 PM PDT 24
Finished Jul 05 04:17:31 PM PDT 24
Peak memory 145720 kb
Host smart-a70a47dc-2935-47eb-9bfc-7aedc0b7c377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799043916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2799043916
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.2323960889
Short name T22
Test name
Test status
Simulation time 11790542 ps
CPU time 0.49 seconds
Started Jul 05 04:17:35 PM PDT 24
Finished Jul 05 04:17:37 PM PDT 24
Peak memory 143604 kb
Host smart-2c9cfa56-34d0-4b4e-bce1-0bd238018819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323960889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2323960889
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3620131081
Short name T1
Test name
Test status
Simulation time 11346595 ps
CPU time 0.37 seconds
Started Jul 05 04:22:50 PM PDT 24
Finished Jul 05 04:22:51 PM PDT 24
Peak memory 145640 kb
Host smart-d842c93d-116b-4ba8-85f0-ccb9a1b7c533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620131081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3620131081
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.4089192686
Short name T9
Test name
Test status
Simulation time 11452412 ps
CPU time 0.43 seconds
Started Jul 05 04:20:00 PM PDT 24
Finished Jul 05 04:20:01 PM PDT 24
Peak memory 145748 kb
Host smart-f1132f14-c0ae-4aaf-8f9e-3d2790e362b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089192686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.4089192686
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2325093510
Short name T3
Test name
Test status
Simulation time 10924588 ps
CPU time 0.41 seconds
Started Jul 05 04:17:29 PM PDT 24
Finished Jul 05 04:17:30 PM PDT 24
Peak memory 145600 kb
Host smart-a8644d58-0a72-4372-97a6-d6130a65a293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325093510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2325093510
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3245651275
Short name T51
Test name
Test status
Simulation time 28361944 ps
CPU time 0.5 seconds
Started Jul 05 04:17:35 PM PDT 24
Finished Jul 05 04:17:37 PM PDT 24
Peak memory 143492 kb
Host smart-e7335a32-944c-46e0-9aa9-5b87d9a35fd3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3245651275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3245651275
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3575120459
Short name T43
Test name
Test status
Simulation time 32067222 ps
CPU time 0.4 seconds
Started Jul 05 04:17:35 PM PDT 24
Finished Jul 05 04:17:36 PM PDT 24
Peak memory 145236 kb
Host smart-23e3609c-3079-4dc8-8e34-8fb44a73ed98
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3575120459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3575120459
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.289076519
Short name T39
Test name
Test status
Simulation time 29987155 ps
CPU time 0.4 seconds
Started Jul 05 04:17:21 PM PDT 24
Finished Jul 05 04:17:22 PM PDT 24
Peak memory 145464 kb
Host smart-b10ef9c5-07af-464b-8775-ad518b1ac905
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=289076519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.289076519
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2395726053
Short name T45
Test name
Test status
Simulation time 30644894 ps
CPU time 0.42 seconds
Started Jul 05 04:22:56 PM PDT 24
Finished Jul 05 04:22:58 PM PDT 24
Peak memory 144940 kb
Host smart-189602d7-bcf9-421d-b73c-4a1a59a1c62b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2395726053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2395726053
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3925326850
Short name T56
Test name
Test status
Simulation time 31890329 ps
CPU time 0.4 seconds
Started Jul 05 04:17:23 PM PDT 24
Finished Jul 05 04:17:23 PM PDT 24
Peak memory 144644 kb
Host smart-6eb00f61-7e3e-4712-b055-c5ecd58d58a4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3925326850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3925326850
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2608085678
Short name T46
Test name
Test status
Simulation time 30890358 ps
CPU time 0.41 seconds
Started Jul 05 04:22:56 PM PDT 24
Finished Jul 05 04:22:58 PM PDT 24
Peak memory 144916 kb
Host smart-0d9fb6c1-95aa-4674-b102-27fbd5a5d220
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2608085678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2608085678
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1641479384
Short name T54
Test name
Test status
Simulation time 29124125 ps
CPU time 0.38 seconds
Started Jul 05 04:22:06 PM PDT 24
Finished Jul 05 04:22:07 PM PDT 24
Peak memory 144740 kb
Host smart-4a6b4ad7-0b45-4e4e-aa97-c86edfce7e90
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1641479384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1641479384
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.82615158
Short name T44
Test name
Test status
Simulation time 30174184 ps
CPU time 0.4 seconds
Started Jul 05 04:17:38 PM PDT 24
Finished Jul 05 04:17:38 PM PDT 24
Peak memory 145228 kb
Host smart-cd288261-266e-4999-9660-3ad824bc5100
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=82615158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.82615158
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3852504376
Short name T40
Test name
Test status
Simulation time 31132703 ps
CPU time 0.4 seconds
Started Jul 05 04:22:46 PM PDT 24
Finished Jul 05 04:22:46 PM PDT 24
Peak memory 144868 kb
Host smart-ab941f1b-dabf-4af4-8111-66bcf8d2e461
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3852504376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3852504376
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.131752113
Short name T57
Test name
Test status
Simulation time 30829792 ps
CPU time 0.38 seconds
Started Jul 05 04:22:45 PM PDT 24
Finished Jul 05 04:22:46 PM PDT 24
Peak memory 144744 kb
Host smart-477e88aa-af4f-45b2-8add-237db5272438
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=131752113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.131752113
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1308234483
Short name T52
Test name
Test status
Simulation time 30182045 ps
CPU time 0.52 seconds
Started Jul 05 04:17:26 PM PDT 24
Finished Jul 05 04:17:28 PM PDT 24
Peak memory 144816 kb
Host smart-4c66535c-5065-415a-8d65-bb00f3cf7b97
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1308234483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1308234483
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3308517918
Short name T41
Test name
Test status
Simulation time 28126214 ps
CPU time 0.5 seconds
Started Jul 05 04:17:35 PM PDT 24
Finished Jul 05 04:17:37 PM PDT 24
Peak memory 143716 kb
Host smart-e381a060-1ecd-4830-aa1a-2182b80f9040
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3308517918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3308517918
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2495240529
Short name T42
Test name
Test status
Simulation time 28836788 ps
CPU time 0.43 seconds
Started Jul 05 04:17:36 PM PDT 24
Finished Jul 05 04:17:37 PM PDT 24
Peak memory 145240 kb
Host smart-110ad96a-6da8-4998-91ca-c8eb2abb37ab
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2495240529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2495240529
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.216734170
Short name T4
Test name
Test status
Simulation time 30560535 ps
CPU time 0.5 seconds
Started Jul 05 04:17:35 PM PDT 24
Finished Jul 05 04:17:37 PM PDT 24
Peak memory 142808 kb
Host smart-6916c2dc-843f-40c1-84fd-b85ce7fef3b7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=216734170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.216734170
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1999073722
Short name T50
Test name
Test status
Simulation time 28393443 ps
CPU time 0.45 seconds
Started Jul 05 04:17:30 PM PDT 24
Finished Jul 05 04:17:31 PM PDT 24
Peak memory 145280 kb
Host smart-00eaac1a-081e-4779-bd43-5fc5eb46b867
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1999073722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1999073722
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3242049740
Short name T53
Test name
Test status
Simulation time 29286523 ps
CPU time 0.39 seconds
Started Jul 05 04:17:35 PM PDT 24
Finished Jul 05 04:17:36 PM PDT 24
Peak memory 145164 kb
Host smart-5172cf49-f056-48b0-96a2-6e66ce37ba40
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3242049740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3242049740
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.52087580
Short name T55
Test name
Test status
Simulation time 30133442 ps
CPU time 0.41 seconds
Started Jul 05 04:18:28 PM PDT 24
Finished Jul 05 04:18:29 PM PDT 24
Peak memory 145240 kb
Host smart-dd920311-57c2-4d4c-a367-cb4241282883
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=52087580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.52087580
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3426435340
Short name T61
Test name
Test status
Simulation time 8417592 ps
CPU time 0.37 seconds
Started Jul 05 04:22:49 PM PDT 24
Finished Jul 05 04:22:51 PM PDT 24
Peak memory 145452 kb
Host smart-7fd1e55c-fd85-4ef1-bde8-74af98a9e22c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3426435340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3426435340
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2489203096
Short name T59
Test name
Test status
Simulation time 8511124 ps
CPU time 0.38 seconds
Started Jul 05 04:20:19 PM PDT 24
Finished Jul 05 04:20:22 PM PDT 24
Peak memory 145176 kb
Host smart-42f3689f-c2ca-4344-a736-fca7715dd4fe
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2489203096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2489203096
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.868440121
Short name T37
Test name
Test status
Simulation time 8888153 ps
CPU time 0.39 seconds
Started Jul 05 04:17:38 PM PDT 24
Finished Jul 05 04:17:38 PM PDT 24
Peak memory 145328 kb
Host smart-d44a4676-4d43-4a5e-b8da-b44eaabe9d4a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=868440121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.868440121
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3731981683
Short name T60
Test name
Test status
Simulation time 9857948 ps
CPU time 0.41 seconds
Started Jul 05 04:22:39 PM PDT 24
Finished Jul 05 04:22:41 PM PDT 24
Peak memory 145272 kb
Host smart-13645679-bc56-47c7-afe5-4a40be4bb89b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3731981683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3731981683
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2850899192
Short name T28
Test name
Test status
Simulation time 8995318 ps
CPU time 0.5 seconds
Started Jul 05 04:17:28 PM PDT 24
Finished Jul 05 04:17:30 PM PDT 24
Peak memory 145792 kb
Host smart-d2e4666d-4171-4a6c-9436-e1a26b131eb2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2850899192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2850899192
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2639075704
Short name T34
Test name
Test status
Simulation time 8536257 ps
CPU time 0.39 seconds
Started Jul 05 04:22:32 PM PDT 24
Finished Jul 05 04:22:33 PM PDT 24
Peak memory 144696 kb
Host smart-3075c44d-5508-4bb8-b336-6a39e22a3c2c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2639075704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2639075704
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.964233485
Short name T25
Test name
Test status
Simulation time 9124099 ps
CPU time 0.38 seconds
Started Jul 05 04:22:55 PM PDT 24
Finished Jul 05 04:22:57 PM PDT 24
Peak memory 145188 kb
Host smart-1d682a0e-4411-4bef-a121-f634da925826
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=964233485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.964233485
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3847648468
Short name T24
Test name
Test status
Simulation time 9836768 ps
CPU time 0.41 seconds
Started Jul 05 04:18:44 PM PDT 24
Finished Jul 05 04:18:45 PM PDT 24
Peak memory 145452 kb
Host smart-74881603-c503-44f6-abfe-c660b78b8691
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3847648468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3847648468
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1854122645
Short name T33
Test name
Test status
Simulation time 9499655 ps
CPU time 0.38 seconds
Started Jul 05 04:22:49 PM PDT 24
Finished Jul 05 04:22:50 PM PDT 24
Peak memory 145192 kb
Host smart-771f6603-1a33-4afc-bc40-9c2f08cb0b18
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1854122645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1854122645
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3391703079
Short name T32
Test name
Test status
Simulation time 9933181 ps
CPU time 0.38 seconds
Started Jul 05 04:17:36 PM PDT 24
Finished Jul 05 04:17:37 PM PDT 24
Peak memory 145412 kb
Host smart-dadb0314-641a-4362-8243-c3b75b40880f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3391703079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3391703079
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3719225603
Short name T38
Test name
Test status
Simulation time 8881778 ps
CPU time 0.4 seconds
Started Jul 05 04:20:54 PM PDT 24
Finished Jul 05 04:20:55 PM PDT 24
Peak memory 145452 kb
Host smart-e6031b19-a4ba-4a45-9b98-195aec8b9ad9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3719225603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3719225603
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3998275872
Short name T26
Test name
Test status
Simulation time 8837091 ps
CPU time 0.39 seconds
Started Jul 05 04:17:29 PM PDT 24
Finished Jul 05 04:17:30 PM PDT 24
Peak memory 145496 kb
Host smart-9cfd3513-6ef9-4c3f-8e74-ae7d3da0f417
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3998275872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3998275872
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.477240275
Short name T35
Test name
Test status
Simulation time 10088340 ps
CPU time 0.38 seconds
Started Jul 05 04:17:20 PM PDT 24
Finished Jul 05 04:17:20 PM PDT 24
Peak memory 145740 kb
Host smart-6188f645-95a4-4671-9be8-fe8aadc296f7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=477240275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.477240275
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.148327614
Short name T31
Test name
Test status
Simulation time 9065090 ps
CPU time 0.39 seconds
Started Jul 05 04:17:38 PM PDT 24
Finished Jul 05 04:17:38 PM PDT 24
Peak memory 145292 kb
Host smart-c78450c1-4d90-49d3-8bd9-0f06805cddcd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=148327614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.148327614
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3064976198
Short name T29
Test name
Test status
Simulation time 8397319 ps
CPU time 0.37 seconds
Started Jul 05 04:19:22 PM PDT 24
Finished Jul 05 04:19:23 PM PDT 24
Peak memory 145500 kb
Host smart-8688df1e-561f-4b06-97ad-ea740649d715
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3064976198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3064976198
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2353208536
Short name T58
Test name
Test status
Simulation time 9564286 ps
CPU time 0.39 seconds
Started Jul 05 04:22:32 PM PDT 24
Finished Jul 05 04:22:33 PM PDT 24
Peak memory 144672 kb
Host smart-18c42327-46c4-4792-9baa-d95f2f6fb8c2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2353208536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2353208536
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.80538639
Short name T27
Test name
Test status
Simulation time 10581299 ps
CPU time 0.41 seconds
Started Jul 05 04:22:44 PM PDT 24
Finished Jul 05 04:22:45 PM PDT 24
Peak memory 145840 kb
Host smart-376caa2d-d3bc-4b7c-b13d-71b5128b0ce2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=80538639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.80538639
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4184775717
Short name T67
Test name
Test status
Simulation time 26873748 ps
CPU time 0.41 seconds
Started Jul 05 04:17:36 PM PDT 24
Finished Jul 05 04:17:37 PM PDT 24
Peak memory 145396 kb
Host smart-a58f6888-e4ae-432d-b52c-91acaf8b32ac
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4184775717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4184775717
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.807788353
Short name T75
Test name
Test status
Simulation time 27852920 ps
CPU time 0.4 seconds
Started Jul 05 04:18:37 PM PDT 24
Finished Jul 05 04:18:38 PM PDT 24
Peak memory 145740 kb
Host smart-4a16d588-ac6f-40e5-a1c1-bb5cf9cba3c2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=807788353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.807788353
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.620867169
Short name T12
Test name
Test status
Simulation time 26673000 ps
CPU time 0.41 seconds
Started Jul 05 04:19:28 PM PDT 24
Finished Jul 05 04:19:29 PM PDT 24
Peak memory 145552 kb
Host smart-04463393-41ca-4201-b739-22ab55836944
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=620867169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.620867169
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1705017061
Short name T6
Test name
Test status
Simulation time 28850331 ps
CPU time 0.4 seconds
Started Jul 05 04:20:18 PM PDT 24
Finished Jul 05 04:20:21 PM PDT 24
Peak memory 144676 kb
Host smart-ee6f9c88-595c-4f33-b785-900cab0637f0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1705017061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1705017061
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.574965385
Short name T76
Test name
Test status
Simulation time 25474645 ps
CPU time 0.41 seconds
Started Jul 05 04:22:54 PM PDT 24
Finished Jul 05 04:22:56 PM PDT 24
Peak memory 145196 kb
Host smart-75d4eae9-40e0-41e7-acbb-60dad5951a38
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=574965385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.574965385
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3426595342
Short name T73
Test name
Test status
Simulation time 28947863 ps
CPU time 0.4 seconds
Started Jul 05 04:20:18 PM PDT 24
Finished Jul 05 04:20:21 PM PDT 24
Peak memory 144712 kb
Host smart-9386bc6e-47ad-4aeb-8d60-9460ed788430
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3426595342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3426595342
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2465265667
Short name T79
Test name
Test status
Simulation time 29716177 ps
CPU time 0.41 seconds
Started Jul 05 04:19:30 PM PDT 24
Finished Jul 05 04:19:31 PM PDT 24
Peak memory 145544 kb
Host smart-f6b2b5cb-f2fb-4020-9154-a61c5c53b11f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2465265667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2465265667
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3841538377
Short name T65
Test name
Test status
Simulation time 29501697 ps
CPU time 0.47 seconds
Started Jul 05 04:20:05 PM PDT 24
Finished Jul 05 04:20:07 PM PDT 24
Peak memory 143992 kb
Host smart-371f2e06-8936-4e67-b361-2be68f514eab
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3841538377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3841538377
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2273620592
Short name T62
Test name
Test status
Simulation time 29272492 ps
CPU time 0.45 seconds
Started Jul 05 04:20:05 PM PDT 24
Finished Jul 05 04:20:07 PM PDT 24
Peak memory 144860 kb
Host smart-32ca6711-15f2-478f-91ff-f05b5ed714b8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2273620592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2273620592
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.384657377
Short name T68
Test name
Test status
Simulation time 26117835 ps
CPU time 0.38 seconds
Started Jul 05 04:22:39 PM PDT 24
Finished Jul 05 04:22:40 PM PDT 24
Peak memory 145260 kb
Host smart-42947f39-9ba2-43bd-b315-70600e95d507
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=384657377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.384657377
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2936816033
Short name T63
Test name
Test status
Simulation time 27890976 ps
CPU time 0.45 seconds
Started Jul 05 04:20:05 PM PDT 24
Finished Jul 05 04:20:07 PM PDT 24
Peak memory 143396 kb
Host smart-a414826a-9ef9-43c8-adeb-a62bf7a82fa6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2936816033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2936816033
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3897381694
Short name T70
Test name
Test status
Simulation time 27101405 ps
CPU time 0.38 seconds
Started Jul 05 04:22:39 PM PDT 24
Finished Jul 05 04:22:40 PM PDT 24
Peak memory 145272 kb
Host smart-b9ec202b-2a68-42ea-85c8-e2d0575a8360
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3897381694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3897381694
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1447736313
Short name T69
Test name
Test status
Simulation time 26768601 ps
CPU time 0.39 seconds
Started Jul 05 04:18:42 PM PDT 24
Finished Jul 05 04:18:44 PM PDT 24
Peak memory 145712 kb
Host smart-52cde534-1a43-415d-8323-eb00e80fd31c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1447736313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1447736313
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1986379581
Short name T64
Test name
Test status
Simulation time 25468673 ps
CPU time 0.46 seconds
Started Jul 05 04:22:54 PM PDT 24
Finished Jul 05 04:22:55 PM PDT 24
Peak memory 144096 kb
Host smart-6dab24ef-ebbd-4515-b7e7-69f691226f6f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1986379581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1986379581
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.43234653
Short name T66
Test name
Test status
Simulation time 26728780 ps
CPU time 0.42 seconds
Started Jul 05 04:22:39 PM PDT 24
Finished Jul 05 04:22:41 PM PDT 24
Peak memory 144576 kb
Host smart-c74b31db-071a-4cd5-94e3-29da2348aa1d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=43234653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.43234653
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.641815317
Short name T74
Test name
Test status
Simulation time 26952588 ps
CPU time 0.39 seconds
Started Jul 05 04:18:28 PM PDT 24
Finished Jul 05 04:18:29 PM PDT 24
Peak memory 145524 kb
Host smart-d16ef34f-dece-4a6b-8883-6cbbc2184b8f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=641815317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.641815317
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.893917239
Short name T71
Test name
Test status
Simulation time 28303806 ps
CPU time 0.41 seconds
Started Jul 05 04:22:54 PM PDT 24
Finished Jul 05 04:22:55 PM PDT 24
Peak memory 144336 kb
Host smart-b48d6a83-8700-45da-b207-9dc545fb2308
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=893917239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.893917239
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.360701789
Short name T72
Test name
Test status
Simulation time 25690891 ps
CPU time 0.43 seconds
Started Jul 05 04:23:04 PM PDT 24
Finished Jul 05 04:23:05 PM PDT 24
Peak memory 145856 kb
Host smart-e3267a67-f85b-4e6b-b4d3-ad132d4d7081
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=360701789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.360701789
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3767281826
Short name T78
Test name
Test status
Simulation time 26564803 ps
CPU time 0.42 seconds
Started Jul 05 04:22:56 PM PDT 24
Finished Jul 05 04:22:58 PM PDT 24
Peak memory 145200 kb
Host smart-b2e8c8b3-fa21-4b67-ae26-3b48ca822f95
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3767281826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3767281826
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3710519661
Short name T77
Test name
Test status
Simulation time 28543559 ps
CPU time 0.41 seconds
Started Jul 05 04:18:00 PM PDT 24
Finished Jul 05 04:18:01 PM PDT 24
Peak memory 145456 kb
Host smart-7fe0e3f5-5ff3-400e-b76d-fb0c14642218
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3710519661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3710519661
Directory /workspace/9.prim_sync_fatal_alert/latest
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