| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 89.02 | 89.02 | 100.00 | 100.00 | 95.83 | 95.83 | 100.00 | 100.00 | 75.00 | 75.00 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/4.prim_async_alert.2174580346 |
| 92.15 | 3.13 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/1.prim_sync_alert.4138787067 |
| 94.25 | 2.11 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 85.71 | 3.57 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1706550659 |
| 94.85 | 0.60 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/10.prim_async_alert.3286101075 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/17.prim_sync_alert.287598760 |
| Name |
|---|
| /workspace/coverage/default/1.prim_async_alert.356925387 |
| /workspace/coverage/default/11.prim_async_alert.1316615106 |
| /workspace/coverage/default/12.prim_async_alert.1021107431 |
| /workspace/coverage/default/13.prim_async_alert.2438844755 |
| /workspace/coverage/default/14.prim_async_alert.833067968 |
| /workspace/coverage/default/15.prim_async_alert.1740281 |
| /workspace/coverage/default/16.prim_async_alert.3058914255 |
| /workspace/coverage/default/17.prim_async_alert.616889114 |
| /workspace/coverage/default/18.prim_async_alert.344634881 |
| /workspace/coverage/default/2.prim_async_alert.3988960297 |
| /workspace/coverage/default/3.prim_async_alert.2492934747 |
| /workspace/coverage/default/5.prim_async_alert.2094181592 |
| /workspace/coverage/default/6.prim_async_alert.3724601519 |
| /workspace/coverage/default/7.prim_async_alert.3216935086 |
| /workspace/coverage/default/8.prim_async_alert.3165940324 |
| /workspace/coverage/default/9.prim_async_alert.1422188734 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.849852564 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2060116727 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2186533945 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.927036589 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3318776976 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3476621791 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1701056764 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4064717773 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.620924280 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.920690835 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3399785088 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2516228980 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.631930891 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.453334951 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2807831583 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.260299127 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.494734335 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.1321715668 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.1173232063 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1410347479 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.797095447 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1147003695 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.3582581683 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.1176153580 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.1439263997 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.3771225608 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.1654827394 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2298235581 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3476210133 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.2344019143 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.1451921226 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.2715618391 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.2362132821 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.834792878 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.3925945267 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4097438558 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.406149486 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.211672500 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4187802653 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1286406679 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.57540912 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2086226243 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1274219481 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3339226199 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4283986502 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2369412568 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.884108539 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1347412176 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3946958869 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.495798944 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.764416549 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.536601087 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2922957995 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2983278429 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3039180589 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/4.prim_async_alert.2174580346 | Jul 06 04:18:36 PM PDT 24 | Jul 06 04:18:39 PM PDT 24 | 13232657 ps | ||
| T2 | /workspace/coverage/default/11.prim_async_alert.1316615106 | Jul 06 04:18:35 PM PDT 24 | Jul 06 04:18:37 PM PDT 24 | 11008085 ps | ||
| T3 | /workspace/coverage/default/1.prim_async_alert.356925387 | Jul 06 04:18:21 PM PDT 24 | Jul 06 04:18:22 PM PDT 24 | 11266441 ps | ||
| T8 | /workspace/coverage/default/7.prim_async_alert.3216935086 | Jul 06 04:18:36 PM PDT 24 | Jul 06 04:18:39 PM PDT 24 | 10966688 ps | ||
| T9 | /workspace/coverage/default/14.prim_async_alert.833067968 | Jul 06 04:18:36 PM PDT 24 | Jul 06 04:18:38 PM PDT 24 | 11592927 ps | ||
| T18 | /workspace/coverage/default/5.prim_async_alert.2094181592 | Jul 06 04:18:37 PM PDT 24 | Jul 06 04:18:39 PM PDT 24 | 11988536 ps | ||
| T21 | /workspace/coverage/default/9.prim_async_alert.1422188734 | Jul 06 04:18:37 PM PDT 24 | Jul 06 04:18:39 PM PDT 24 | 11445584 ps | ||
| T7 | /workspace/coverage/default/16.prim_async_alert.3058914255 | Jul 06 04:18:21 PM PDT 24 | Jul 06 04:18:22 PM PDT 24 | 10680649 ps | ||
| T12 | /workspace/coverage/default/10.prim_async_alert.3286101075 | Jul 06 04:18:36 PM PDT 24 | Jul 06 04:18:39 PM PDT 24 | 11369152 ps | ||
| T19 | /workspace/coverage/default/13.prim_async_alert.2438844755 | Jul 06 04:18:35 PM PDT 24 | Jul 06 04:18:36 PM PDT 24 | 12233883 ps | ||
| T34 | /workspace/coverage/default/17.prim_async_alert.616889114 | Jul 06 04:18:27 PM PDT 24 | Jul 06 04:18:27 PM PDT 24 | 11541782 ps | ||
| T13 | /workspace/coverage/default/2.prim_async_alert.3988960297 | Jul 06 04:18:36 PM PDT 24 | Jul 06 04:18:39 PM PDT 24 | 12240420 ps | ||
| T48 | /workspace/coverage/default/18.prim_async_alert.344634881 | Jul 06 04:18:35 PM PDT 24 | Jul 06 04:18:37 PM PDT 24 | 10679733 ps | ||
| T49 | /workspace/coverage/default/3.prim_async_alert.2492934747 | Jul 06 04:18:36 PM PDT 24 | Jul 06 04:18:39 PM PDT 24 | 12659727 ps | ||
| T20 | /workspace/coverage/default/8.prim_async_alert.3165940324 | Jul 06 04:18:36 PM PDT 24 | Jul 06 04:18:38 PM PDT 24 | 11152928 ps | ||
| T50 | /workspace/coverage/default/12.prim_async_alert.1021107431 | Jul 06 04:18:37 PM PDT 24 | Jul 06 04:18:39 PM PDT 24 | 11336264 ps | ||
| T22 | /workspace/coverage/default/6.prim_async_alert.3724601519 | Jul 06 04:18:37 PM PDT 24 | Jul 06 04:18:39 PM PDT 24 | 12207127 ps | ||
| T23 | /workspace/coverage/default/15.prim_async_alert.1740281 | Jul 06 04:18:36 PM PDT 24 | Jul 06 04:18:39 PM PDT 24 | 11416921 ps | ||
| T4 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1706550659 | Jul 06 04:20:11 PM PDT 24 | Jul 06 04:20:12 PM PDT 24 | 30366878 ps | ||
| T41 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2516228980 | Jul 06 04:19:36 PM PDT 24 | Jul 06 04:19:38 PM PDT 24 | 30632567 ps | ||
| T42 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3399785088 | Jul 06 04:19:31 PM PDT 24 | Jul 06 04:19:32 PM PDT 24 | 31966667 ps | ||
| T15 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.920690835 | Jul 06 04:23:35 PM PDT 24 | Jul 06 04:23:36 PM PDT 24 | 30262887 ps | ||
| T43 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.453334951 | Jul 06 04:19:36 PM PDT 24 | Jul 06 04:19:38 PM PDT 24 | 31550688 ps | ||
| T44 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.631930891 | Jul 06 04:19:53 PM PDT 24 | Jul 06 04:19:54 PM PDT 24 | 30619145 ps | ||
| T16 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3476621791 | Jul 06 04:19:26 PM PDT 24 | Jul 06 04:19:26 PM PDT 24 | 31103970 ps | ||
| T45 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2807831583 | Jul 06 04:20:05 PM PDT 24 | Jul 06 04:20:05 PM PDT 24 | 30055816 ps | ||
| T46 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2186533945 | Jul 06 04:20:11 PM PDT 24 | Jul 06 04:20:12 PM PDT 24 | 29225204 ps | ||
| T47 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.494734335 | Jul 06 04:20:37 PM PDT 24 | Jul 06 04:20:37 PM PDT 24 | 30384755 ps | ||
| T24 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.260299127 | Jul 06 04:19:04 PM PDT 24 | Jul 06 04:19:05 PM PDT 24 | 28731403 ps | ||
| T51 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3318776976 | Jul 06 04:20:38 PM PDT 24 | Jul 06 04:20:39 PM PDT 24 | 29878874 ps | ||
| T17 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.927036589 | Jul 06 04:20:23 PM PDT 24 | Jul 06 04:20:24 PM PDT 24 | 31602878 ps | ||
| T5 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2060116727 | Jul 06 04:20:15 PM PDT 24 | Jul 06 04:20:16 PM PDT 24 | 30329600 ps | ||
| T52 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.849852564 | Jul 06 04:19:22 PM PDT 24 | Jul 06 04:19:23 PM PDT 24 | 29919354 ps | ||
| T53 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.620924280 | Jul 06 04:23:42 PM PDT 24 | Jul 06 04:23:43 PM PDT 24 | 29764935 ps | ||
| T6 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4064717773 | Jul 06 04:23:42 PM PDT 24 | Jul 06 04:23:43 PM PDT 24 | 27766860 ps | ||
| T54 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1701056764 | Jul 06 04:20:09 PM PDT 24 | Jul 06 04:20:10 PM PDT 24 | 31786505 ps | ||
| T10 | /workspace/coverage/sync_alert/17.prim_sync_alert.287598760 | Jul 06 04:18:39 PM PDT 24 | Jul 06 04:18:40 PM PDT 24 | 8520173 ps | ||
| T35 | /workspace/coverage/sync_alert/12.prim_sync_alert.797095447 | Jul 06 04:18:39 PM PDT 24 | Jul 06 04:18:40 PM PDT 24 | 9451727 ps | ||
| T36 | /workspace/coverage/sync_alert/15.prim_sync_alert.1176153580 | Jul 06 04:19:36 PM PDT 24 | Jul 06 04:19:37 PM PDT 24 | 9276310 ps | ||
| T37 | /workspace/coverage/sync_alert/7.prim_sync_alert.2362132821 | Jul 06 04:18:35 PM PDT 24 | Jul 06 04:18:36 PM PDT 24 | 9134643 ps | ||
| T38 | /workspace/coverage/sync_alert/5.prim_sync_alert.1451921226 | Jul 06 04:18:35 PM PDT 24 | Jul 06 04:18:36 PM PDT 24 | 8811530 ps | ||
| T14 | /workspace/coverage/sync_alert/0.prim_sync_alert.1321715668 | Jul 06 04:20:38 PM PDT 24 | Jul 06 04:20:39 PM PDT 24 | 9179048 ps | ||
| T25 | /workspace/coverage/sync_alert/11.prim_sync_alert.1410347479 | Jul 06 04:18:35 PM PDT 24 | Jul 06 04:18:37 PM PDT 24 | 8805694 ps | ||
| T39 | /workspace/coverage/sync_alert/8.prim_sync_alert.834792878 | Jul 06 04:18:35 PM PDT 24 | Jul 06 04:18:36 PM PDT 24 | 8815136 ps | ||
| T26 | /workspace/coverage/sync_alert/1.prim_sync_alert.4138787067 | Jul 06 04:19:31 PM PDT 24 | Jul 06 04:19:32 PM PDT 24 | 9525006 ps | ||
| T40 | /workspace/coverage/sync_alert/10.prim_sync_alert.1173232063 | Jul 06 04:18:35 PM PDT 24 | Jul 06 04:18:37 PM PDT 24 | 8760226 ps | ||
| T55 | /workspace/coverage/sync_alert/4.prim_sync_alert.2344019143 | Jul 06 04:18:35 PM PDT 24 | Jul 06 04:18:36 PM PDT 24 | 10163996 ps | ||
| T27 | /workspace/coverage/sync_alert/9.prim_sync_alert.3925945267 | Jul 06 04:20:27 PM PDT 24 | Jul 06 04:20:28 PM PDT 24 | 9677744 ps | ||
| T56 | /workspace/coverage/sync_alert/14.prim_sync_alert.3582581683 | Jul 06 04:18:39 PM PDT 24 | Jul 06 04:18:40 PM PDT 24 | 9204950 ps | ||
| T28 | /workspace/coverage/sync_alert/6.prim_sync_alert.2715618391 | Jul 06 04:18:59 PM PDT 24 | Jul 06 04:18:59 PM PDT 24 | 9085393 ps | ||
| T29 | /workspace/coverage/sync_alert/3.prim_sync_alert.3476210133 | Jul 06 04:19:02 PM PDT 24 | Jul 06 04:19:03 PM PDT 24 | 8355693 ps | ||
| T57 | /workspace/coverage/sync_alert/16.prim_sync_alert.1439263997 | Jul 06 04:19:37 PM PDT 24 | Jul 06 04:19:38 PM PDT 24 | 8946588 ps | ||
| T58 | /workspace/coverage/sync_alert/2.prim_sync_alert.2298235581 | Jul 06 04:20:19 PM PDT 24 | Jul 06 04:20:20 PM PDT 24 | 8836866 ps | ||
| T30 | /workspace/coverage/sync_alert/18.prim_sync_alert.3771225608 | Jul 06 04:18:39 PM PDT 24 | Jul 06 04:18:40 PM PDT 24 | 8893264 ps | ||
| T59 | /workspace/coverage/sync_alert/19.prim_sync_alert.1654827394 | Jul 06 04:18:39 PM PDT 24 | Jul 06 04:18:40 PM PDT 24 | 9898593 ps | ||
| T31 | /workspace/coverage/sync_alert/13.prim_sync_alert.1147003695 | Jul 06 04:18:35 PM PDT 24 | Jul 06 04:18:36 PM PDT 24 | 8875843 ps | ||
| T32 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2922957995 | Jul 06 04:40:52 PM PDT 24 | Jul 06 04:40:52 PM PDT 24 | 26802225 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4283986502 | Jul 06 04:41:02 PM PDT 24 | Jul 06 04:41:03 PM PDT 24 | 26620808 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.406149486 | Jul 06 04:41:00 PM PDT 24 | Jul 06 04:41:00 PM PDT 24 | 26052304 ps | ||
| T33 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2369412568 | Jul 06 04:40:58 PM PDT 24 | Jul 06 04:40:59 PM PDT 24 | 28437308 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4187802653 | Jul 06 04:41:02 PM PDT 24 | Jul 06 04:41:03 PM PDT 24 | 26759948 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2086226243 | Jul 06 04:40:51 PM PDT 24 | Jul 06 04:40:51 PM PDT 24 | 27364731 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4097438558 | Jul 06 04:40:49 PM PDT 24 | Jul 06 04:40:50 PM PDT 24 | 27955010 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.884108539 | Jul 06 04:41:05 PM PDT 24 | Jul 06 04:41:06 PM PDT 24 | 27384371 ps | ||
| T11 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1274219481 | Jul 06 04:41:02 PM PDT 24 | Jul 06 04:41:03 PM PDT 24 | 29907295 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.57540912 | Jul 06 04:41:03 PM PDT 24 | Jul 06 04:41:04 PM PDT 24 | 27676585 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.536601087 | Jul 06 04:40:49 PM PDT 24 | Jul 06 04:40:50 PM PDT 24 | 27620536 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2983278429 | Jul 06 04:40:58 PM PDT 24 | Jul 06 04:40:59 PM PDT 24 | 27337094 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.764416549 | Jul 06 04:40:54 PM PDT 24 | Jul 06 04:40:55 PM PDT 24 | 26827310 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3339226199 | Jul 06 04:40:56 PM PDT 24 | Jul 06 04:40:56 PM PDT 24 | 30109898 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3039180589 | Jul 06 04:40:50 PM PDT 24 | Jul 06 04:40:51 PM PDT 24 | 26585726 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3946958869 | Jul 06 04:40:50 PM PDT 24 | Jul 06 04:40:51 PM PDT 24 | 28062712 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.495798944 | Jul 06 04:40:52 PM PDT 24 | Jul 06 04:40:52 PM PDT 24 | 29790741 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1347412176 | Jul 06 04:40:58 PM PDT 24 | Jul 06 04:40:59 PM PDT 24 | 27652767 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.211672500 | Jul 06 04:41:00 PM PDT 24 | Jul 06 04:41:00 PM PDT 24 | 27119403 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1286406679 | Jul 06 04:41:02 PM PDT 24 | Jul 06 04:41:03 PM PDT 24 | 26953088 ps |
| Test location | /workspace/coverage/default/4.prim_async_alert.2174580346 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 13232657 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:18:36 PM PDT 24 |
| Finished | Jul 06 04:18:39 PM PDT 24 |
| Peak memory | 143740 kb |
| Host | smart-b5aad8e5-f1f6-4fac-925c-b7e4e343c430 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174580346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2174580346 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.4138787067 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9525006 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:19:31 PM PDT 24 |
| Finished | Jul 06 04:19:32 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-f37e9447-a39f-468a-8d14-7937687cbfdd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4138787067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.4138787067 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1706550659 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30366878 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:20:11 PM PDT 24 |
| Finished | Jul 06 04:20:12 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-d1741ace-082c-4443-b35b-27f5ce26d616 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1706550659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1706550659 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.3286101075 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11369152 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:18:36 PM PDT 24 |
| Finished | Jul 06 04:18:39 PM PDT 24 |
| Peak memory | 145324 kb |
| Host | smart-74c1e0cd-73ca-4a86-839b-48e551f3b4fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3286101075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3286101075 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.287598760 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8520173 ps |
| CPU time | 0.43 seconds |
| Started | Jul 06 04:18:39 PM PDT 24 |
| Finished | Jul 06 04:18:40 PM PDT 24 |
| Peak memory | 143744 kb |
| Host | smart-48d6db1c-d6fd-4b6d-a222-70a88f7aa59b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=287598760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.287598760 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.356925387 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11266441 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:21 PM PDT 24 |
| Finished | Jul 06 04:18:22 PM PDT 24 |
| Peak memory | 145944 kb |
| Host | smart-c0fa923a-ddcd-44b1-af84-cca296873133 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=356925387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.356925387 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.1316615106 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11008085 ps |
| CPU time | 0.42 seconds |
| Started | Jul 06 04:18:35 PM PDT 24 |
| Finished | Jul 06 04:18:37 PM PDT 24 |
| Peak memory | 143248 kb |
| Host | smart-a01510eb-0fca-4fdd-8338-488e33c241e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1316615106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1316615106 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.1021107431 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11336264 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:18:37 PM PDT 24 |
| Finished | Jul 06 04:18:39 PM PDT 24 |
| Peak memory | 146420 kb |
| Host | smart-2dc56a70-d5e7-4134-9eff-1193deebd64c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021107431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1021107431 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.2438844755 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 12233883 ps |
| CPU time | 0.37 seconds |
| Started | Jul 06 04:18:35 PM PDT 24 |
| Finished | Jul 06 04:18:36 PM PDT 24 |
| Peak memory | 145240 kb |
| Host | smart-2516eec8-b843-457d-a8be-d582c9912e29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2438844755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2438844755 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.833067968 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11592927 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:36 PM PDT 24 |
| Finished | Jul 06 04:18:38 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-43d714d0-fe74-40bf-84ac-3ee992d809f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=833067968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.833067968 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1740281 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11416921 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:36 PM PDT 24 |
| Finished | Jul 06 04:18:39 PM PDT 24 |
| Peak memory | 144832 kb |
| Host | smart-d1dd45c4-dc5f-4c4b-883b-7cc25a24d31e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1740281 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.3058914255 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10680649 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:21 PM PDT 24 |
| Finished | Jul 06 04:18:22 PM PDT 24 |
| Peak memory | 145936 kb |
| Host | smart-546d6f89-0103-49b0-9ee4-e612cad13416 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3058914255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3058914255 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.616889114 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11541782 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:27 PM PDT 24 |
| Finished | Jul 06 04:18:27 PM PDT 24 |
| Peak memory | 145960 kb |
| Host | smart-c1dff1e1-9059-4986-ac6b-005643e8f785 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616889114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.616889114 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.344634881 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10679733 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:35 PM PDT 24 |
| Finished | Jul 06 04:18:37 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-5acdd7ec-c859-414a-a2d5-6937414be3aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=344634881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.344634881 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3988960297 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12240420 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:36 PM PDT 24 |
| Finished | Jul 06 04:18:39 PM PDT 24 |
| Peak memory | 143988 kb |
| Host | smart-a5cdcdba-db5e-491e-9a62-4ec1244c666d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3988960297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3988960297 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.2492934747 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 12659727 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:18:36 PM PDT 24 |
| Finished | Jul 06 04:18:39 PM PDT 24 |
| Peak memory | 145324 kb |
| Host | smart-cc38ad37-669d-4a77-a0f8-9c46b01d994e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492934747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2492934747 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.2094181592 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11988536 ps |
| CPU time | 0.44 seconds |
| Started | Jul 06 04:18:37 PM PDT 24 |
| Finished | Jul 06 04:18:39 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-38827feb-c812-4b70-9c3d-a0bcdc2ffa76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2094181592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2094181592 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.3724601519 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 12207127 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:37 PM PDT 24 |
| Finished | Jul 06 04:18:39 PM PDT 24 |
| Peak memory | 145380 kb |
| Host | smart-0dfbfefd-8be7-4192-952a-5a884acb0cd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724601519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3724601519 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.3216935086 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10966688 ps |
| CPU time | 0.51 seconds |
| Started | Jul 06 04:18:36 PM PDT 24 |
| Finished | Jul 06 04:18:39 PM PDT 24 |
| Peak memory | 144064 kb |
| Host | smart-edf3ff76-dfa9-48f0-9f54-8c2baeb12935 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3216935086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3216935086 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.3165940324 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11152928 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:36 PM PDT 24 |
| Finished | Jul 06 04:18:38 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-9b82351b-6d04-421a-b843-c9bfaa587c98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3165940324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3165940324 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.1422188734 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11445584 ps |
| CPU time | 0.43 seconds |
| Started | Jul 06 04:18:37 PM PDT 24 |
| Finished | Jul 06 04:18:39 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-efe69ff8-24a0-446a-984e-f4897391b32c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422188734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1422188734 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.849852564 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 29919354 ps |
| CPU time | 0.43 seconds |
| Started | Jul 06 04:19:22 PM PDT 24 |
| Finished | Jul 06 04:19:23 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-efef323b-78c7-4998-a77c-b0fc5e3ab307 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=849852564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.849852564 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2060116727 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30329600 ps |
| CPU time | 0.41 seconds |
| Started | Jul 06 04:20:15 PM PDT 24 |
| Finished | Jul 06 04:20:16 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-ddcae3fb-b468-40bb-8ad0-21f654727eaf |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2060116727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2060116727 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2186533945 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29225204 ps |
| CPU time | 0.42 seconds |
| Started | Jul 06 04:20:11 PM PDT 24 |
| Finished | Jul 06 04:20:12 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-3680dc9e-44e5-4ed2-9259-a8dedcf83d6a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2186533945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2186533945 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.927036589 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 31602878 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:20:23 PM PDT 24 |
| Finished | Jul 06 04:20:24 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-7aabb9c3-2714-488f-80b1-e4e056228a33 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=927036589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.927036589 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3318776976 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29878874 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:20:38 PM PDT 24 |
| Finished | Jul 06 04:20:39 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-514c4007-4d0d-4917-a21b-46310a08a79c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3318776976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3318776976 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3476621791 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 31103970 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:19:26 PM PDT 24 |
| Finished | Jul 06 04:19:26 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-8ea5555d-3d88-452a-a411-c47787648565 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3476621791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3476621791 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1701056764 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 31786505 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:20:09 PM PDT 24 |
| Finished | Jul 06 04:20:10 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-72bc7eb8-5405-4ecd-be6c-a1289aac2a84 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1701056764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1701056764 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4064717773 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27766860 ps |
| CPU time | 0.44 seconds |
| Started | Jul 06 04:23:42 PM PDT 24 |
| Finished | Jul 06 04:23:43 PM PDT 24 |
| Peak memory | 144832 kb |
| Host | smart-93260049-ab3e-4358-91db-14d3a5f8d281 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4064717773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.4064717773 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.620924280 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 29764935 ps |
| CPU time | 0.44 seconds |
| Started | Jul 06 04:23:42 PM PDT 24 |
| Finished | Jul 06 04:23:43 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-4e6f651a-d48b-41eb-b7ea-d8f49088a66d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=620924280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.620924280 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.920690835 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 30262887 ps |
| CPU time | 0.43 seconds |
| Started | Jul 06 04:23:35 PM PDT 24 |
| Finished | Jul 06 04:23:36 PM PDT 24 |
| Peak memory | 145476 kb |
| Host | smart-66bdf39d-b532-47bf-8d51-ea0ea9fc69a0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=920690835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.920690835 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3399785088 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 31966667 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:19:31 PM PDT 24 |
| Finished | Jul 06 04:19:32 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-664c6062-f4c0-4be2-8a04-4f6f0ef613cb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3399785088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3399785088 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2516228980 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30632567 ps |
| CPU time | 0.43 seconds |
| Started | Jul 06 04:19:36 PM PDT 24 |
| Finished | Jul 06 04:19:38 PM PDT 24 |
| Peak memory | 144424 kb |
| Host | smart-d86c4013-8372-4adf-98f8-1f9b850a4e78 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2516228980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2516228980 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.631930891 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30619145 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:19:53 PM PDT 24 |
| Finished | Jul 06 04:19:54 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-6eeccfd6-1c54-4e29-bce9-41758cff5295 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=631930891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.631930891 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.453334951 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 31550688 ps |
| CPU time | 0.5 seconds |
| Started | Jul 06 04:19:36 PM PDT 24 |
| Finished | Jul 06 04:19:38 PM PDT 24 |
| Peak memory | 144180 kb |
| Host | smart-4e3dfc05-bde7-4d72-bbe9-137ebf9efac1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=453334951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.453334951 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2807831583 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30055816 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:20:05 PM PDT 24 |
| Finished | Jul 06 04:20:05 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-7f1d29a2-132c-4389-97a8-b52d55768500 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2807831583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2807831583 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.260299127 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 28731403 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:19:04 PM PDT 24 |
| Finished | Jul 06 04:19:05 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-01a0e0ba-88c5-4227-a5b8-21874ba3a68a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=260299127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.260299127 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.494734335 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 30384755 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:20:37 PM PDT 24 |
| Finished | Jul 06 04:20:37 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-bdeecf9d-10ec-4a99-adcb-d932f6eea69a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=494734335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.494734335 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.1321715668 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 9179048 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:20:38 PM PDT 24 |
| Finished | Jul 06 04:20:39 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-43659425-4bc8-4223-b9f6-b0fcac02af6d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1321715668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1321715668 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.1173232063 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8760226 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:18:35 PM PDT 24 |
| Finished | Jul 06 04:18:37 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-61aee2b6-cd16-4820-9f8c-2ce3f80c2dd2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1173232063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1173232063 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1410347479 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8805694 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:35 PM PDT 24 |
| Finished | Jul 06 04:18:37 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-b0b590db-4f8e-46a1-a819-39903a2fe716 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1410347479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1410347479 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.797095447 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9451727 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:39 PM PDT 24 |
| Finished | Jul 06 04:18:40 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-2fbd5f21-3507-432e-9904-0ca519dd780e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=797095447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.797095447 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1147003695 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8875843 ps |
| CPU time | 0.45 seconds |
| Started | Jul 06 04:18:35 PM PDT 24 |
| Finished | Jul 06 04:18:36 PM PDT 24 |
| Peak memory | 144024 kb |
| Host | smart-8b7caa24-62d5-470c-b261-db064778a556 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1147003695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1147003695 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.3582581683 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9204950 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:18:39 PM PDT 24 |
| Finished | Jul 06 04:18:40 PM PDT 24 |
| Peak memory | 144772 kb |
| Host | smart-baa83467-729b-4c94-b42a-2ce1e7846cd2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3582581683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3582581683 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.1176153580 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9276310 ps |
| CPU time | 0.36 seconds |
| Started | Jul 06 04:19:36 PM PDT 24 |
| Finished | Jul 06 04:19:37 PM PDT 24 |
| Peak memory | 146044 kb |
| Host | smart-99278da7-7d30-44c2-91e2-c48fe607f775 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1176153580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1176153580 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.1439263997 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8946588 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:19:37 PM PDT 24 |
| Finished | Jul 06 04:19:38 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-597b1aec-0814-4fe5-b5b0-5d16b6c3d992 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1439263997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1439263997 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.3771225608 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8893264 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:39 PM PDT 24 |
| Finished | Jul 06 04:18:40 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-07af1391-fb11-49dc-abfc-cf7784eb1267 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3771225608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3771225608 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.1654827394 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9898593 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:39 PM PDT 24 |
| Finished | Jul 06 04:18:40 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-cf3398d7-cd98-4da6-adb6-adb3cc638538 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1654827394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1654827394 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2298235581 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8836866 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:20:19 PM PDT 24 |
| Finished | Jul 06 04:20:20 PM PDT 24 |
| Peak memory | 145448 kb |
| Host | smart-f2c538b8-3d02-4d57-85f9-196c462d5a3a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2298235581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2298235581 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3476210133 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8355693 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:19:02 PM PDT 24 |
| Finished | Jul 06 04:19:03 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-d7b21e3f-789c-474f-845a-ee7187887181 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3476210133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3476210133 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.2344019143 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 10163996 ps |
| CPU time | 0.43 seconds |
| Started | Jul 06 04:18:35 PM PDT 24 |
| Finished | Jul 06 04:18:36 PM PDT 24 |
| Peak memory | 143320 kb |
| Host | smart-44b765af-f7ed-4bd7-9af8-e988cdaea353 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2344019143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2344019143 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1451921226 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8811530 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:18:35 PM PDT 24 |
| Finished | Jul 06 04:18:36 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-9be3ac7f-3895-434a-bad3-80c82a33aa71 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1451921226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1451921226 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.2715618391 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9085393 ps |
| CPU time | 0.37 seconds |
| Started | Jul 06 04:18:59 PM PDT 24 |
| Finished | Jul 06 04:18:59 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-4d2d72f5-4321-45a7-ade5-a7cbbe0e00f1 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2715618391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2715618391 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.2362132821 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9134643 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:18:35 PM PDT 24 |
| Finished | Jul 06 04:18:36 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-00c6594d-e184-4391-b60b-50824972da83 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2362132821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2362132821 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.834792878 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8815136 ps |
| CPU time | 0.45 seconds |
| Started | Jul 06 04:18:35 PM PDT 24 |
| Finished | Jul 06 04:18:36 PM PDT 24 |
| Peak memory | 144488 kb |
| Host | smart-f0a2e8bb-c131-4b25-a17e-203fcf68c408 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=834792878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.834792878 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.3925945267 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9677744 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:20:27 PM PDT 24 |
| Finished | Jul 06 04:20:28 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-277a2d8e-b5c3-43ed-9350-a08a8c80d49e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3925945267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3925945267 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4097438558 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27955010 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:40:49 PM PDT 24 |
| Finished | Jul 06 04:40:50 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-4339f63c-91cf-427e-957e-d0c9cf1e7c88 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4097438558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4097438558 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.406149486 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 26052304 ps |
| CPU time | 0.41 seconds |
| Started | Jul 06 04:41:00 PM PDT 24 |
| Finished | Jul 06 04:41:00 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-332784c8-95be-4db7-9d09-e2cc4b420479 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=406149486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.406149486 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.211672500 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27119403 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:41:00 PM PDT 24 |
| Finished | Jul 06 04:41:00 PM PDT 24 |
| Peak memory | 145400 kb |
| Host | smart-00604547-b5ba-4e27-a7c0-63efabb3a5b6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=211672500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.211672500 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4187802653 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 26759948 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:41:02 PM PDT 24 |
| Finished | Jul 06 04:41:03 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-de914169-f57f-4815-b4c8-e05426e53649 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4187802653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.4187802653 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1286406679 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 26953088 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:41:02 PM PDT 24 |
| Finished | Jul 06 04:41:03 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-9c98c423-9397-4fbf-a64f-460452bf93f8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1286406679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1286406679 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.57540912 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27676585 ps |
| CPU time | 0.51 seconds |
| Started | Jul 06 04:41:03 PM PDT 24 |
| Finished | Jul 06 04:41:04 PM PDT 24 |
| Peak memory | 145856 kb |
| Host | smart-bad3889a-828c-4427-979a-bd1c3064d1a2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=57540912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.57540912 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2086226243 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27364731 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:40:51 PM PDT 24 |
| Finished | Jul 06 04:40:51 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-6c2b72b9-d512-407a-943e-cdf1ed420cbb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2086226243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2086226243 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1274219481 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 29907295 ps |
| CPU time | 0.41 seconds |
| Started | Jul 06 04:41:02 PM PDT 24 |
| Finished | Jul 06 04:41:03 PM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-72986d0d-2594-4b75-8038-950c79f7b65e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1274219481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1274219481 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3339226199 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 30109898 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:40:56 PM PDT 24 |
| Finished | Jul 06 04:40:56 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-94c34933-e05a-44cb-b284-c68c104fd7ae |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3339226199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3339226199 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4283986502 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 26620808 ps |
| CPU time | 0.41 seconds |
| Started | Jul 06 04:41:02 PM PDT 24 |
| Finished | Jul 06 04:41:03 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-109132ea-c9f5-4506-99da-3cefd391f9d3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4283986502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.4283986502 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2369412568 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 28437308 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:40:58 PM PDT 24 |
| Finished | Jul 06 04:40:59 PM PDT 24 |
| Peak memory | 145400 kb |
| Host | smart-d6349f78-1338-4430-8636-e5e640d987c7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2369412568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2369412568 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.884108539 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27384371 ps |
| CPU time | 0.41 seconds |
| Started | Jul 06 04:41:05 PM PDT 24 |
| Finished | Jul 06 04:41:06 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-ddd052ca-78ad-4392-9421-6a807331922a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=884108539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.884108539 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1347412176 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27652767 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:40:58 PM PDT 24 |
| Finished | Jul 06 04:40:59 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-15e60ae1-8953-4058-938f-feb49834becd |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1347412176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1347412176 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3946958869 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28062712 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:40:50 PM PDT 24 |
| Finished | Jul 06 04:40:51 PM PDT 24 |
| Peak memory | 145376 kb |
| Host | smart-b9599eaf-4eed-4175-9905-cc75dee62597 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3946958869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3946958869 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.495798944 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 29790741 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:40:52 PM PDT 24 |
| Finished | Jul 06 04:40:52 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-01456259-6211-4f64-b430-d6371873da4d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=495798944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.495798944 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.764416549 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 26827310 ps |
| CPU time | 0.43 seconds |
| Started | Jul 06 04:40:54 PM PDT 24 |
| Finished | Jul 06 04:40:55 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-70349c21-7db2-4625-a4f2-50e94913de8f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=764416549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.764416549 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.536601087 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27620536 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:40:49 PM PDT 24 |
| Finished | Jul 06 04:40:50 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-0ba21b8d-3ee5-4930-a7e4-cfb237580cb2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=536601087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.536601087 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2922957995 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 26802225 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:40:52 PM PDT 24 |
| Finished | Jul 06 04:40:52 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-6dc3e1f6-0afe-469e-a8b9-9ca4cef770c3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2922957995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2922957995 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2983278429 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27337094 ps |
| CPU time | 0.54 seconds |
| Started | Jul 06 04:40:58 PM PDT 24 |
| Finished | Jul 06 04:40:59 PM PDT 24 |
| Peak memory | 145856 kb |
| Host | smart-c73175ac-f9d6-48ee-863f-4a7a6413cbca |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2983278429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2983278429 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3039180589 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26585726 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:40:50 PM PDT 24 |
| Finished | Jul 06 04:40:51 PM PDT 24 |
| Peak memory | 145388 kb |
| Host | smart-adbeff84-7619-402f-a7d4-2d81fa8a6c37 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3039180589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3039180589 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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