Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.08 88.08 100.00 100.00 93.75 93.75 96.43 96.43 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/16.prim_async_alert.381302207
91.80 3.72 100.00 0.00 93.75 0.00 96.43 0.00 85.71 10.71 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/15.prim_sync_alert.369337755
94.50 2.70 100.00 0.00 95.83 2.08 100.00 3.57 89.29 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.493709232
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.409464637
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.994473474

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1491486886
/workspace/coverage/default/1.prim_async_alert.3086172115
/workspace/coverage/default/10.prim_async_alert.1338810818
/workspace/coverage/default/11.prim_async_alert.3172737686
/workspace/coverage/default/12.prim_async_alert.1703637311
/workspace/coverage/default/13.prim_async_alert.660647250
/workspace/coverage/default/14.prim_async_alert.3972950684
/workspace/coverage/default/15.prim_async_alert.435820715
/workspace/coverage/default/17.prim_async_alert.3734903966
/workspace/coverage/default/18.prim_async_alert.615481786
/workspace/coverage/default/19.prim_async_alert.250441354
/workspace/coverage/default/2.prim_async_alert.3002907582
/workspace/coverage/default/3.prim_async_alert.549610674
/workspace/coverage/default/4.prim_async_alert.321771035
/workspace/coverage/default/5.prim_async_alert.2553124990
/workspace/coverage/default/6.prim_async_alert.3197840143
/workspace/coverage/default/7.prim_async_alert.955170897
/workspace/coverage/default/8.prim_async_alert.3038803180
/workspace/coverage/default/9.prim_async_alert.1834369611
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2186782938
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3541686356
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1035195451
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3777835062
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2964040660
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.804893323
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.466222486
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.122348686
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2829687443
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.749633166
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1766962737
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3016673482
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.499633118
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4188307405
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1649430944
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.222749047
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.435335311
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1714936045
/workspace/coverage/sync_alert/0.prim_sync_alert.2637212616
/workspace/coverage/sync_alert/1.prim_sync_alert.80642740
/workspace/coverage/sync_alert/10.prim_sync_alert.3533857144
/workspace/coverage/sync_alert/11.prim_sync_alert.3632492774
/workspace/coverage/sync_alert/12.prim_sync_alert.2811639773
/workspace/coverage/sync_alert/13.prim_sync_alert.1948307724
/workspace/coverage/sync_alert/14.prim_sync_alert.3881689596
/workspace/coverage/sync_alert/16.prim_sync_alert.905778400
/workspace/coverage/sync_alert/17.prim_sync_alert.1449233587
/workspace/coverage/sync_alert/18.prim_sync_alert.2033630187
/workspace/coverage/sync_alert/19.prim_sync_alert.207702402
/workspace/coverage/sync_alert/2.prim_sync_alert.299876683
/workspace/coverage/sync_alert/3.prim_sync_alert.4000159784
/workspace/coverage/sync_alert/4.prim_sync_alert.1634109542
/workspace/coverage/sync_alert/5.prim_sync_alert.2222726217
/workspace/coverage/sync_alert/6.prim_sync_alert.3580623173
/workspace/coverage/sync_alert/7.prim_sync_alert.1529306778
/workspace/coverage/sync_alert/8.prim_sync_alert.1879764928
/workspace/coverage/sync_alert/9.prim_sync_alert.532293984
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.779659130
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.10371286
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2765103998
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3703418066
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2218158154
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1002506062
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.862202913
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2850002572
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1055521138
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3602175429
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.587943466
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4078658983
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.685218650
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.505064067
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2070158352
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.255272529
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1610966882
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.605213438
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1827716044



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/12.prim_async_alert.1703637311 Jul 07 04:16:30 PM PDT 24 Jul 07 04:16:31 PM PDT 24 10653049 ps
T2 /workspace/coverage/default/2.prim_async_alert.3002907582 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:31 PM PDT 24 11137049 ps
T3 /workspace/coverage/default/10.prim_async_alert.1338810818 Jul 07 04:16:27 PM PDT 24 Jul 07 04:16:28 PM PDT 24 12542209 ps
T20 /workspace/coverage/default/17.prim_async_alert.3734903966 Jul 07 04:16:31 PM PDT 24 Jul 07 04:16:32 PM PDT 24 10843166 ps
T21 /workspace/coverage/default/11.prim_async_alert.3172737686 Jul 07 04:16:37 PM PDT 24 Jul 07 04:16:37 PM PDT 24 10944335 ps
T7 /workspace/coverage/default/13.prim_async_alert.660647250 Jul 07 04:16:26 PM PDT 24 Jul 07 04:16:27 PM PDT 24 10836772 ps
T22 /workspace/coverage/default/0.prim_async_alert.1491486886 Jul 07 04:16:30 PM PDT 24 Jul 07 04:16:31 PM PDT 24 11093997 ps
T9 /workspace/coverage/default/5.prim_async_alert.2553124990 Jul 07 04:16:26 PM PDT 24 Jul 07 04:16:27 PM PDT 24 12253842 ps
T10 /workspace/coverage/default/16.prim_async_alert.381302207 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:30 PM PDT 24 10650313 ps
T23 /workspace/coverage/default/4.prim_async_alert.321771035 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:30 PM PDT 24 10429806 ps
T14 /workspace/coverage/default/9.prim_async_alert.1834369611 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:30 PM PDT 24 11544617 ps
T11 /workspace/coverage/default/1.prim_async_alert.3086172115 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:30 PM PDT 24 11671154 ps
T8 /workspace/coverage/default/8.prim_async_alert.3038803180 Jul 07 04:16:26 PM PDT 24 Jul 07 04:16:27 PM PDT 24 11199884 ps
T24 /workspace/coverage/default/6.prim_async_alert.3197840143 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:30 PM PDT 24 11714430 ps
T25 /workspace/coverage/default/7.prim_async_alert.955170897 Jul 07 04:16:30 PM PDT 24 Jul 07 04:16:32 PM PDT 24 11273312 ps
T26 /workspace/coverage/default/3.prim_async_alert.549610674 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:31 PM PDT 24 11413271 ps
T47 /workspace/coverage/default/14.prim_async_alert.3972950684 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:30 PM PDT 24 10832075 ps
T48 /workspace/coverage/default/15.prim_async_alert.435820715 Jul 07 04:16:26 PM PDT 24 Jul 07 04:16:27 PM PDT 24 11676006 ps
T49 /workspace/coverage/default/18.prim_async_alert.615481786 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:31 PM PDT 24 11872671 ps
T50 /workspace/coverage/default/19.prim_async_alert.250441354 Jul 07 04:16:27 PM PDT 24 Jul 07 04:16:28 PM PDT 24 10940817 ps
T41 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3777835062 Jul 07 04:16:28 PM PDT 24 Jul 07 04:16:28 PM PDT 24 31073282 ps
T42 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.122348686 Jul 07 04:16:31 PM PDT 24 Jul 07 04:16:32 PM PDT 24 30018465 ps
T4 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.409464637 Jul 07 04:16:27 PM PDT 24 Jul 07 04:16:28 PM PDT 24 30535643 ps
T43 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2829687443 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:30 PM PDT 24 29173712 ps
T15 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.493709232 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:30 PM PDT 24 30980204 ps
T19 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.499633118 Jul 07 04:16:34 PM PDT 24 Jul 07 04:16:34 PM PDT 24 30822655 ps
T44 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3541686356 Jul 07 04:16:26 PM PDT 24 Jul 07 04:16:27 PM PDT 24 27975746 ps
T45 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3016673482 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:30 PM PDT 24 28882242 ps
T46 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2186782938 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:30 PM PDT 24 30695866 ps
T40 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2964040660 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:30 PM PDT 24 31338450 ps
T51 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.804893323 Jul 07 04:16:27 PM PDT 24 Jul 07 04:16:28 PM PDT 24 32426373 ps
T52 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.435335311 Jul 07 04:16:30 PM PDT 24 Jul 07 04:16:31 PM PDT 24 28402898 ps
T53 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.222749047 Jul 07 04:16:26 PM PDT 24 Jul 07 04:16:27 PM PDT 24 31227098 ps
T17 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1649430944 Jul 07 04:16:30 PM PDT 24 Jul 07 04:16:31 PM PDT 24 31564110 ps
T5 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4188307405 Jul 07 04:16:31 PM PDT 24 Jul 07 04:16:32 PM PDT 24 30466222 ps
T54 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.749633166 Jul 07 04:16:30 PM PDT 24 Jul 07 04:16:31 PM PDT 24 29644453 ps
T16 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1714936045 Jul 07 04:16:36 PM PDT 24 Jul 07 04:16:37 PM PDT 24 30955141 ps
T55 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.466222486 Jul 07 04:16:30 PM PDT 24 Jul 07 04:16:31 PM PDT 24 30472834 ps
T56 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1035195451 Jul 07 04:16:28 PM PDT 24 Jul 07 04:16:29 PM PDT 24 29622110 ps
T57 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1766962737 Jul 07 04:16:26 PM PDT 24 Jul 07 04:16:27 PM PDT 24 29336636 ps
T18 /workspace/coverage/sync_alert/17.prim_sync_alert.1449233587 Jul 07 04:46:04 PM PDT 24 Jul 07 04:46:05 PM PDT 24 10194200 ps
T27 /workspace/coverage/sync_alert/15.prim_sync_alert.369337755 Jul 07 04:45:54 PM PDT 24 Jul 07 04:45:55 PM PDT 24 9365372 ps
T36 /workspace/coverage/sync_alert/12.prim_sync_alert.2811639773 Jul 07 04:46:06 PM PDT 24 Jul 07 04:46:07 PM PDT 24 8567268 ps
T28 /workspace/coverage/sync_alert/0.prim_sync_alert.2637212616 Jul 07 04:45:58 PM PDT 24 Jul 07 04:45:59 PM PDT 24 8973932 ps
T29 /workspace/coverage/sync_alert/8.prim_sync_alert.1879764928 Jul 07 04:45:49 PM PDT 24 Jul 07 04:45:50 PM PDT 24 10967081 ps
T37 /workspace/coverage/sync_alert/3.prim_sync_alert.4000159784 Jul 07 04:45:52 PM PDT 24 Jul 07 04:45:53 PM PDT 24 8175591 ps
T30 /workspace/coverage/sync_alert/9.prim_sync_alert.532293984 Jul 07 04:45:50 PM PDT 24 Jul 07 04:45:50 PM PDT 24 8554855 ps
T38 /workspace/coverage/sync_alert/6.prim_sync_alert.3580623173 Jul 07 04:45:47 PM PDT 24 Jul 07 04:45:47 PM PDT 24 8063778 ps
T39 /workspace/coverage/sync_alert/10.prim_sync_alert.3533857144 Jul 07 04:45:53 PM PDT 24 Jul 07 04:45:54 PM PDT 24 9858500 ps
T31 /workspace/coverage/sync_alert/5.prim_sync_alert.2222726217 Jul 07 04:45:53 PM PDT 24 Jul 07 04:45:54 PM PDT 24 9535906 ps
T58 /workspace/coverage/sync_alert/18.prim_sync_alert.2033630187 Jul 07 04:45:53 PM PDT 24 Jul 07 04:45:54 PM PDT 24 9145053 ps
T59 /workspace/coverage/sync_alert/1.prim_sync_alert.80642740 Jul 07 04:45:48 PM PDT 24 Jul 07 04:45:48 PM PDT 24 8676880 ps
T32 /workspace/coverage/sync_alert/13.prim_sync_alert.1948307724 Jul 07 04:45:54 PM PDT 24 Jul 07 04:45:54 PM PDT 24 9216474 ps
T33 /workspace/coverage/sync_alert/14.prim_sync_alert.3881689596 Jul 07 04:46:06 PM PDT 24 Jul 07 04:46:07 PM PDT 24 10652732 ps
T34 /workspace/coverage/sync_alert/19.prim_sync_alert.207702402 Jul 07 04:45:57 PM PDT 24 Jul 07 04:45:58 PM PDT 24 8763320 ps
T60 /workspace/coverage/sync_alert/7.prim_sync_alert.1529306778 Jul 07 04:45:56 PM PDT 24 Jul 07 04:45:57 PM PDT 24 10400396 ps
T61 /workspace/coverage/sync_alert/16.prim_sync_alert.905778400 Jul 07 04:45:48 PM PDT 24 Jul 07 04:45:49 PM PDT 24 9113142 ps
T35 /workspace/coverage/sync_alert/2.prim_sync_alert.299876683 Jul 07 04:45:51 PM PDT 24 Jul 07 04:45:51 PM PDT 24 9093439 ps
T62 /workspace/coverage/sync_alert/11.prim_sync_alert.3632492774 Jul 07 04:46:10 PM PDT 24 Jul 07 04:46:11 PM PDT 24 8378904 ps
T63 /workspace/coverage/sync_alert/4.prim_sync_alert.1634109542 Jul 07 04:46:05 PM PDT 24 Jul 07 04:46:05 PM PDT 24 9163279 ps
T64 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.605213438 Jul 07 04:16:36 PM PDT 24 Jul 07 04:16:37 PM PDT 24 26348811 ps
T65 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1827716044 Jul 07 04:16:28 PM PDT 24 Jul 07 04:16:29 PM PDT 24 28665324 ps
T66 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2070158352 Jul 07 04:16:31 PM PDT 24 Jul 07 04:16:32 PM PDT 24 26466995 ps
T67 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3602175429 Jul 07 04:16:31 PM PDT 24 Jul 07 04:16:32 PM PDT 24 28620696 ps
T68 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.587943466 Jul 07 04:16:36 PM PDT 24 Jul 07 04:16:37 PM PDT 24 26276157 ps
T12 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1055521138 Jul 07 04:16:30 PM PDT 24 Jul 07 04:16:31 PM PDT 24 27234680 ps
T69 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2765103998 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:30 PM PDT 24 27815930 ps
T70 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.10371286 Jul 07 04:16:30 PM PDT 24 Jul 07 04:16:32 PM PDT 24 25972465 ps
T71 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3703418066 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:31 PM PDT 24 27517624 ps
T72 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4078658983 Jul 07 04:16:37 PM PDT 24 Jul 07 04:16:37 PM PDT 24 28039767 ps
T73 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2850002572 Jul 07 04:16:26 PM PDT 24 Jul 07 04:16:27 PM PDT 24 27895757 ps
T74 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1610966882 Jul 07 04:16:31 PM PDT 24 Jul 07 04:16:32 PM PDT 24 27402174 ps
T6 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.862202913 Jul 07 04:16:27 PM PDT 24 Jul 07 04:16:28 PM PDT 24 27602842 ps
T13 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.994473474 Jul 07 04:16:37 PM PDT 24 Jul 07 04:16:37 PM PDT 24 27939078 ps
T75 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.255272529 Jul 07 04:16:30 PM PDT 24 Jul 07 04:16:31 PM PDT 24 29551661 ps
T76 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2218158154 Jul 07 04:16:29 PM PDT 24 Jul 07 04:16:30 PM PDT 24 26913010 ps
T77 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.505064067 Jul 07 04:16:27 PM PDT 24 Jul 07 04:16:28 PM PDT 24 26653143 ps
T78 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.779659130 Jul 07 04:16:34 PM PDT 24 Jul 07 04:16:34 PM PDT 24 25723172 ps
T79 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1002506062 Jul 07 04:16:30 PM PDT 24 Jul 07 04:16:31 PM PDT 24 27712683 ps
T80 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.685218650 Jul 07 04:16:31 PM PDT 24 Jul 07 04:16:32 PM PDT 24 29584026 ps

Test location /workspace/coverage/default/16.prim_async_alert.381302207
Short name T10
Test name
Test status
Simulation time 10650313 ps
CPU time 0.39 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:30 PM PDT 24
Peak memory 145700 kb
Host smart-7a309b84-e421-4157-bb3d-07e836246045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381302207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.381302207
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.369337755
Short name T27
Test name
Test status
Simulation time 9365372 ps
CPU time 0.41 seconds
Started Jul 07 04:45:54 PM PDT 24
Finished Jul 07 04:45:55 PM PDT 24
Peak memory 145424 kb
Host smart-5081a334-ab69-4331-9b2a-e3f7996e45a0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=369337755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.369337755
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.493709232
Short name T15
Test name
Test status
Simulation time 30980204 ps
CPU time 0.4 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:30 PM PDT 24
Peak memory 145240 kb
Host smart-d48dcbc6-e0b0-44d0-bc7a-7b862e13683b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=493709232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.493709232
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.409464637
Short name T4
Test name
Test status
Simulation time 30535643 ps
CPU time 0.41 seconds
Started Jul 07 04:16:27 PM PDT 24
Finished Jul 07 04:16:28 PM PDT 24
Peak memory 145260 kb
Host smart-ffbab36a-43d5-468e-96a4-1a6569ebc4d8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=409464637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.409464637
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.994473474
Short name T13
Test name
Test status
Simulation time 27939078 ps
CPU time 0.4 seconds
Started Jul 07 04:16:37 PM PDT 24
Finished Jul 07 04:16:37 PM PDT 24
Peak memory 145764 kb
Host smart-06bad21c-62cb-4b84-98fb-887557381c11
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=994473474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.994473474
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1491486886
Short name T22
Test name
Test status
Simulation time 11093997 ps
CPU time 0.39 seconds
Started Jul 07 04:16:30 PM PDT 24
Finished Jul 07 04:16:31 PM PDT 24
Peak memory 145708 kb
Host smart-5e5348d4-1353-4fe5-ba42-6a3efff42743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491486886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1491486886
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3086172115
Short name T11
Test name
Test status
Simulation time 11671154 ps
CPU time 0.43 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:30 PM PDT 24
Peak memory 144944 kb
Host smart-2fa01197-8acd-43c2-8917-99ca5d5b671d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086172115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3086172115
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1338810818
Short name T3
Test name
Test status
Simulation time 12542209 ps
CPU time 0.39 seconds
Started Jul 07 04:16:27 PM PDT 24
Finished Jul 07 04:16:28 PM PDT 24
Peak memory 145716 kb
Host smart-350ceeab-1c13-4e51-ade0-f6667450c936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338810818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1338810818
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3172737686
Short name T21
Test name
Test status
Simulation time 10944335 ps
CPU time 0.4 seconds
Started Jul 07 04:16:37 PM PDT 24
Finished Jul 07 04:16:37 PM PDT 24
Peak memory 145944 kb
Host smart-c06b488f-fc45-433e-9dbb-35f8e2f9012c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172737686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3172737686
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1703637311
Short name T1
Test name
Test status
Simulation time 10653049 ps
CPU time 0.38 seconds
Started Jul 07 04:16:30 PM PDT 24
Finished Jul 07 04:16:31 PM PDT 24
Peak memory 145172 kb
Host smart-3cc37de6-908e-44bf-b64d-2c7222740135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703637311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1703637311
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.660647250
Short name T7
Test name
Test status
Simulation time 10836772 ps
CPU time 0.38 seconds
Started Jul 07 04:16:26 PM PDT 24
Finished Jul 07 04:16:27 PM PDT 24
Peak memory 145704 kb
Host smart-ee77ecc0-a50a-4e54-8f21-a68c51841cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660647250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.660647250
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.3972950684
Short name T47
Test name
Test status
Simulation time 10832075 ps
CPU time 0.43 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:30 PM PDT 24
Peak memory 144904 kb
Host smart-feca5a1c-dbf3-4010-9680-7fef180440df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972950684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3972950684
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.435820715
Short name T48
Test name
Test status
Simulation time 11676006 ps
CPU time 0.39 seconds
Started Jul 07 04:16:26 PM PDT 24
Finished Jul 07 04:16:27 PM PDT 24
Peak memory 145704 kb
Host smart-84a5e2eb-bef7-430c-b9c7-947d4ca3ac11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435820715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.435820715
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3734903966
Short name T20
Test name
Test status
Simulation time 10843166 ps
CPU time 0.39 seconds
Started Jul 07 04:16:31 PM PDT 24
Finished Jul 07 04:16:32 PM PDT 24
Peak memory 145708 kb
Host smart-e65b5f06-b001-4f86-8e29-9a85bd2098de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734903966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3734903966
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.615481786
Short name T49
Test name
Test status
Simulation time 11872671 ps
CPU time 0.39 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:31 PM PDT 24
Peak memory 145212 kb
Host smart-6c88b542-524c-42b9-9cff-c08c57491fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615481786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.615481786
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.250441354
Short name T50
Test name
Test status
Simulation time 10940817 ps
CPU time 0.38 seconds
Started Jul 07 04:16:27 PM PDT 24
Finished Jul 07 04:16:28 PM PDT 24
Peak memory 145300 kb
Host smart-9c77fdbb-7598-42b8-be80-de5ff8fd1da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250441354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.250441354
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3002907582
Short name T2
Test name
Test status
Simulation time 11137049 ps
CPU time 0.41 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:31 PM PDT 24
Peak memory 145944 kb
Host smart-94196895-ebf6-4a49-9767-a3636e802e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002907582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3002907582
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.549610674
Short name T26
Test name
Test status
Simulation time 11413271 ps
CPU time 0.39 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:31 PM PDT 24
Peak memory 145212 kb
Host smart-bd5fab68-afe4-49c6-b172-f427134c10c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549610674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.549610674
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.321771035
Short name T23
Test name
Test status
Simulation time 10429806 ps
CPU time 0.38 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:30 PM PDT 24
Peak memory 145152 kb
Host smart-593ddeae-8dff-453a-b304-6833ddedb6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321771035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.321771035
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2553124990
Short name T9
Test name
Test status
Simulation time 12253842 ps
CPU time 0.5 seconds
Started Jul 07 04:16:26 PM PDT 24
Finished Jul 07 04:16:27 PM PDT 24
Peak memory 145572 kb
Host smart-8ccbe749-af4a-419c-a4df-1052b5cb9913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553124990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2553124990
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3197840143
Short name T24
Test name
Test status
Simulation time 11714430 ps
CPU time 0.41 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:30 PM PDT 24
Peak memory 145104 kb
Host smart-94b5cab7-6b16-46f5-bc98-a346d449c026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197840143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3197840143
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.955170897
Short name T25
Test name
Test status
Simulation time 11273312 ps
CPU time 0.38 seconds
Started Jul 07 04:16:30 PM PDT 24
Finished Jul 07 04:16:32 PM PDT 24
Peak memory 145708 kb
Host smart-7f9cdd8b-2227-43fd-978b-a3bdc6811118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955170897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.955170897
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3038803180
Short name T8
Test name
Test status
Simulation time 11199884 ps
CPU time 0.37 seconds
Started Jul 07 04:16:26 PM PDT 24
Finished Jul 07 04:16:27 PM PDT 24
Peak memory 146200 kb
Host smart-235ae3f0-43a3-4004-a2ca-3eee39eb27de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038803180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3038803180
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1834369611
Short name T14
Test name
Test status
Simulation time 11544617 ps
CPU time 0.39 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:30 PM PDT 24
Peak memory 145704 kb
Host smart-df01a5ad-db66-4f1a-9f1d-f0ae7306ccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834369611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1834369611
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2186782938
Short name T46
Test name
Test status
Simulation time 30695866 ps
CPU time 0.4 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:30 PM PDT 24
Peak memory 145444 kb
Host smart-0381aa57-28bd-42c3-b74b-54ba221845ef
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2186782938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2186782938
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3541686356
Short name T44
Test name
Test status
Simulation time 27975746 ps
CPU time 0.42 seconds
Started Jul 07 04:16:26 PM PDT 24
Finished Jul 07 04:16:27 PM PDT 24
Peak memory 144880 kb
Host smart-bc4bae98-3756-4c63-b3a1-a256bb16b304
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3541686356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3541686356
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1035195451
Short name T56
Test name
Test status
Simulation time 29622110 ps
CPU time 0.4 seconds
Started Jul 07 04:16:28 PM PDT 24
Finished Jul 07 04:16:29 PM PDT 24
Peak memory 145160 kb
Host smart-36263598-ea13-4c1f-8fba-c08cbd3c634e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1035195451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1035195451
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3777835062
Short name T41
Test name
Test status
Simulation time 31073282 ps
CPU time 0.4 seconds
Started Jul 07 04:16:28 PM PDT 24
Finished Jul 07 04:16:28 PM PDT 24
Peak memory 144956 kb
Host smart-91d85377-fa90-49ba-add7-15d3f8b10976
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3777835062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3777835062
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2964040660
Short name T40
Test name
Test status
Simulation time 31338450 ps
CPU time 0.41 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:30 PM PDT 24
Peak memory 146708 kb
Host smart-bb4f8e18-cb5a-4954-a360-b288f7fc08b5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2964040660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2964040660
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.804893323
Short name T51
Test name
Test status
Simulation time 32426373 ps
CPU time 0.4 seconds
Started Jul 07 04:16:27 PM PDT 24
Finished Jul 07 04:16:28 PM PDT 24
Peak memory 145260 kb
Host smart-dbf7eee5-4435-45db-a2e7-e228e9cc03d5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=804893323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.804893323
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.466222486
Short name T55
Test name
Test status
Simulation time 30472834 ps
CPU time 0.4 seconds
Started Jul 07 04:16:30 PM PDT 24
Finished Jul 07 04:16:31 PM PDT 24
Peak memory 145208 kb
Host smart-3fea53ac-1d23-4018-ade3-212d2a40e8e9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=466222486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.466222486
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.122348686
Short name T42
Test name
Test status
Simulation time 30018465 ps
CPU time 0.4 seconds
Started Jul 07 04:16:31 PM PDT 24
Finished Jul 07 04:16:32 PM PDT 24
Peak memory 145272 kb
Host smart-c4551070-7a05-4633-82d2-5a1d53981717
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=122348686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.122348686
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2829687443
Short name T43
Test name
Test status
Simulation time 29173712 ps
CPU time 0.4 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:30 PM PDT 24
Peak memory 145232 kb
Host smart-91fc65fd-386d-49d2-8fc8-033ad5d6da6d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2829687443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2829687443
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.749633166
Short name T54
Test name
Test status
Simulation time 29644453 ps
CPU time 0.4 seconds
Started Jul 07 04:16:30 PM PDT 24
Finished Jul 07 04:16:31 PM PDT 24
Peak memory 145432 kb
Host smart-782e7d0a-6901-4536-96ef-fddb911328d3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=749633166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.749633166
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1766962737
Short name T57
Test name
Test status
Simulation time 29336636 ps
CPU time 0.39 seconds
Started Jul 07 04:16:26 PM PDT 24
Finished Jul 07 04:16:27 PM PDT 24
Peak memory 144960 kb
Host smart-a74c01d2-34d0-426e-a27e-75a34afef140
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1766962737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1766962737
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3016673482
Short name T45
Test name
Test status
Simulation time 28882242 ps
CPU time 0.45 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:30 PM PDT 24
Peak memory 144368 kb
Host smart-9ea416e0-4ee1-4c81-86f7-6a97ff726c78
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3016673482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3016673482
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.499633118
Short name T19
Test name
Test status
Simulation time 30822655 ps
CPU time 0.39 seconds
Started Jul 07 04:16:34 PM PDT 24
Finished Jul 07 04:16:34 PM PDT 24
Peak memory 144996 kb
Host smart-f3c2a19d-260a-47ef-9a2d-1006354a2c2d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=499633118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.499633118
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4188307405
Short name T5
Test name
Test status
Simulation time 30466222 ps
CPU time 0.39 seconds
Started Jul 07 04:16:31 PM PDT 24
Finished Jul 07 04:16:32 PM PDT 24
Peak memory 145264 kb
Host smart-4c1bba03-6f26-4b11-a58f-c628c4616348
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4188307405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.4188307405
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1649430944
Short name T17
Test name
Test status
Simulation time 31564110 ps
CPU time 0.41 seconds
Started Jul 07 04:16:30 PM PDT 24
Finished Jul 07 04:16:31 PM PDT 24
Peak memory 145192 kb
Host smart-831cfd8f-c09b-4fa6-8578-659748fb1e5d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1649430944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1649430944
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.222749047
Short name T53
Test name
Test status
Simulation time 31227098 ps
CPU time 0.4 seconds
Started Jul 07 04:16:26 PM PDT 24
Finished Jul 07 04:16:27 PM PDT 24
Peak memory 144760 kb
Host smart-21119d72-764d-4832-8b1e-c73ca7040d6c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=222749047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.222749047
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.435335311
Short name T52
Test name
Test status
Simulation time 28402898 ps
CPU time 0.39 seconds
Started Jul 07 04:16:30 PM PDT 24
Finished Jul 07 04:16:31 PM PDT 24
Peak memory 144752 kb
Host smart-0cbfbb4c-0523-43f9-8f78-236a898f355b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=435335311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.435335311
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1714936045
Short name T16
Test name
Test status
Simulation time 30955141 ps
CPU time 0.39 seconds
Started Jul 07 04:16:36 PM PDT 24
Finished Jul 07 04:16:37 PM PDT 24
Peak memory 145256 kb
Host smart-959f6f8e-294d-4a7c-8039-5fa3ce201693
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1714936045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1714936045
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2637212616
Short name T28
Test name
Test status
Simulation time 8973932 ps
CPU time 0.39 seconds
Started Jul 07 04:45:58 PM PDT 24
Finished Jul 07 04:45:59 PM PDT 24
Peak memory 145428 kb
Host smart-c4cdbf54-519a-4643-9e2d-b1d398b6812b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2637212616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2637212616
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.80642740
Short name T59
Test name
Test status
Simulation time 8676880 ps
CPU time 0.38 seconds
Started Jul 07 04:45:48 PM PDT 24
Finished Jul 07 04:45:48 PM PDT 24
Peak memory 145424 kb
Host smart-d506a428-8d56-4fd5-a8ba-b9cf51453add
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=80642740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.80642740
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3533857144
Short name T39
Test name
Test status
Simulation time 9858500 ps
CPU time 0.41 seconds
Started Jul 07 04:45:53 PM PDT 24
Finished Jul 07 04:45:54 PM PDT 24
Peak memory 145396 kb
Host smart-defc0c81-72ea-4bdb-a2e2-98f66374e363
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3533857144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3533857144
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3632492774
Short name T62
Test name
Test status
Simulation time 8378904 ps
CPU time 0.4 seconds
Started Jul 07 04:46:10 PM PDT 24
Finished Jul 07 04:46:11 PM PDT 24
Peak memory 145416 kb
Host smart-35071919-ae2d-47ce-8e8e-0e3e383fcd85
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3632492774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3632492774
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2811639773
Short name T36
Test name
Test status
Simulation time 8567268 ps
CPU time 0.39 seconds
Started Jul 07 04:46:06 PM PDT 24
Finished Jul 07 04:46:07 PM PDT 24
Peak memory 145520 kb
Host smart-788dc87c-5ecb-4a85-92a2-502c6b7e14f9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2811639773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2811639773
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1948307724
Short name T32
Test name
Test status
Simulation time 9216474 ps
CPU time 0.4 seconds
Started Jul 07 04:45:54 PM PDT 24
Finished Jul 07 04:45:54 PM PDT 24
Peak memory 145416 kb
Host smart-c93155bb-a4e8-4dec-a82b-c7397eaeae4e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1948307724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1948307724
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3881689596
Short name T33
Test name
Test status
Simulation time 10652732 ps
CPU time 0.39 seconds
Started Jul 07 04:46:06 PM PDT 24
Finished Jul 07 04:46:07 PM PDT 24
Peak memory 145524 kb
Host smart-2014f27d-4434-4fe0-b3b1-87535f408f64
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3881689596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3881689596
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.905778400
Short name T61
Test name
Test status
Simulation time 9113142 ps
CPU time 0.38 seconds
Started Jul 07 04:45:48 PM PDT 24
Finished Jul 07 04:45:49 PM PDT 24
Peak memory 145464 kb
Host smart-c8349d46-ba24-43fd-89c9-a8f3be30e668
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=905778400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.905778400
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1449233587
Short name T18
Test name
Test status
Simulation time 10194200 ps
CPU time 0.37 seconds
Started Jul 07 04:46:04 PM PDT 24
Finished Jul 07 04:46:05 PM PDT 24
Peak memory 145404 kb
Host smart-09ceebdc-d056-4937-b384-ccb587495b45
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1449233587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1449233587
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2033630187
Short name T58
Test name
Test status
Simulation time 9145053 ps
CPU time 0.39 seconds
Started Jul 07 04:45:53 PM PDT 24
Finished Jul 07 04:45:54 PM PDT 24
Peak memory 145380 kb
Host smart-34fee705-9adc-4dfc-bb12-314d7df3afc8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2033630187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2033630187
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.207702402
Short name T34
Test name
Test status
Simulation time 8763320 ps
CPU time 0.36 seconds
Started Jul 07 04:45:57 PM PDT 24
Finished Jul 07 04:45:58 PM PDT 24
Peak memory 145404 kb
Host smart-ef3e9647-2601-44df-874e-bd83c33c801a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=207702402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.207702402
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.299876683
Short name T35
Test name
Test status
Simulation time 9093439 ps
CPU time 0.38 seconds
Started Jul 07 04:45:51 PM PDT 24
Finished Jul 07 04:45:51 PM PDT 24
Peak memory 145432 kb
Host smart-7874e308-c632-493c-9427-f1c685c474a6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=299876683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.299876683
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.4000159784
Short name T37
Test name
Test status
Simulation time 8175591 ps
CPU time 0.38 seconds
Started Jul 07 04:45:52 PM PDT 24
Finished Jul 07 04:45:53 PM PDT 24
Peak memory 145412 kb
Host smart-852e06a9-5066-4c65-a56b-67eacc0eb2ef
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4000159784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.4000159784
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1634109542
Short name T63
Test name
Test status
Simulation time 9163279 ps
CPU time 0.41 seconds
Started Jul 07 04:46:05 PM PDT 24
Finished Jul 07 04:46:05 PM PDT 24
Peak memory 145528 kb
Host smart-28ec40dd-5eea-44b0-acf1-9368b33fa6e1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1634109542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1634109542
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2222726217
Short name T31
Test name
Test status
Simulation time 9535906 ps
CPU time 0.38 seconds
Started Jul 07 04:45:53 PM PDT 24
Finished Jul 07 04:45:54 PM PDT 24
Peak memory 145424 kb
Host smart-229bb8b9-ac39-4413-8c4f-2cb2babd2285
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2222726217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2222726217
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3580623173
Short name T38
Test name
Test status
Simulation time 8063778 ps
CPU time 0.39 seconds
Started Jul 07 04:45:47 PM PDT 24
Finished Jul 07 04:45:47 PM PDT 24
Peak memory 145420 kb
Host smart-9cf8bf45-d51c-4558-ac89-96af52dde6a1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3580623173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3580623173
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1529306778
Short name T60
Test name
Test status
Simulation time 10400396 ps
CPU time 0.37 seconds
Started Jul 07 04:45:56 PM PDT 24
Finished Jul 07 04:45:57 PM PDT 24
Peak memory 145428 kb
Host smart-c42941e3-332e-4913-adf2-e2a5c7219820
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1529306778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1529306778
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1879764928
Short name T29
Test name
Test status
Simulation time 10967081 ps
CPU time 0.39 seconds
Started Jul 07 04:45:49 PM PDT 24
Finished Jul 07 04:45:50 PM PDT 24
Peak memory 145420 kb
Host smart-6c5b9be9-2bfd-4746-b3ae-fe231c311a3e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1879764928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1879764928
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.532293984
Short name T30
Test name
Test status
Simulation time 8554855 ps
CPU time 0.39 seconds
Started Jul 07 04:45:50 PM PDT 24
Finished Jul 07 04:45:50 PM PDT 24
Peak memory 145428 kb
Host smart-e23b6881-edec-44cb-9540-b65f1a7b17a5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=532293984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.532293984
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.779659130
Short name T78
Test name
Test status
Simulation time 25723172 ps
CPU time 0.38 seconds
Started Jul 07 04:16:34 PM PDT 24
Finished Jul 07 04:16:34 PM PDT 24
Peak memory 145260 kb
Host smart-63d692b0-4be9-412d-868a-8f341b7ec620
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=779659130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.779659130
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.10371286
Short name T70
Test name
Test status
Simulation time 25972465 ps
CPU time 0.4 seconds
Started Jul 07 04:16:30 PM PDT 24
Finished Jul 07 04:16:32 PM PDT 24
Peak memory 145492 kb
Host smart-c39e1b58-6cb2-4b13-8057-b2ec193ee149
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=10371286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.10371286
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2765103998
Short name T69
Test name
Test status
Simulation time 27815930 ps
CPU time 0.41 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:30 PM PDT 24
Peak memory 146928 kb
Host smart-92e3c0b8-8008-48db-bebf-10eca4ca7c46
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2765103998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2765103998
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3703418066
Short name T71
Test name
Test status
Simulation time 27517624 ps
CPU time 0.4 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:31 PM PDT 24
Peak memory 145528 kb
Host smart-e9498927-4bf9-4811-a95a-4159b4c10768
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3703418066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3703418066
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2218158154
Short name T76
Test name
Test status
Simulation time 26913010 ps
CPU time 0.48 seconds
Started Jul 07 04:16:29 PM PDT 24
Finished Jul 07 04:16:30 PM PDT 24
Peak memory 144720 kb
Host smart-5900824c-0d94-4d5d-91ab-bacec6b39d2a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2218158154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2218158154
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1002506062
Short name T79
Test name
Test status
Simulation time 27712683 ps
CPU time 0.4 seconds
Started Jul 07 04:16:30 PM PDT 24
Finished Jul 07 04:16:31 PM PDT 24
Peak memory 145528 kb
Host smart-d4c9d71f-65fa-41c3-9b9e-e5326ff38f3e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1002506062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1002506062
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.862202913
Short name T6
Test name
Test status
Simulation time 27602842 ps
CPU time 0.41 seconds
Started Jul 07 04:16:27 PM PDT 24
Finished Jul 07 04:16:28 PM PDT 24
Peak memory 145524 kb
Host smart-9d744073-6de7-4e55-b4d0-db79baf3845d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=862202913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.862202913
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2850002572
Short name T73
Test name
Test status
Simulation time 27895757 ps
CPU time 0.39 seconds
Started Jul 07 04:16:26 PM PDT 24
Finished Jul 07 04:16:27 PM PDT 24
Peak memory 145068 kb
Host smart-bd73508b-f9d5-4982-8588-42d5b5256df8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2850002572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2850002572
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1055521138
Short name T12
Test name
Test status
Simulation time 27234680 ps
CPU time 0.4 seconds
Started Jul 07 04:16:30 PM PDT 24
Finished Jul 07 04:16:31 PM PDT 24
Peak memory 145696 kb
Host smart-7ea661ca-725e-4294-bdb0-bb02aaf4b058
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1055521138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1055521138
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3602175429
Short name T67
Test name
Test status
Simulation time 28620696 ps
CPU time 0.4 seconds
Started Jul 07 04:16:31 PM PDT 24
Finished Jul 07 04:16:32 PM PDT 24
Peak memory 145524 kb
Host smart-f1b1f69a-5182-468b-aceb-c7be97e50315
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3602175429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3602175429
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.587943466
Short name T68
Test name
Test status
Simulation time 26276157 ps
CPU time 0.4 seconds
Started Jul 07 04:16:36 PM PDT 24
Finished Jul 07 04:16:37 PM PDT 24
Peak memory 145756 kb
Host smart-5da04e71-2f09-43c1-af6c-bc36c1fbd6b9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=587943466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.587943466
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4078658983
Short name T72
Test name
Test status
Simulation time 28039767 ps
CPU time 0.39 seconds
Started Jul 07 04:16:37 PM PDT 24
Finished Jul 07 04:16:37 PM PDT 24
Peak memory 145528 kb
Host smart-03ed35c0-ba05-4e80-a18c-ce4b9097d176
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4078658983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.4078658983
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.685218650
Short name T80
Test name
Test status
Simulation time 29584026 ps
CPU time 0.4 seconds
Started Jul 07 04:16:31 PM PDT 24
Finished Jul 07 04:16:32 PM PDT 24
Peak memory 145440 kb
Host smart-37eea6d0-69f1-47b2-b189-8b24d7dc4603
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=685218650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.685218650
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.505064067
Short name T77
Test name
Test status
Simulation time 26653143 ps
CPU time 0.4 seconds
Started Jul 07 04:16:27 PM PDT 24
Finished Jul 07 04:16:28 PM PDT 24
Peak memory 145096 kb
Host smart-1fe2cc2d-f43e-4179-8ccf-03548c5621aa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=505064067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.505064067
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2070158352
Short name T66
Test name
Test status
Simulation time 26466995 ps
CPU time 0.39 seconds
Started Jul 07 04:16:31 PM PDT 24
Finished Jul 07 04:16:32 PM PDT 24
Peak memory 145528 kb
Host smart-361f858d-b98c-4cd1-8e29-8f37a374f7a5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2070158352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2070158352
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.255272529
Short name T75
Test name
Test status
Simulation time 29551661 ps
CPU time 0.4 seconds
Started Jul 07 04:16:30 PM PDT 24
Finished Jul 07 04:16:31 PM PDT 24
Peak memory 145520 kb
Host smart-9bdd42d9-6de5-4d49-833e-cc00470a30e9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=255272529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.255272529
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1610966882
Short name T74
Test name
Test status
Simulation time 27402174 ps
CPU time 0.38 seconds
Started Jul 07 04:16:31 PM PDT 24
Finished Jul 07 04:16:32 PM PDT 24
Peak memory 145500 kb
Host smart-13966737-88a4-4fd1-9910-4e5bec2377bf
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1610966882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1610966882
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.605213438
Short name T64
Test name
Test status
Simulation time 26348811 ps
CPU time 0.39 seconds
Started Jul 07 04:16:36 PM PDT 24
Finished Jul 07 04:16:37 PM PDT 24
Peak memory 145760 kb
Host smart-eb5f7b03-48c8-4315-a7e7-c69f5096fbb4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=605213438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.605213438
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1827716044
Short name T65
Test name
Test status
Simulation time 28665324 ps
CPU time 0.4 seconds
Started Jul 07 04:16:28 PM PDT 24
Finished Jul 07 04:16:29 PM PDT 24
Peak memory 145760 kb
Host smart-08a54a39-81ee-4fde-8fe4-a0c91bf5f6f1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1827716044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1827716044
Directory /workspace/9.prim_sync_fatal_alert/latest
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