Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.32 88.32 100.00 100.00 91.67 91.67 100.00 100.00 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/14.prim_async_alert.2943589246
91.45 3.13 100.00 0.00 91.67 0.00 100.00 0.00 82.14 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/14.prim_sync_alert.4149523441
93.56 2.11 100.00 0.00 93.75 2.08 100.00 0.00 85.71 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1609027475
94.50 0.94 100.00 0.00 95.83 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4549236
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/1.prim_async_alert.2369288629
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/16.prim_sync_alert.304096194

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.699785538
/workspace/coverage/default/10.prim_async_alert.1224370422
/workspace/coverage/default/12.prim_async_alert.795133336
/workspace/coverage/default/13.prim_async_alert.2604270908
/workspace/coverage/default/15.prim_async_alert.3077815300
/workspace/coverage/default/16.prim_async_alert.3731971406
/workspace/coverage/default/17.prim_async_alert.1161902533
/workspace/coverage/default/18.prim_async_alert.272689607
/workspace/coverage/default/19.prim_async_alert.2328868623
/workspace/coverage/default/2.prim_async_alert.1427161908
/workspace/coverage/default/3.prim_async_alert.1739847738
/workspace/coverage/default/4.prim_async_alert.2598820827
/workspace/coverage/default/5.prim_async_alert.2270163280
/workspace/coverage/default/6.prim_async_alert.531375173
/workspace/coverage/default/7.prim_async_alert.863350646
/workspace/coverage/default/8.prim_async_alert.3085931134
/workspace/coverage/default/9.prim_async_alert.1039246207
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2899009248
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3831215452
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3371606684
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1993692838
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2372402737
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4122592406
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1136967321
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.569999593
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2326416166
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3670779837
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3811034062
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4168403807
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.476109724
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1032865869
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2434654555
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3861245812
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2116879984
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1776583771
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2769626030
/workspace/coverage/sync_alert/0.prim_sync_alert.2546983399
/workspace/coverage/sync_alert/1.prim_sync_alert.773441991
/workspace/coverage/sync_alert/10.prim_sync_alert.692938338
/workspace/coverage/sync_alert/11.prim_sync_alert.1824195343
/workspace/coverage/sync_alert/12.prim_sync_alert.1392546540
/workspace/coverage/sync_alert/13.prim_sync_alert.1865470240
/workspace/coverage/sync_alert/15.prim_sync_alert.1806524176
/workspace/coverage/sync_alert/17.prim_sync_alert.3547201995
/workspace/coverage/sync_alert/18.prim_sync_alert.2832465087
/workspace/coverage/sync_alert/19.prim_sync_alert.1987101813
/workspace/coverage/sync_alert/2.prim_sync_alert.2044092642
/workspace/coverage/sync_alert/3.prim_sync_alert.2222437734
/workspace/coverage/sync_alert/4.prim_sync_alert.3245401229
/workspace/coverage/sync_alert/5.prim_sync_alert.2911233993
/workspace/coverage/sync_alert/6.prim_sync_alert.3229288287
/workspace/coverage/sync_alert/7.prim_sync_alert.936008367
/workspace/coverage/sync_alert/8.prim_sync_alert.2995407056
/workspace/coverage/sync_alert/9.prim_sync_alert.3341797125
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1684628637
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2655811974
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1890940995
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3449882428
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.51931873
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1042616704
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3453870764
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2924894173
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3444598572
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2317554207
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1729718521
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2270792196
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1591322290
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1760060688
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1618551695
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3268788102
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3416983206
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1532566111
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3731238800



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/6.prim_async_alert.531375173 Jul 09 04:25:23 PM PDT 24 Jul 09 04:25:24 PM PDT 24 11211901 ps
T2 /workspace/coverage/default/18.prim_async_alert.272689607 Jul 09 04:27:18 PM PDT 24 Jul 09 04:27:22 PM PDT 24 10659290 ps
T3 /workspace/coverage/default/9.prim_async_alert.1039246207 Jul 09 04:25:22 PM PDT 24 Jul 09 04:25:22 PM PDT 24 11177737 ps
T12 /workspace/coverage/default/14.prim_async_alert.2943589246 Jul 09 04:26:42 PM PDT 24 Jul 09 04:26:45 PM PDT 24 11848302 ps
T8 /workspace/coverage/default/10.prim_async_alert.1224370422 Jul 09 04:22:29 PM PDT 24 Jul 09 04:22:30 PM PDT 24 10555040 ps
T7 /workspace/coverage/default/12.prim_async_alert.795133336 Jul 09 04:27:05 PM PDT 24 Jul 09 04:27:11 PM PDT 24 11277110 ps
T19 /workspace/coverage/default/17.prim_async_alert.1161902533 Jul 09 04:26:50 PM PDT 24 Jul 09 04:26:51 PM PDT 24 10611876 ps
T20 /workspace/coverage/default/3.prim_async_alert.1739847738 Jul 09 04:26:38 PM PDT 24 Jul 09 04:26:39 PM PDT 24 11326250 ps
T21 /workspace/coverage/default/16.prim_async_alert.3731971406 Jul 09 04:27:07 PM PDT 24 Jul 09 04:27:14 PM PDT 24 10686378 ps
T22 /workspace/coverage/default/7.prim_async_alert.863350646 Jul 09 04:26:54 PM PDT 24 Jul 09 04:27:00 PM PDT 24 10363047 ps
T13 /workspace/coverage/default/19.prim_async_alert.2328868623 Jul 09 04:27:28 PM PDT 24 Jul 09 04:27:34 PM PDT 24 11439411 ps
T23 /workspace/coverage/default/2.prim_async_alert.1427161908 Jul 09 04:24:46 PM PDT 24 Jul 09 04:24:47 PM PDT 24 11592273 ps
T25 /workspace/coverage/default/13.prim_async_alert.2604270908 Jul 09 04:26:43 PM PDT 24 Jul 09 04:26:46 PM PDT 24 11328811 ps
T24 /workspace/coverage/default/4.prim_async_alert.2598820827 Jul 09 04:27:31 PM PDT 24 Jul 09 04:27:38 PM PDT 24 11896550 ps
T26 /workspace/coverage/default/0.prim_async_alert.699785538 Jul 09 04:25:30 PM PDT 24 Jul 09 04:25:30 PM PDT 24 11073539 ps
T27 /workspace/coverage/default/1.prim_async_alert.2369288629 Jul 09 04:22:54 PM PDT 24 Jul 09 04:22:55 PM PDT 24 10911107 ps
T51 /workspace/coverage/default/15.prim_async_alert.3077815300 Jul 09 04:27:07 PM PDT 24 Jul 09 04:27:14 PM PDT 24 10500783 ps
T52 /workspace/coverage/default/8.prim_async_alert.3085931134 Jul 09 04:23:54 PM PDT 24 Jul 09 04:23:54 PM PDT 24 11075882 ps
T53 /workspace/coverage/default/5.prim_async_alert.2270163280 Jul 09 04:26:40 PM PDT 24 Jul 09 04:26:44 PM PDT 24 10546512 ps
T14 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3811034062 Jul 09 04:37:29 PM PDT 24 Jul 09 04:37:31 PM PDT 24 29852823 ps
T4 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2769626030 Jul 09 04:26:41 PM PDT 24 Jul 09 04:26:44 PM PDT 24 30223754 ps
T46 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2326416166 Jul 09 04:37:28 PM PDT 24 Jul 09 04:37:28 PM PDT 24 30765919 ps
T17 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4122592406 Jul 09 04:37:29 PM PDT 24 Jul 09 04:37:30 PM PDT 24 30892077 ps
T47 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.569999593 Jul 09 04:37:29 PM PDT 24 Jul 09 04:37:31 PM PDT 24 29563005 ps
T48 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1993692838 Jul 09 04:37:29 PM PDT 24 Jul 09 04:37:30 PM PDT 24 29693341 ps
T43 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1776583771 Jul 09 04:23:52 PM PDT 24 Jul 09 04:23:53 PM PDT 24 29381504 ps
T44 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1609027475 Jul 09 04:37:30 PM PDT 24 Jul 09 04:37:32 PM PDT 24 30524039 ps
T49 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3861245812 Jul 09 04:26:13 PM PDT 24 Jul 09 04:26:14 PM PDT 24 30223571 ps
T50 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2899009248 Jul 09 04:27:27 PM PDT 24 Jul 09 04:27:34 PM PDT 24 27815707 ps
T18 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1136967321 Jul 09 04:37:29 PM PDT 24 Jul 09 04:37:30 PM PDT 24 30990300 ps
T5 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1032865869 Jul 09 04:26:52 PM PDT 24 Jul 09 04:26:54 PM PDT 24 29522045 ps
T54 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.476109724 Jul 09 04:27:10 PM PDT 24 Jul 09 04:27:17 PM PDT 24 31096161 ps
T55 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3831215452 Jul 09 04:27:27 PM PDT 24 Jul 09 04:27:34 PM PDT 24 30305527 ps
T56 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2434654555 Jul 09 04:27:43 PM PDT 24 Jul 09 04:27:59 PM PDT 24 29810478 ps
T57 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4168403807 Jul 09 04:27:44 PM PDT 24 Jul 09 04:27:45 PM PDT 24 29998334 ps
T58 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3371606684 Jul 09 04:37:30 PM PDT 24 Jul 09 04:37:33 PM PDT 24 32084520 ps
T45 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2372402737 Jul 09 04:37:29 PM PDT 24 Jul 09 04:37:30 PM PDT 24 29626653 ps
T59 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3670779837 Jul 09 04:37:30 PM PDT 24 Jul 09 04:37:33 PM PDT 24 31073755 ps
T60 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2116879984 Jul 09 04:24:45 PM PDT 24 Jul 09 04:24:46 PM PDT 24 27968449 ps
T28 /workspace/coverage/sync_alert/1.prim_sync_alert.773441991 Jul 09 04:39:45 PM PDT 24 Jul 09 04:39:47 PM PDT 24 9029776 ps
T37 /workspace/coverage/sync_alert/3.prim_sync_alert.2222437734 Jul 09 04:39:46 PM PDT 24 Jul 09 04:39:48 PM PDT 24 9393771 ps
T38 /workspace/coverage/sync_alert/2.prim_sync_alert.2044092642 Jul 09 04:39:44 PM PDT 24 Jul 09 04:39:46 PM PDT 24 10420413 ps
T29 /workspace/coverage/sync_alert/12.prim_sync_alert.1392546540 Jul 09 04:39:52 PM PDT 24 Jul 09 04:39:53 PM PDT 24 9159385 ps
T30 /workspace/coverage/sync_alert/9.prim_sync_alert.3341797125 Jul 09 04:39:46 PM PDT 24 Jul 09 04:39:48 PM PDT 24 9145183 ps
T39 /workspace/coverage/sync_alert/6.prim_sync_alert.3229288287 Jul 09 04:39:44 PM PDT 24 Jul 09 04:39:46 PM PDT 24 8380229 ps
T40 /workspace/coverage/sync_alert/14.prim_sync_alert.4149523441 Jul 09 04:39:43 PM PDT 24 Jul 09 04:39:45 PM PDT 24 9080440 ps
T41 /workspace/coverage/sync_alert/18.prim_sync_alert.2832465087 Jul 09 04:39:45 PM PDT 24 Jul 09 04:39:47 PM PDT 24 8567000 ps
T42 /workspace/coverage/sync_alert/13.prim_sync_alert.1865470240 Jul 09 04:39:48 PM PDT 24 Jul 09 04:39:49 PM PDT 24 8708274 ps
T31 /workspace/coverage/sync_alert/15.prim_sync_alert.1806524176 Jul 09 04:39:44 PM PDT 24 Jul 09 04:39:46 PM PDT 24 9811350 ps
T32 /workspace/coverage/sync_alert/4.prim_sync_alert.3245401229 Jul 09 04:39:45 PM PDT 24 Jul 09 04:39:47 PM PDT 24 8410588 ps
T61 /workspace/coverage/sync_alert/10.prim_sync_alert.692938338 Jul 09 04:39:44 PM PDT 24 Jul 09 04:39:46 PM PDT 24 8668292 ps
T33 /workspace/coverage/sync_alert/5.prim_sync_alert.2911233993 Jul 09 04:39:46 PM PDT 24 Jul 09 04:39:48 PM PDT 24 8782036 ps
T34 /workspace/coverage/sync_alert/17.prim_sync_alert.3547201995 Jul 09 04:39:46 PM PDT 24 Jul 09 04:39:48 PM PDT 24 9465962 ps
T62 /workspace/coverage/sync_alert/11.prim_sync_alert.1824195343 Jul 09 04:39:44 PM PDT 24 Jul 09 04:39:46 PM PDT 24 9673226 ps
T63 /workspace/coverage/sync_alert/19.prim_sync_alert.1987101813 Jul 09 04:39:46 PM PDT 24 Jul 09 04:39:48 PM PDT 24 9487596 ps
T9 /workspace/coverage/sync_alert/7.prim_sync_alert.936008367 Jul 09 04:39:43 PM PDT 24 Jul 09 04:39:45 PM PDT 24 9219263 ps
T10 /workspace/coverage/sync_alert/16.prim_sync_alert.304096194 Jul 09 04:39:43 PM PDT 24 Jul 09 04:39:45 PM PDT 24 9140674 ps
T64 /workspace/coverage/sync_alert/8.prim_sync_alert.2995407056 Jul 09 04:39:46 PM PDT 24 Jul 09 04:39:48 PM PDT 24 8768150 ps
T65 /workspace/coverage/sync_alert/0.prim_sync_alert.2546983399 Jul 09 04:39:43 PM PDT 24 Jul 09 04:39:45 PM PDT 24 8023307 ps
T6 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1760060688 Jul 09 04:39:47 PM PDT 24 Jul 09 04:39:48 PM PDT 24 26760914 ps
T15 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2655811974 Jul 09 04:39:46 PM PDT 24 Jul 09 04:39:48 PM PDT 24 28003324 ps
T35 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1684628637 Jul 09 04:39:49 PM PDT 24 Jul 09 04:39:50 PM PDT 24 28920553 ps
T36 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3453870764 Jul 09 04:39:53 PM PDT 24 Jul 09 04:39:54 PM PDT 24 30520234 ps
T66 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3731238800 Jul 09 04:40:03 PM PDT 24 Jul 09 04:40:04 PM PDT 24 27644770 ps
T11 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1532566111 Jul 09 04:39:55 PM PDT 24 Jul 09 04:39:56 PM PDT 24 23859171 ps
T67 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.51931873 Jul 09 04:39:49 PM PDT 24 Jul 09 04:39:50 PM PDT 24 27107964 ps
T68 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3444598572 Jul 09 04:39:51 PM PDT 24 Jul 09 04:39:52 PM PDT 24 27675103 ps
T16 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4549236 Jul 09 04:39:52 PM PDT 24 Jul 09 04:39:53 PM PDT 24 28608492 ps
T69 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2317554207 Jul 09 04:39:57 PM PDT 24 Jul 09 04:39:58 PM PDT 24 28325806 ps
T70 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2270792196 Jul 09 04:39:49 PM PDT 24 Jul 09 04:39:50 PM PDT 24 28343319 ps
T71 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1591322290 Jul 09 04:39:45 PM PDT 24 Jul 09 04:39:47 PM PDT 24 25852576 ps
T72 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3416983206 Jul 09 04:39:51 PM PDT 24 Jul 09 04:39:52 PM PDT 24 29816284 ps
T73 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3268788102 Jul 09 04:39:42 PM PDT 24 Jul 09 04:39:44 PM PDT 24 25936272 ps
T74 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1890940995 Jul 09 04:39:53 PM PDT 24 Jul 09 04:39:53 PM PDT 24 25817539 ps
T75 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3449882428 Jul 09 04:39:50 PM PDT 24 Jul 09 04:39:51 PM PDT 24 28230665 ps
T76 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1618551695 Jul 09 04:39:48 PM PDT 24 Jul 09 04:39:49 PM PDT 24 26748007 ps
T77 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2924894173 Jul 09 04:39:50 PM PDT 24 Jul 09 04:39:50 PM PDT 24 27925196 ps
T78 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1042616704 Jul 09 04:39:53 PM PDT 24 Jul 09 04:39:54 PM PDT 24 27812271 ps
T79 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1729718521 Jul 09 04:39:48 PM PDT 24 Jul 09 04:39:49 PM PDT 24 28028088 ps

Test location /workspace/coverage/default/14.prim_async_alert.2943589246
Short name T12
Test name
Test status
Simulation time 11848302 ps
CPU time 0.38 seconds
Started Jul 09 04:26:42 PM PDT 24
Finished Jul 09 04:26:45 PM PDT 24
Peak memory 145104 kb
Host smart-25551338-0fb0-40da-b6c0-c050882ccefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943589246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2943589246
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.4149523441
Short name T40
Test name
Test status
Simulation time 9080440 ps
CPU time 0.38 seconds
Started Jul 09 04:39:43 PM PDT 24
Finished Jul 09 04:39:45 PM PDT 24
Peak memory 145632 kb
Host smart-2d98eecc-43e6-48b4-a1e7-c2574ea4b2b4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4149523441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.4149523441
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1609027475
Short name T44
Test name
Test status
Simulation time 30524039 ps
CPU time 0.4 seconds
Started Jul 09 04:37:30 PM PDT 24
Finished Jul 09 04:37:32 PM PDT 24
Peak memory 145276 kb
Host smart-1f05fd09-54b3-4f60-8ec2-8427e041f808
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1609027475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1609027475
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4549236
Short name T16
Test name
Test status
Simulation time 28608492 ps
CPU time 0.41 seconds
Started Jul 09 04:39:52 PM PDT 24
Finished Jul 09 04:39:53 PM PDT 24
Peak memory 145560 kb
Host smart-0f3b84c9-ebc6-44c4-9712-d8b000f415f8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4549236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.4549236
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2369288629
Short name T27
Test name
Test status
Simulation time 10911107 ps
CPU time 0.4 seconds
Started Jul 09 04:22:54 PM PDT 24
Finished Jul 09 04:22:55 PM PDT 24
Peak memory 145612 kb
Host smart-e7f719a9-acab-4803-a411-ca577aaf0d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369288629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2369288629
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.304096194
Short name T10
Test name
Test status
Simulation time 9140674 ps
CPU time 0.37 seconds
Started Jul 09 04:39:43 PM PDT 24
Finished Jul 09 04:39:45 PM PDT 24
Peak memory 145460 kb
Host smart-3aed4b68-1ae6-45a6-ae9b-3229d5b75e76
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=304096194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.304096194
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.699785538
Short name T26
Test name
Test status
Simulation time 11073539 ps
CPU time 0.39 seconds
Started Jul 09 04:25:30 PM PDT 24
Finished Jul 09 04:25:30 PM PDT 24
Peak memory 145748 kb
Host smart-d6df59e1-7bf8-4820-abc3-5ec0a387788b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699785538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.699785538
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1224370422
Short name T8
Test name
Test status
Simulation time 10555040 ps
CPU time 0.43 seconds
Started Jul 09 04:22:29 PM PDT 24
Finished Jul 09 04:22:30 PM PDT 24
Peak memory 145936 kb
Host smart-2ce4fcfa-5ee4-4177-8aa9-da3910167efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224370422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1224370422
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.795133336
Short name T7
Test name
Test status
Simulation time 11277110 ps
CPU time 0.41 seconds
Started Jul 09 04:27:05 PM PDT 24
Finished Jul 09 04:27:11 PM PDT 24
Peak memory 144804 kb
Host smart-14a45184-9e04-46b2-a33e-89d80717b3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795133336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.795133336
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2604270908
Short name T25
Test name
Test status
Simulation time 11328811 ps
CPU time 0.38 seconds
Started Jul 09 04:26:43 PM PDT 24
Finished Jul 09 04:26:46 PM PDT 24
Peak memory 145352 kb
Host smart-82c7be12-1628-4553-9cbd-ae878353d13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604270908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2604270908
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.3077815300
Short name T51
Test name
Test status
Simulation time 10500783 ps
CPU time 0.38 seconds
Started Jul 09 04:27:07 PM PDT 24
Finished Jul 09 04:27:14 PM PDT 24
Peak memory 146928 kb
Host smart-737eb0ea-8f96-48c3-98b5-0468e9798ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077815300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3077815300
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3731971406
Short name T21
Test name
Test status
Simulation time 10686378 ps
CPU time 0.4 seconds
Started Jul 09 04:27:07 PM PDT 24
Finished Jul 09 04:27:14 PM PDT 24
Peak memory 146904 kb
Host smart-ea9e5d42-acb8-483c-a7fe-2cf3c3fda8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731971406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3731971406
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1161902533
Short name T19
Test name
Test status
Simulation time 10611876 ps
CPU time 0.41 seconds
Started Jul 09 04:26:50 PM PDT 24
Finished Jul 09 04:26:51 PM PDT 24
Peak memory 144496 kb
Host smart-afa116cd-5f55-42c4-8ef8-590ec1498fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161902533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1161902533
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.272689607
Short name T2
Test name
Test status
Simulation time 10659290 ps
CPU time 0.38 seconds
Started Jul 09 04:27:18 PM PDT 24
Finished Jul 09 04:27:22 PM PDT 24
Peak memory 145592 kb
Host smart-b4b569dc-5cc0-4376-b683-63f526728bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272689607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.272689607
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2328868623
Short name T13
Test name
Test status
Simulation time 11439411 ps
CPU time 0.38 seconds
Started Jul 09 04:27:28 PM PDT 24
Finished Jul 09 04:27:34 PM PDT 24
Peak memory 145644 kb
Host smart-9a4fc7ae-2248-4bec-8be4-e9f7c32a1ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328868623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2328868623
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.1427161908
Short name T23
Test name
Test status
Simulation time 11592273 ps
CPU time 0.45 seconds
Started Jul 09 04:24:46 PM PDT 24
Finished Jul 09 04:24:47 PM PDT 24
Peak memory 145888 kb
Host smart-ecfc828f-a789-4ae4-a108-fd144e429867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427161908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1427161908
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1739847738
Short name T20
Test name
Test status
Simulation time 11326250 ps
CPU time 0.42 seconds
Started Jul 09 04:26:38 PM PDT 24
Finished Jul 09 04:26:39 PM PDT 24
Peak memory 144352 kb
Host smart-747b7e5c-1163-4b09-94d5-1d5175fe4bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739847738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1739847738
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2598820827
Short name T24
Test name
Test status
Simulation time 11896550 ps
CPU time 0.42 seconds
Started Jul 09 04:27:31 PM PDT 24
Finished Jul 09 04:27:38 PM PDT 24
Peak memory 145172 kb
Host smart-8a798e6b-147f-4ea1-9746-13b39ef7e5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598820827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2598820827
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2270163280
Short name T53
Test name
Test status
Simulation time 10546512 ps
CPU time 0.41 seconds
Started Jul 09 04:26:40 PM PDT 24
Finished Jul 09 04:26:44 PM PDT 24
Peak memory 144396 kb
Host smart-2ee8349a-c600-42f5-b1fc-ffc7f7a5ed48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270163280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2270163280
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.531375173
Short name T1
Test name
Test status
Simulation time 11211901 ps
CPU time 0.39 seconds
Started Jul 09 04:25:23 PM PDT 24
Finished Jul 09 04:25:24 PM PDT 24
Peak memory 145620 kb
Host smart-ab274d4f-5852-45b9-9365-712f270ee66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531375173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.531375173
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.863350646
Short name T22
Test name
Test status
Simulation time 10363047 ps
CPU time 0.38 seconds
Started Jul 09 04:26:54 PM PDT 24
Finished Jul 09 04:27:00 PM PDT 24
Peak memory 145628 kb
Host smart-9862a9bb-1a4d-4e1f-a742-c786f071b63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863350646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.863350646
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3085931134
Short name T52
Test name
Test status
Simulation time 11075882 ps
CPU time 0.4 seconds
Started Jul 09 04:23:54 PM PDT 24
Finished Jul 09 04:23:54 PM PDT 24
Peak memory 145636 kb
Host smart-9238c9f3-3f52-43d7-a502-cedc028e186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085931134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3085931134
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1039246207
Short name T3
Test name
Test status
Simulation time 11177737 ps
CPU time 0.39 seconds
Started Jul 09 04:25:22 PM PDT 24
Finished Jul 09 04:25:22 PM PDT 24
Peak memory 145676 kb
Host smart-71d2aafa-b649-431e-babc-323d799dac40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039246207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1039246207
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2899009248
Short name T50
Test name
Test status
Simulation time 27815707 ps
CPU time 0.39 seconds
Started Jul 09 04:27:27 PM PDT 24
Finished Jul 09 04:27:34 PM PDT 24
Peak memory 145196 kb
Host smart-1a473950-4528-4565-980a-5ae5772b0a89
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2899009248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2899009248
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3831215452
Short name T55
Test name
Test status
Simulation time 30305527 ps
CPU time 0.38 seconds
Started Jul 09 04:27:27 PM PDT 24
Finished Jul 09 04:27:34 PM PDT 24
Peak memory 145216 kb
Host smart-0854b341-e36b-4552-9a7d-aa6b6dba2958
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3831215452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3831215452
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3371606684
Short name T58
Test name
Test status
Simulation time 32084520 ps
CPU time 0.38 seconds
Started Jul 09 04:37:30 PM PDT 24
Finished Jul 09 04:37:33 PM PDT 24
Peak memory 145084 kb
Host smart-ada0c864-32b2-4838-8679-fd32df81c94b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3371606684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3371606684
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1993692838
Short name T48
Test name
Test status
Simulation time 29693341 ps
CPU time 0.39 seconds
Started Jul 09 04:37:29 PM PDT 24
Finished Jul 09 04:37:30 PM PDT 24
Peak memory 145176 kb
Host smart-72cd334e-533b-4bbe-bceb-73b0929838c2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1993692838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1993692838
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2372402737
Short name T45
Test name
Test status
Simulation time 29626653 ps
CPU time 0.39 seconds
Started Jul 09 04:37:29 PM PDT 24
Finished Jul 09 04:37:30 PM PDT 24
Peak memory 145276 kb
Host smart-a2a9f6bc-7cde-436c-b4f0-eed6d721f07b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2372402737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2372402737
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4122592406
Short name T17
Test name
Test status
Simulation time 30892077 ps
CPU time 0.39 seconds
Started Jul 09 04:37:29 PM PDT 24
Finished Jul 09 04:37:30 PM PDT 24
Peak memory 145180 kb
Host smart-558eeb94-ae21-4df5-92b1-d544653c4bfc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4122592406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.4122592406
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1136967321
Short name T18
Test name
Test status
Simulation time 30990300 ps
CPU time 0.39 seconds
Started Jul 09 04:37:29 PM PDT 24
Finished Jul 09 04:37:30 PM PDT 24
Peak memory 145216 kb
Host smart-e29dd063-bb1d-4ed2-a9c2-8cd28832d828
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1136967321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1136967321
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.569999593
Short name T47
Test name
Test status
Simulation time 29563005 ps
CPU time 0.41 seconds
Started Jul 09 04:37:29 PM PDT 24
Finished Jul 09 04:37:31 PM PDT 24
Peak memory 145176 kb
Host smart-9eecd6ab-08d9-4fb1-b89d-49a400d6d787
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=569999593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.569999593
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2326416166
Short name T46
Test name
Test status
Simulation time 30765919 ps
CPU time 0.39 seconds
Started Jul 09 04:37:28 PM PDT 24
Finished Jul 09 04:37:28 PM PDT 24
Peak memory 145228 kb
Host smart-622afb45-7937-430d-b8cc-3966bf0b9b14
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2326416166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2326416166
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3670779837
Short name T59
Test name
Test status
Simulation time 31073755 ps
CPU time 0.39 seconds
Started Jul 09 04:37:30 PM PDT 24
Finished Jul 09 04:37:33 PM PDT 24
Peak memory 145096 kb
Host smart-dd9baa2c-3966-415a-a131-96095f648e94
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3670779837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3670779837
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3811034062
Short name T14
Test name
Test status
Simulation time 29852823 ps
CPU time 0.41 seconds
Started Jul 09 04:37:29 PM PDT 24
Finished Jul 09 04:37:31 PM PDT 24
Peak memory 145316 kb
Host smart-5113bca3-b0ae-4231-ad61-5d4a2fe119a7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3811034062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3811034062
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4168403807
Short name T57
Test name
Test status
Simulation time 29998334 ps
CPU time 0.38 seconds
Started Jul 09 04:27:44 PM PDT 24
Finished Jul 09 04:27:45 PM PDT 24
Peak memory 145300 kb
Host smart-4b4aa709-1eea-42e5-84ef-61e6d7416429
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4168403807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4168403807
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.476109724
Short name T54
Test name
Test status
Simulation time 31096161 ps
CPU time 0.43 seconds
Started Jul 09 04:27:10 PM PDT 24
Finished Jul 09 04:27:17 PM PDT 24
Peak memory 144192 kb
Host smart-456521f9-3c0f-4701-aefb-f8f2aeeea002
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=476109724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.476109724
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1032865869
Short name T5
Test name
Test status
Simulation time 29522045 ps
CPU time 0.44 seconds
Started Jul 09 04:26:52 PM PDT 24
Finished Jul 09 04:26:54 PM PDT 24
Peak memory 144112 kb
Host smart-e19db13f-e325-499f-88e4-24600fa342b6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1032865869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1032865869
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2434654555
Short name T56
Test name
Test status
Simulation time 29810478 ps
CPU time 0.4 seconds
Started Jul 09 04:27:43 PM PDT 24
Finished Jul 09 04:27:59 PM PDT 24
Peak memory 145228 kb
Host smart-7cd7f05d-6138-40ae-a5c3-105fcaf0d8de
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2434654555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2434654555
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3861245812
Short name T49
Test name
Test status
Simulation time 30223571 ps
CPU time 0.42 seconds
Started Jul 09 04:26:13 PM PDT 24
Finished Jul 09 04:26:14 PM PDT 24
Peak memory 145168 kb
Host smart-51b4db21-bb54-4014-8bce-582139aef9be
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3861245812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3861245812
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2116879984
Short name T60
Test name
Test status
Simulation time 27968449 ps
CPU time 0.41 seconds
Started Jul 09 04:24:45 PM PDT 24
Finished Jul 09 04:24:46 PM PDT 24
Peak memory 145284 kb
Host smart-1c7eda20-ef84-41be-8023-7114a1134f35
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2116879984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2116879984
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1776583771
Short name T43
Test name
Test status
Simulation time 29381504 ps
CPU time 0.4 seconds
Started Jul 09 04:23:52 PM PDT 24
Finished Jul 09 04:23:53 PM PDT 24
Peak memory 145216 kb
Host smart-0e284354-1792-4d75-b3a0-6febd681a2cd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1776583771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1776583771
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2769626030
Short name T4
Test name
Test status
Simulation time 30223754 ps
CPU time 0.4 seconds
Started Jul 09 04:26:41 PM PDT 24
Finished Jul 09 04:26:44 PM PDT 24
Peak memory 144364 kb
Host smart-1442b457-79c3-444e-9edb-d74623446791
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2769626030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2769626030
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2546983399
Short name T65
Test name
Test status
Simulation time 8023307 ps
CPU time 0.38 seconds
Started Jul 09 04:39:43 PM PDT 24
Finished Jul 09 04:39:45 PM PDT 24
Peak memory 145480 kb
Host smart-43816ba3-01d5-4e61-a9dc-80dc4ece3150
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2546983399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2546983399
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.773441991
Short name T28
Test name
Test status
Simulation time 9029776 ps
CPU time 0.39 seconds
Started Jul 09 04:39:45 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 145488 kb
Host smart-bcda0a05-1319-4b49-a90f-e5085a6c9096
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=773441991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.773441991
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.692938338
Short name T61
Test name
Test status
Simulation time 8668292 ps
CPU time 0.39 seconds
Started Jul 09 04:39:44 PM PDT 24
Finished Jul 09 04:39:46 PM PDT 24
Peak memory 145468 kb
Host smart-aae9af05-8416-4bee-bb2f-06cf2005be98
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=692938338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.692938338
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1824195343
Short name T62
Test name
Test status
Simulation time 9673226 ps
CPU time 0.38 seconds
Started Jul 09 04:39:44 PM PDT 24
Finished Jul 09 04:39:46 PM PDT 24
Peak memory 145560 kb
Host smart-c2f05d02-edb0-4b22-9fd7-2b03ee194f95
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1824195343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1824195343
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.1392546540
Short name T29
Test name
Test status
Simulation time 9159385 ps
CPU time 0.41 seconds
Started Jul 09 04:39:52 PM PDT 24
Finished Jul 09 04:39:53 PM PDT 24
Peak memory 145452 kb
Host smart-b61b1094-e770-45d0-8288-305e15e0cf0a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1392546540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1392546540
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1865470240
Short name T42
Test name
Test status
Simulation time 8708274 ps
CPU time 0.4 seconds
Started Jul 09 04:39:48 PM PDT 24
Finished Jul 09 04:39:49 PM PDT 24
Peak memory 145484 kb
Host smart-e0444f28-1067-43b3-b17f-074f62d0fec4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1865470240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1865470240
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1806524176
Short name T31
Test name
Test status
Simulation time 9811350 ps
CPU time 0.4 seconds
Started Jul 09 04:39:44 PM PDT 24
Finished Jul 09 04:39:46 PM PDT 24
Peak memory 145524 kb
Host smart-6c9530c4-15c4-4c41-ba1f-acda906f43cf
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1806524176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1806524176
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3547201995
Short name T34
Test name
Test status
Simulation time 9465962 ps
CPU time 0.38 seconds
Started Jul 09 04:39:46 PM PDT 24
Finished Jul 09 04:39:48 PM PDT 24
Peak memory 145564 kb
Host smart-685030df-a5e8-4346-a82f-15ea17d4ac45
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3547201995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3547201995
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2832465087
Short name T41
Test name
Test status
Simulation time 8567000 ps
CPU time 0.37 seconds
Started Jul 09 04:39:45 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 145480 kb
Host smart-f0dfff45-c2c1-4af4-a59d-aef205688d91
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2832465087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2832465087
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1987101813
Short name T63
Test name
Test status
Simulation time 9487596 ps
CPU time 0.37 seconds
Started Jul 09 04:39:46 PM PDT 24
Finished Jul 09 04:39:48 PM PDT 24
Peak memory 145480 kb
Host smart-38eb02db-bc67-4fab-95d8-b598eb4d2217
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1987101813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1987101813
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2044092642
Short name T38
Test name
Test status
Simulation time 10420413 ps
CPU time 0.38 seconds
Started Jul 09 04:39:44 PM PDT 24
Finished Jul 09 04:39:46 PM PDT 24
Peak memory 145464 kb
Host smart-d5bfd75f-88b8-4b6a-8df8-4b8ab9ab0548
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2044092642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2044092642
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2222437734
Short name T37
Test name
Test status
Simulation time 9393771 ps
CPU time 0.39 seconds
Started Jul 09 04:39:46 PM PDT 24
Finished Jul 09 04:39:48 PM PDT 24
Peak memory 145476 kb
Host smart-a393c1e1-9fae-42da-a0cb-b82f0262606c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2222437734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2222437734
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3245401229
Short name T32
Test name
Test status
Simulation time 8410588 ps
CPU time 0.37 seconds
Started Jul 09 04:39:45 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 145456 kb
Host smart-b9ae5970-2f10-4e46-9782-2868b8de146e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3245401229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3245401229
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2911233993
Short name T33
Test name
Test status
Simulation time 8782036 ps
CPU time 0.38 seconds
Started Jul 09 04:39:46 PM PDT 24
Finished Jul 09 04:39:48 PM PDT 24
Peak memory 145456 kb
Host smart-49946b09-7545-40a9-8707-cb0f57eb2872
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2911233993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2911233993
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3229288287
Short name T39
Test name
Test status
Simulation time 8380229 ps
CPU time 0.38 seconds
Started Jul 09 04:39:44 PM PDT 24
Finished Jul 09 04:39:46 PM PDT 24
Peak memory 145464 kb
Host smart-9d707d2f-de8d-4681-ae8c-425324e1e3df
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3229288287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3229288287
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.936008367
Short name T9
Test name
Test status
Simulation time 9219263 ps
CPU time 0.37 seconds
Started Jul 09 04:39:43 PM PDT 24
Finished Jul 09 04:39:45 PM PDT 24
Peak memory 145464 kb
Host smart-fc0d069c-64f4-439a-9862-9743547c03f1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=936008367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.936008367
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2995407056
Short name T64
Test name
Test status
Simulation time 8768150 ps
CPU time 0.41 seconds
Started Jul 09 04:39:46 PM PDT 24
Finished Jul 09 04:39:48 PM PDT 24
Peak memory 145480 kb
Host smart-416e6b8e-f146-4851-bbbf-0d9350bdcbf2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2995407056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2995407056
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3341797125
Short name T30
Test name
Test status
Simulation time 9145183 ps
CPU time 0.38 seconds
Started Jul 09 04:39:46 PM PDT 24
Finished Jul 09 04:39:48 PM PDT 24
Peak memory 145564 kb
Host smart-e2ea7a77-6b52-4394-9f21-6d45f2aedf6a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3341797125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3341797125
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1684628637
Short name T35
Test name
Test status
Simulation time 28920553 ps
CPU time 0.41 seconds
Started Jul 09 04:39:49 PM PDT 24
Finished Jul 09 04:39:50 PM PDT 24
Peak memory 145696 kb
Host smart-ffd35655-e10e-4995-be74-1372e8590b56
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1684628637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1684628637
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2655811974
Short name T15
Test name
Test status
Simulation time 28003324 ps
CPU time 0.4 seconds
Started Jul 09 04:39:46 PM PDT 24
Finished Jul 09 04:39:48 PM PDT 24
Peak memory 145568 kb
Host smart-930b9f96-eebf-4dbc-aaae-fb948f7ec7c1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2655811974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2655811974
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1890940995
Short name T74
Test name
Test status
Simulation time 25817539 ps
CPU time 0.38 seconds
Started Jul 09 04:39:53 PM PDT 24
Finished Jul 09 04:39:53 PM PDT 24
Peak memory 145460 kb
Host smart-738fbaaf-3991-4fb9-ad12-1879a4475d37
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1890940995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1890940995
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3449882428
Short name T75
Test name
Test status
Simulation time 28230665 ps
CPU time 0.42 seconds
Started Jul 09 04:39:50 PM PDT 24
Finished Jul 09 04:39:51 PM PDT 24
Peak memory 145468 kb
Host smart-951b835e-13ac-4f8b-8dbc-fe4e043b9aa6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3449882428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3449882428
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.51931873
Short name T67
Test name
Test status
Simulation time 27107964 ps
CPU time 0.44 seconds
Started Jul 09 04:39:49 PM PDT 24
Finished Jul 09 04:39:50 PM PDT 24
Peak memory 145612 kb
Host smart-a0f6ac31-5247-4e07-8b4e-45a16154709b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=51931873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.51931873
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1042616704
Short name T78
Test name
Test status
Simulation time 27812271 ps
CPU time 0.4 seconds
Started Jul 09 04:39:53 PM PDT 24
Finished Jul 09 04:39:54 PM PDT 24
Peak memory 145468 kb
Host smart-62bbff9c-cbde-48af-86dc-a6bae12fc639
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1042616704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1042616704
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3453870764
Short name T36
Test name
Test status
Simulation time 30520234 ps
CPU time 0.38 seconds
Started Jul 09 04:39:53 PM PDT 24
Finished Jul 09 04:39:54 PM PDT 24
Peak memory 145456 kb
Host smart-860c5406-b630-4636-bb84-4e2feb2e34f9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3453870764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3453870764
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2924894173
Short name T77
Test name
Test status
Simulation time 27925196 ps
CPU time 0.38 seconds
Started Jul 09 04:39:50 PM PDT 24
Finished Jul 09 04:39:50 PM PDT 24
Peak memory 145444 kb
Host smart-830e096f-8e41-43eb-ad87-59f14d6383d1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2924894173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2924894173
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3444598572
Short name T68
Test name
Test status
Simulation time 27675103 ps
CPU time 0.4 seconds
Started Jul 09 04:39:51 PM PDT 24
Finished Jul 09 04:39:52 PM PDT 24
Peak memory 145464 kb
Host smart-688d7686-eab2-469a-9e87-cf31c81ef169
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3444598572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3444598572
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2317554207
Short name T69
Test name
Test status
Simulation time 28325806 ps
CPU time 0.39 seconds
Started Jul 09 04:39:57 PM PDT 24
Finished Jul 09 04:39:58 PM PDT 24
Peak memory 145456 kb
Host smart-759d0eae-f24f-49c6-aff9-8a9a09889c6e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2317554207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2317554207
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1729718521
Short name T79
Test name
Test status
Simulation time 28028088 ps
CPU time 0.41 seconds
Started Jul 09 04:39:48 PM PDT 24
Finished Jul 09 04:39:49 PM PDT 24
Peak memory 145496 kb
Host smart-bbdfe7be-ae7e-46fd-a9c9-5f71e0038613
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1729718521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1729718521
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2270792196
Short name T70
Test name
Test status
Simulation time 28343319 ps
CPU time 0.43 seconds
Started Jul 09 04:39:49 PM PDT 24
Finished Jul 09 04:39:50 PM PDT 24
Peak memory 145384 kb
Host smart-607684ce-26f5-4d8b-a196-6e2fda30aa92
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2270792196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2270792196
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1591322290
Short name T71
Test name
Test status
Simulation time 25852576 ps
CPU time 0.41 seconds
Started Jul 09 04:39:45 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 145468 kb
Host smart-a25693ad-3d42-41bc-82f7-7203713367da
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1591322290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1591322290
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1760060688
Short name T6
Test name
Test status
Simulation time 26760914 ps
CPU time 0.41 seconds
Started Jul 09 04:39:47 PM PDT 24
Finished Jul 09 04:39:48 PM PDT 24
Peak memory 145560 kb
Host smart-8fc2bfdc-68e6-42c7-a73f-54652e845bad
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1760060688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1760060688
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1618551695
Short name T76
Test name
Test status
Simulation time 26748007 ps
CPU time 0.4 seconds
Started Jul 09 04:39:48 PM PDT 24
Finished Jul 09 04:39:49 PM PDT 24
Peak memory 145492 kb
Host smart-5b798e45-7c0c-42f0-b474-5d9dda33c27e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1618551695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1618551695
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3268788102
Short name T73
Test name
Test status
Simulation time 25936272 ps
CPU time 0.38 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:39:44 PM PDT 24
Peak memory 145488 kb
Host smart-c720417d-aeb7-4147-b03f-a6d09654d361
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3268788102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3268788102
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3416983206
Short name T72
Test name
Test status
Simulation time 29816284 ps
CPU time 0.39 seconds
Started Jul 09 04:39:51 PM PDT 24
Finished Jul 09 04:39:52 PM PDT 24
Peak memory 145456 kb
Host smart-20c4a535-b080-4990-b766-93aa1181acf8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3416983206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3416983206
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1532566111
Short name T11
Test name
Test status
Simulation time 23859171 ps
CPU time 0.43 seconds
Started Jul 09 04:39:55 PM PDT 24
Finished Jul 09 04:39:56 PM PDT 24
Peak memory 145456 kb
Host smart-44d8bc5a-76da-415d-bcea-a510b41b3b69
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1532566111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1532566111
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3731238800
Short name T66
Test name
Test status
Simulation time 27644770 ps
CPU time 0.4 seconds
Started Jul 09 04:40:03 PM PDT 24
Finished Jul 09 04:40:04 PM PDT 24
Peak memory 145560 kb
Host smart-b5c58a81-a9eb-42bf-92f7-ddd837f2adef
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3731238800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3731238800
Directory /workspace/9.prim_sync_fatal_alert/latest
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