Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.42 88.42 100.00 100.00 95.83 95.83 96.43 96.43 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/0.prim_async_alert.3210209221
92.15 3.72 100.00 0.00 95.83 0.00 96.43 0.00 85.71 10.71 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/5.prim_sync_alert.2470833956
94.50 2.35 100.00 0.00 95.83 0.00 100.00 3.57 89.29 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1075619041
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2459162938
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/17.prim_sync_alert.1279348250

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.1106711048
/workspace/coverage/default/10.prim_async_alert.1703538082
/workspace/coverage/default/11.prim_async_alert.284485715
/workspace/coverage/default/12.prim_async_alert.2805809553
/workspace/coverage/default/13.prim_async_alert.3289576354
/workspace/coverage/default/14.prim_async_alert.3627005677
/workspace/coverage/default/15.prim_async_alert.607775847
/workspace/coverage/default/16.prim_async_alert.1141713552
/workspace/coverage/default/17.prim_async_alert.3908944239
/workspace/coverage/default/18.prim_async_alert.3258463458
/workspace/coverage/default/19.prim_async_alert.1153915701
/workspace/coverage/default/2.prim_async_alert.156122078
/workspace/coverage/default/3.prim_async_alert.1993541812
/workspace/coverage/default/4.prim_async_alert.3393699264
/workspace/coverage/default/5.prim_async_alert.3008948191
/workspace/coverage/default/6.prim_async_alert.53914163
/workspace/coverage/default/7.prim_async_alert.4246311894
/workspace/coverage/default/8.prim_async_alert.2289090386
/workspace/coverage/default/9.prim_async_alert.2610963597
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4054254195
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3546731110
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4221665509
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3141903068
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.66000450
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1594754150
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2906722530
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3655034590
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1280465175
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2915912872
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3865804204
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1489404131
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2083379880
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3159565133
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.612341438
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.175127801
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3712974367
/workspace/coverage/sync_alert/0.prim_sync_alert.503085815
/workspace/coverage/sync_alert/1.prim_sync_alert.2757071616
/workspace/coverage/sync_alert/10.prim_sync_alert.1344356395
/workspace/coverage/sync_alert/11.prim_sync_alert.3060693380
/workspace/coverage/sync_alert/12.prim_sync_alert.2067269048
/workspace/coverage/sync_alert/13.prim_sync_alert.2908153727
/workspace/coverage/sync_alert/14.prim_sync_alert.1039555289
/workspace/coverage/sync_alert/15.prim_sync_alert.67201810
/workspace/coverage/sync_alert/16.prim_sync_alert.123381856
/workspace/coverage/sync_alert/18.prim_sync_alert.3046140119
/workspace/coverage/sync_alert/19.prim_sync_alert.566553568
/workspace/coverage/sync_alert/2.prim_sync_alert.769236340
/workspace/coverage/sync_alert/3.prim_sync_alert.2596863526
/workspace/coverage/sync_alert/4.prim_sync_alert.2223911947
/workspace/coverage/sync_alert/6.prim_sync_alert.568908670
/workspace/coverage/sync_alert/7.prim_sync_alert.3611545317
/workspace/coverage/sync_alert/8.prim_sync_alert.763813796
/workspace/coverage/sync_alert/9.prim_sync_alert.1371746731
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2070170018
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.97162095
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.793582948
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3043787867
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4127987284
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2039791225
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.477169828
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2883257298
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2978606492
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.368668524
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.957724461
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1677472511
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1815587482
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2970588077
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.67522260
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3050949708
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.621344043
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2015264441
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3771095360
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1364335849



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/9.prim_async_alert.2610963597 Jul 10 04:19:47 PM PDT 24 Jul 10 04:19:48 PM PDT 24 10646910 ps
T2 /workspace/coverage/default/2.prim_async_alert.156122078 Jul 10 04:21:14 PM PDT 24 Jul 10 04:21:15 PM PDT 24 11525129 ps
T3 /workspace/coverage/default/4.prim_async_alert.3393699264 Jul 10 04:25:53 PM PDT 24 Jul 10 04:25:54 PM PDT 24 10464089 ps
T16 /workspace/coverage/default/12.prim_async_alert.2805809553 Jul 10 04:20:59 PM PDT 24 Jul 10 04:21:00 PM PDT 24 11089907 ps
T7 /workspace/coverage/default/0.prim_async_alert.3210209221 Jul 10 04:19:43 PM PDT 24 Jul 10 04:19:44 PM PDT 24 10473244 ps
T18 /workspace/coverage/default/6.prim_async_alert.53914163 Jul 10 04:19:50 PM PDT 24 Jul 10 04:19:51 PM PDT 24 11271085 ps
T10 /workspace/coverage/default/5.prim_async_alert.3008948191 Jul 10 04:19:51 PM PDT 24 Jul 10 04:19:53 PM PDT 24 11228736 ps
T21 /workspace/coverage/default/16.prim_async_alert.1141713552 Jul 10 04:19:51 PM PDT 24 Jul 10 04:19:53 PM PDT 24 10781455 ps
T22 /workspace/coverage/default/11.prim_async_alert.284485715 Jul 10 04:19:51 PM PDT 24 Jul 10 04:19:52 PM PDT 24 11605955 ps
T23 /workspace/coverage/default/13.prim_async_alert.3289576354 Jul 10 04:19:50 PM PDT 24 Jul 10 04:19:51 PM PDT 24 10770647 ps
T49 /workspace/coverage/default/10.prim_async_alert.1703538082 Jul 10 04:19:51 PM PDT 24 Jul 10 04:19:53 PM PDT 24 10023589 ps
T24 /workspace/coverage/default/7.prim_async_alert.4246311894 Jul 10 04:19:47 PM PDT 24 Jul 10 04:19:48 PM PDT 24 10742093 ps
T11 /workspace/coverage/default/18.prim_async_alert.3258463458 Jul 10 04:20:47 PM PDT 24 Jul 10 04:20:49 PM PDT 24 11175632 ps
T17 /workspace/coverage/default/8.prim_async_alert.2289090386 Jul 10 04:20:09 PM PDT 24 Jul 10 04:20:10 PM PDT 24 11321794 ps
T12 /workspace/coverage/default/17.prim_async_alert.3908944239 Jul 10 04:20:46 PM PDT 24 Jul 10 04:20:47 PM PDT 24 12728168 ps
T19 /workspace/coverage/default/1.prim_async_alert.1106711048 Jul 10 04:19:50 PM PDT 24 Jul 10 04:19:52 PM PDT 24 11473127 ps
T25 /workspace/coverage/default/3.prim_async_alert.1993541812 Jul 10 04:19:50 PM PDT 24 Jul 10 04:19:51 PM PDT 24 10462649 ps
T50 /workspace/coverage/default/14.prim_async_alert.3627005677 Jul 10 04:19:51 PM PDT 24 Jul 10 04:19:53 PM PDT 24 11152512 ps
T13 /workspace/coverage/default/19.prim_async_alert.1153915701 Jul 10 04:21:04 PM PDT 24 Jul 10 04:21:05 PM PDT 24 11341564 ps
T51 /workspace/coverage/default/15.prim_async_alert.607775847 Jul 10 04:21:00 PM PDT 24 Jul 10 04:21:01 PM PDT 24 10853483 ps
T20 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2083379880 Jul 10 04:20:28 PM PDT 24 Jul 10 04:20:29 PM PDT 24 29055730 ps
T41 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2915912872 Jul 10 04:20:03 PM PDT 24 Jul 10 04:20:04 PM PDT 24 31480055 ps
T42 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1280465175 Jul 10 04:26:13 PM PDT 24 Jul 10 04:26:15 PM PDT 24 29722349 ps
T43 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1075619041 Jul 10 04:26:14 PM PDT 24 Jul 10 04:26:15 PM PDT 24 29737702 ps
T44 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3159565133 Jul 10 04:20:32 PM PDT 24 Jul 10 04:20:33 PM PDT 24 30204484 ps
T45 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3865804204 Jul 10 04:20:59 PM PDT 24 Jul 10 04:21:00 PM PDT 24 31433829 ps
T4 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2459162938 Jul 10 04:21:11 PM PDT 24 Jul 10 04:21:12 PM PDT 24 31530701 ps
T46 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2906722530 Jul 10 04:21:15 PM PDT 24 Jul 10 04:21:17 PM PDT 24 31651993 ps
T47 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3712974367 Jul 10 04:20:47 PM PDT 24 Jul 10 04:20:49 PM PDT 24 27892935 ps
T48 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1594754150 Jul 10 04:20:47 PM PDT 24 Jul 10 04:20:49 PM PDT 24 30124645 ps
T52 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3655034590 Jul 10 04:20:47 PM PDT 24 Jul 10 04:20:49 PM PDT 24 29768358 ps
T53 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.66000450 Jul 10 04:20:47 PM PDT 24 Jul 10 04:20:49 PM PDT 24 29221230 ps
T54 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4221665509 Jul 10 04:20:10 PM PDT 24 Jul 10 04:20:12 PM PDT 24 30595817 ps
T55 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3546731110 Jul 10 04:21:04 PM PDT 24 Jul 10 04:21:06 PM PDT 24 31978134 ps
T56 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.612341438 Jul 10 04:21:04 PM PDT 24 Jul 10 04:21:05 PM PDT 24 29882290 ps
T57 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3141903068 Jul 10 04:29:26 PM PDT 24 Jul 10 04:29:28 PM PDT 24 31709435 ps
T14 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4054254195 Jul 10 04:19:50 PM PDT 24 Jul 10 04:19:52 PM PDT 24 30170943 ps
T58 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.175127801 Jul 10 04:20:47 PM PDT 24 Jul 10 04:20:48 PM PDT 24 30196691 ps
T59 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1489404131 Jul 10 04:20:47 PM PDT 24 Jul 10 04:20:49 PM PDT 24 29596890 ps
T33 /workspace/coverage/sync_alert/8.prim_sync_alert.763813796 Jul 10 05:26:28 PM PDT 24 Jul 10 05:26:30 PM PDT 24 9682879 ps
T26 /workspace/coverage/sync_alert/9.prim_sync_alert.1371746731 Jul 10 05:26:30 PM PDT 24 Jul 10 05:26:32 PM PDT 24 9308486 ps
T34 /workspace/coverage/sync_alert/0.prim_sync_alert.503085815 Jul 10 05:26:22 PM PDT 24 Jul 10 05:26:23 PM PDT 24 8282336 ps
T35 /workspace/coverage/sync_alert/13.prim_sync_alert.2908153727 Jul 10 05:26:29 PM PDT 24 Jul 10 05:26:31 PM PDT 24 9421340 ps
T36 /workspace/coverage/sync_alert/6.prim_sync_alert.568908670 Jul 10 05:26:20 PM PDT 24 Jul 10 05:26:21 PM PDT 24 10224631 ps
T37 /workspace/coverage/sync_alert/16.prim_sync_alert.123381856 Jul 10 05:26:29 PM PDT 24 Jul 10 05:26:31 PM PDT 24 8863882 ps
T38 /workspace/coverage/sync_alert/12.prim_sync_alert.2067269048 Jul 10 05:26:30 PM PDT 24 Jul 10 05:26:32 PM PDT 24 9382929 ps
T8 /workspace/coverage/sync_alert/7.prim_sync_alert.3611545317 Jul 10 05:26:28 PM PDT 24 Jul 10 05:26:30 PM PDT 24 8368906 ps
T15 /workspace/coverage/sync_alert/5.prim_sync_alert.2470833956 Jul 10 05:26:22 PM PDT 24 Jul 10 05:26:24 PM PDT 24 9893079 ps
T39 /workspace/coverage/sync_alert/4.prim_sync_alert.2223911947 Jul 10 05:26:20 PM PDT 24 Jul 10 05:26:22 PM PDT 24 9107780 ps
T40 /workspace/coverage/sync_alert/18.prim_sync_alert.3046140119 Jul 10 05:26:27 PM PDT 24 Jul 10 05:26:28 PM PDT 24 8298873 ps
T60 /workspace/coverage/sync_alert/3.prim_sync_alert.2596863526 Jul 10 05:26:20 PM PDT 24 Jul 10 05:26:22 PM PDT 24 9100227 ps
T27 /workspace/coverage/sync_alert/2.prim_sync_alert.769236340 Jul 10 05:26:22 PM PDT 24 Jul 10 05:26:24 PM PDT 24 8280550 ps
T61 /workspace/coverage/sync_alert/11.prim_sync_alert.3060693380 Jul 10 05:26:32 PM PDT 24 Jul 10 05:26:33 PM PDT 24 8950998 ps
T28 /workspace/coverage/sync_alert/1.prim_sync_alert.2757071616 Jul 10 05:26:21 PM PDT 24 Jul 10 05:26:23 PM PDT 24 9587483 ps
T62 /workspace/coverage/sync_alert/15.prim_sync_alert.67201810 Jul 10 05:26:28 PM PDT 24 Jul 10 05:26:30 PM PDT 24 9551801 ps
T29 /workspace/coverage/sync_alert/14.prim_sync_alert.1039555289 Jul 10 05:26:28 PM PDT 24 Jul 10 05:26:29 PM PDT 24 10867661 ps
T30 /workspace/coverage/sync_alert/19.prim_sync_alert.566553568 Jul 10 05:26:30 PM PDT 24 Jul 10 05:26:32 PM PDT 24 9512091 ps
T63 /workspace/coverage/sync_alert/10.prim_sync_alert.1344356395 Jul 10 05:26:28 PM PDT 24 Jul 10 05:26:30 PM PDT 24 9099515 ps
T9 /workspace/coverage/sync_alert/17.prim_sync_alert.1279348250 Jul 10 05:26:29 PM PDT 24 Jul 10 05:26:31 PM PDT 24 8893998 ps
T5 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2883257298 Jul 10 05:50:52 PM PDT 24 Jul 10 05:50:54 PM PDT 24 25415666 ps
T31 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3050949708 Jul 10 05:50:48 PM PDT 24 Jul 10 05:50:50 PM PDT 24 26011368 ps
T32 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1815587482 Jul 10 05:50:52 PM PDT 24 Jul 10 05:50:54 PM PDT 24 26962799 ps
T64 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.793582948 Jul 10 05:50:59 PM PDT 24 Jul 10 05:51:05 PM PDT 24 28268793 ps
T65 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.621344043 Jul 10 05:50:52 PM PDT 24 Jul 10 05:50:54 PM PDT 24 28035995 ps
T6 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2015264441 Jul 10 05:50:47 PM PDT 24 Jul 10 05:50:49 PM PDT 24 26943994 ps
T66 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2039791225 Jul 10 05:50:54 PM PDT 24 Jul 10 05:50:56 PM PDT 24 27480352 ps
T67 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.957724461 Jul 10 05:50:53 PM PDT 24 Jul 10 05:50:55 PM PDT 24 25115160 ps
T68 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3771095360 Jul 10 05:51:02 PM PDT 24 Jul 10 05:51:08 PM PDT 24 27968630 ps
T69 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2978606492 Jul 10 05:50:57 PM PDT 24 Jul 10 05:51:02 PM PDT 24 28539120 ps
T70 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.368668524 Jul 10 05:50:51 PM PDT 24 Jul 10 05:50:53 PM PDT 24 27654438 ps
T71 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3043787867 Jul 10 05:50:51 PM PDT 24 Jul 10 05:50:53 PM PDT 24 26942484 ps
T72 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1364335849 Jul 10 05:50:52 PM PDT 24 Jul 10 05:50:54 PM PDT 24 27019237 ps
T73 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4127987284 Jul 10 05:50:54 PM PDT 24 Jul 10 05:50:56 PM PDT 24 27318476 ps
T74 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1677472511 Jul 10 05:50:54 PM PDT 24 Jul 10 05:50:56 PM PDT 24 27311000 ps
T75 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.477169828 Jul 10 05:50:53 PM PDT 24 Jul 10 05:50:55 PM PDT 24 28069469 ps
T76 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2970588077 Jul 10 05:50:47 PM PDT 24 Jul 10 05:50:49 PM PDT 24 25606732 ps
T77 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.97162095 Jul 10 05:50:57 PM PDT 24 Jul 10 05:51:03 PM PDT 24 27164982 ps
T78 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2070170018 Jul 10 05:50:58 PM PDT 24 Jul 10 05:51:03 PM PDT 24 25600249 ps
T79 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.67522260 Jul 10 05:50:48 PM PDT 24 Jul 10 05:50:49 PM PDT 24 27206002 ps

Test location /workspace/coverage/default/0.prim_async_alert.3210209221
Short name T7
Test name
Test status
Simulation time 10473244 ps
CPU time 0.39 seconds
Started Jul 10 04:19:43 PM PDT 24
Finished Jul 10 04:19:44 PM PDT 24
Peak memory 145532 kb
Host smart-137aa7c1-c75e-4205-b3e9-4bf7a4ab32ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210209221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3210209221
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2470833956
Short name T15
Test name
Test status
Simulation time 9893079 ps
CPU time 0.39 seconds
Started Jul 10 05:26:22 PM PDT 24
Finished Jul 10 05:26:24 PM PDT 24
Peak memory 145564 kb
Host smart-ff79f34f-5481-43bd-b7e7-e62706a542f7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2470833956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2470833956
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1075619041
Short name T43
Test name
Test status
Simulation time 29737702 ps
CPU time 0.42 seconds
Started Jul 10 04:26:14 PM PDT 24
Finished Jul 10 04:26:15 PM PDT 24
Peak memory 144768 kb
Host smart-5359b0d9-a37d-421e-a69f-b204c0720f95
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1075619041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1075619041
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2459162938
Short name T4
Test name
Test status
Simulation time 31530701 ps
CPU time 0.4 seconds
Started Jul 10 04:21:11 PM PDT 24
Finished Jul 10 04:21:12 PM PDT 24
Peak memory 144996 kb
Host smart-3524ca66-5015-46fd-8ff1-d3a999ecc276
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2459162938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2459162938
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1279348250
Short name T9
Test name
Test status
Simulation time 8893998 ps
CPU time 0.38 seconds
Started Jul 10 05:26:29 PM PDT 24
Finished Jul 10 05:26:31 PM PDT 24
Peak memory 145488 kb
Host smart-6f05f574-113b-42b8-ad27-786ff0555e8f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1279348250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1279348250
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1106711048
Short name T19
Test name
Test status
Simulation time 11473127 ps
CPU time 0.38 seconds
Started Jul 10 04:19:50 PM PDT 24
Finished Jul 10 04:19:52 PM PDT 24
Peak memory 145200 kb
Host smart-22bfc605-f880-4a72-aba4-f815f53ab87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106711048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1106711048
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1703538082
Short name T49
Test name
Test status
Simulation time 10023589 ps
CPU time 0.38 seconds
Started Jul 10 04:19:51 PM PDT 24
Finished Jul 10 04:19:53 PM PDT 24
Peak memory 145888 kb
Host smart-55d8ef0c-2074-4ecd-a7af-ea03b548f737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703538082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1703538082
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.284485715
Short name T22
Test name
Test status
Simulation time 11605955 ps
CPU time 0.39 seconds
Started Jul 10 04:19:51 PM PDT 24
Finished Jul 10 04:19:52 PM PDT 24
Peak memory 145228 kb
Host smart-ac10ea37-fea5-42d5-afcd-2c810122d0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284485715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.284485715
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2805809553
Short name T16
Test name
Test status
Simulation time 11089907 ps
CPU time 0.38 seconds
Started Jul 10 04:20:59 PM PDT 24
Finished Jul 10 04:21:00 PM PDT 24
Peak memory 145096 kb
Host smart-84b7ea59-35bf-4c44-bd59-7b7fff093243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805809553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2805809553
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3289576354
Short name T23
Test name
Test status
Simulation time 10770647 ps
CPU time 0.38 seconds
Started Jul 10 04:19:50 PM PDT 24
Finished Jul 10 04:19:51 PM PDT 24
Peak memory 145136 kb
Host smart-49b645ba-46ca-4496-a582-5ded389275db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289576354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3289576354
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.3627005677
Short name T50
Test name
Test status
Simulation time 11152512 ps
CPU time 0.38 seconds
Started Jul 10 04:19:51 PM PDT 24
Finished Jul 10 04:19:53 PM PDT 24
Peak memory 145464 kb
Host smart-e0f42f63-bfe7-460b-8316-7ece1f7d38bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627005677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3627005677
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.607775847
Short name T51
Test name
Test status
Simulation time 10853483 ps
CPU time 0.37 seconds
Started Jul 10 04:21:00 PM PDT 24
Finished Jul 10 04:21:01 PM PDT 24
Peak memory 145168 kb
Host smart-b4e914ae-78f9-4b7a-8cca-348b9a1ee51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607775847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.607775847
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1141713552
Short name T21
Test name
Test status
Simulation time 10781455 ps
CPU time 0.39 seconds
Started Jul 10 04:19:51 PM PDT 24
Finished Jul 10 04:19:53 PM PDT 24
Peak memory 145448 kb
Host smart-3308c4fe-bcef-4f0d-b6fa-6f985138ac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141713552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1141713552
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3908944239
Short name T12
Test name
Test status
Simulation time 12728168 ps
CPU time 0.39 seconds
Started Jul 10 04:20:46 PM PDT 24
Finished Jul 10 04:20:47 PM PDT 24
Peak memory 145888 kb
Host smart-23a7331c-87b0-4e30-aaa3-36a1fc21fc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908944239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3908944239
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3258463458
Short name T11
Test name
Test status
Simulation time 11175632 ps
CPU time 0.39 seconds
Started Jul 10 04:20:47 PM PDT 24
Finished Jul 10 04:20:49 PM PDT 24
Peak memory 145888 kb
Host smart-20681db4-2dee-452d-a9af-727635d414af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258463458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3258463458
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1153915701
Short name T13
Test name
Test status
Simulation time 11341564 ps
CPU time 0.38 seconds
Started Jul 10 04:21:04 PM PDT 24
Finished Jul 10 04:21:05 PM PDT 24
Peak memory 145008 kb
Host smart-57e34021-4b2d-4a99-bfff-08e5ef11762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153915701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1153915701
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.156122078
Short name T2
Test name
Test status
Simulation time 11525129 ps
CPU time 0.38 seconds
Started Jul 10 04:21:14 PM PDT 24
Finished Jul 10 04:21:15 PM PDT 24
Peak memory 145424 kb
Host smart-3b76b06a-4205-4336-8982-6e363acae684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156122078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.156122078
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1993541812
Short name T25
Test name
Test status
Simulation time 10462649 ps
CPU time 0.38 seconds
Started Jul 10 04:19:50 PM PDT 24
Finished Jul 10 04:19:51 PM PDT 24
Peak memory 145192 kb
Host smart-9f46f473-8404-4158-b880-aad4b436c4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993541812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1993541812
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3393699264
Short name T3
Test name
Test status
Simulation time 10464089 ps
CPU time 0.44 seconds
Started Jul 10 04:25:53 PM PDT 24
Finished Jul 10 04:25:54 PM PDT 24
Peak memory 145172 kb
Host smart-33d196fd-c6a0-4041-9c72-a24892e6c887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393699264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3393699264
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3008948191
Short name T10
Test name
Test status
Simulation time 11228736 ps
CPU time 0.39 seconds
Started Jul 10 04:19:51 PM PDT 24
Finished Jul 10 04:19:53 PM PDT 24
Peak memory 145316 kb
Host smart-d3b8d833-1a39-4b8e-9cec-ca7d219ca193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008948191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3008948191
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.53914163
Short name T18
Test name
Test status
Simulation time 11271085 ps
CPU time 0.42 seconds
Started Jul 10 04:19:50 PM PDT 24
Finished Jul 10 04:19:51 PM PDT 24
Peak memory 145188 kb
Host smart-c5e2cea9-d55a-438c-8cc0-60f8b2654cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53914163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.53914163
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.4246311894
Short name T24
Test name
Test status
Simulation time 10742093 ps
CPU time 0.38 seconds
Started Jul 10 04:19:47 PM PDT 24
Finished Jul 10 04:19:48 PM PDT 24
Peak memory 145216 kb
Host smart-7b6b0480-adc3-4153-b106-782b926b0fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246311894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.4246311894
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2289090386
Short name T17
Test name
Test status
Simulation time 11321794 ps
CPU time 0.39 seconds
Started Jul 10 04:20:09 PM PDT 24
Finished Jul 10 04:20:10 PM PDT 24
Peak memory 145416 kb
Host smart-e7a8e358-51c9-4cf6-b607-51bee289fc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289090386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2289090386
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2610963597
Short name T1
Test name
Test status
Simulation time 10646910 ps
CPU time 0.41 seconds
Started Jul 10 04:19:47 PM PDT 24
Finished Jul 10 04:19:48 PM PDT 24
Peak memory 145184 kb
Host smart-b307c6cd-2afb-4927-9596-779f3a8e3f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610963597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2610963597
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4054254195
Short name T14
Test name
Test status
Simulation time 30170943 ps
CPU time 0.41 seconds
Started Jul 10 04:19:50 PM PDT 24
Finished Jul 10 04:19:52 PM PDT 24
Peak memory 145408 kb
Host smart-953f43f2-d863-4eb3-9862-2a80107ffcac
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4054254195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4054254195
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3546731110
Short name T55
Test name
Test status
Simulation time 31978134 ps
CPU time 0.4 seconds
Started Jul 10 04:21:04 PM PDT 24
Finished Jul 10 04:21:06 PM PDT 24
Peak memory 144996 kb
Host smart-cf3d8c74-5cac-4aa1-ad62-8f39de85b351
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3546731110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3546731110
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4221665509
Short name T54
Test name
Test status
Simulation time 30595817 ps
CPU time 0.41 seconds
Started Jul 10 04:20:10 PM PDT 24
Finished Jul 10 04:20:12 PM PDT 24
Peak memory 145076 kb
Host smart-ebac8383-ffa8-41c3-adad-80d84dbad308
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4221665509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.4221665509
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3141903068
Short name T57
Test name
Test status
Simulation time 31709435 ps
CPU time 0.45 seconds
Started Jul 10 04:29:26 PM PDT 24
Finished Jul 10 04:29:28 PM PDT 24
Peak memory 144876 kb
Host smart-f3594b5a-b887-4e41-82ad-e16ca2b12f0a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3141903068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3141903068
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.66000450
Short name T53
Test name
Test status
Simulation time 29221230 ps
CPU time 0.43 seconds
Started Jul 10 04:20:47 PM PDT 24
Finished Jul 10 04:20:49 PM PDT 24
Peak memory 145156 kb
Host smart-9c39f17f-ed31-4bd8-add1-1132e741d8cb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=66000450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.66000450
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1594754150
Short name T48
Test name
Test status
Simulation time 30124645 ps
CPU time 0.43 seconds
Started Jul 10 04:20:47 PM PDT 24
Finished Jul 10 04:20:49 PM PDT 24
Peak memory 144828 kb
Host smart-c9346b13-cdee-4ec6-b9b2-1555b03641fd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1594754150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1594754150
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2906722530
Short name T46
Test name
Test status
Simulation time 31651993 ps
CPU time 0.41 seconds
Started Jul 10 04:21:15 PM PDT 24
Finished Jul 10 04:21:17 PM PDT 24
Peak memory 145096 kb
Host smart-f790a967-7a68-4a65-948b-17194637042c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2906722530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2906722530
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3655034590
Short name T52
Test name
Test status
Simulation time 29768358 ps
CPU time 0.43 seconds
Started Jul 10 04:20:47 PM PDT 24
Finished Jul 10 04:20:49 PM PDT 24
Peak memory 144380 kb
Host smart-dc885194-7e5e-4067-a6e4-228374293b67
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3655034590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3655034590
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1280465175
Short name T42
Test name
Test status
Simulation time 29722349 ps
CPU time 0.5 seconds
Started Jul 10 04:26:13 PM PDT 24
Finished Jul 10 04:26:15 PM PDT 24
Peak memory 145132 kb
Host smart-62ef4e9d-1ec6-45cf-a338-dec1b1070e4d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1280465175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1280465175
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2915912872
Short name T41
Test name
Test status
Simulation time 31480055 ps
CPU time 0.48 seconds
Started Jul 10 04:20:03 PM PDT 24
Finished Jul 10 04:20:04 PM PDT 24
Peak memory 144820 kb
Host smart-d42d0072-2213-4d9b-8512-ff1626a02cca
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2915912872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2915912872
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3865804204
Short name T45
Test name
Test status
Simulation time 31433829 ps
CPU time 0.43 seconds
Started Jul 10 04:20:59 PM PDT 24
Finished Jul 10 04:21:00 PM PDT 24
Peak memory 145312 kb
Host smart-80d3adbb-7dec-49ca-8c7d-28b3e8d45057
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3865804204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3865804204
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1489404131
Short name T59
Test name
Test status
Simulation time 29596890 ps
CPU time 0.41 seconds
Started Jul 10 04:20:47 PM PDT 24
Finished Jul 10 04:20:49 PM PDT 24
Peak memory 145400 kb
Host smart-cf03d08b-9f82-45ca-8651-b16d55c00151
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1489404131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1489404131
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2083379880
Short name T20
Test name
Test status
Simulation time 29055730 ps
CPU time 0.42 seconds
Started Jul 10 04:20:28 PM PDT 24
Finished Jul 10 04:20:29 PM PDT 24
Peak memory 144996 kb
Host smart-3fd6812f-7ce0-4992-aa32-46fe329c7353
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2083379880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2083379880
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3159565133
Short name T44
Test name
Test status
Simulation time 30204484 ps
CPU time 0.41 seconds
Started Jul 10 04:20:32 PM PDT 24
Finished Jul 10 04:20:33 PM PDT 24
Peak memory 145096 kb
Host smart-11026398-bc79-48f0-bf53-d52462ba53c0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3159565133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3159565133
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.612341438
Short name T56
Test name
Test status
Simulation time 29882290 ps
CPU time 0.39 seconds
Started Jul 10 04:21:04 PM PDT 24
Finished Jul 10 04:21:05 PM PDT 24
Peak memory 144616 kb
Host smart-7353619e-70bd-42af-92c1-af9a89cfcfe0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=612341438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.612341438
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.175127801
Short name T58
Test name
Test status
Simulation time 30196691 ps
CPU time 0.39 seconds
Started Jul 10 04:20:47 PM PDT 24
Finished Jul 10 04:20:48 PM PDT 24
Peak memory 145404 kb
Host smart-31de976b-f754-47a6-90b9-67317e6888ee
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=175127801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.175127801
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3712974367
Short name T47
Test name
Test status
Simulation time 27892935 ps
CPU time 0.4 seconds
Started Jul 10 04:20:47 PM PDT 24
Finished Jul 10 04:20:49 PM PDT 24
Peak memory 145408 kb
Host smart-811004da-eab4-47c8-bea2-b15a921de521
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3712974367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3712974367
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.503085815
Short name T34
Test name
Test status
Simulation time 8282336 ps
CPU time 0.39 seconds
Started Jul 10 05:26:22 PM PDT 24
Finished Jul 10 05:26:23 PM PDT 24
Peak memory 145576 kb
Host smart-12994978-0395-4363-b650-d3fe63341a78
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=503085815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.503085815
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2757071616
Short name T28
Test name
Test status
Simulation time 9587483 ps
CPU time 0.43 seconds
Started Jul 10 05:26:21 PM PDT 24
Finished Jul 10 05:26:23 PM PDT 24
Peak memory 145480 kb
Host smart-1bcd2a86-04d0-45ff-9be0-0e38c83cb135
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2757071616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2757071616
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1344356395
Short name T63
Test name
Test status
Simulation time 9099515 ps
CPU time 0.4 seconds
Started Jul 10 05:26:28 PM PDT 24
Finished Jul 10 05:26:30 PM PDT 24
Peak memory 145572 kb
Host smart-088196b4-cb91-43ea-b343-e888befb6419
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1344356395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1344356395
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3060693380
Short name T61
Test name
Test status
Simulation time 8950998 ps
CPU time 0.39 seconds
Started Jul 10 05:26:32 PM PDT 24
Finished Jul 10 05:26:33 PM PDT 24
Peak memory 145516 kb
Host smart-1e33f50f-8f1f-498c-a2bb-699b701e40db
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3060693380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3060693380
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2067269048
Short name T38
Test name
Test status
Simulation time 9382929 ps
CPU time 0.38 seconds
Started Jul 10 05:26:30 PM PDT 24
Finished Jul 10 05:26:32 PM PDT 24
Peak memory 145580 kb
Host smart-c535086e-a25e-4bb7-832d-4651bc24685c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2067269048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2067269048
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2908153727
Short name T35
Test name
Test status
Simulation time 9421340 ps
CPU time 0.39 seconds
Started Jul 10 05:26:29 PM PDT 24
Finished Jul 10 05:26:31 PM PDT 24
Peak memory 145560 kb
Host smart-f77756e3-92f5-4741-9328-83396391e2da
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2908153727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2908153727
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.1039555289
Short name T29
Test name
Test status
Simulation time 10867661 ps
CPU time 0.39 seconds
Started Jul 10 05:26:28 PM PDT 24
Finished Jul 10 05:26:29 PM PDT 24
Peak memory 145580 kb
Host smart-f3efd9f1-ec5f-4d32-9559-4c0597ff1026
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1039555289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1039555289
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.67201810
Short name T62
Test name
Test status
Simulation time 9551801 ps
CPU time 0.38 seconds
Started Jul 10 05:26:28 PM PDT 24
Finished Jul 10 05:26:30 PM PDT 24
Peak memory 145608 kb
Host smart-530ff907-bde9-42c0-b11d-d373732d0343
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=67201810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.67201810
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.123381856
Short name T37
Test name
Test status
Simulation time 8863882 ps
CPU time 0.38 seconds
Started Jul 10 05:26:29 PM PDT 24
Finished Jul 10 05:26:31 PM PDT 24
Peak memory 145488 kb
Host smart-2d37c714-2820-4331-b390-3aac3aae2c8a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=123381856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.123381856
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3046140119
Short name T40
Test name
Test status
Simulation time 8298873 ps
CPU time 0.39 seconds
Started Jul 10 05:26:27 PM PDT 24
Finished Jul 10 05:26:28 PM PDT 24
Peak memory 145560 kb
Host smart-0fb703b5-acc8-442b-8f47-7b8f20f60a60
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3046140119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3046140119
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.566553568
Short name T30
Test name
Test status
Simulation time 9512091 ps
CPU time 0.39 seconds
Started Jul 10 05:26:30 PM PDT 24
Finished Jul 10 05:26:32 PM PDT 24
Peak memory 145556 kb
Host smart-4d211f6a-5115-453f-ae54-d845379e3d3f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=566553568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.566553568
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.769236340
Short name T27
Test name
Test status
Simulation time 8280550 ps
CPU time 0.43 seconds
Started Jul 10 05:26:22 PM PDT 24
Finished Jul 10 05:26:24 PM PDT 24
Peak memory 145484 kb
Host smart-171f46a9-9e00-48ef-a424-e3e5a07d98de
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=769236340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.769236340
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2596863526
Short name T60
Test name
Test status
Simulation time 9100227 ps
CPU time 0.38 seconds
Started Jul 10 05:26:20 PM PDT 24
Finished Jul 10 05:26:22 PM PDT 24
Peak memory 145564 kb
Host smart-6770d9d9-24d3-49bc-b9f5-be6d84b07d5b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2596863526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2596863526
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2223911947
Short name T39
Test name
Test status
Simulation time 9107780 ps
CPU time 0.4 seconds
Started Jul 10 05:26:20 PM PDT 24
Finished Jul 10 05:26:22 PM PDT 24
Peak memory 145572 kb
Host smart-cad8db9a-fb36-4109-8f3a-c61bc5e9abed
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2223911947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2223911947
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.568908670
Short name T36
Test name
Test status
Simulation time 10224631 ps
CPU time 0.42 seconds
Started Jul 10 05:26:20 PM PDT 24
Finished Jul 10 05:26:21 PM PDT 24
Peak memory 145572 kb
Host smart-9a2739ca-5cbd-4679-8947-2dfd6b80eab9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=568908670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.568908670
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3611545317
Short name T8
Test name
Test status
Simulation time 8368906 ps
CPU time 0.39 seconds
Started Jul 10 05:26:28 PM PDT 24
Finished Jul 10 05:26:30 PM PDT 24
Peak memory 145504 kb
Host smart-9a1cc75c-f9f5-4308-a745-5c44b6903e7d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3611545317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3611545317
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.763813796
Short name T33
Test name
Test status
Simulation time 9682879 ps
CPU time 0.38 seconds
Started Jul 10 05:26:28 PM PDT 24
Finished Jul 10 05:26:30 PM PDT 24
Peak memory 145648 kb
Host smart-deba6499-e17a-44cf-a01b-4c30c9dd3b49
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=763813796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.763813796
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1371746731
Short name T26
Test name
Test status
Simulation time 9308486 ps
CPU time 0.38 seconds
Started Jul 10 05:26:30 PM PDT 24
Finished Jul 10 05:26:32 PM PDT 24
Peak memory 145548 kb
Host smart-f87b6573-c627-450e-bbe5-31de94ff8e86
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1371746731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1371746731
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2070170018
Short name T78
Test name
Test status
Simulation time 25600249 ps
CPU time 0.41 seconds
Started Jul 10 05:50:58 PM PDT 24
Finished Jul 10 05:51:03 PM PDT 24
Peak memory 145720 kb
Host smart-e566897d-b61e-4a99-88fd-e3c0321edb5a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2070170018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2070170018
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.97162095
Short name T77
Test name
Test status
Simulation time 27164982 ps
CPU time 0.38 seconds
Started Jul 10 05:50:57 PM PDT 24
Finished Jul 10 05:51:03 PM PDT 24
Peak memory 145572 kb
Host smart-961349a9-c2ab-4209-8483-48ef88d8a161
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=97162095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.97162095
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.793582948
Short name T64
Test name
Test status
Simulation time 28268793 ps
CPU time 0.41 seconds
Started Jul 10 05:50:59 PM PDT 24
Finished Jul 10 05:51:05 PM PDT 24
Peak memory 145548 kb
Host smart-143d33cc-7f14-416d-9c55-ca93a7f511b2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=793582948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.793582948
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3043787867
Short name T71
Test name
Test status
Simulation time 26942484 ps
CPU time 0.39 seconds
Started Jul 10 05:50:51 PM PDT 24
Finished Jul 10 05:50:53 PM PDT 24
Peak memory 145552 kb
Host smart-9ac2d92c-41ff-4313-9b67-b5038f876ff9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3043787867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3043787867
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4127987284
Short name T73
Test name
Test status
Simulation time 27318476 ps
CPU time 0.4 seconds
Started Jul 10 05:50:54 PM PDT 24
Finished Jul 10 05:50:56 PM PDT 24
Peak memory 145576 kb
Host smart-329004ba-6b4b-4d55-9193-2bb2bd0a40eb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4127987284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.4127987284
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2039791225
Short name T66
Test name
Test status
Simulation time 27480352 ps
CPU time 0.4 seconds
Started Jul 10 05:50:54 PM PDT 24
Finished Jul 10 05:50:56 PM PDT 24
Peak memory 145576 kb
Host smart-eadf862c-eaad-4d7d-855b-84ff63931dbc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2039791225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2039791225
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.477169828
Short name T75
Test name
Test status
Simulation time 28069469 ps
CPU time 0.42 seconds
Started Jul 10 05:50:53 PM PDT 24
Finished Jul 10 05:50:55 PM PDT 24
Peak memory 145700 kb
Host smart-a6d02acb-b6b9-4d7d-a7c6-2924288e691c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=477169828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.477169828
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2883257298
Short name T5
Test name
Test status
Simulation time 25415666 ps
CPU time 0.4 seconds
Started Jul 10 05:50:52 PM PDT 24
Finished Jul 10 05:50:54 PM PDT 24
Peak memory 145568 kb
Host smart-7dbd413c-0cea-429d-9a51-7137904f5538
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2883257298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2883257298
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2978606492
Short name T69
Test name
Test status
Simulation time 28539120 ps
CPU time 0.4 seconds
Started Jul 10 05:50:57 PM PDT 24
Finished Jul 10 05:51:02 PM PDT 24
Peak memory 145576 kb
Host smart-44e23b4c-b837-4681-8420-314ac8722baa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2978606492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2978606492
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.368668524
Short name T70
Test name
Test status
Simulation time 27654438 ps
CPU time 0.41 seconds
Started Jul 10 05:50:51 PM PDT 24
Finished Jul 10 05:50:53 PM PDT 24
Peak memory 145568 kb
Host smart-82df9e01-9c0c-4b05-ba53-bfa3ee27ad31
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=368668524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.368668524
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.957724461
Short name T67
Test name
Test status
Simulation time 25115160 ps
CPU time 0.41 seconds
Started Jul 10 05:50:53 PM PDT 24
Finished Jul 10 05:50:55 PM PDT 24
Peak memory 145560 kb
Host smart-e94c15e7-00c9-4501-8a1c-ef46d6a289e7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=957724461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.957724461
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1677472511
Short name T74
Test name
Test status
Simulation time 27311000 ps
CPU time 0.4 seconds
Started Jul 10 05:50:54 PM PDT 24
Finished Jul 10 05:50:56 PM PDT 24
Peak memory 145576 kb
Host smart-db4a4014-1825-496c-974d-662d11e6a247
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1677472511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1677472511
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1815587482
Short name T32
Test name
Test status
Simulation time 26962799 ps
CPU time 0.4 seconds
Started Jul 10 05:50:52 PM PDT 24
Finished Jul 10 05:50:54 PM PDT 24
Peak memory 145588 kb
Host smart-92116685-7a0c-439a-b006-a481e1ee36c7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1815587482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1815587482
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2970588077
Short name T76
Test name
Test status
Simulation time 25606732 ps
CPU time 0.43 seconds
Started Jul 10 05:50:47 PM PDT 24
Finished Jul 10 05:50:49 PM PDT 24
Peak memory 145568 kb
Host smart-83ee53e8-d0a6-4be8-aa6b-402a84545115
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2970588077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2970588077
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.67522260
Short name T79
Test name
Test status
Simulation time 27206002 ps
CPU time 0.41 seconds
Started Jul 10 05:50:48 PM PDT 24
Finished Jul 10 05:50:49 PM PDT 24
Peak memory 145556 kb
Host smart-2b132dbf-d311-4be1-accd-fae6d3c8922e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=67522260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.67522260
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3050949708
Short name T31
Test name
Test status
Simulation time 26011368 ps
CPU time 0.39 seconds
Started Jul 10 05:50:48 PM PDT 24
Finished Jul 10 05:50:50 PM PDT 24
Peak memory 145588 kb
Host smart-1df3d16a-f4f6-491a-8114-fc23795e14d4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3050949708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3050949708
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.621344043
Short name T65
Test name
Test status
Simulation time 28035995 ps
CPU time 0.41 seconds
Started Jul 10 05:50:52 PM PDT 24
Finished Jul 10 05:50:54 PM PDT 24
Peak memory 145580 kb
Host smart-dd3a1623-5f15-454e-a6a4-cce50a82111a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=621344043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.621344043
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2015264441
Short name T6
Test name
Test status
Simulation time 26943994 ps
CPU time 0.41 seconds
Started Jul 10 05:50:47 PM PDT 24
Finished Jul 10 05:50:49 PM PDT 24
Peak memory 145552 kb
Host smart-ffa0b760-1971-4c2d-ae69-30150d124f69
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2015264441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2015264441
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3771095360
Short name T68
Test name
Test status
Simulation time 27968630 ps
CPU time 0.39 seconds
Started Jul 10 05:51:02 PM PDT 24
Finished Jul 10 05:51:08 PM PDT 24
Peak memory 145472 kb
Host smart-d34a9a27-2809-42bd-8064-f38dfc7c6512
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3771095360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3771095360
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1364335849
Short name T72
Test name
Test status
Simulation time 27019237 ps
CPU time 0.39 seconds
Started Jul 10 05:50:52 PM PDT 24
Finished Jul 10 05:50:54 PM PDT 24
Peak memory 145568 kb
Host smart-cde3728c-a803-4dd4-b344-1055f9ffb690
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1364335849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1364335849
Directory /workspace/9.prim_sync_fatal_alert/latest
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