Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.02 89.02 100.00 100.00 95.83 95.83 96.43 96.43 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/14.prim_async_alert.469527264
92.15 3.13 100.00 0.00 95.83 0.00 96.43 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/13.prim_sync_alert.39369995
93.90 1.76 100.00 0.00 95.83 0.00 100.00 3.57 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2090765054
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3629775940
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1686682101
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/3.prim_sync_alert.1442276143

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2282914450
/workspace/coverage/default/1.prim_async_alert.1333420111
/workspace/coverage/default/10.prim_async_alert.3548569280
/workspace/coverage/default/11.prim_async_alert.44401696
/workspace/coverage/default/12.prim_async_alert.2437091766
/workspace/coverage/default/13.prim_async_alert.3894473794
/workspace/coverage/default/15.prim_async_alert.421903306
/workspace/coverage/default/16.prim_async_alert.1110418662
/workspace/coverage/default/17.prim_async_alert.801800610
/workspace/coverage/default/18.prim_async_alert.242218705
/workspace/coverage/default/19.prim_async_alert.1563013746
/workspace/coverage/default/2.prim_async_alert.2837664172
/workspace/coverage/default/3.prim_async_alert.1494276301
/workspace/coverage/default/4.prim_async_alert.2400727442
/workspace/coverage/default/5.prim_async_alert.833580460
/workspace/coverage/default/6.prim_async_alert.33984158
/workspace/coverage/default/7.prim_async_alert.15992608
/workspace/coverage/default/8.prim_async_alert.4141923948
/workspace/coverage/default/9.prim_async_alert.2485065361
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.410683990
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.45958691
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.388189389
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2024798808
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.817751236
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3981393349
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1125935441
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.394864415
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2428357833
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1184358130
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1200735117
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.806818351
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3319917549
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4015589626
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1606624073
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4144686096
/workspace/coverage/sync_alert/0.prim_sync_alert.2402379986
/workspace/coverage/sync_alert/1.prim_sync_alert.929574328
/workspace/coverage/sync_alert/10.prim_sync_alert.307586712
/workspace/coverage/sync_alert/11.prim_sync_alert.429389165
/workspace/coverage/sync_alert/12.prim_sync_alert.9675012
/workspace/coverage/sync_alert/14.prim_sync_alert.3728973649
/workspace/coverage/sync_alert/15.prim_sync_alert.1146043335
/workspace/coverage/sync_alert/16.prim_sync_alert.3656147127
/workspace/coverage/sync_alert/17.prim_sync_alert.1482572453
/workspace/coverage/sync_alert/18.prim_sync_alert.2318510979
/workspace/coverage/sync_alert/19.prim_sync_alert.1791422750
/workspace/coverage/sync_alert/2.prim_sync_alert.4094086389
/workspace/coverage/sync_alert/4.prim_sync_alert.3065062561
/workspace/coverage/sync_alert/5.prim_sync_alert.599250953
/workspace/coverage/sync_alert/6.prim_sync_alert.3644460151
/workspace/coverage/sync_alert/7.prim_sync_alert.1149231919
/workspace/coverage/sync_alert/8.prim_sync_alert.1163676033
/workspace/coverage/sync_alert/9.prim_sync_alert.1624487433
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3709654227
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3952140821
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2505868738
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1443119620
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3638772310
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.916701781
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1065240676
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3985632261
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.812469386
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2094446880
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.379107884
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2655699298
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1633753005
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1681953635
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3559367863
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3772141876
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3748191870
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4055855383
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2039556710
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3604237382



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/16.prim_async_alert.1110418662 Jul 11 04:47:04 PM PDT 24 Jul 11 04:47:05 PM PDT 24 11159086 ps
T2 /workspace/coverage/default/9.prim_async_alert.2485065361 Jul 11 04:46:49 PM PDT 24 Jul 11 04:46:51 PM PDT 24 11735821 ps
T3 /workspace/coverage/default/10.prim_async_alert.3548569280 Jul 11 04:46:56 PM PDT 24 Jul 11 04:46:57 PM PDT 24 11043783 ps
T11 /workspace/coverage/default/4.prim_async_alert.2400727442 Jul 11 04:46:58 PM PDT 24 Jul 11 04:46:59 PM PDT 24 11926563 ps
T19 /workspace/coverage/default/11.prim_async_alert.44401696 Jul 11 04:46:50 PM PDT 24 Jul 11 04:46:51 PM PDT 24 10892905 ps
T7 /workspace/coverage/default/13.prim_async_alert.3894473794 Jul 11 04:46:56 PM PDT 24 Jul 11 04:46:58 PM PDT 24 10434347 ps
T8 /workspace/coverage/default/6.prim_async_alert.33984158 Jul 11 04:47:00 PM PDT 24 Jul 11 04:47:02 PM PDT 24 11594152 ps
T16 /workspace/coverage/default/14.prim_async_alert.469527264 Jul 11 04:46:52 PM PDT 24 Jul 11 04:46:54 PM PDT 24 11533593 ps
T20 /workspace/coverage/default/3.prim_async_alert.1494276301 Jul 11 04:46:53 PM PDT 24 Jul 11 04:46:55 PM PDT 24 11321699 ps
T12 /workspace/coverage/default/19.prim_async_alert.1563013746 Jul 11 04:46:56 PM PDT 24 Jul 11 04:46:58 PM PDT 24 11573656 ps
T21 /workspace/coverage/default/2.prim_async_alert.2837664172 Jul 11 04:46:59 PM PDT 24 Jul 11 04:47:01 PM PDT 24 11197521 ps
T22 /workspace/coverage/default/12.prim_async_alert.2437091766 Jul 11 04:46:55 PM PDT 24 Jul 11 04:46:56 PM PDT 24 11910234 ps
T48 /workspace/coverage/default/7.prim_async_alert.15992608 Jul 11 04:46:52 PM PDT 24 Jul 11 04:46:53 PM PDT 24 11705600 ps
T23 /workspace/coverage/default/1.prim_async_alert.1333420111 Jul 11 04:46:56 PM PDT 24 Jul 11 04:46:58 PM PDT 24 12705183 ps
T17 /workspace/coverage/default/15.prim_async_alert.421903306 Jul 11 04:46:53 PM PDT 24 Jul 11 04:46:54 PM PDT 24 11275648 ps
T15 /workspace/coverage/default/8.prim_async_alert.4141923948 Jul 11 04:46:49 PM PDT 24 Jul 11 04:46:50 PM PDT 24 11215901 ps
T49 /workspace/coverage/default/17.prim_async_alert.801800610 Jul 11 04:46:56 PM PDT 24 Jul 11 04:46:58 PM PDT 24 10358009 ps
T24 /workspace/coverage/default/18.prim_async_alert.242218705 Jul 11 04:47:00 PM PDT 24 Jul 11 04:47:02 PM PDT 24 11128286 ps
T18 /workspace/coverage/default/0.prim_async_alert.2282914450 Jul 11 04:46:53 PM PDT 24 Jul 11 04:46:54 PM PDT 24 10547845 ps
T50 /workspace/coverage/default/5.prim_async_alert.833580460 Jul 11 04:46:53 PM PDT 24 Jul 11 04:46:55 PM PDT 24 11057698 ps
T40 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.806818351 Jul 11 04:51:11 PM PDT 24 Jul 11 04:51:14 PM PDT 24 29573212 ps
T41 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2090765054 Jul 11 04:51:13 PM PDT 24 Jul 11 04:51:15 PM PDT 24 32401269 ps
T42 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.817751236 Jul 11 04:51:21 PM PDT 24 Jul 11 04:51:25 PM PDT 24 28759873 ps
T43 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.388189389 Jul 11 04:51:17 PM PDT 24 Jul 11 04:51:19 PM PDT 24 30811508 ps
T44 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.394864415 Jul 11 04:51:19 PM PDT 24 Jul 11 04:51:21 PM PDT 24 31301904 ps
T4 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4144686096 Jul 11 04:51:22 PM PDT 24 Jul 11 04:51:26 PM PDT 24 29116909 ps
T45 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1125935441 Jul 11 04:51:19 PM PDT 24 Jul 11 04:51:21 PM PDT 24 29965116 ps
T5 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1686682101 Jul 11 04:51:20 PM PDT 24 Jul 11 04:51:24 PM PDT 24 30055121 ps
T46 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2428357833 Jul 11 04:51:20 PM PDT 24 Jul 11 04:51:23 PM PDT 24 30150954 ps
T47 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3981393349 Jul 11 04:51:19 PM PDT 24 Jul 11 04:51:21 PM PDT 24 30001808 ps
T51 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2024798808 Jul 11 04:51:22 PM PDT 24 Jul 11 04:51:27 PM PDT 24 29494272 ps
T52 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1606624073 Jul 11 04:51:14 PM PDT 24 Jul 11 04:51:17 PM PDT 24 30737405 ps
T53 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4015589626 Jul 11 04:51:13 PM PDT 24 Jul 11 04:51:15 PM PDT 24 30773448 ps
T13 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3629775940 Jul 11 04:51:21 PM PDT 24 Jul 11 04:51:25 PM PDT 24 30899511 ps
T54 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.45958691 Jul 11 04:51:20 PM PDT 24 Jul 11 04:51:23 PM PDT 24 27801455 ps
T55 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1200735117 Jul 11 04:51:11 PM PDT 24 Jul 11 04:51:14 PM PDT 24 31786532 ps
T56 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1184358130 Jul 11 04:51:16 PM PDT 24 Jul 11 04:51:18 PM PDT 24 29184217 ps
T57 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3319917549 Jul 11 04:51:21 PM PDT 24 Jul 11 04:51:25 PM PDT 24 29005204 ps
T58 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.410683990 Jul 11 04:51:15 PM PDT 24 Jul 11 04:51:17 PM PDT 24 33505704 ps
T25 /workspace/coverage/sync_alert/2.prim_sync_alert.4094086389 Jul 11 06:06:50 PM PDT 24 Jul 11 06:06:52 PM PDT 24 9041211 ps
T9 /workspace/coverage/sync_alert/3.prim_sync_alert.1442276143 Jul 11 06:06:47 PM PDT 24 Jul 11 06:06:50 PM PDT 24 8502974 ps
T34 /workspace/coverage/sync_alert/8.prim_sync_alert.1163676033 Jul 11 06:06:54 PM PDT 24 Jul 11 06:06:56 PM PDT 24 8390012 ps
T26 /workspace/coverage/sync_alert/4.prim_sync_alert.3065062561 Jul 11 06:06:49 PM PDT 24 Jul 11 06:06:51 PM PDT 24 9694895 ps
T35 /workspace/coverage/sync_alert/1.prim_sync_alert.929574328 Jul 11 06:06:48 PM PDT 24 Jul 11 06:06:50 PM PDT 24 8844168 ps
T36 /workspace/coverage/sync_alert/5.prim_sync_alert.599250953 Jul 11 06:06:56 PM PDT 24 Jul 11 06:06:59 PM PDT 24 8889679 ps
T27 /workspace/coverage/sync_alert/13.prim_sync_alert.39369995 Jul 11 06:06:49 PM PDT 24 Jul 11 06:06:51 PM PDT 24 10336243 ps
T37 /workspace/coverage/sync_alert/18.prim_sync_alert.2318510979 Jul 11 06:06:56 PM PDT 24 Jul 11 06:06:59 PM PDT 24 10034315 ps
T38 /workspace/coverage/sync_alert/14.prim_sync_alert.3728973649 Jul 11 06:06:56 PM PDT 24 Jul 11 06:06:58 PM PDT 24 8533230 ps
T39 /workspace/coverage/sync_alert/11.prim_sync_alert.429389165 Jul 11 06:06:51 PM PDT 24 Jul 11 06:06:53 PM PDT 24 9120224 ps
T59 /workspace/coverage/sync_alert/16.prim_sync_alert.3656147127 Jul 11 06:06:55 PM PDT 24 Jul 11 06:06:57 PM PDT 24 8844351 ps
T28 /workspace/coverage/sync_alert/0.prim_sync_alert.2402379986 Jul 11 06:06:47 PM PDT 24 Jul 11 06:06:49 PM PDT 24 9089981 ps
T60 /workspace/coverage/sync_alert/17.prim_sync_alert.1482572453 Jul 11 06:07:01 PM PDT 24 Jul 11 06:07:03 PM PDT 24 9121151 ps
T29 /workspace/coverage/sync_alert/15.prim_sync_alert.1146043335 Jul 11 06:06:52 PM PDT 24 Jul 11 06:06:54 PM PDT 24 8949810 ps
T61 /workspace/coverage/sync_alert/12.prim_sync_alert.9675012 Jul 11 06:06:51 PM PDT 24 Jul 11 06:06:53 PM PDT 24 9688643 ps
T62 /workspace/coverage/sync_alert/19.prim_sync_alert.1791422750 Jul 11 06:06:58 PM PDT 24 Jul 11 06:07:00 PM PDT 24 8446278 ps
T63 /workspace/coverage/sync_alert/9.prim_sync_alert.1624487433 Jul 11 06:06:55 PM PDT 24 Jul 11 06:06:57 PM PDT 24 9371075 ps
T30 /workspace/coverage/sync_alert/6.prim_sync_alert.3644460151 Jul 11 06:06:50 PM PDT 24 Jul 11 06:06:52 PM PDT 24 9588471 ps
T64 /workspace/coverage/sync_alert/7.prim_sync_alert.1149231919 Jul 11 06:06:50 PM PDT 24 Jul 11 06:06:52 PM PDT 24 8463339 ps
T31 /workspace/coverage/sync_alert/10.prim_sync_alert.307586712 Jul 11 06:06:53 PM PDT 24 Jul 11 06:06:55 PM PDT 24 9922785 ps
T65 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1065240676 Jul 11 06:41:44 PM PDT 24 Jul 11 06:41:45 PM PDT 24 27293455 ps
T32 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1443119620 Jul 11 06:41:45 PM PDT 24 Jul 11 06:41:47 PM PDT 24 26941799 ps
T66 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3748191870 Jul 11 06:41:42 PM PDT 24 Jul 11 06:41:44 PM PDT 24 28039670 ps
T33 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3638772310 Jul 11 06:41:41 PM PDT 24 Jul 11 06:41:42 PM PDT 24 28859209 ps
T67 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2655699298 Jul 11 06:41:46 PM PDT 24 Jul 11 06:41:47 PM PDT 24 27809044 ps
T68 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.379107884 Jul 11 06:41:49 PM PDT 24 Jul 11 06:41:50 PM PDT 24 28912733 ps
T10 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3709654227 Jul 11 06:41:43 PM PDT 24 Jul 11 06:41:44 PM PDT 24 26577276 ps
T69 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1681953635 Jul 11 06:41:45 PM PDT 24 Jul 11 06:41:47 PM PDT 24 28239067 ps
T70 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2039556710 Jul 11 06:41:42 PM PDT 24 Jul 11 06:41:44 PM PDT 24 26959579 ps
T71 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3604237382 Jul 11 06:41:45 PM PDT 24 Jul 11 06:41:47 PM PDT 24 29415250 ps
T72 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4055855383 Jul 11 06:41:44 PM PDT 24 Jul 11 06:41:46 PM PDT 24 28321682 ps
T73 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3985632261 Jul 11 06:41:46 PM PDT 24 Jul 11 06:41:48 PM PDT 24 25668597 ps
T74 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3559367863 Jul 11 06:41:42 PM PDT 24 Jul 11 06:41:43 PM PDT 24 27304236 ps
T75 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.812469386 Jul 11 06:41:43 PM PDT 24 Jul 11 06:41:44 PM PDT 24 27225087 ps
T6 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2094446880 Jul 11 06:41:46 PM PDT 24 Jul 11 06:41:48 PM PDT 24 27868739 ps
T76 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3952140821 Jul 11 06:41:42 PM PDT 24 Jul 11 06:41:44 PM PDT 24 27311235 ps
T77 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.916701781 Jul 11 06:41:49 PM PDT 24 Jul 11 06:41:50 PM PDT 24 26041373 ps
T78 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3772141876 Jul 11 06:41:43 PM PDT 24 Jul 11 06:41:44 PM PDT 24 29480953 ps
T79 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1633753005 Jul 11 06:41:43 PM PDT 24 Jul 11 06:41:44 PM PDT 24 27264335 ps
T14 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2505868738 Jul 11 06:41:43 PM PDT 24 Jul 11 06:41:44 PM PDT 24 26926295 ps

Test location /workspace/coverage/default/14.prim_async_alert.469527264
Short name T16
Test name
Test status
Simulation time 11533593 ps
CPU time 0.4 seconds
Started Jul 11 04:46:52 PM PDT 24
Finished Jul 11 04:46:54 PM PDT 24
Peak memory 145648 kb
Host smart-9927eed0-54b4-496f-a1d7-daca0f01699d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469527264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.469527264
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.39369995
Short name T27
Test name
Test status
Simulation time 10336243 ps
CPU time 0.38 seconds
Started Jul 11 06:06:49 PM PDT 24
Finished Jul 11 06:06:51 PM PDT 24
Peak memory 145516 kb
Host smart-db4ee3fa-0985-4fbc-840b-2fba3af9fde9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=39369995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.39369995
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2090765054
Short name T41
Test name
Test status
Simulation time 32401269 ps
CPU time 0.41 seconds
Started Jul 11 04:51:13 PM PDT 24
Finished Jul 11 04:51:15 PM PDT 24
Peak memory 145404 kb
Host smart-7daa3ec5-916c-411a-993a-36a77960a8b8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2090765054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2090765054
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3629775940
Short name T13
Test name
Test status
Simulation time 30899511 ps
CPU time 0.44 seconds
Started Jul 11 04:51:21 PM PDT 24
Finished Jul 11 04:51:25 PM PDT 24
Peak memory 145320 kb
Host smart-7029763a-a43f-4b4b-a78a-6b5488948642
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3629775940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3629775940
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1686682101
Short name T5
Test name
Test status
Simulation time 30055121 ps
CPU time 0.4 seconds
Started Jul 11 04:51:20 PM PDT 24
Finished Jul 11 04:51:24 PM PDT 24
Peak memory 145248 kb
Host smart-82683bcb-0047-4e09-b8a0-927bd1068b4d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1686682101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1686682101
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1442276143
Short name T9
Test name
Test status
Simulation time 8502974 ps
CPU time 0.38 seconds
Started Jul 11 06:06:47 PM PDT 24
Finished Jul 11 06:06:50 PM PDT 24
Peak memory 145572 kb
Host smart-3fbcb9a4-ca95-4d20-83be-4be5b02add38
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1442276143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1442276143
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2282914450
Short name T18
Test name
Test status
Simulation time 10547845 ps
CPU time 0.42 seconds
Started Jul 11 04:46:53 PM PDT 24
Finished Jul 11 04:46:54 PM PDT 24
Peak memory 145656 kb
Host smart-bfd95e9e-56a8-4c6a-823c-3d267117ec18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282914450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2282914450
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1333420111
Short name T23
Test name
Test status
Simulation time 12705183 ps
CPU time 0.43 seconds
Started Jul 11 04:46:56 PM PDT 24
Finished Jul 11 04:46:58 PM PDT 24
Peak memory 145680 kb
Host smart-8bd8a590-c98f-493c-8582-af5567ff37f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333420111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1333420111
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3548569280
Short name T3
Test name
Test status
Simulation time 11043783 ps
CPU time 0.4 seconds
Started Jul 11 04:46:56 PM PDT 24
Finished Jul 11 04:46:57 PM PDT 24
Peak memory 145792 kb
Host smart-917b3379-acc1-43db-9a8d-10140da52555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548569280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3548569280
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.44401696
Short name T19
Test name
Test status
Simulation time 10892905 ps
CPU time 0.4 seconds
Started Jul 11 04:46:50 PM PDT 24
Finished Jul 11 04:46:51 PM PDT 24
Peak memory 145768 kb
Host smart-f36d9bf4-3946-4781-ba25-147a652cec96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44401696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.44401696
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2437091766
Short name T22
Test name
Test status
Simulation time 11910234 ps
CPU time 0.38 seconds
Started Jul 11 04:46:55 PM PDT 24
Finished Jul 11 04:46:56 PM PDT 24
Peak memory 145788 kb
Host smart-83601626-4bd2-4660-9dd0-60b062f5c5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437091766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2437091766
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3894473794
Short name T7
Test name
Test status
Simulation time 10434347 ps
CPU time 0.4 seconds
Started Jul 11 04:46:56 PM PDT 24
Finished Jul 11 04:46:58 PM PDT 24
Peak memory 145636 kb
Host smart-cde59a20-b693-47f8-885f-1b74f022cf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894473794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3894473794
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.421903306
Short name T17
Test name
Test status
Simulation time 11275648 ps
CPU time 0.41 seconds
Started Jul 11 04:46:53 PM PDT 24
Finished Jul 11 04:46:54 PM PDT 24
Peak memory 145672 kb
Host smart-82e0640e-6a86-474b-b418-89c779806f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421903306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.421903306
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1110418662
Short name T1
Test name
Test status
Simulation time 11159086 ps
CPU time 0.41 seconds
Started Jul 11 04:47:04 PM PDT 24
Finished Jul 11 04:47:05 PM PDT 24
Peak memory 145788 kb
Host smart-0a35789a-b0d5-4917-b127-434f5f0cf575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110418662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1110418662
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.801800610
Short name T49
Test name
Test status
Simulation time 10358009 ps
CPU time 0.42 seconds
Started Jul 11 04:46:56 PM PDT 24
Finished Jul 11 04:46:58 PM PDT 24
Peak memory 145788 kb
Host smart-56167d76-921f-47a3-ace4-d7547f2894a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801800610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.801800610
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.242218705
Short name T24
Test name
Test status
Simulation time 11128286 ps
CPU time 0.4 seconds
Started Jul 11 04:47:00 PM PDT 24
Finished Jul 11 04:47:02 PM PDT 24
Peak memory 145784 kb
Host smart-b9662112-1de5-447c-99da-cfd4e8e4489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242218705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.242218705
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1563013746
Short name T12
Test name
Test status
Simulation time 11573656 ps
CPU time 0.41 seconds
Started Jul 11 04:46:56 PM PDT 24
Finished Jul 11 04:46:58 PM PDT 24
Peak memory 145656 kb
Host smart-9588f9dd-db80-4d40-9f16-f90eb6a2b6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563013746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1563013746
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2837664172
Short name T21
Test name
Test status
Simulation time 11197521 ps
CPU time 0.4 seconds
Started Jul 11 04:46:59 PM PDT 24
Finished Jul 11 04:47:01 PM PDT 24
Peak memory 145772 kb
Host smart-f3764acb-7796-44fd-877c-556e713abef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837664172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2837664172
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1494276301
Short name T20
Test name
Test status
Simulation time 11321699 ps
CPU time 0.4 seconds
Started Jul 11 04:46:53 PM PDT 24
Finished Jul 11 04:46:55 PM PDT 24
Peak memory 145644 kb
Host smart-c1689ae9-c28c-41d8-b31b-961d68770fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494276301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1494276301
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2400727442
Short name T11
Test name
Test status
Simulation time 11926563 ps
CPU time 0.38 seconds
Started Jul 11 04:46:58 PM PDT 24
Finished Jul 11 04:46:59 PM PDT 24
Peak memory 145660 kb
Host smart-2d05ab52-35f7-4edc-a626-ecbe24480f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400727442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2400727442
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.833580460
Short name T50
Test name
Test status
Simulation time 11057698 ps
CPU time 0.39 seconds
Started Jul 11 04:46:53 PM PDT 24
Finished Jul 11 04:46:55 PM PDT 24
Peak memory 145628 kb
Host smart-d3f4c751-05e7-43fc-808b-b376dbfe92c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833580460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.833580460
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.33984158
Short name T8
Test name
Test status
Simulation time 11594152 ps
CPU time 0.38 seconds
Started Jul 11 04:47:00 PM PDT 24
Finished Jul 11 04:47:02 PM PDT 24
Peak memory 145660 kb
Host smart-a25d579c-881b-4748-a6eb-53dcf1df5bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33984158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.33984158
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.15992608
Short name T48
Test name
Test status
Simulation time 11705600 ps
CPU time 0.38 seconds
Started Jul 11 04:46:52 PM PDT 24
Finished Jul 11 04:46:53 PM PDT 24
Peak memory 145656 kb
Host smart-3ee113f4-87ea-41aa-9ad4-efae9d66a5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15992608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.15992608
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.4141923948
Short name T15
Test name
Test status
Simulation time 11215901 ps
CPU time 0.4 seconds
Started Jul 11 04:46:49 PM PDT 24
Finished Jul 11 04:46:50 PM PDT 24
Peak memory 145660 kb
Host smart-0ae5d229-d4d4-4a75-b138-be5682c1b589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141923948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.4141923948
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2485065361
Short name T2
Test name
Test status
Simulation time 11735821 ps
CPU time 0.42 seconds
Started Jul 11 04:46:49 PM PDT 24
Finished Jul 11 04:46:51 PM PDT 24
Peak memory 145648 kb
Host smart-63035066-ce69-4bf2-b01d-e70aff8b686d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485065361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2485065361
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.410683990
Short name T58
Test name
Test status
Simulation time 33505704 ps
CPU time 0.45 seconds
Started Jul 11 04:51:15 PM PDT 24
Finished Jul 11 04:51:17 PM PDT 24
Peak memory 145232 kb
Host smart-fde1ea33-5c57-4318-b9e5-d0cca8196efe
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=410683990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.410683990
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.45958691
Short name T54
Test name
Test status
Simulation time 27801455 ps
CPU time 0.4 seconds
Started Jul 11 04:51:20 PM PDT 24
Finished Jul 11 04:51:23 PM PDT 24
Peak memory 145300 kb
Host smart-cede5f32-ee90-4c9a-af75-e19155e5cd7f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=45958691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.45958691
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.388189389
Short name T43
Test name
Test status
Simulation time 30811508 ps
CPU time 0.39 seconds
Started Jul 11 04:51:17 PM PDT 24
Finished Jul 11 04:51:19 PM PDT 24
Peak memory 145232 kb
Host smart-2eb57a25-3a0f-40f8-a2b0-98cc62d0b742
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=388189389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.388189389
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2024798808
Short name T51
Test name
Test status
Simulation time 29494272 ps
CPU time 0.4 seconds
Started Jul 11 04:51:22 PM PDT 24
Finished Jul 11 04:51:27 PM PDT 24
Peak memory 145320 kb
Host smart-e0a29c6c-d300-4502-b955-e8bade633f87
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2024798808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2024798808
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.817751236
Short name T42
Test name
Test status
Simulation time 28759873 ps
CPU time 0.4 seconds
Started Jul 11 04:51:21 PM PDT 24
Finished Jul 11 04:51:25 PM PDT 24
Peak memory 145316 kb
Host smart-84ace8c3-fd13-43f9-b794-397c350e992c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=817751236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.817751236
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3981393349
Short name T47
Test name
Test status
Simulation time 30001808 ps
CPU time 0.4 seconds
Started Jul 11 04:51:19 PM PDT 24
Finished Jul 11 04:51:21 PM PDT 24
Peak memory 145240 kb
Host smart-9eee49b2-6f4a-40eb-81ff-c16f4b5d655d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3981393349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3981393349
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1125935441
Short name T45
Test name
Test status
Simulation time 29965116 ps
CPU time 0.41 seconds
Started Jul 11 04:51:19 PM PDT 24
Finished Jul 11 04:51:21 PM PDT 24
Peak memory 145228 kb
Host smart-a4d0e932-8c1e-43e6-9b15-35b752777783
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1125935441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1125935441
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.394864415
Short name T44
Test name
Test status
Simulation time 31301904 ps
CPU time 0.47 seconds
Started Jul 11 04:51:19 PM PDT 24
Finished Jul 11 04:51:21 PM PDT 24
Peak memory 145228 kb
Host smart-41e646d4-a2b7-4765-91f6-a29c1ce94575
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=394864415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.394864415
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2428357833
Short name T46
Test name
Test status
Simulation time 30150954 ps
CPU time 0.4 seconds
Started Jul 11 04:51:20 PM PDT 24
Finished Jul 11 04:51:23 PM PDT 24
Peak memory 145252 kb
Host smart-04c5921b-650f-4151-998f-39fefb931a2e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2428357833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2428357833
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1184358130
Short name T56
Test name
Test status
Simulation time 29184217 ps
CPU time 0.41 seconds
Started Jul 11 04:51:16 PM PDT 24
Finished Jul 11 04:51:18 PM PDT 24
Peak memory 145236 kb
Host smart-2aadad71-c076-4538-8636-d0bd70dcc417
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1184358130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1184358130
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1200735117
Short name T55
Test name
Test status
Simulation time 31786532 ps
CPU time 0.4 seconds
Started Jul 11 04:51:11 PM PDT 24
Finished Jul 11 04:51:14 PM PDT 24
Peak memory 145244 kb
Host smart-f057ca54-73fd-41ba-9778-f287f3383c97
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1200735117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1200735117
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.806818351
Short name T40
Test name
Test status
Simulation time 29573212 ps
CPU time 0.4 seconds
Started Jul 11 04:51:11 PM PDT 24
Finished Jul 11 04:51:14 PM PDT 24
Peak memory 145312 kb
Host smart-606f6a26-5738-4c2a-8b77-1601bff1b5ea
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=806818351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.806818351
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3319917549
Short name T57
Test name
Test status
Simulation time 29005204 ps
CPU time 0.4 seconds
Started Jul 11 04:51:21 PM PDT 24
Finished Jul 11 04:51:25 PM PDT 24
Peak memory 145320 kb
Host smart-e4a5562f-71e0-4301-bb7d-d005c84e6d9f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3319917549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3319917549
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4015589626
Short name T53
Test name
Test status
Simulation time 30773448 ps
CPU time 0.4 seconds
Started Jul 11 04:51:13 PM PDT 24
Finished Jul 11 04:51:15 PM PDT 24
Peak memory 145184 kb
Host smart-48261e18-d239-410c-a1a3-f6e470addfd4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4015589626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.4015589626
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1606624073
Short name T52
Test name
Test status
Simulation time 30737405 ps
CPU time 0.41 seconds
Started Jul 11 04:51:14 PM PDT 24
Finished Jul 11 04:51:17 PM PDT 24
Peak memory 145316 kb
Host smart-d767ef8d-3d16-47d6-aef3-c11e8a25af92
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1606624073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1606624073
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4144686096
Short name T4
Test name
Test status
Simulation time 29116909 ps
CPU time 0.41 seconds
Started Jul 11 04:51:22 PM PDT 24
Finished Jul 11 04:51:26 PM PDT 24
Peak memory 145320 kb
Host smart-27e275bd-35bf-4acf-8811-77955608372a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4144686096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.4144686096
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2402379986
Short name T28
Test name
Test status
Simulation time 9089981 ps
CPU time 0.42 seconds
Started Jul 11 06:06:47 PM PDT 24
Finished Jul 11 06:06:49 PM PDT 24
Peak memory 145580 kb
Host smart-86070003-70aa-447f-9531-43b7b3263fed
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2402379986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2402379986
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.929574328
Short name T35
Test name
Test status
Simulation time 8844168 ps
CPU time 0.39 seconds
Started Jul 11 06:06:48 PM PDT 24
Finished Jul 11 06:06:50 PM PDT 24
Peak memory 145584 kb
Host smart-d6db7fbf-8f8a-4be3-9dec-89ca32e2ec65
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=929574328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.929574328
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.307586712
Short name T31
Test name
Test status
Simulation time 9922785 ps
CPU time 0.39 seconds
Started Jul 11 06:06:53 PM PDT 24
Finished Jul 11 06:06:55 PM PDT 24
Peak memory 145588 kb
Host smart-b018367c-9022-44e2-a9b0-aba371c4d045
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=307586712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.307586712
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.429389165
Short name T39
Test name
Test status
Simulation time 9120224 ps
CPU time 0.38 seconds
Started Jul 11 06:06:51 PM PDT 24
Finished Jul 11 06:06:53 PM PDT 24
Peak memory 145588 kb
Host smart-eb64a967-3ffb-46ab-ac1f-aa38bc8f0ea7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=429389165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.429389165
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.9675012
Short name T61
Test name
Test status
Simulation time 9688643 ps
CPU time 0.39 seconds
Started Jul 11 06:06:51 PM PDT 24
Finished Jul 11 06:06:53 PM PDT 24
Peak memory 145572 kb
Host smart-8e5bed10-4bf5-4cc3-8456-bc5f59f4a71f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=9675012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.9675012
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3728973649
Short name T38
Test name
Test status
Simulation time 8533230 ps
CPU time 0.37 seconds
Started Jul 11 06:06:56 PM PDT 24
Finished Jul 11 06:06:58 PM PDT 24
Peak memory 145576 kb
Host smart-521a5af7-b698-4a24-beb1-ebe0eed0733d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3728973649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3728973649
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1146043335
Short name T29
Test name
Test status
Simulation time 8949810 ps
CPU time 0.39 seconds
Started Jul 11 06:06:52 PM PDT 24
Finished Jul 11 06:06:54 PM PDT 24
Peak memory 145572 kb
Host smart-abe943c8-0413-4644-b86c-fc929ca1ccc8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1146043335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1146043335
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3656147127
Short name T59
Test name
Test status
Simulation time 8844351 ps
CPU time 0.38 seconds
Started Jul 11 06:06:55 PM PDT 24
Finished Jul 11 06:06:57 PM PDT 24
Peak memory 145576 kb
Host smart-87b95997-ec21-49ea-b643-b8a6553ca77c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3656147127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3656147127
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1482572453
Short name T60
Test name
Test status
Simulation time 9121151 ps
CPU time 0.39 seconds
Started Jul 11 06:07:01 PM PDT 24
Finished Jul 11 06:07:03 PM PDT 24
Peak memory 145576 kb
Host smart-116c73b6-97dc-46b5-bb00-160e0dbb1693
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1482572453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1482572453
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2318510979
Short name T37
Test name
Test status
Simulation time 10034315 ps
CPU time 0.37 seconds
Started Jul 11 06:06:56 PM PDT 24
Finished Jul 11 06:06:59 PM PDT 24
Peak memory 145548 kb
Host smart-e1c3fc99-dc23-4467-8da3-9070d98467b4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2318510979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2318510979
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1791422750
Short name T62
Test name
Test status
Simulation time 8446278 ps
CPU time 0.38 seconds
Started Jul 11 06:06:58 PM PDT 24
Finished Jul 11 06:07:00 PM PDT 24
Peak memory 145576 kb
Host smart-fb8ccdbe-76f5-40c8-b7f2-840057e66907
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1791422750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1791422750
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.4094086389
Short name T25
Test name
Test status
Simulation time 9041211 ps
CPU time 0.39 seconds
Started Jul 11 06:06:50 PM PDT 24
Finished Jul 11 06:06:52 PM PDT 24
Peak memory 145548 kb
Host smart-cb8c9fff-0612-4290-b85f-68f7cd1e4dae
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4094086389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.4094086389
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3065062561
Short name T26
Test name
Test status
Simulation time 9694895 ps
CPU time 0.38 seconds
Started Jul 11 06:06:49 PM PDT 24
Finished Jul 11 06:06:51 PM PDT 24
Peak memory 145576 kb
Host smart-f64b8299-6919-4dd7-9b43-44ef652bfc15
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3065062561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3065062561
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.599250953
Short name T36
Test name
Test status
Simulation time 8889679 ps
CPU time 0.38 seconds
Started Jul 11 06:06:56 PM PDT 24
Finished Jul 11 06:06:59 PM PDT 24
Peak memory 145576 kb
Host smart-df9c9878-ad97-46b5-b57a-73a726b5dc76
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=599250953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.599250953
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3644460151
Short name T30
Test name
Test status
Simulation time 9588471 ps
CPU time 0.4 seconds
Started Jul 11 06:06:50 PM PDT 24
Finished Jul 11 06:06:52 PM PDT 24
Peak memory 145592 kb
Host smart-9b755524-96ae-40ef-a91d-c022832005a6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3644460151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3644460151
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1149231919
Short name T64
Test name
Test status
Simulation time 8463339 ps
CPU time 0.38 seconds
Started Jul 11 06:06:50 PM PDT 24
Finished Jul 11 06:06:52 PM PDT 24
Peak memory 145580 kb
Host smart-974a1363-a3c4-4942-b752-3d4435deeb53
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1149231919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1149231919
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1163676033
Short name T34
Test name
Test status
Simulation time 8390012 ps
CPU time 0.38 seconds
Started Jul 11 06:06:54 PM PDT 24
Finished Jul 11 06:06:56 PM PDT 24
Peak memory 145516 kb
Host smart-7a2a8d7c-2318-46bc-8bf7-1b19c5ddc89d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1163676033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1163676033
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1624487433
Short name T63
Test name
Test status
Simulation time 9371075 ps
CPU time 0.39 seconds
Started Jul 11 06:06:55 PM PDT 24
Finished Jul 11 06:06:57 PM PDT 24
Peak memory 145516 kb
Host smart-388ea3b8-6507-4e58-92c6-a852946b434a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1624487433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1624487433
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3709654227
Short name T10
Test name
Test status
Simulation time 26577276 ps
CPU time 0.4 seconds
Started Jul 11 06:41:43 PM PDT 24
Finished Jul 11 06:41:44 PM PDT 24
Peak memory 145572 kb
Host smart-b956ba67-175a-41f2-9531-f389c62331de
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3709654227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3709654227
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3952140821
Short name T76
Test name
Test status
Simulation time 27311235 ps
CPU time 0.4 seconds
Started Jul 11 06:41:42 PM PDT 24
Finished Jul 11 06:41:44 PM PDT 24
Peak memory 145576 kb
Host smart-ff782fcd-4eea-48ad-9268-79983481e8b3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3952140821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3952140821
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2505868738
Short name T14
Test name
Test status
Simulation time 26926295 ps
CPU time 0.4 seconds
Started Jul 11 06:41:43 PM PDT 24
Finished Jul 11 06:41:44 PM PDT 24
Peak memory 145600 kb
Host smart-c19c7bc1-9144-438e-a1ff-86ad2a9047c9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2505868738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2505868738
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1443119620
Short name T32
Test name
Test status
Simulation time 26941799 ps
CPU time 0.39 seconds
Started Jul 11 06:41:45 PM PDT 24
Finished Jul 11 06:41:47 PM PDT 24
Peak memory 145596 kb
Host smart-d23012df-da69-4438-9b3c-e60f0ca434b5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1443119620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1443119620
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3638772310
Short name T33
Test name
Test status
Simulation time 28859209 ps
CPU time 0.4 seconds
Started Jul 11 06:41:41 PM PDT 24
Finished Jul 11 06:41:42 PM PDT 24
Peak memory 145560 kb
Host smart-7195d477-daf8-46cf-8c68-2b3473db875c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3638772310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3638772310
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.916701781
Short name T77
Test name
Test status
Simulation time 26041373 ps
CPU time 0.38 seconds
Started Jul 11 06:41:49 PM PDT 24
Finished Jul 11 06:41:50 PM PDT 24
Peak memory 145580 kb
Host smart-269f83aa-5c0b-41e8-a62d-8c79605b3e43
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=916701781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.916701781
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1065240676
Short name T65
Test name
Test status
Simulation time 27293455 ps
CPU time 0.39 seconds
Started Jul 11 06:41:44 PM PDT 24
Finished Jul 11 06:41:45 PM PDT 24
Peak memory 145596 kb
Host smart-97cd182c-e8d9-4236-acef-69ee333dabf8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1065240676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1065240676
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3985632261
Short name T73
Test name
Test status
Simulation time 25668597 ps
CPU time 0.39 seconds
Started Jul 11 06:41:46 PM PDT 24
Finished Jul 11 06:41:48 PM PDT 24
Peak memory 145600 kb
Host smart-6af3273d-1c4b-4628-a9ba-df5082778cef
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3985632261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3985632261
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.812469386
Short name T75
Test name
Test status
Simulation time 27225087 ps
CPU time 0.46 seconds
Started Jul 11 06:41:43 PM PDT 24
Finished Jul 11 06:41:44 PM PDT 24
Peak memory 145572 kb
Host smart-1dd724b9-0b62-4350-947b-98fcb9af02b2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=812469386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.812469386
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2094446880
Short name T6
Test name
Test status
Simulation time 27868739 ps
CPU time 0.41 seconds
Started Jul 11 06:41:46 PM PDT 24
Finished Jul 11 06:41:48 PM PDT 24
Peak memory 145600 kb
Host smart-b6efcde7-ba41-4282-a713-426353ef680d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2094446880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2094446880
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.379107884
Short name T68
Test name
Test status
Simulation time 28912733 ps
CPU time 0.41 seconds
Started Jul 11 06:41:49 PM PDT 24
Finished Jul 11 06:41:50 PM PDT 24
Peak memory 145580 kb
Host smart-0fab1c10-9220-4745-9728-9435ae649211
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=379107884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.379107884
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2655699298
Short name T67
Test name
Test status
Simulation time 27809044 ps
CPU time 0.41 seconds
Started Jul 11 06:41:46 PM PDT 24
Finished Jul 11 06:41:47 PM PDT 24
Peak memory 145588 kb
Host smart-06853d35-8aa4-41db-b61a-0a54528b9c8c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2655699298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2655699298
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1633753005
Short name T79
Test name
Test status
Simulation time 27264335 ps
CPU time 0.38 seconds
Started Jul 11 06:41:43 PM PDT 24
Finished Jul 11 06:41:44 PM PDT 24
Peak memory 145580 kb
Host smart-0cf7a423-2ef7-468f-805a-0175234174cf
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1633753005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1633753005
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1681953635
Short name T69
Test name
Test status
Simulation time 28239067 ps
CPU time 0.41 seconds
Started Jul 11 06:41:45 PM PDT 24
Finished Jul 11 06:41:47 PM PDT 24
Peak memory 145600 kb
Host smart-6f6d92e2-4056-46ea-9ed9-c1afc6802dbb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1681953635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1681953635
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3559367863
Short name T74
Test name
Test status
Simulation time 27304236 ps
CPU time 0.39 seconds
Started Jul 11 06:41:42 PM PDT 24
Finished Jul 11 06:41:43 PM PDT 24
Peak memory 145588 kb
Host smart-173af435-a175-4090-bc27-4623a6db8ffe
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3559367863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3559367863
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3772141876
Short name T78
Test name
Test status
Simulation time 29480953 ps
CPU time 0.4 seconds
Started Jul 11 06:41:43 PM PDT 24
Finished Jul 11 06:41:44 PM PDT 24
Peak memory 145588 kb
Host smart-2574a8a1-e4f2-48bd-9ac8-9f1d52c2c53f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3772141876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3772141876
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3748191870
Short name T66
Test name
Test status
Simulation time 28039670 ps
CPU time 0.39 seconds
Started Jul 11 06:41:42 PM PDT 24
Finished Jul 11 06:41:44 PM PDT 24
Peak memory 145600 kb
Host smart-e8724d40-6354-4cc8-be3b-6196ded6a6ab
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3748191870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3748191870
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4055855383
Short name T72
Test name
Test status
Simulation time 28321682 ps
CPU time 0.4 seconds
Started Jul 11 06:41:44 PM PDT 24
Finished Jul 11 06:41:46 PM PDT 24
Peak memory 145492 kb
Host smart-a28fb0e5-c5c7-40d6-90d6-6937b8f22b65
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4055855383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.4055855383
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2039556710
Short name T70
Test name
Test status
Simulation time 26959579 ps
CPU time 0.4 seconds
Started Jul 11 06:41:42 PM PDT 24
Finished Jul 11 06:41:44 PM PDT 24
Peak memory 145580 kb
Host smart-1dde8f29-331a-416c-8bf1-7502e82b547c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2039556710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2039556710
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3604237382
Short name T71
Test name
Test status
Simulation time 29415250 ps
CPU time 0.44 seconds
Started Jul 11 06:41:45 PM PDT 24
Finished Jul 11 06:41:47 PM PDT 24
Peak memory 145596 kb
Host smart-db57d144-ce7a-48e0-a2a3-6308394555f1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3604237382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3604237382
Directory /workspace/9.prim_sync_fatal_alert/latest
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