Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 78
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.51 89.51 100.00 100.00 91.67 91.67 100.00 100.00 82.14 82.14 95.83 95.83 67.44 67.44 /workspace/coverage/default/9.prim_async_alert.2763817892
92.05 2.53 100.00 0.00 91.67 0.00 100.00 0.00 85.71 3.57 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/1.prim_sync_alert.2026846090
93.56 1.51 100.00 0.00 93.75 2.08 100.00 0.00 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2341223707
94.50 0.94 100.00 0.00 95.83 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4179647146
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/13.prim_async_alert.2358334918

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1410076811
/workspace/coverage/default/1.prim_async_alert.3552890122
/workspace/coverage/default/10.prim_async_alert.3508845752
/workspace/coverage/default/11.prim_async_alert.1852561750
/workspace/coverage/default/12.prim_async_alert.4155577848
/workspace/coverage/default/14.prim_async_alert.3941244669
/workspace/coverage/default/15.prim_async_alert.3136482053
/workspace/coverage/default/16.prim_async_alert.3858706407
/workspace/coverage/default/17.prim_async_alert.1213749028
/workspace/coverage/default/18.prim_async_alert.2960249071
/workspace/coverage/default/2.prim_async_alert.1089804316
/workspace/coverage/default/3.prim_async_alert.1884524720
/workspace/coverage/default/4.prim_async_alert.3529764007
/workspace/coverage/default/5.prim_async_alert.3685082010
/workspace/coverage/default/6.prim_async_alert.1142251119
/workspace/coverage/default/7.prim_async_alert.2355183810
/workspace/coverage/default/8.prim_async_alert.1304450315
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3331946131
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3192163877
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3846675503
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.447099137
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1731850379
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3467682969
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.486051761
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2945777321
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3819398634
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.25567346
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3197539979
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3628985267
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3063998080
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.924120946
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.131216204
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.511024935
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.712769307
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.755275263
/workspace/coverage/sync_alert/0.prim_sync_alert.2473064862
/workspace/coverage/sync_alert/10.prim_sync_alert.2673781769
/workspace/coverage/sync_alert/11.prim_sync_alert.3443279530
/workspace/coverage/sync_alert/12.prim_sync_alert.2808346545
/workspace/coverage/sync_alert/13.prim_sync_alert.4175790740
/workspace/coverage/sync_alert/14.prim_sync_alert.4078157111
/workspace/coverage/sync_alert/15.prim_sync_alert.2543539461
/workspace/coverage/sync_alert/16.prim_sync_alert.814071278
/workspace/coverage/sync_alert/17.prim_sync_alert.3068716861
/workspace/coverage/sync_alert/18.prim_sync_alert.2071341776
/workspace/coverage/sync_alert/19.prim_sync_alert.2668090183
/workspace/coverage/sync_alert/2.prim_sync_alert.154362162
/workspace/coverage/sync_alert/3.prim_sync_alert.4196639661
/workspace/coverage/sync_alert/4.prim_sync_alert.3393855939
/workspace/coverage/sync_alert/5.prim_sync_alert.2729355827
/workspace/coverage/sync_alert/6.prim_sync_alert.1676570200
/workspace/coverage/sync_alert/7.prim_sync_alert.485044488
/workspace/coverage/sync_alert/8.prim_sync_alert.1551301973
/workspace/coverage/sync_alert/9.prim_sync_alert.3203912967
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4240301713
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.666148350
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3848738707
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2552153818
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2345295297
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2164864268
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2175319548
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.981166212
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3478353353
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2758817830
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2202952875
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3649737259
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.180104729
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2382066120
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3932356497
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3172500186
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2025331419
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.418354563
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1233111248



Total test records in report: 78
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.prim_async_alert.1410076811 Jul 12 05:04:09 PM PDT 24 Jul 12 05:04:11 PM PDT 24 10128762 ps
T2 /workspace/coverage/default/18.prim_async_alert.2960249071 Jul 12 05:04:03 PM PDT 24 Jul 12 05:04:06 PM PDT 24 12078450 ps
T3 /workspace/coverage/default/1.prim_async_alert.3552890122 Jul 12 05:03:59 PM PDT 24 Jul 12 05:04:02 PM PDT 24 10794330 ps
T10 /workspace/coverage/default/15.prim_async_alert.3136482053 Jul 12 05:03:58 PM PDT 24 Jul 12 05:04:02 PM PDT 24 10823794 ps
T11 /workspace/coverage/default/9.prim_async_alert.2763817892 Jul 12 05:04:00 PM PDT 24 Jul 12 05:04:04 PM PDT 24 13002266 ps
T7 /workspace/coverage/default/13.prim_async_alert.2358334918 Jul 12 05:04:00 PM PDT 24 Jul 12 05:04:04 PM PDT 24 10900846 ps
T18 /workspace/coverage/default/16.prim_async_alert.3858706407 Jul 12 05:04:00 PM PDT 24 Jul 12 05:04:03 PM PDT 24 11182736 ps
T19 /workspace/coverage/default/8.prim_async_alert.1304450315 Jul 12 05:04:09 PM PDT 24 Jul 12 05:04:10 PM PDT 24 10855498 ps
T8 /workspace/coverage/default/4.prim_async_alert.3529764007 Jul 12 05:04:01 PM PDT 24 Jul 12 05:04:05 PM PDT 24 11578885 ps
T14 /workspace/coverage/default/11.prim_async_alert.1852561750 Jul 12 05:04:03 PM PDT 24 Jul 12 05:04:06 PM PDT 24 10795757 ps
T44 /workspace/coverage/default/7.prim_async_alert.2355183810 Jul 12 05:04:02 PM PDT 24 Jul 12 05:04:06 PM PDT 24 10323962 ps
T15 /workspace/coverage/default/3.prim_async_alert.1884524720 Jul 12 05:04:06 PM PDT 24 Jul 12 05:04:08 PM PDT 24 12315937 ps
T9 /workspace/coverage/default/5.prim_async_alert.3685082010 Jul 12 05:03:58 PM PDT 24 Jul 12 05:04:00 PM PDT 24 11614733 ps
T20 /workspace/coverage/default/10.prim_async_alert.3508845752 Jul 12 05:04:06 PM PDT 24 Jul 12 05:04:08 PM PDT 24 11037400 ps
T45 /workspace/coverage/default/12.prim_async_alert.4155577848 Jul 12 05:04:02 PM PDT 24 Jul 12 05:04:06 PM PDT 24 11079565 ps
T46 /workspace/coverage/default/14.prim_async_alert.3941244669 Jul 12 05:04:09 PM PDT 24 Jul 12 05:04:10 PM PDT 24 11305279 ps
T16 /workspace/coverage/default/17.prim_async_alert.1213749028 Jul 12 05:04:01 PM PDT 24 Jul 12 05:04:05 PM PDT 24 11152182 ps
T17 /workspace/coverage/default/2.prim_async_alert.1089804316 Jul 12 05:04:03 PM PDT 24 Jul 12 05:04:07 PM PDT 24 12245599 ps
T47 /workspace/coverage/default/6.prim_async_alert.1142251119 Jul 12 05:04:02 PM PDT 24 Jul 12 05:04:06 PM PDT 24 10721674 ps
T12 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.25567346 Jul 12 05:09:49 PM PDT 24 Jul 12 05:09:50 PM PDT 24 29945118 ps
T21 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.511024935 Jul 12 05:09:35 PM PDT 24 Jul 12 05:09:36 PM PDT 24 28668206 ps
T36 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.131216204 Jul 12 05:09:35 PM PDT 24 Jul 12 05:09:37 PM PDT 24 29312978 ps
T37 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.924120946 Jul 12 05:09:35 PM PDT 24 Jul 12 05:09:37 PM PDT 24 30821313 ps
T38 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.755275263 Jul 12 05:09:36 PM PDT 24 Jul 12 05:09:38 PM PDT 24 30562916 ps
T39 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2341223707 Jul 12 05:09:42 PM PDT 24 Jul 12 05:09:44 PM PDT 24 29707347 ps
T40 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3063998080 Jul 12 05:09:36 PM PDT 24 Jul 12 05:09:37 PM PDT 24 31095722 ps
T41 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.447099137 Jul 12 05:09:42 PM PDT 24 Jul 12 05:09:44 PM PDT 24 28802250 ps
T42 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3819398634 Jul 12 05:09:52 PM PDT 24 Jul 12 05:09:53 PM PDT 24 31138557 ps
T43 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.486051761 Jul 12 05:09:44 PM PDT 24 Jul 12 05:09:45 PM PDT 24 31607043 ps
T48 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3331946131 Jul 12 05:09:37 PM PDT 24 Jul 12 05:09:38 PM PDT 24 29700308 ps
T4 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3628985267 Jul 12 05:09:37 PM PDT 24 Jul 12 05:09:38 PM PDT 24 29935915 ps
T13 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3467682969 Jul 12 05:09:43 PM PDT 24 Jul 12 05:09:44 PM PDT 24 31154815 ps
T49 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1731850379 Jul 12 05:09:46 PM PDT 24 Jul 12 05:09:47 PM PDT 24 28967809 ps
T50 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3192163877 Jul 12 05:09:40 PM PDT 24 Jul 12 05:09:41 PM PDT 24 29209675 ps
T51 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3197539979 Jul 12 05:09:37 PM PDT 24 Jul 12 05:09:38 PM PDT 24 30345057 ps
T5 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3846675503 Jul 12 05:09:43 PM PDT 24 Jul 12 05:09:45 PM PDT 24 31863230 ps
T52 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.712769307 Jul 12 05:09:36 PM PDT 24 Jul 12 05:09:37 PM PDT 24 28214225 ps
T53 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2945777321 Jul 12 05:09:51 PM PDT 24 Jul 12 05:09:52 PM PDT 24 30621546 ps
T22 /workspace/coverage/sync_alert/19.prim_sync_alert.2668090183 Jul 12 05:10:03 PM PDT 24 Jul 12 05:10:04 PM PDT 24 8112166 ps
T31 /workspace/coverage/sync_alert/12.prim_sync_alert.2808346545 Jul 12 05:10:00 PM PDT 24 Jul 12 05:10:01 PM PDT 24 9066897 ps
T23 /workspace/coverage/sync_alert/2.prim_sync_alert.154362162 Jul 12 05:09:49 PM PDT 24 Jul 12 05:09:50 PM PDT 24 8935049 ps
T32 /workspace/coverage/sync_alert/3.prim_sync_alert.4196639661 Jul 12 05:09:51 PM PDT 24 Jul 12 05:09:52 PM PDT 24 9009130 ps
T33 /workspace/coverage/sync_alert/14.prim_sync_alert.4078157111 Jul 12 05:10:05 PM PDT 24 Jul 12 05:10:06 PM PDT 24 9017679 ps
T24 /workspace/coverage/sync_alert/6.prim_sync_alert.1676570200 Jul 12 05:09:52 PM PDT 24 Jul 12 05:09:53 PM PDT 24 9429015 ps
T34 /workspace/coverage/sync_alert/1.prim_sync_alert.2026846090 Jul 12 05:09:52 PM PDT 24 Jul 12 05:09:53 PM PDT 24 8446952 ps
T35 /workspace/coverage/sync_alert/16.prim_sync_alert.814071278 Jul 12 05:10:03 PM PDT 24 Jul 12 05:10:05 PM PDT 24 9855740 ps
T25 /workspace/coverage/sync_alert/4.prim_sync_alert.3393855939 Jul 12 05:09:50 PM PDT 24 Jul 12 05:09:51 PM PDT 24 9031737 ps
T26 /workspace/coverage/sync_alert/9.prim_sync_alert.3203912967 Jul 12 05:09:57 PM PDT 24 Jul 12 05:09:59 PM PDT 24 8324835 ps
T54 /workspace/coverage/sync_alert/10.prim_sync_alert.2673781769 Jul 12 05:09:59 PM PDT 24 Jul 12 05:10:01 PM PDT 24 8706950 ps
T55 /workspace/coverage/sync_alert/5.prim_sync_alert.2729355827 Jul 12 05:09:52 PM PDT 24 Jul 12 05:09:53 PM PDT 24 10146826 ps
T27 /workspace/coverage/sync_alert/7.prim_sync_alert.485044488 Jul 12 05:09:49 PM PDT 24 Jul 12 05:09:50 PM PDT 24 9595493 ps
T56 /workspace/coverage/sync_alert/17.prim_sync_alert.3068716861 Jul 12 05:10:03 PM PDT 24 Jul 12 05:10:04 PM PDT 24 9148378 ps
T28 /workspace/coverage/sync_alert/18.prim_sync_alert.2071341776 Jul 12 05:10:03 PM PDT 24 Jul 12 05:10:04 PM PDT 24 9008418 ps
T57 /workspace/coverage/sync_alert/15.prim_sync_alert.2543539461 Jul 12 05:10:06 PM PDT 24 Jul 12 05:10:07 PM PDT 24 8730055 ps
T29 /workspace/coverage/sync_alert/13.prim_sync_alert.4175790740 Jul 12 05:09:58 PM PDT 24 Jul 12 05:10:00 PM PDT 24 9928720 ps
T58 /workspace/coverage/sync_alert/0.prim_sync_alert.2473064862 Jul 12 05:09:50 PM PDT 24 Jul 12 05:09:51 PM PDT 24 10327509 ps
T30 /workspace/coverage/sync_alert/11.prim_sync_alert.3443279530 Jul 12 05:09:58 PM PDT 24 Jul 12 05:10:00 PM PDT 24 10131452 ps
T59 /workspace/coverage/sync_alert/8.prim_sync_alert.1551301973 Jul 12 05:09:57 PM PDT 24 Jul 12 05:09:59 PM PDT 24 9073360 ps
T60 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2345295297 Jul 12 05:10:11 PM PDT 24 Jul 12 05:10:12 PM PDT 24 28133633 ps
T6 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4179647146 Jul 12 05:10:10 PM PDT 24 Jul 12 05:10:11 PM PDT 24 27256036 ps
T61 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3932356497 Jul 12 05:10:05 PM PDT 24 Jul 12 05:10:06 PM PDT 24 27649047 ps
T62 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.418354563 Jul 12 05:10:03 PM PDT 24 Jul 12 05:10:04 PM PDT 24 27875674 ps
T63 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.981166212 Jul 12 05:10:12 PM PDT 24 Jul 12 05:10:13 PM PDT 24 27630149 ps
T64 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2382066120 Jul 12 05:10:03 PM PDT 24 Jul 12 05:10:05 PM PDT 24 28467634 ps
T65 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.666148350 Jul 12 05:10:03 PM PDT 24 Jul 12 05:10:04 PM PDT 24 28604398 ps
T66 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2552153818 Jul 12 05:10:09 PM PDT 24 Jul 12 05:10:09 PM PDT 24 27506602 ps
T67 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3848738707 Jul 12 05:10:09 PM PDT 24 Jul 12 05:10:10 PM PDT 24 27991918 ps
T68 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3649737259 Jul 12 05:10:03 PM PDT 24 Jul 12 05:10:05 PM PDT 24 25870897 ps
T69 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4240301713 Jul 12 05:10:04 PM PDT 24 Jul 12 05:10:06 PM PDT 24 27266214 ps
T70 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2175319548 Jul 12 05:10:10 PM PDT 24 Jul 12 05:10:11 PM PDT 24 30107114 ps
T71 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3172500186 Jul 12 05:10:04 PM PDT 24 Jul 12 05:10:06 PM PDT 24 27378872 ps
T72 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2202952875 Jul 12 05:10:11 PM PDT 24 Jul 12 05:10:12 PM PDT 24 25666784 ps
T73 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.180104729 Jul 12 05:10:03 PM PDT 24 Jul 12 05:10:04 PM PDT 24 25676559 ps
T74 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2164864268 Jul 12 05:10:09 PM PDT 24 Jul 12 05:10:10 PM PDT 24 26324343 ps
T75 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1233111248 Jul 12 05:10:10 PM PDT 24 Jul 12 05:10:11 PM PDT 24 29586247 ps
T76 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3478353353 Jul 12 05:10:11 PM PDT 24 Jul 12 05:10:12 PM PDT 24 28554411 ps
T77 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2025331419 Jul 12 05:10:03 PM PDT 24 Jul 12 05:10:05 PM PDT 24 27105228 ps
T78 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2758817830 Jul 12 05:10:09 PM PDT 24 Jul 12 05:10:10 PM PDT 24 27011888 ps

Test location /workspace/coverage/default/9.prim_async_alert.2763817892
Short name T11
Test name
Test status
Simulation time 13002266 ps
CPU time 0.39 seconds
Started Jul 12 05:04:00 PM PDT 24
Finished Jul 12 05:04:04 PM PDT 24
Peak memory 145692 kb
Host smart-6b93f180-0db4-409f-8253-d802e2de2d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763817892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2763817892
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2026846090
Short name T34
Test name
Test status
Simulation time 8446952 ps
CPU time 0.37 seconds
Started Jul 12 05:09:52 PM PDT 24
Finished Jul 12 05:09:53 PM PDT 24
Peak memory 145580 kb
Host smart-23db5194-acfb-464b-bddf-e4f612a36c7e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2026846090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2026846090
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2341223707
Short name T39
Test name
Test status
Simulation time 29707347 ps
CPU time 0.39 seconds
Started Jul 12 05:09:42 PM PDT 24
Finished Jul 12 05:09:44 PM PDT 24
Peak memory 145336 kb
Host smart-95b4f9d6-42c7-44ab-88b9-f947ca782274
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2341223707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2341223707
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4179647146
Short name T6
Test name
Test status
Simulation time 27256036 ps
CPU time 0.39 seconds
Started Jul 12 05:10:10 PM PDT 24
Finished Jul 12 05:10:11 PM PDT 24
Peak memory 145592 kb
Host smart-0d75eeff-bfd5-43a5-bde8-5a421a2e4829
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4179647146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.4179647146
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2358334918
Short name T7
Test name
Test status
Simulation time 10900846 ps
CPU time 0.4 seconds
Started Jul 12 05:04:00 PM PDT 24
Finished Jul 12 05:04:04 PM PDT 24
Peak memory 145700 kb
Host smart-5ddb666e-c7ef-4dc8-914c-d2d3ab7bd9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358334918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2358334918
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1410076811
Short name T1
Test name
Test status
Simulation time 10128762 ps
CPU time 0.38 seconds
Started Jul 12 05:04:09 PM PDT 24
Finished Jul 12 05:04:11 PM PDT 24
Peak memory 145788 kb
Host smart-45afdefc-1868-4b51-b341-c3964080616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410076811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1410076811
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3552890122
Short name T3
Test name
Test status
Simulation time 10794330 ps
CPU time 0.4 seconds
Started Jul 12 05:03:59 PM PDT 24
Finished Jul 12 05:04:02 PM PDT 24
Peak memory 145700 kb
Host smart-734910ae-cd54-44a5-b6ec-df9c76af35c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552890122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3552890122
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3508845752
Short name T20
Test name
Test status
Simulation time 11037400 ps
CPU time 0.39 seconds
Started Jul 12 05:04:06 PM PDT 24
Finished Jul 12 05:04:08 PM PDT 24
Peak memory 145780 kb
Host smart-2d65e4d4-bf20-4e43-b030-53d0ffcc38cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508845752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3508845752
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1852561750
Short name T14
Test name
Test status
Simulation time 10795757 ps
CPU time 0.39 seconds
Started Jul 12 05:04:03 PM PDT 24
Finished Jul 12 05:04:06 PM PDT 24
Peak memory 145792 kb
Host smart-12ac5f66-d1b1-4327-ba60-858371f2d368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852561750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1852561750
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.4155577848
Short name T45
Test name
Test status
Simulation time 11079565 ps
CPU time 0.39 seconds
Started Jul 12 05:04:02 PM PDT 24
Finished Jul 12 05:04:06 PM PDT 24
Peak memory 145664 kb
Host smart-6a913f86-3a3d-480a-8b0e-78ecb1087e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155577848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.4155577848
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.3941244669
Short name T46
Test name
Test status
Simulation time 11305279 ps
CPU time 0.38 seconds
Started Jul 12 05:04:09 PM PDT 24
Finished Jul 12 05:04:10 PM PDT 24
Peak memory 145764 kb
Host smart-2e007896-ee4e-4955-afdc-53d25463e98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941244669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3941244669
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.3136482053
Short name T10
Test name
Test status
Simulation time 10823794 ps
CPU time 0.39 seconds
Started Jul 12 05:03:58 PM PDT 24
Finished Jul 12 05:04:02 PM PDT 24
Peak memory 145772 kb
Host smart-8518a627-cb19-46b5-b507-bc170d9b19f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136482053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3136482053
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3858706407
Short name T18
Test name
Test status
Simulation time 11182736 ps
CPU time 0.38 seconds
Started Jul 12 05:04:00 PM PDT 24
Finished Jul 12 05:04:03 PM PDT 24
Peak memory 145764 kb
Host smart-bc6086b3-88f1-4ea9-aa0f-61db01830615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858706407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3858706407
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1213749028
Short name T16
Test name
Test status
Simulation time 11152182 ps
CPU time 0.42 seconds
Started Jul 12 05:04:01 PM PDT 24
Finished Jul 12 05:04:05 PM PDT 24
Peak memory 145812 kb
Host smart-d07839b9-f28d-42a7-9787-ee36e502d6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213749028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1213749028
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2960249071
Short name T2
Test name
Test status
Simulation time 12078450 ps
CPU time 0.43 seconds
Started Jul 12 05:04:03 PM PDT 24
Finished Jul 12 05:04:06 PM PDT 24
Peak memory 145792 kb
Host smart-714a3a19-717c-4d43-8fed-da91b8b5843d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960249071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2960249071
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.1089804316
Short name T17
Test name
Test status
Simulation time 12245599 ps
CPU time 0.39 seconds
Started Jul 12 05:04:03 PM PDT 24
Finished Jul 12 05:04:07 PM PDT 24
Peak memory 145744 kb
Host smart-95f9d7e8-c359-48de-90f1-1bc15097a884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089804316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1089804316
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1884524720
Short name T15
Test name
Test status
Simulation time 12315937 ps
CPU time 0.38 seconds
Started Jul 12 05:04:06 PM PDT 24
Finished Jul 12 05:04:08 PM PDT 24
Peak memory 145772 kb
Host smart-e385e43a-c43e-4fc2-8f5c-bff1a3b89a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884524720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1884524720
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3529764007
Short name T8
Test name
Test status
Simulation time 11578885 ps
CPU time 0.41 seconds
Started Jul 12 05:04:01 PM PDT 24
Finished Jul 12 05:04:05 PM PDT 24
Peak memory 145788 kb
Host smart-9e4f9130-42d7-4f9b-aac9-59eb6b577764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529764007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3529764007
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3685082010
Short name T9
Test name
Test status
Simulation time 11614733 ps
CPU time 0.4 seconds
Started Jul 12 05:03:58 PM PDT 24
Finished Jul 12 05:04:00 PM PDT 24
Peak memory 145772 kb
Host smart-679a9384-1264-4c34-aa0e-7919268923a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685082010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3685082010
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1142251119
Short name T47
Test name
Test status
Simulation time 10721674 ps
CPU time 0.39 seconds
Started Jul 12 05:04:02 PM PDT 24
Finished Jul 12 05:04:06 PM PDT 24
Peak memory 145644 kb
Host smart-012275ab-c825-4dce-81f7-76eaa3132c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142251119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1142251119
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2355183810
Short name T44
Test name
Test status
Simulation time 10323962 ps
CPU time 0.41 seconds
Started Jul 12 05:04:02 PM PDT 24
Finished Jul 12 05:04:06 PM PDT 24
Peak memory 145652 kb
Host smart-f5a77d8c-d976-4e3e-a2d2-c6b736d28fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355183810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2355183810
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1304450315
Short name T19
Test name
Test status
Simulation time 10855498 ps
CPU time 0.38 seconds
Started Jul 12 05:04:09 PM PDT 24
Finished Jul 12 05:04:10 PM PDT 24
Peak memory 145788 kb
Host smart-87169a16-e315-430a-be29-04370acd5a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304450315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1304450315
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3331946131
Short name T48
Test name
Test status
Simulation time 29700308 ps
CPU time 0.4 seconds
Started Jul 12 05:09:37 PM PDT 24
Finished Jul 12 05:09:38 PM PDT 24
Peak memory 145284 kb
Host smart-585a30b4-e69f-4680-b460-b2e1043da1de
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3331946131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3331946131
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3192163877
Short name T50
Test name
Test status
Simulation time 29209675 ps
CPU time 0.39 seconds
Started Jul 12 05:09:40 PM PDT 24
Finished Jul 12 05:09:41 PM PDT 24
Peak memory 145288 kb
Host smart-61a54961-8807-4e44-85dc-561e398cbad8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3192163877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3192163877
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3846675503
Short name T5
Test name
Test status
Simulation time 31863230 ps
CPU time 0.4 seconds
Started Jul 12 05:09:43 PM PDT 24
Finished Jul 12 05:09:45 PM PDT 24
Peak memory 145284 kb
Host smart-7b5d78ec-83a6-4840-837b-045855f16b3f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3846675503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3846675503
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.447099137
Short name T41
Test name
Test status
Simulation time 28802250 ps
CPU time 0.4 seconds
Started Jul 12 05:09:42 PM PDT 24
Finished Jul 12 05:09:44 PM PDT 24
Peak memory 145228 kb
Host smart-50cf746d-a7cf-489e-baf2-b747e382609d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=447099137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.447099137
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1731850379
Short name T49
Test name
Test status
Simulation time 28967809 ps
CPU time 0.4 seconds
Started Jul 12 05:09:46 PM PDT 24
Finished Jul 12 05:09:47 PM PDT 24
Peak memory 145320 kb
Host smart-4430eb03-2ca4-47f2-b641-052c3e76df9c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1731850379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1731850379
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3467682969
Short name T13
Test name
Test status
Simulation time 31154815 ps
CPU time 0.42 seconds
Started Jul 12 05:09:43 PM PDT 24
Finished Jul 12 05:09:44 PM PDT 24
Peak memory 145360 kb
Host smart-ea045d79-e1c7-4b7a-8a87-fb7132a7d394
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3467682969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3467682969
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.486051761
Short name T43
Test name
Test status
Simulation time 31607043 ps
CPU time 0.41 seconds
Started Jul 12 05:09:44 PM PDT 24
Finished Jul 12 05:09:45 PM PDT 24
Peak memory 145332 kb
Host smart-b97cea5a-e3c5-4c1a-a188-56c4b1c02cc2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=486051761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.486051761
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2945777321
Short name T53
Test name
Test status
Simulation time 30621546 ps
CPU time 0.44 seconds
Started Jul 12 05:09:51 PM PDT 24
Finished Jul 12 05:09:52 PM PDT 24
Peak memory 145328 kb
Host smart-885b8214-3c07-4980-9f82-0e82c06aee4b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2945777321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2945777321
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3819398634
Short name T42
Test name
Test status
Simulation time 31138557 ps
CPU time 0.4 seconds
Started Jul 12 05:09:52 PM PDT 24
Finished Jul 12 05:09:53 PM PDT 24
Peak memory 145316 kb
Host smart-2eb27bb4-92e1-4186-b476-e3dafa9ab29f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3819398634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3819398634
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.25567346
Short name T12
Test name
Test status
Simulation time 29945118 ps
CPU time 0.4 seconds
Started Jul 12 05:09:49 PM PDT 24
Finished Jul 12 05:09:50 PM PDT 24
Peak memory 145244 kb
Host smart-ef18e542-9f1c-4d50-878e-468098c5c7a2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=25567346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.25567346
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3197539979
Short name T51
Test name
Test status
Simulation time 30345057 ps
CPU time 0.4 seconds
Started Jul 12 05:09:37 PM PDT 24
Finished Jul 12 05:09:38 PM PDT 24
Peak memory 145336 kb
Host smart-830d99f2-022f-4907-9d07-78d3c0e3a3aa
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3197539979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3197539979
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3628985267
Short name T4
Test name
Test status
Simulation time 29935915 ps
CPU time 0.4 seconds
Started Jul 12 05:09:37 PM PDT 24
Finished Jul 12 05:09:38 PM PDT 24
Peak memory 145248 kb
Host smart-c4d38797-d15f-406b-8585-7c8b773af7ec
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3628985267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3628985267
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3063998080
Short name T40
Test name
Test status
Simulation time 31095722 ps
CPU time 0.4 seconds
Started Jul 12 05:09:36 PM PDT 24
Finished Jul 12 05:09:37 PM PDT 24
Peak memory 145324 kb
Host smart-500f2792-9d79-46e4-8d89-02b7a3c95299
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3063998080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3063998080
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.924120946
Short name T37
Test name
Test status
Simulation time 30821313 ps
CPU time 0.4 seconds
Started Jul 12 05:09:35 PM PDT 24
Finished Jul 12 05:09:37 PM PDT 24
Peak memory 145328 kb
Host smart-61da9b5a-025c-40c2-9a7a-d9a7678b9ec0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=924120946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.924120946
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.131216204
Short name T36
Test name
Test status
Simulation time 29312978 ps
CPU time 0.41 seconds
Started Jul 12 05:09:35 PM PDT 24
Finished Jul 12 05:09:37 PM PDT 24
Peak memory 145312 kb
Host smart-7834bf23-5247-4fe8-a19b-c0e79e77998e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=131216204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.131216204
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.511024935
Short name T21
Test name
Test status
Simulation time 28668206 ps
CPU time 0.39 seconds
Started Jul 12 05:09:35 PM PDT 24
Finished Jul 12 05:09:36 PM PDT 24
Peak memory 145288 kb
Host smart-fbac92aa-faff-4bfd-b409-d96247a1a928
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=511024935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.511024935
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.712769307
Short name T52
Test name
Test status
Simulation time 28214225 ps
CPU time 0.4 seconds
Started Jul 12 05:09:36 PM PDT 24
Finished Jul 12 05:09:37 PM PDT 24
Peak memory 145252 kb
Host smart-e2aaaca6-4bf2-4828-acd5-beb5889dc037
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=712769307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.712769307
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.755275263
Short name T38
Test name
Test status
Simulation time 30562916 ps
CPU time 0.41 seconds
Started Jul 12 05:09:36 PM PDT 24
Finished Jul 12 05:09:38 PM PDT 24
Peak memory 145312 kb
Host smart-4e190565-9b33-41bb-991d-42cc8fef223b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=755275263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.755275263
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2473064862
Short name T58
Test name
Test status
Simulation time 10327509 ps
CPU time 0.37 seconds
Started Jul 12 05:09:50 PM PDT 24
Finished Jul 12 05:09:51 PM PDT 24
Peak memory 145560 kb
Host smart-fccc248f-ca01-4e63-b365-5632ea72a439
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2473064862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2473064862
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2673781769
Short name T54
Test name
Test status
Simulation time 8706950 ps
CPU time 0.41 seconds
Started Jul 12 05:09:59 PM PDT 24
Finished Jul 12 05:10:01 PM PDT 24
Peak memory 145560 kb
Host smart-c598da5e-dad2-4718-977b-c92285ecd715
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2673781769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2673781769
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3443279530
Short name T30
Test name
Test status
Simulation time 10131452 ps
CPU time 0.38 seconds
Started Jul 12 05:09:58 PM PDT 24
Finished Jul 12 05:10:00 PM PDT 24
Peak memory 145572 kb
Host smart-da6d9ed0-5a35-4839-9a0b-cdee4a587492
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3443279530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3443279530
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2808346545
Short name T31
Test name
Test status
Simulation time 9066897 ps
CPU time 0.37 seconds
Started Jul 12 05:10:00 PM PDT 24
Finished Jul 12 05:10:01 PM PDT 24
Peak memory 145564 kb
Host smart-26a59a1a-fefd-4870-bb85-1a73e9733712
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2808346545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2808346545
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.4175790740
Short name T29
Test name
Test status
Simulation time 9928720 ps
CPU time 0.39 seconds
Started Jul 12 05:09:58 PM PDT 24
Finished Jul 12 05:10:00 PM PDT 24
Peak memory 145572 kb
Host smart-fdde35ea-f2f6-4279-a9f0-59571019b57c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4175790740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.4175790740
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.4078157111
Short name T33
Test name
Test status
Simulation time 9017679 ps
CPU time 0.38 seconds
Started Jul 12 05:10:05 PM PDT 24
Finished Jul 12 05:10:06 PM PDT 24
Peak memory 145484 kb
Host smart-0472b565-f5d8-4045-8f93-11abb1fc2464
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4078157111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.4078157111
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2543539461
Short name T57
Test name
Test status
Simulation time 8730055 ps
CPU time 0.37 seconds
Started Jul 12 05:10:06 PM PDT 24
Finished Jul 12 05:10:07 PM PDT 24
Peak memory 145544 kb
Host smart-be80920a-e52c-4069-9948-060e92325613
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2543539461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2543539461
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.814071278
Short name T35
Test name
Test status
Simulation time 9855740 ps
CPU time 0.38 seconds
Started Jul 12 05:10:03 PM PDT 24
Finished Jul 12 05:10:05 PM PDT 24
Peak memory 145576 kb
Host smart-55e6b644-f860-4011-b487-be59f4cc5070
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=814071278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.814071278
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3068716861
Short name T56
Test name
Test status
Simulation time 9148378 ps
CPU time 0.38 seconds
Started Jul 12 05:10:03 PM PDT 24
Finished Jul 12 05:10:04 PM PDT 24
Peak memory 145444 kb
Host smart-5d73859a-31e1-4b3e-95e5-228d77d19dba
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3068716861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3068716861
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2071341776
Short name T28
Test name
Test status
Simulation time 9008418 ps
CPU time 0.37 seconds
Started Jul 12 05:10:03 PM PDT 24
Finished Jul 12 05:10:04 PM PDT 24
Peak memory 145452 kb
Host smart-3c111e7e-4213-4c84-8195-f7e64df6634a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2071341776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2071341776
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2668090183
Short name T22
Test name
Test status
Simulation time 8112166 ps
CPU time 0.41 seconds
Started Jul 12 05:10:03 PM PDT 24
Finished Jul 12 05:10:04 PM PDT 24
Peak memory 145464 kb
Host smart-78da40c6-7765-4f21-a721-d9c21c0c47e6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2668090183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2668090183
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.154362162
Short name T23
Test name
Test status
Simulation time 8935049 ps
CPU time 0.38 seconds
Started Jul 12 05:09:49 PM PDT 24
Finished Jul 12 05:09:50 PM PDT 24
Peak memory 145460 kb
Host smart-fa84efeb-7b3c-4405-ac97-b83ea12748aa
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=154362162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.154362162
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.4196639661
Short name T32
Test name
Test status
Simulation time 9009130 ps
CPU time 0.37 seconds
Started Jul 12 05:09:51 PM PDT 24
Finished Jul 12 05:09:52 PM PDT 24
Peak memory 145484 kb
Host smart-3f12075e-539b-4df4-a94e-5daba80dd9f5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4196639661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.4196639661
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3393855939
Short name T25
Test name
Test status
Simulation time 9031737 ps
CPU time 0.38 seconds
Started Jul 12 05:09:50 PM PDT 24
Finished Jul 12 05:09:51 PM PDT 24
Peak memory 145548 kb
Host smart-1a7a7430-7f77-497d-9c69-a9656cf9f5fa
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3393855939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3393855939
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2729355827
Short name T55
Test name
Test status
Simulation time 10146826 ps
CPU time 0.39 seconds
Started Jul 12 05:09:52 PM PDT 24
Finished Jul 12 05:09:53 PM PDT 24
Peak memory 145644 kb
Host smart-ba6069a9-1ab4-4c5b-860a-24505c6c1373
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2729355827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2729355827
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1676570200
Short name T24
Test name
Test status
Simulation time 9429015 ps
CPU time 0.37 seconds
Started Jul 12 05:09:52 PM PDT 24
Finished Jul 12 05:09:53 PM PDT 24
Peak memory 145564 kb
Host smart-7be83cf9-9772-47a1-99bb-fc781abc96f1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1676570200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1676570200
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.485044488
Short name T27
Test name
Test status
Simulation time 9595493 ps
CPU time 0.39 seconds
Started Jul 12 05:09:49 PM PDT 24
Finished Jul 12 05:09:50 PM PDT 24
Peak memory 145508 kb
Host smart-62f1a554-5ede-4dd7-8427-a09a0d1c93ea
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=485044488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.485044488
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1551301973
Short name T59
Test name
Test status
Simulation time 9073360 ps
CPU time 0.39 seconds
Started Jul 12 05:09:57 PM PDT 24
Finished Jul 12 05:09:59 PM PDT 24
Peak memory 145588 kb
Host smart-2c6eb289-d36e-438e-a735-e34b36f9892b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1551301973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1551301973
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3203912967
Short name T26
Test name
Test status
Simulation time 8324835 ps
CPU time 0.36 seconds
Started Jul 12 05:09:57 PM PDT 24
Finished Jul 12 05:09:59 PM PDT 24
Peak memory 145556 kb
Host smart-e68f2c3a-135b-47ef-a5c7-556bc4a7946e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3203912967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3203912967
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4240301713
Short name T69
Test name
Test status
Simulation time 27266214 ps
CPU time 0.39 seconds
Started Jul 12 05:10:04 PM PDT 24
Finished Jul 12 05:10:06 PM PDT 24
Peak memory 145548 kb
Host smart-7b3fa6b7-6cc3-4ddc-8228-8e7d044817a0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4240301713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4240301713
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.666148350
Short name T65
Test name
Test status
Simulation time 28604398 ps
CPU time 0.41 seconds
Started Jul 12 05:10:03 PM PDT 24
Finished Jul 12 05:10:04 PM PDT 24
Peak memory 145604 kb
Host smart-24635f15-ae5f-471a-b7d2-9561fdeb6956
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=666148350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.666148350
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3848738707
Short name T67
Test name
Test status
Simulation time 27991918 ps
CPU time 0.42 seconds
Started Jul 12 05:10:09 PM PDT 24
Finished Jul 12 05:10:10 PM PDT 24
Peak memory 145592 kb
Host smart-65e32381-a9c7-4153-94d4-1aa7b09d885d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3848738707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3848738707
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2552153818
Short name T66
Test name
Test status
Simulation time 27506602 ps
CPU time 0.39 seconds
Started Jul 12 05:10:09 PM PDT 24
Finished Jul 12 05:10:09 PM PDT 24
Peak memory 145520 kb
Host smart-6e0f7b4c-879e-4959-87ad-7280821a974b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2552153818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2552153818
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2345295297
Short name T60
Test name
Test status
Simulation time 28133633 ps
CPU time 0.4 seconds
Started Jul 12 05:10:11 PM PDT 24
Finished Jul 12 05:10:12 PM PDT 24
Peak memory 145492 kb
Host smart-3e767ebb-f049-452d-897c-f01126a22109
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2345295297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2345295297
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2164864268
Short name T74
Test name
Test status
Simulation time 26324343 ps
CPU time 0.39 seconds
Started Jul 12 05:10:09 PM PDT 24
Finished Jul 12 05:10:10 PM PDT 24
Peak memory 145572 kb
Host smart-5d9f8829-3428-4c5f-9712-e07c2a2dc346
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2164864268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2164864268
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2175319548
Short name T70
Test name
Test status
Simulation time 30107114 ps
CPU time 0.4 seconds
Started Jul 12 05:10:10 PM PDT 24
Finished Jul 12 05:10:11 PM PDT 24
Peak memory 145560 kb
Host smart-805fa05f-73da-41d2-85cd-1be3af6568c2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2175319548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2175319548
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.981166212
Short name T63
Test name
Test status
Simulation time 27630149 ps
CPU time 0.4 seconds
Started Jul 12 05:10:12 PM PDT 24
Finished Jul 12 05:10:13 PM PDT 24
Peak memory 145568 kb
Host smart-344a0631-60dd-487a-9055-48a59209e8ee
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=981166212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.981166212
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3478353353
Short name T76
Test name
Test status
Simulation time 28554411 ps
CPU time 0.41 seconds
Started Jul 12 05:10:11 PM PDT 24
Finished Jul 12 05:10:12 PM PDT 24
Peak memory 145592 kb
Host smart-f271dd33-4a5e-4a7f-8bc5-f659d1d09fb8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3478353353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3478353353
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2758817830
Short name T78
Test name
Test status
Simulation time 27011888 ps
CPU time 0.4 seconds
Started Jul 12 05:10:09 PM PDT 24
Finished Jul 12 05:10:10 PM PDT 24
Peak memory 145592 kb
Host smart-0b034826-d02a-4fbd-a19e-e3d205926870
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2758817830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2758817830
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2202952875
Short name T72
Test name
Test status
Simulation time 25666784 ps
CPU time 0.45 seconds
Started Jul 12 05:10:11 PM PDT 24
Finished Jul 12 05:10:12 PM PDT 24
Peak memory 145560 kb
Host smart-5cd392bb-da30-4f87-9a80-204e19229059
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2202952875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2202952875
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3649737259
Short name T68
Test name
Test status
Simulation time 25870897 ps
CPU time 0.39 seconds
Started Jul 12 05:10:03 PM PDT 24
Finished Jul 12 05:10:05 PM PDT 24
Peak memory 145492 kb
Host smart-d9ffdd36-84a4-4cc0-9b6c-1797590780b9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3649737259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3649737259
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.180104729
Short name T73
Test name
Test status
Simulation time 25676559 ps
CPU time 0.43 seconds
Started Jul 12 05:10:03 PM PDT 24
Finished Jul 12 05:10:04 PM PDT 24
Peak memory 145580 kb
Host smart-5c1cc83b-0472-4ce5-87d8-5daaf1b921c0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=180104729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.180104729
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2382066120
Short name T64
Test name
Test status
Simulation time 28467634 ps
CPU time 0.39 seconds
Started Jul 12 05:10:03 PM PDT 24
Finished Jul 12 05:10:05 PM PDT 24
Peak memory 145488 kb
Host smart-767a4867-b086-4625-8e30-67990b3f118a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2382066120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2382066120
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3932356497
Short name T61
Test name
Test status
Simulation time 27649047 ps
CPU time 0.4 seconds
Started Jul 12 05:10:05 PM PDT 24
Finished Jul 12 05:10:06 PM PDT 24
Peak memory 145580 kb
Host smart-078cda9c-37cd-4147-9149-9399d56bce2f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3932356497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3932356497
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3172500186
Short name T71
Test name
Test status
Simulation time 27378872 ps
CPU time 0.4 seconds
Started Jul 12 05:10:04 PM PDT 24
Finished Jul 12 05:10:06 PM PDT 24
Peak memory 145512 kb
Host smart-430a9273-9965-442a-a5e0-c1d9d96f5e49
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3172500186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3172500186
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2025331419
Short name T77
Test name
Test status
Simulation time 27105228 ps
CPU time 0.45 seconds
Started Jul 12 05:10:03 PM PDT 24
Finished Jul 12 05:10:05 PM PDT 24
Peak memory 145572 kb
Host smart-8de134a0-d492-4853-9da5-5a0b795c6858
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2025331419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2025331419
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.418354563
Short name T62
Test name
Test status
Simulation time 27875674 ps
CPU time 0.38 seconds
Started Jul 12 05:10:03 PM PDT 24
Finished Jul 12 05:10:04 PM PDT 24
Peak memory 145572 kb
Host smart-73a77b57-c53f-4693-a472-96cf2b3d33e0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=418354563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.418354563
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1233111248
Short name T75
Test name
Test status
Simulation time 29586247 ps
CPU time 0.4 seconds
Started Jul 12 05:10:10 PM PDT 24
Finished Jul 12 05:10:11 PM PDT 24
Peak memory 145600 kb
Host smart-5fecc432-eb3f-4c6a-9d7e-9c4ac9b606d1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1233111248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1233111248
Directory /workspace/9.prim_sync_fatal_alert/latest
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