Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.88 88.88 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/6.prim_async_alert.1670852179
92.60 3.72 100.00 0.00 93.75 0.00 100.00 0.00 89.29 10.71 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/0.prim_sync_alert.2698308153
94.11 1.51 100.00 0.00 95.83 2.08 100.00 0.00 89.29 0.00 95.83 0.00 83.72 6.98 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3396611804
94.50 0.39 100.00 0.00 95.83 0.00 100.00 0.00 89.29 0.00 95.83 0.00 86.05 2.33 /workspace/coverage/default/0.prim_async_alert.925076708
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2907733099
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/15.prim_sync_alert.884567996

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.4151014105
/workspace/coverage/default/10.prim_async_alert.28383847
/workspace/coverage/default/11.prim_async_alert.3470072798
/workspace/coverage/default/12.prim_async_alert.2957712702
/workspace/coverage/default/13.prim_async_alert.2394946395
/workspace/coverage/default/14.prim_async_alert.1729036087
/workspace/coverage/default/15.prim_async_alert.3602035834
/workspace/coverage/default/16.prim_async_alert.2996860731
/workspace/coverage/default/17.prim_async_alert.4237381161
/workspace/coverage/default/18.prim_async_alert.1179961600
/workspace/coverage/default/19.prim_async_alert.2099386294
/workspace/coverage/default/2.prim_async_alert.3904000017
/workspace/coverage/default/3.prim_async_alert.3865337840
/workspace/coverage/default/4.prim_async_alert.1385264997
/workspace/coverage/default/5.prim_async_alert.1836143126
/workspace/coverage/default/7.prim_async_alert.3816004625
/workspace/coverage/default/8.prim_async_alert.3267870296
/workspace/coverage/default/9.prim_async_alert.2084882911
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1768669040
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1298056507
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3161364328
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4247419026
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2578248755
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3686022541
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3358534697
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2287174041
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.61662971
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3768590054
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3075879023
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2502984425
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2559240205
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3092830588
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.435997874
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2097913503
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3441552232
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.517557709
/workspace/coverage/sync_alert/1.prim_sync_alert.3903048719
/workspace/coverage/sync_alert/10.prim_sync_alert.49829130
/workspace/coverage/sync_alert/11.prim_sync_alert.2584710795
/workspace/coverage/sync_alert/12.prim_sync_alert.2231759548
/workspace/coverage/sync_alert/13.prim_sync_alert.547141573
/workspace/coverage/sync_alert/14.prim_sync_alert.1665718737
/workspace/coverage/sync_alert/16.prim_sync_alert.2502165727
/workspace/coverage/sync_alert/17.prim_sync_alert.2121801728
/workspace/coverage/sync_alert/18.prim_sync_alert.2939887184
/workspace/coverage/sync_alert/19.prim_sync_alert.793411127
/workspace/coverage/sync_alert/2.prim_sync_alert.360018578
/workspace/coverage/sync_alert/3.prim_sync_alert.4161636019
/workspace/coverage/sync_alert/4.prim_sync_alert.1984378820
/workspace/coverage/sync_alert/5.prim_sync_alert.1678061056
/workspace/coverage/sync_alert/6.prim_sync_alert.2186993315
/workspace/coverage/sync_alert/7.prim_sync_alert.1180064771
/workspace/coverage/sync_alert/8.prim_sync_alert.2738509502
/workspace/coverage/sync_alert/9.prim_sync_alert.2734603343
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.903830870
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3943976458
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3901089576
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.931985360
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1011161052
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.418817327
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2017844650
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4088495704
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.477794013
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1245570079
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.13416440
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2329405399
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.413863098
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3690863957
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3502990845
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1376778028
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4007295123
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1602430273
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1189085169
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3044376450



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/6.prim_async_alert.1670852179 Jul 13 04:19:35 PM PDT 24 Jul 13 04:19:36 PM PDT 24 12444041 ps
T2 /workspace/coverage/default/13.prim_async_alert.2394946395 Jul 13 04:19:38 PM PDT 24 Jul 13 04:19:39 PM PDT 24 11690871 ps
T3 /workspace/coverage/default/3.prim_async_alert.3865337840 Jul 13 04:19:27 PM PDT 24 Jul 13 04:19:28 PM PDT 24 11282894 ps
T18 /workspace/coverage/default/11.prim_async_alert.3470072798 Jul 13 04:19:28 PM PDT 24 Jul 13 04:19:29 PM PDT 24 11607865 ps
T11 /workspace/coverage/default/16.prim_async_alert.2996860731 Jul 13 04:20:41 PM PDT 24 Jul 13 04:20:42 PM PDT 24 12353597 ps
T19 /workspace/coverage/default/15.prim_async_alert.3602035834 Jul 13 04:19:55 PM PDT 24 Jul 13 04:19:56 PM PDT 24 10740738 ps
T20 /workspace/coverage/default/2.prim_async_alert.3904000017 Jul 13 04:19:38 PM PDT 24 Jul 13 04:19:39 PM PDT 24 10798882 ps
T12 /workspace/coverage/default/0.prim_async_alert.925076708 Jul 13 04:20:54 PM PDT 24 Jul 13 04:20:54 PM PDT 24 11935494 ps
T7 /workspace/coverage/default/14.prim_async_alert.1729036087 Jul 13 04:19:36 PM PDT 24 Jul 13 04:19:37 PM PDT 24 10854104 ps
T21 /workspace/coverage/default/8.prim_async_alert.3267870296 Jul 13 04:19:39 PM PDT 24 Jul 13 04:19:40 PM PDT 24 10585236 ps
T22 /workspace/coverage/default/12.prim_async_alert.2957712702 Jul 13 04:19:26 PM PDT 24 Jul 13 04:19:27 PM PDT 24 11248892 ps
T46 /workspace/coverage/default/4.prim_async_alert.1385264997 Jul 13 04:21:10 PM PDT 24 Jul 13 04:21:11 PM PDT 24 10922120 ps
T8 /workspace/coverage/default/19.prim_async_alert.2099386294 Jul 13 04:19:36 PM PDT 24 Jul 13 04:19:37 PM PDT 24 11410412 ps
T47 /workspace/coverage/default/9.prim_async_alert.2084882911 Jul 13 04:19:39 PM PDT 24 Jul 13 04:19:40 PM PDT 24 11163602 ps
T48 /workspace/coverage/default/1.prim_async_alert.4151014105 Jul 13 04:19:42 PM PDT 24 Jul 13 04:19:42 PM PDT 24 10919958 ps
T23 /workspace/coverage/default/5.prim_async_alert.1836143126 Jul 13 04:19:25 PM PDT 24 Jul 13 04:19:27 PM PDT 24 10849817 ps
T49 /workspace/coverage/default/17.prim_async_alert.4237381161 Jul 13 04:19:40 PM PDT 24 Jul 13 04:19:41 PM PDT 24 11654045 ps
T50 /workspace/coverage/default/18.prim_async_alert.1179961600 Jul 13 04:19:27 PM PDT 24 Jul 13 04:19:28 PM PDT 24 11413989 ps
T51 /workspace/coverage/default/7.prim_async_alert.3816004625 Jul 13 04:19:26 PM PDT 24 Jul 13 04:19:27 PM PDT 24 10834633 ps
T52 /workspace/coverage/default/10.prim_async_alert.28383847 Jul 13 04:21:11 PM PDT 24 Jul 13 04:21:11 PM PDT 24 11235560 ps
T39 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2578248755 Jul 13 04:19:38 PM PDT 24 Jul 13 04:19:39 PM PDT 24 32241550 ps
T40 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3396611804 Jul 13 04:19:35 PM PDT 24 Jul 13 04:19:36 PM PDT 24 31757671 ps
T41 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1768669040 Jul 13 04:19:35 PM PDT 24 Jul 13 04:19:36 PM PDT 24 29104489 ps
T42 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3686022541 Jul 13 04:19:38 PM PDT 24 Jul 13 04:19:39 PM PDT 24 29867968 ps
T17 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3092830588 Jul 13 04:19:29 PM PDT 24 Jul 13 04:19:29 PM PDT 24 29635054 ps
T43 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2502984425 Jul 13 04:19:35 PM PDT 24 Jul 13 04:19:36 PM PDT 24 30553016 ps
T4 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2907733099 Jul 13 04:20:40 PM PDT 24 Jul 13 04:20:42 PM PDT 24 32208460 ps
T44 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2097913503 Jul 13 04:20:51 PM PDT 24 Jul 13 04:20:51 PM PDT 24 29065751 ps
T45 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.517557709 Jul 13 04:19:39 PM PDT 24 Jul 13 04:19:41 PM PDT 24 29511121 ps
T13 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2559240205 Jul 13 04:19:37 PM PDT 24 Jul 13 04:19:38 PM PDT 24 30243257 ps
T53 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3441552232 Jul 13 04:19:26 PM PDT 24 Jul 13 04:19:27 PM PDT 24 29041206 ps
T54 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2287174041 Jul 13 04:19:32 PM PDT 24 Jul 13 04:19:33 PM PDT 24 30698095 ps
T55 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3768590054 Jul 13 04:19:54 PM PDT 24 Jul 13 04:19:54 PM PDT 24 30522620 ps
T38 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1298056507 Jul 13 04:25:35 PM PDT 24 Jul 13 04:25:36 PM PDT 24 30419399 ps
T5 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3075879023 Jul 13 04:19:35 PM PDT 24 Jul 13 04:19:36 PM PDT 24 30625075 ps
T15 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4247419026 Jul 13 04:25:19 PM PDT 24 Jul 13 04:25:20 PM PDT 24 31548319 ps
T14 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3161364328 Jul 13 04:19:38 PM PDT 24 Jul 13 04:19:38 PM PDT 24 29419568 ps
T56 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3358534697 Jul 13 04:19:39 PM PDT 24 Jul 13 04:19:40 PM PDT 24 31308051 ps
T57 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.61662971 Jul 13 04:19:36 PM PDT 24 Jul 13 04:19:37 PM PDT 24 30834071 ps
T58 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.435997874 Jul 13 04:19:31 PM PDT 24 Jul 13 04:19:32 PM PDT 24 30124273 ps
T16 /workspace/coverage/sync_alert/0.prim_sync_alert.2698308153 Jul 13 04:25:52 PM PDT 24 Jul 13 04:25:52 PM PDT 24 10192649 ps
T24 /workspace/coverage/sync_alert/16.prim_sync_alert.2502165727 Jul 13 04:20:24 PM PDT 24 Jul 13 04:20:24 PM PDT 24 8747674 ps
T9 /workspace/coverage/sync_alert/15.prim_sync_alert.884567996 Jul 13 04:19:39 PM PDT 24 Jul 13 04:19:40 PM PDT 24 9272230 ps
T32 /workspace/coverage/sync_alert/4.prim_sync_alert.1984378820 Jul 13 04:19:56 PM PDT 24 Jul 13 04:19:57 PM PDT 24 10541144 ps
T25 /workspace/coverage/sync_alert/10.prim_sync_alert.49829130 Jul 13 04:19:39 PM PDT 24 Jul 13 04:19:40 PM PDT 24 10246123 ps
T33 /workspace/coverage/sync_alert/6.prim_sync_alert.2186993315 Jul 13 04:24:53 PM PDT 24 Jul 13 04:24:54 PM PDT 24 9094440 ps
T34 /workspace/coverage/sync_alert/5.prim_sync_alert.1678061056 Jul 13 04:19:39 PM PDT 24 Jul 13 04:19:41 PM PDT 24 10279122 ps
T35 /workspace/coverage/sync_alert/2.prim_sync_alert.360018578 Jul 13 04:19:51 PM PDT 24 Jul 13 04:19:52 PM PDT 24 9312180 ps
T36 /workspace/coverage/sync_alert/17.prim_sync_alert.2121801728 Jul 13 04:19:37 PM PDT 24 Jul 13 04:19:38 PM PDT 24 9596811 ps
T37 /workspace/coverage/sync_alert/19.prim_sync_alert.793411127 Jul 13 04:26:13 PM PDT 24 Jul 13 04:26:14 PM PDT 24 9567885 ps
T59 /workspace/coverage/sync_alert/13.prim_sync_alert.547141573 Jul 13 04:19:28 PM PDT 24 Jul 13 04:19:29 PM PDT 24 8939890 ps
T26 /workspace/coverage/sync_alert/9.prim_sync_alert.2734603343 Jul 13 04:20:54 PM PDT 24 Jul 13 04:20:54 PM PDT 24 9609456 ps
T27 /workspace/coverage/sync_alert/3.prim_sync_alert.4161636019 Jul 13 04:19:54 PM PDT 24 Jul 13 04:19:54 PM PDT 24 9948300 ps
T28 /workspace/coverage/sync_alert/8.prim_sync_alert.2738509502 Jul 13 04:19:39 PM PDT 24 Jul 13 04:19:41 PM PDT 24 9987286 ps
T60 /workspace/coverage/sync_alert/11.prim_sync_alert.2584710795 Jul 13 04:20:24 PM PDT 24 Jul 13 04:20:25 PM PDT 24 9506003 ps
T61 /workspace/coverage/sync_alert/7.prim_sync_alert.1180064771 Jul 13 04:19:38 PM PDT 24 Jul 13 04:19:39 PM PDT 24 9035376 ps
T29 /workspace/coverage/sync_alert/14.prim_sync_alert.1665718737 Jul 13 04:19:27 PM PDT 24 Jul 13 04:19:28 PM PDT 24 9409685 ps
T30 /workspace/coverage/sync_alert/12.prim_sync_alert.2231759548 Jul 13 04:19:39 PM PDT 24 Jul 13 04:19:41 PM PDT 24 8503924 ps
T31 /workspace/coverage/sync_alert/18.prim_sync_alert.2939887184 Jul 13 04:25:36 PM PDT 24 Jul 13 04:25:37 PM PDT 24 8261758 ps
T62 /workspace/coverage/sync_alert/1.prim_sync_alert.3903048719 Jul 13 04:20:08 PM PDT 24 Jul 13 04:20:08 PM PDT 24 8916683 ps
T63 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4007295123 Jul 13 04:20:40 PM PDT 24 Jul 13 04:20:42 PM PDT 24 28121346 ps
T64 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1189085169 Jul 13 04:20:41 PM PDT 24 Jul 13 04:20:42 PM PDT 24 27443367 ps
T65 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.477794013 Jul 13 04:19:56 PM PDT 24 Jul 13 04:19:57 PM PDT 24 26104633 ps
T10 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.931985360 Jul 13 04:20:41 PM PDT 24 Jul 13 04:20:42 PM PDT 24 26606250 ps
T6 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3502990845 Jul 13 04:19:38 PM PDT 24 Jul 13 04:19:40 PM PDT 24 27373663 ps
T66 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1602430273 Jul 13 04:23:53 PM PDT 24 Jul 13 04:23:54 PM PDT 24 26990069 ps
T67 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3044376450 Jul 13 04:20:41 PM PDT 24 Jul 13 04:20:42 PM PDT 24 25795127 ps
T68 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3690863957 Jul 13 04:20:10 PM PDT 24 Jul 13 04:20:10 PM PDT 24 26537527 ps
T69 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3943976458 Jul 13 04:19:38 PM PDT 24 Jul 13 04:19:39 PM PDT 24 27208377 ps
T70 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2017844650 Jul 13 04:20:10 PM PDT 24 Jul 13 04:20:10 PM PDT 24 28053742 ps
T71 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.413863098 Jul 13 04:19:39 PM PDT 24 Jul 13 04:19:40 PM PDT 24 26469257 ps
T72 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1245570079 Jul 13 04:20:40 PM PDT 24 Jul 13 04:20:42 PM PDT 24 28981246 ps
T73 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1011161052 Jul 13 04:24:03 PM PDT 24 Jul 13 04:24:04 PM PDT 24 30180285 ps
T74 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.13416440 Jul 13 04:19:55 PM PDT 24 Jul 13 04:19:56 PM PDT 24 28274219 ps
T75 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2329405399 Jul 13 04:19:56 PM PDT 24 Jul 13 04:19:56 PM PDT 24 24594936 ps
T76 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4088495704 Jul 13 04:20:40 PM PDT 24 Jul 13 04:20:42 PM PDT 24 25983960 ps
T77 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.418817327 Jul 13 04:20:40 PM PDT 24 Jul 13 04:20:42 PM PDT 24 28493218 ps
T78 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3901089576 Jul 13 04:23:54 PM PDT 24 Jul 13 04:23:55 PM PDT 24 28155618 ps
T79 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1376778028 Jul 13 04:21:16 PM PDT 24 Jul 13 04:21:16 PM PDT 24 28340306 ps
T80 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.903830870 Jul 13 04:20:51 PM PDT 24 Jul 13 04:20:52 PM PDT 24 28038637 ps

Test location /workspace/coverage/default/6.prim_async_alert.1670852179
Short name T1
Test name
Test status
Simulation time 12444041 ps
CPU time 0.4 seconds
Started Jul 13 04:19:35 PM PDT 24
Finished Jul 13 04:19:36 PM PDT 24
Peak memory 145708 kb
Host smart-f10ca40c-9f33-436d-bd29-d55bf8a6ff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670852179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1670852179
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2698308153
Short name T16
Test name
Test status
Simulation time 10192649 ps
CPU time 0.38 seconds
Started Jul 13 04:25:52 PM PDT 24
Finished Jul 13 04:25:52 PM PDT 24
Peak memory 146360 kb
Host smart-26fdd51f-5111-4756-ae8f-3ef0175350ca
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2698308153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2698308153
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3396611804
Short name T40
Test name
Test status
Simulation time 31757671 ps
CPU time 0.39 seconds
Started Jul 13 04:19:35 PM PDT 24
Finished Jul 13 04:19:36 PM PDT 24
Peak memory 145264 kb
Host smart-e211f1c2-4527-4f2e-8f60-f4745c9ef2ca
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3396611804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3396611804
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.925076708
Short name T12
Test name
Test status
Simulation time 11935494 ps
CPU time 0.39 seconds
Started Jul 13 04:20:54 PM PDT 24
Finished Jul 13 04:20:54 PM PDT 24
Peak memory 145380 kb
Host smart-b44dd547-38d0-46a3-baff-b3422946d20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925076708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.925076708
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2907733099
Short name T4
Test name
Test status
Simulation time 32208460 ps
CPU time 0.42 seconds
Started Jul 13 04:20:40 PM PDT 24
Finished Jul 13 04:20:42 PM PDT 24
Peak memory 144176 kb
Host smart-e19e9ed3-f731-4075-863f-5489469a9b98
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2907733099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2907733099
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.884567996
Short name T9
Test name
Test status
Simulation time 9272230 ps
CPU time 0.4 seconds
Started Jul 13 04:19:39 PM PDT 24
Finished Jul 13 04:19:40 PM PDT 24
Peak memory 145684 kb
Host smart-50d6fd2d-c43a-49c1-903d-52fc07b72c27
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=884567996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.884567996
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.4151014105
Short name T48
Test name
Test status
Simulation time 10919958 ps
CPU time 0.38 seconds
Started Jul 13 04:19:42 PM PDT 24
Finished Jul 13 04:19:42 PM PDT 24
Peak memory 145712 kb
Host smart-db19dcac-9156-4faf-9ec5-338ad87b0df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151014105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.4151014105
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.28383847
Short name T52
Test name
Test status
Simulation time 11235560 ps
CPU time 0.39 seconds
Started Jul 13 04:21:11 PM PDT 24
Finished Jul 13 04:21:11 PM PDT 24
Peak memory 145548 kb
Host smart-19cc075c-1dea-4c3d-940c-31d6f5e34235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28383847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.28383847
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3470072798
Short name T18
Test name
Test status
Simulation time 11607865 ps
CPU time 0.41 seconds
Started Jul 13 04:19:28 PM PDT 24
Finished Jul 13 04:19:29 PM PDT 24
Peak memory 145436 kb
Host smart-95793553-dd4f-4d6a-9c94-83a086fadd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470072798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3470072798
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2957712702
Short name T22
Test name
Test status
Simulation time 11248892 ps
CPU time 0.43 seconds
Started Jul 13 04:19:26 PM PDT 24
Finished Jul 13 04:19:27 PM PDT 24
Peak memory 144588 kb
Host smart-0aaeb572-86e3-441e-b683-0d42b7ae7689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957712702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2957712702
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2394946395
Short name T2
Test name
Test status
Simulation time 11690871 ps
CPU time 0.39 seconds
Started Jul 13 04:19:38 PM PDT 24
Finished Jul 13 04:19:39 PM PDT 24
Peak memory 145860 kb
Host smart-3e3f70a8-59d2-4f91-92ff-f02697fbd922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394946395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2394946395
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1729036087
Short name T7
Test name
Test status
Simulation time 10854104 ps
CPU time 0.39 seconds
Started Jul 13 04:19:36 PM PDT 24
Finished Jul 13 04:19:37 PM PDT 24
Peak memory 145708 kb
Host smart-7868ba34-0d80-46d4-a5c6-a9a5c68d3e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729036087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1729036087
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.3602035834
Short name T19
Test name
Test status
Simulation time 10740738 ps
CPU time 0.41 seconds
Started Jul 13 04:19:55 PM PDT 24
Finished Jul 13 04:19:56 PM PDT 24
Peak memory 145424 kb
Host smart-fc7054fe-7c2e-46e5-b87b-35536cf8c022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602035834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3602035834
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2996860731
Short name T11
Test name
Test status
Simulation time 12353597 ps
CPU time 0.38 seconds
Started Jul 13 04:20:41 PM PDT 24
Finished Jul 13 04:20:42 PM PDT 24
Peak memory 145856 kb
Host smart-a07689d0-73bd-4197-9dca-04d0193c1940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996860731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2996860731
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.4237381161
Short name T49
Test name
Test status
Simulation time 11654045 ps
CPU time 0.44 seconds
Started Jul 13 04:19:40 PM PDT 24
Finished Jul 13 04:19:41 PM PDT 24
Peak memory 145928 kb
Host smart-2918afc1-8273-49ca-a34e-16fb643e0701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237381161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.4237381161
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1179961600
Short name T50
Test name
Test status
Simulation time 11413989 ps
CPU time 0.46 seconds
Started Jul 13 04:19:27 PM PDT 24
Finished Jul 13 04:19:28 PM PDT 24
Peak memory 145240 kb
Host smart-dae974ca-f5ca-4bdb-b311-44a61fd61fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179961600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1179961600
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2099386294
Short name T8
Test name
Test status
Simulation time 11410412 ps
CPU time 0.41 seconds
Started Jul 13 04:19:36 PM PDT 24
Finished Jul 13 04:19:37 PM PDT 24
Peak memory 145708 kb
Host smart-67081624-9be4-4c72-8f8f-ad1b427e30a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099386294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2099386294
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3904000017
Short name T20
Test name
Test status
Simulation time 10798882 ps
CPU time 0.42 seconds
Started Jul 13 04:19:38 PM PDT 24
Finished Jul 13 04:19:39 PM PDT 24
Peak memory 145936 kb
Host smart-5c753296-191b-456a-b825-024e61b9e137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904000017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3904000017
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3865337840
Short name T3
Test name
Test status
Simulation time 11282894 ps
CPU time 0.41 seconds
Started Jul 13 04:19:27 PM PDT 24
Finished Jul 13 04:19:28 PM PDT 24
Peak memory 145040 kb
Host smart-7ebc9203-1c94-4768-88f6-09abb8a4e454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865337840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3865337840
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1385264997
Short name T46
Test name
Test status
Simulation time 10922120 ps
CPU time 0.39 seconds
Started Jul 13 04:21:10 PM PDT 24
Finished Jul 13 04:21:11 PM PDT 24
Peak memory 145536 kb
Host smart-30bde900-a23e-4b60-810f-e5505eaea106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385264997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1385264997
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1836143126
Short name T23
Test name
Test status
Simulation time 10849817 ps
CPU time 0.47 seconds
Started Jul 13 04:19:25 PM PDT 24
Finished Jul 13 04:19:27 PM PDT 24
Peak memory 145196 kb
Host smart-7d3f6ec9-a467-42a6-b30f-a34a3a1b9064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836143126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1836143126
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3816004625
Short name T51
Test name
Test status
Simulation time 10834633 ps
CPU time 0.42 seconds
Started Jul 13 04:19:26 PM PDT 24
Finished Jul 13 04:19:27 PM PDT 24
Peak memory 143640 kb
Host smart-81deec5a-af4c-4b0e-be3d-182979dc8ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816004625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3816004625
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3267870296
Short name T21
Test name
Test status
Simulation time 10585236 ps
CPU time 0.4 seconds
Started Jul 13 04:19:39 PM PDT 24
Finished Jul 13 04:19:40 PM PDT 24
Peak memory 145860 kb
Host smart-8680e3f7-8fe4-4887-9861-736c7aa3cd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267870296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3267870296
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2084882911
Short name T47
Test name
Test status
Simulation time 11163602 ps
CPU time 0.4 seconds
Started Jul 13 04:19:39 PM PDT 24
Finished Jul 13 04:19:40 PM PDT 24
Peak memory 145936 kb
Host smart-86184f7d-f2a3-48f4-89a5-4f20465d796a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084882911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2084882911
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1768669040
Short name T41
Test name
Test status
Simulation time 29104489 ps
CPU time 0.41 seconds
Started Jul 13 04:19:35 PM PDT 24
Finished Jul 13 04:19:36 PM PDT 24
Peak memory 145192 kb
Host smart-a03197d1-5524-4cec-84af-79b9f1af1c68
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1768669040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1768669040
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1298056507
Short name T38
Test name
Test status
Simulation time 30419399 ps
CPU time 0.4 seconds
Started Jul 13 04:25:35 PM PDT 24
Finished Jul 13 04:25:36 PM PDT 24
Peak memory 145012 kb
Host smart-9e333253-325f-4abc-85c9-945869b9cb4a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1298056507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1298056507
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3161364328
Short name T14
Test name
Test status
Simulation time 29419568 ps
CPU time 0.4 seconds
Started Jul 13 04:19:38 PM PDT 24
Finished Jul 13 04:19:38 PM PDT 24
Peak memory 145368 kb
Host smart-55ff8109-b06c-432b-94ac-4610c53bf409
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3161364328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3161364328
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4247419026
Short name T15
Test name
Test status
Simulation time 31548319 ps
CPU time 0.42 seconds
Started Jul 13 04:25:19 PM PDT 24
Finished Jul 13 04:25:20 PM PDT 24
Peak memory 144876 kb
Host smart-07a79aea-dfed-4c33-ad28-6d96059f9e56
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4247419026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.4247419026
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2578248755
Short name T39
Test name
Test status
Simulation time 32241550 ps
CPU time 0.41 seconds
Started Jul 13 04:19:38 PM PDT 24
Finished Jul 13 04:19:39 PM PDT 24
Peak memory 145344 kb
Host smart-3e8a1b14-0730-4de4-b95a-df0e96139d6d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2578248755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2578248755
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3686022541
Short name T42
Test name
Test status
Simulation time 29867968 ps
CPU time 0.42 seconds
Started Jul 13 04:19:38 PM PDT 24
Finished Jul 13 04:19:39 PM PDT 24
Peak memory 145368 kb
Host smart-87149062-20c4-4532-b900-aefa6b8144dc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3686022541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3686022541
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3358534697
Short name T56
Test name
Test status
Simulation time 31308051 ps
CPU time 0.44 seconds
Started Jul 13 04:19:39 PM PDT 24
Finished Jul 13 04:19:40 PM PDT 24
Peak memory 145428 kb
Host smart-4117a2fe-e1de-4f58-8b84-628f6ec8b5c3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3358534697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3358534697
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2287174041
Short name T54
Test name
Test status
Simulation time 30698095 ps
CPU time 0.4 seconds
Started Jul 13 04:19:32 PM PDT 24
Finished Jul 13 04:19:33 PM PDT 24
Peak memory 145004 kb
Host smart-7d0b5b70-abc1-4962-8620-7c4434d12e29
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2287174041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2287174041
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.61662971
Short name T57
Test name
Test status
Simulation time 30834071 ps
CPU time 0.42 seconds
Started Jul 13 04:19:36 PM PDT 24
Finished Jul 13 04:19:37 PM PDT 24
Peak memory 145264 kb
Host smart-ade405fb-0f29-4ab9-a354-b005ea6df45c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=61662971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.61662971
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3768590054
Short name T55
Test name
Test status
Simulation time 30522620 ps
CPU time 0.42 seconds
Started Jul 13 04:19:54 PM PDT 24
Finished Jul 13 04:19:54 PM PDT 24
Peak memory 144956 kb
Host smart-c2a2d84b-ff08-4cce-b365-e6985d48044a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3768590054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3768590054
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3075879023
Short name T5
Test name
Test status
Simulation time 30625075 ps
CPU time 0.44 seconds
Started Jul 13 04:19:35 PM PDT 24
Finished Jul 13 04:19:36 PM PDT 24
Peak memory 145268 kb
Host smart-d9bf4fca-cd04-4b63-98b8-ccccd95c0a06
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3075879023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3075879023
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2502984425
Short name T43
Test name
Test status
Simulation time 30553016 ps
CPU time 0.41 seconds
Started Jul 13 04:19:35 PM PDT 24
Finished Jul 13 04:19:36 PM PDT 24
Peak memory 145264 kb
Host smart-b15e690a-fff4-4a0e-8ccd-437999e08076
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2502984425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2502984425
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2559240205
Short name T13
Test name
Test status
Simulation time 30243257 ps
CPU time 0.42 seconds
Started Jul 13 04:19:37 PM PDT 24
Finished Jul 13 04:19:38 PM PDT 24
Peak memory 145388 kb
Host smart-69c74cd6-4d72-4e32-8eed-b0991b0e2b9d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2559240205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2559240205
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3092830588
Short name T17
Test name
Test status
Simulation time 29635054 ps
CPU time 0.4 seconds
Started Jul 13 04:19:29 PM PDT 24
Finished Jul 13 04:19:29 PM PDT 24
Peak memory 145004 kb
Host smart-90035ae4-e85d-4c7b-8a78-3f5b04fe4a92
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3092830588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3092830588
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.435997874
Short name T58
Test name
Test status
Simulation time 30124273 ps
CPU time 0.41 seconds
Started Jul 13 04:19:31 PM PDT 24
Finished Jul 13 04:19:32 PM PDT 24
Peak memory 145040 kb
Host smart-21f05ff2-7171-40bd-a137-7eaff145e4da
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=435997874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.435997874
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2097913503
Short name T44
Test name
Test status
Simulation time 29065751 ps
CPU time 0.41 seconds
Started Jul 13 04:20:51 PM PDT 24
Finished Jul 13 04:20:51 PM PDT 24
Peak memory 145052 kb
Host smart-fb029348-6c06-46e7-90a7-c9a30e3cd94e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2097913503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2097913503
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3441552232
Short name T53
Test name
Test status
Simulation time 29041206 ps
CPU time 0.43 seconds
Started Jul 13 04:19:26 PM PDT 24
Finished Jul 13 04:19:27 PM PDT 24
Peak memory 144392 kb
Host smart-efadd737-84e2-4ca5-9c5c-0ccebb2856ee
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3441552232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3441552232
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.517557709
Short name T45
Test name
Test status
Simulation time 29511121 ps
CPU time 0.42 seconds
Started Jul 13 04:19:39 PM PDT 24
Finished Jul 13 04:19:41 PM PDT 24
Peak memory 145432 kb
Host smart-cf2b8391-2988-48ae-b17f-7640c3ca6dcd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=517557709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.517557709
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3903048719
Short name T62
Test name
Test status
Simulation time 8916683 ps
CPU time 0.42 seconds
Started Jul 13 04:20:08 PM PDT 24
Finished Jul 13 04:20:08 PM PDT 24
Peak memory 145276 kb
Host smart-3100748f-69b1-445b-a500-d6018dd89d9f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3903048719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3903048719
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.49829130
Short name T25
Test name
Test status
Simulation time 10246123 ps
CPU time 0.4 seconds
Started Jul 13 04:19:39 PM PDT 24
Finished Jul 13 04:19:40 PM PDT 24
Peak memory 145740 kb
Host smart-24fbba28-6013-49a6-abee-93a62e64a6cd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=49829130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.49829130
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2584710795
Short name T60
Test name
Test status
Simulation time 9506003 ps
CPU time 0.38 seconds
Started Jul 13 04:20:24 PM PDT 24
Finished Jul 13 04:20:25 PM PDT 24
Peak memory 145528 kb
Host smart-c335d73b-7177-46c9-8671-2f7e40fecaf7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2584710795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2584710795
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2231759548
Short name T30
Test name
Test status
Simulation time 8503924 ps
CPU time 0.42 seconds
Started Jul 13 04:19:39 PM PDT 24
Finished Jul 13 04:19:41 PM PDT 24
Peak memory 145248 kb
Host smart-94994a13-5aac-4358-8884-c5add17af514
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2231759548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2231759548
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.547141573
Short name T59
Test name
Test status
Simulation time 8939890 ps
CPU time 0.38 seconds
Started Jul 13 04:19:28 PM PDT 24
Finished Jul 13 04:19:29 PM PDT 24
Peak memory 145092 kb
Host smart-c64423b9-3d9b-4798-8b28-492c15930525
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=547141573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.547141573
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.1665718737
Short name T29
Test name
Test status
Simulation time 9409685 ps
CPU time 0.46 seconds
Started Jul 13 04:19:27 PM PDT 24
Finished Jul 13 04:19:28 PM PDT 24
Peak memory 145236 kb
Host smart-b0eb5f61-c4b4-40e9-b6e5-72be28a8b7b2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1665718737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1665718737
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2502165727
Short name T24
Test name
Test status
Simulation time 8747674 ps
CPU time 0.38 seconds
Started Jul 13 04:20:24 PM PDT 24
Finished Jul 13 04:20:24 PM PDT 24
Peak memory 145524 kb
Host smart-58dc3185-9b25-4e69-9303-c128f8674a76
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2502165727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2502165727
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2121801728
Short name T36
Test name
Test status
Simulation time 9596811 ps
CPU time 0.39 seconds
Started Jul 13 04:19:37 PM PDT 24
Finished Jul 13 04:19:38 PM PDT 24
Peak memory 145684 kb
Host smart-4f7206da-6174-45d8-b89f-aa4a1e2e1663
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2121801728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2121801728
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2939887184
Short name T31
Test name
Test status
Simulation time 8261758 ps
CPU time 0.39 seconds
Started Jul 13 04:25:36 PM PDT 24
Finished Jul 13 04:25:37 PM PDT 24
Peak memory 145176 kb
Host smart-6c8ae2ad-5899-476c-b8a4-6743136ba4f4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2939887184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2939887184
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.793411127
Short name T37
Test name
Test status
Simulation time 9567885 ps
CPU time 0.38 seconds
Started Jul 13 04:26:13 PM PDT 24
Finished Jul 13 04:26:14 PM PDT 24
Peak memory 145276 kb
Host smart-89b1b7f6-db08-41b4-96c3-172c5860deb7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=793411127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.793411127
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.360018578
Short name T35
Test name
Test status
Simulation time 9312180 ps
CPU time 0.4 seconds
Started Jul 13 04:19:51 PM PDT 24
Finished Jul 13 04:19:52 PM PDT 24
Peak memory 145676 kb
Host smart-cb7bd3bf-7e67-43b5-a988-2b09fe5d6645
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=360018578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.360018578
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.4161636019
Short name T27
Test name
Test status
Simulation time 9948300 ps
CPU time 0.44 seconds
Started Jul 13 04:19:54 PM PDT 24
Finished Jul 13 04:19:54 PM PDT 24
Peak memory 145188 kb
Host smart-70621881-5a82-4962-9e9b-a1b5cd96f0d3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4161636019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.4161636019
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1984378820
Short name T32
Test name
Test status
Simulation time 10541144 ps
CPU time 0.41 seconds
Started Jul 13 04:19:56 PM PDT 24
Finished Jul 13 04:19:57 PM PDT 24
Peak memory 145208 kb
Host smart-605b4bc4-5e38-4f3e-9022-752c28bf54e9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1984378820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1984378820
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1678061056
Short name T34
Test name
Test status
Simulation time 10279122 ps
CPU time 0.42 seconds
Started Jul 13 04:19:39 PM PDT 24
Finished Jul 13 04:19:41 PM PDT 24
Peak memory 145724 kb
Host smart-43d501c0-c507-4987-9436-3b862de5a652
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1678061056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1678061056
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2186993315
Short name T33
Test name
Test status
Simulation time 9094440 ps
CPU time 0.46 seconds
Started Jul 13 04:24:53 PM PDT 24
Finished Jul 13 04:24:54 PM PDT 24
Peak memory 145852 kb
Host smart-be916080-05ce-4552-9f61-f88078438b38
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2186993315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2186993315
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1180064771
Short name T61
Test name
Test status
Simulation time 9035376 ps
CPU time 0.39 seconds
Started Jul 13 04:19:38 PM PDT 24
Finished Jul 13 04:19:39 PM PDT 24
Peak memory 145668 kb
Host smart-289d8b35-042c-4595-b1fa-d7c0fdd8448b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1180064771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1180064771
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2738509502
Short name T28
Test name
Test status
Simulation time 9987286 ps
CPU time 0.42 seconds
Started Jul 13 04:19:39 PM PDT 24
Finished Jul 13 04:19:41 PM PDT 24
Peak memory 145724 kb
Host smart-73539556-5bc6-4921-8643-7968c4d966b0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2738509502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2738509502
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2734603343
Short name T26
Test name
Test status
Simulation time 9609456 ps
CPU time 0.36 seconds
Started Jul 13 04:20:54 PM PDT 24
Finished Jul 13 04:20:54 PM PDT 24
Peak memory 145116 kb
Host smart-bfe5da30-3267-49a5-be8c-1a279eb8874c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2734603343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2734603343
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.903830870
Short name T80
Test name
Test status
Simulation time 28038637 ps
CPU time 0.44 seconds
Started Jul 13 04:20:51 PM PDT 24
Finished Jul 13 04:20:52 PM PDT 24
Peak memory 145316 kb
Host smart-a935c1e8-6876-47db-931b-fa5424ad9b6a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=903830870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.903830870
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3943976458
Short name T69
Test name
Test status
Simulation time 27208377 ps
CPU time 0.4 seconds
Started Jul 13 04:19:38 PM PDT 24
Finished Jul 13 04:19:39 PM PDT 24
Peak memory 145740 kb
Host smart-ff1433d2-594d-4812-a961-3aec0ef254c5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3943976458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3943976458
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3901089576
Short name T78
Test name
Test status
Simulation time 28155618 ps
CPU time 0.4 seconds
Started Jul 13 04:23:54 PM PDT 24
Finished Jul 13 04:23:55 PM PDT 24
Peak memory 145376 kb
Host smart-a960ee75-a76b-4013-9bce-edb63cdca091
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3901089576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3901089576
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.931985360
Short name T10
Test name
Test status
Simulation time 26606250 ps
CPU time 0.37 seconds
Started Jul 13 04:20:41 PM PDT 24
Finished Jul 13 04:20:42 PM PDT 24
Peak memory 146016 kb
Host smart-8fd25fdf-9e1e-49ff-add9-a86b64fa8623
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=931985360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.931985360
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1011161052
Short name T73
Test name
Test status
Simulation time 30180285 ps
CPU time 0.41 seconds
Started Jul 13 04:24:03 PM PDT 24
Finished Jul 13 04:24:04 PM PDT 24
Peak memory 145332 kb
Host smart-cbe1be5c-8ae5-4685-9eb3-63c6958a0d5f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1011161052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1011161052
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.418817327
Short name T77
Test name
Test status
Simulation time 28493218 ps
CPU time 0.43 seconds
Started Jul 13 04:20:40 PM PDT 24
Finished Jul 13 04:20:42 PM PDT 24
Peak memory 143140 kb
Host smart-dc6df504-14ee-49c2-8abb-b423bed3eec5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=418817327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.418817327
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2017844650
Short name T70
Test name
Test status
Simulation time 28053742 ps
CPU time 0.41 seconds
Started Jul 13 04:20:10 PM PDT 24
Finished Jul 13 04:20:10 PM PDT 24
Peak memory 145264 kb
Host smart-6d2c1495-c15b-41ef-b830-2ffab0744b07
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2017844650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2017844650
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4088495704
Short name T76
Test name
Test status
Simulation time 25983960 ps
CPU time 0.4 seconds
Started Jul 13 04:20:40 PM PDT 24
Finished Jul 13 04:20:42 PM PDT 24
Peak memory 144124 kb
Host smart-1982762a-eda9-4abd-bd75-48cc4530da97
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4088495704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.4088495704
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.477794013
Short name T65
Test name
Test status
Simulation time 26104633 ps
CPU time 0.42 seconds
Started Jul 13 04:19:56 PM PDT 24
Finished Jul 13 04:19:57 PM PDT 24
Peak memory 145264 kb
Host smart-2a0d5788-e85d-42e4-b394-643d099326ac
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=477794013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.477794013
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1245570079
Short name T72
Test name
Test status
Simulation time 28981246 ps
CPU time 0.42 seconds
Started Jul 13 04:20:40 PM PDT 24
Finished Jul 13 04:20:42 PM PDT 24
Peak memory 144312 kb
Host smart-315a87ed-4ca9-4bca-b3ef-ec37f150f429
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1245570079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1245570079
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.13416440
Short name T74
Test name
Test status
Simulation time 28274219 ps
CPU time 0.42 seconds
Started Jul 13 04:19:55 PM PDT 24
Finished Jul 13 04:19:56 PM PDT 24
Peak memory 145264 kb
Host smart-cda21f0d-5d0e-4f04-aaa1-35113333972d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=13416440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.13416440
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2329405399
Short name T75
Test name
Test status
Simulation time 24594936 ps
CPU time 0.41 seconds
Started Jul 13 04:19:56 PM PDT 24
Finished Jul 13 04:19:56 PM PDT 24
Peak memory 145264 kb
Host smart-1ba34b99-a539-4522-a6f8-0f0f74d2c5b6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2329405399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2329405399
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.413863098
Short name T71
Test name
Test status
Simulation time 26469257 ps
CPU time 0.4 seconds
Started Jul 13 04:19:39 PM PDT 24
Finished Jul 13 04:19:40 PM PDT 24
Peak memory 145740 kb
Host smart-cfb3c19a-49e5-4814-9359-e9c36f2d6a11
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=413863098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.413863098
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3690863957
Short name T68
Test name
Test status
Simulation time 26537527 ps
CPU time 0.44 seconds
Started Jul 13 04:20:10 PM PDT 24
Finished Jul 13 04:20:10 PM PDT 24
Peak memory 145260 kb
Host smart-a734d6bf-d896-4c56-928a-1f3476a5cf2f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3690863957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3690863957
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3502990845
Short name T6
Test name
Test status
Simulation time 27373663 ps
CPU time 0.41 seconds
Started Jul 13 04:19:38 PM PDT 24
Finished Jul 13 04:19:40 PM PDT 24
Peak memory 145744 kb
Host smart-c509c93c-c153-4e3c-8a48-543c21905a01
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3502990845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3502990845
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1376778028
Short name T79
Test name
Test status
Simulation time 28340306 ps
CPU time 0.47 seconds
Started Jul 13 04:21:16 PM PDT 24
Finished Jul 13 04:21:16 PM PDT 24
Peak memory 145348 kb
Host smart-204ea178-1902-4508-a727-147b6cfc1ef4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1376778028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1376778028
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4007295123
Short name T63
Test name
Test status
Simulation time 28121346 ps
CPU time 0.38 seconds
Started Jul 13 04:20:40 PM PDT 24
Finished Jul 13 04:20:42 PM PDT 24
Peak memory 145664 kb
Host smart-34b7354f-7b3b-456a-bf95-c84007d9e164
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4007295123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.4007295123
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1602430273
Short name T66
Test name
Test status
Simulation time 26990069 ps
CPU time 0.41 seconds
Started Jul 13 04:23:53 PM PDT 24
Finished Jul 13 04:23:54 PM PDT 24
Peak memory 145316 kb
Host smart-6aa9a08c-8f6d-4dec-8f5c-c256565cf34d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1602430273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1602430273
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1189085169
Short name T64
Test name
Test status
Simulation time 27443367 ps
CPU time 0.39 seconds
Started Jul 13 04:20:41 PM PDT 24
Finished Jul 13 04:20:42 PM PDT 24
Peak memory 144928 kb
Host smart-97d0e9d0-9a1c-471b-b75d-0dd1a6911bc6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1189085169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1189085169
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3044376450
Short name T67
Test name
Test status
Simulation time 25795127 ps
CPU time 0.38 seconds
Started Jul 13 04:20:41 PM PDT 24
Finished Jul 13 04:20:42 PM PDT 24
Peak memory 145856 kb
Host smart-dd8e1a52-4816-4240-9a74-e27438a0b5f8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3044376450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3044376450
Directory /workspace/9.prim_sync_fatal_alert/latest
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