Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.02 89.02 100.00 100.00 95.83 95.83 100.00 100.00 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/6.prim_async_alert.520559552
92.49 3.48 100.00 0.00 97.92 2.08 100.00 0.00 82.14 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/0.prim_sync_alert.904622060
93.68 1.19 100.00 0.00 97.92 0.00 100.00 0.00 89.29 7.14 95.83 0.00 79.07 0.00 /workspace/coverage/default/4.prim_async_alert.2666063478
94.85 1.16 100.00 0.00 97.92 0.00 100.00 0.00 89.29 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2265626959
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4122523064

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3343857367
/workspace/coverage/default/1.prim_async_alert.2273129464
/workspace/coverage/default/10.prim_async_alert.2489301198
/workspace/coverage/default/11.prim_async_alert.4274974478
/workspace/coverage/default/12.prim_async_alert.3331795961
/workspace/coverage/default/13.prim_async_alert.3731800144
/workspace/coverage/default/14.prim_async_alert.233133207
/workspace/coverage/default/15.prim_async_alert.1455558588
/workspace/coverage/default/16.prim_async_alert.1342257486
/workspace/coverage/default/17.prim_async_alert.588335465
/workspace/coverage/default/18.prim_async_alert.2747105680
/workspace/coverage/default/19.prim_async_alert.2487781964
/workspace/coverage/default/2.prim_async_alert.3599964334
/workspace/coverage/default/3.prim_async_alert.819598546
/workspace/coverage/default/5.prim_async_alert.3043061505
/workspace/coverage/default/7.prim_async_alert.3933387230
/workspace/coverage/default/8.prim_async_alert.3585202989
/workspace/coverage/default/9.prim_async_alert.1799266159
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2364182000
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2198652192
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2060729371
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2871535454
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.25806397
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2371367877
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3373729170
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3732158231
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1852746355
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1658767109
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1480911839
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2760683226
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.942629278
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.462212302
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3730402954
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1240603162
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2605342331
/workspace/coverage/sync_alert/1.prim_sync_alert.2877205151
/workspace/coverage/sync_alert/10.prim_sync_alert.336456017
/workspace/coverage/sync_alert/11.prim_sync_alert.3065147650
/workspace/coverage/sync_alert/12.prim_sync_alert.3763314137
/workspace/coverage/sync_alert/13.prim_sync_alert.1461700139
/workspace/coverage/sync_alert/14.prim_sync_alert.2343137017
/workspace/coverage/sync_alert/15.prim_sync_alert.3417779519
/workspace/coverage/sync_alert/16.prim_sync_alert.2661752492
/workspace/coverage/sync_alert/17.prim_sync_alert.494150918
/workspace/coverage/sync_alert/18.prim_sync_alert.1933109694
/workspace/coverage/sync_alert/19.prim_sync_alert.4130390885
/workspace/coverage/sync_alert/2.prim_sync_alert.3241844281
/workspace/coverage/sync_alert/3.prim_sync_alert.1212266760
/workspace/coverage/sync_alert/4.prim_sync_alert.2685730945
/workspace/coverage/sync_alert/5.prim_sync_alert.2808572855
/workspace/coverage/sync_alert/6.prim_sync_alert.299861751
/workspace/coverage/sync_alert/7.prim_sync_alert.3434459160
/workspace/coverage/sync_alert/8.prim_sync_alert.4009819451
/workspace/coverage/sync_alert/9.prim_sync_alert.2535934734
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2711045641
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3798244086
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.213775865
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4271062485
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3698471654
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3706124142
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.667874719
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1254933309
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.965137319
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1205678848
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3751488138
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3580025046
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1479474415
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2523937664
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1680863009
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1574707305
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.357146678
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.405420337
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4071512724
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1995755432



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/15.prim_async_alert.1455558588 Jul 14 04:22:25 PM PDT 24 Jul 14 04:22:26 PM PDT 24 11206527 ps
T2 /workspace/coverage/default/2.prim_async_alert.3599964334 Jul 14 04:19:27 PM PDT 24 Jul 14 04:19:28 PM PDT 24 11558959 ps
T3 /workspace/coverage/default/5.prim_async_alert.3043061505 Jul 14 04:23:01 PM PDT 24 Jul 14 04:23:03 PM PDT 24 11916725 ps
T8 /workspace/coverage/default/17.prim_async_alert.588335465 Jul 14 04:22:25 PM PDT 24 Jul 14 04:22:26 PM PDT 24 10299403 ps
T14 /workspace/coverage/default/13.prim_async_alert.3731800144 Jul 14 04:18:42 PM PDT 24 Jul 14 04:18:43 PM PDT 24 11732958 ps
T7 /workspace/coverage/default/6.prim_async_alert.520559552 Jul 14 04:21:53 PM PDT 24 Jul 14 04:21:56 PM PDT 24 12119268 ps
T18 /workspace/coverage/default/18.prim_async_alert.2747105680 Jul 14 04:22:26 PM PDT 24 Jul 14 04:22:28 PM PDT 24 11335477 ps
T19 /workspace/coverage/default/11.prim_async_alert.4274974478 Jul 14 04:21:45 PM PDT 24 Jul 14 04:21:46 PM PDT 24 10519053 ps
T20 /workspace/coverage/default/3.prim_async_alert.819598546 Jul 14 04:21:54 PM PDT 24 Jul 14 04:21:56 PM PDT 24 11225294 ps
T17 /workspace/coverage/default/8.prim_async_alert.3585202989 Jul 14 04:22:07 PM PDT 24 Jul 14 04:22:08 PM PDT 24 11438971 ps
T11 /workspace/coverage/default/4.prim_async_alert.2666063478 Jul 14 04:21:54 PM PDT 24 Jul 14 04:21:56 PM PDT 24 12017306 ps
T21 /workspace/coverage/default/7.prim_async_alert.3933387230 Jul 14 04:22:07 PM PDT 24 Jul 14 04:22:08 PM PDT 24 10726590 ps
T22 /workspace/coverage/default/14.prim_async_alert.233133207 Jul 14 04:22:24 PM PDT 24 Jul 14 04:22:26 PM PDT 24 10919764 ps
T23 /workspace/coverage/default/12.prim_async_alert.3331795961 Jul 14 04:21:50 PM PDT 24 Jul 14 04:21:52 PM PDT 24 11145135 ps
T24 /workspace/coverage/default/9.prim_async_alert.1799266159 Jul 14 04:22:05 PM PDT 24 Jul 14 04:22:06 PM PDT 24 11610487 ps
T25 /workspace/coverage/default/0.prim_async_alert.3343857367 Jul 14 04:22:07 PM PDT 24 Jul 14 04:22:08 PM PDT 24 10847410 ps
T26 /workspace/coverage/default/19.prim_async_alert.2487781964 Jul 14 04:22:26 PM PDT 24 Jul 14 04:22:28 PM PDT 24 10361408 ps
T51 /workspace/coverage/default/16.prim_async_alert.1342257486 Jul 14 04:22:25 PM PDT 24 Jul 14 04:22:26 PM PDT 24 10821939 ps
T52 /workspace/coverage/default/10.prim_async_alert.2489301198 Jul 14 04:20:08 PM PDT 24 Jul 14 04:20:09 PM PDT 24 10843424 ps
T15 /workspace/coverage/default/1.prim_async_alert.2273129464 Jul 14 04:22:05 PM PDT 24 Jul 14 04:22:06 PM PDT 24 12000475 ps
T43 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2605342331 Jul 14 05:59:03 PM PDT 24 Jul 14 05:59:04 PM PDT 24 31176300 ps
T44 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.462212302 Jul 14 05:59:07 PM PDT 24 Jul 14 05:59:08 PM PDT 24 28980192 ps
T45 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2265626959 Jul 14 05:59:00 PM PDT 24 Jul 14 05:59:02 PM PDT 24 28623340 ps
T46 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1480911839 Jul 14 05:59:08 PM PDT 24 Jul 14 05:59:09 PM PDT 24 30105560 ps
T47 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2760683226 Jul 14 05:59:07 PM PDT 24 Jul 14 05:59:08 PM PDT 24 28476911 ps
T48 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3732158231 Jul 14 05:59:03 PM PDT 24 Jul 14 05:59:04 PM PDT 24 31024408 ps
T16 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1852746355 Jul 14 05:59:05 PM PDT 24 Jul 14 05:59:05 PM PDT 24 32042838 ps
T42 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3730402954 Jul 14 05:59:06 PM PDT 24 Jul 14 05:59:07 PM PDT 24 29870591 ps
T49 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2371367877 Jul 14 05:59:07 PM PDT 24 Jul 14 05:59:08 PM PDT 24 29167534 ps
T50 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3373729170 Jul 14 05:59:10 PM PDT 24 Jul 14 05:59:11 PM PDT 24 28311315 ps
T53 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.942629278 Jul 14 05:59:05 PM PDT 24 Jul 14 05:59:06 PM PDT 24 27970700 ps
T54 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1658767109 Jul 14 05:59:07 PM PDT 24 Jul 14 05:59:08 PM PDT 24 30048705 ps
T55 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.25806397 Jul 14 05:59:06 PM PDT 24 Jul 14 05:59:06 PM PDT 24 29040034 ps
T56 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2198652192 Jul 14 05:59:08 PM PDT 24 Jul 14 05:59:09 PM PDT 24 29521749 ps
T57 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1240603162 Jul 14 05:59:04 PM PDT 24 Jul 14 05:59:05 PM PDT 24 30215256 ps
T58 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2364182000 Jul 14 05:59:06 PM PDT 24 Jul 14 05:59:07 PM PDT 24 29505064 ps
T12 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2871535454 Jul 14 05:59:03 PM PDT 24 Jul 14 05:59:04 PM PDT 24 31260028 ps
T4 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4122523064 Jul 14 05:59:07 PM PDT 24 Jul 14 05:59:08 PM PDT 24 28760932 ps
T13 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2060729371 Jul 14 05:59:09 PM PDT 24 Jul 14 05:59:10 PM PDT 24 31745334 ps
T36 /workspace/coverage/sync_alert/14.prim_sync_alert.2343137017 Jul 14 04:22:42 PM PDT 24 Jul 14 04:22:44 PM PDT 24 9719118 ps
T27 /workspace/coverage/sync_alert/9.prim_sync_alert.2535934734 Jul 14 04:23:02 PM PDT 24 Jul 14 04:23:04 PM PDT 24 9519028 ps
T37 /workspace/coverage/sync_alert/3.prim_sync_alert.1212266760 Jul 14 04:22:49 PM PDT 24 Jul 14 04:22:50 PM PDT 24 10252141 ps
T38 /workspace/coverage/sync_alert/13.prim_sync_alert.1461700139 Jul 14 04:22:18 PM PDT 24 Jul 14 04:22:19 PM PDT 24 8022782 ps
T39 /workspace/coverage/sync_alert/2.prim_sync_alert.3241844281 Jul 14 04:22:42 PM PDT 24 Jul 14 04:22:44 PM PDT 24 9540453 ps
T40 /workspace/coverage/sync_alert/15.prim_sync_alert.3417779519 Jul 14 04:22:27 PM PDT 24 Jul 14 04:22:30 PM PDT 24 9297382 ps
T28 /workspace/coverage/sync_alert/4.prim_sync_alert.2685730945 Jul 14 04:21:59 PM PDT 24 Jul 14 04:22:02 PM PDT 24 8653685 ps
T9 /workspace/coverage/sync_alert/0.prim_sync_alert.904622060 Jul 14 04:22:30 PM PDT 24 Jul 14 04:22:32 PM PDT 24 9602607 ps
T29 /workspace/coverage/sync_alert/19.prim_sync_alert.4130390885 Jul 14 04:21:54 PM PDT 24 Jul 14 04:21:57 PM PDT 24 9810186 ps
T41 /workspace/coverage/sync_alert/10.prim_sync_alert.336456017 Jul 14 04:21:44 PM PDT 24 Jul 14 04:21:45 PM PDT 24 8717771 ps
T30 /workspace/coverage/sync_alert/12.prim_sync_alert.3763314137 Jul 14 04:22:40 PM PDT 24 Jul 14 04:22:42 PM PDT 24 9596205 ps
T31 /workspace/coverage/sync_alert/1.prim_sync_alert.2877205151 Jul 14 04:22:49 PM PDT 24 Jul 14 04:22:50 PM PDT 24 10323621 ps
T32 /workspace/coverage/sync_alert/18.prim_sync_alert.1933109694 Jul 14 04:22:27 PM PDT 24 Jul 14 04:22:30 PM PDT 24 10233390 ps
T33 /workspace/coverage/sync_alert/6.prim_sync_alert.299861751 Jul 14 04:23:02 PM PDT 24 Jul 14 04:23:04 PM PDT 24 8413501 ps
T59 /workspace/coverage/sync_alert/5.prim_sync_alert.2808572855 Jul 14 04:23:17 PM PDT 24 Jul 14 04:23:18 PM PDT 24 9775011 ps
T34 /workspace/coverage/sync_alert/8.prim_sync_alert.4009819451 Jul 14 04:18:55 PM PDT 24 Jul 14 04:18:56 PM PDT 24 8634018 ps
T35 /workspace/coverage/sync_alert/16.prim_sync_alert.2661752492 Jul 14 04:22:42 PM PDT 24 Jul 14 04:22:45 PM PDT 24 8643594 ps
T60 /workspace/coverage/sync_alert/17.prim_sync_alert.494150918 Jul 14 04:20:20 PM PDT 24 Jul 14 04:20:21 PM PDT 24 8817371 ps
T61 /workspace/coverage/sync_alert/7.prim_sync_alert.3434459160 Jul 14 04:20:40 PM PDT 24 Jul 14 04:20:41 PM PDT 24 9365682 ps
T10 /workspace/coverage/sync_alert/11.prim_sync_alert.3065147650 Jul 14 04:21:44 PM PDT 24 Jul 14 04:21:45 PM PDT 24 8776835 ps
T62 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.405420337 Jul 14 04:21:46 PM PDT 24 Jul 14 04:21:47 PM PDT 24 27963141 ps
T63 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1254933309 Jul 14 04:22:21 PM PDT 24 Jul 14 04:22:22 PM PDT 24 28394528 ps
T64 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3798244086 Jul 14 04:23:16 PM PDT 24 Jul 14 04:23:17 PM PDT 24 26831930 ps
T65 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2523937664 Jul 14 04:17:55 PM PDT 24 Jul 14 04:17:56 PM PDT 24 27929648 ps
T66 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3580025046 Jul 14 04:22:26 PM PDT 24 Jul 14 04:22:28 PM PDT 24 25566711 ps
T67 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1479474415 Jul 14 04:20:07 PM PDT 24 Jul 14 04:20:08 PM PDT 24 28066469 ps
T68 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2711045641 Jul 14 04:21:50 PM PDT 24 Jul 14 04:21:51 PM PDT 24 28064419 ps
T69 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.357146678 Jul 14 04:22:05 PM PDT 24 Jul 14 04:22:07 PM PDT 24 26537302 ps
T70 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3698471654 Jul 14 04:22:25 PM PDT 24 Jul 14 04:22:26 PM PDT 24 28978327 ps
T71 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.965137319 Jul 14 04:22:26 PM PDT 24 Jul 14 04:22:28 PM PDT 24 28439405 ps
T5 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4271062485 Jul 14 04:22:24 PM PDT 24 Jul 14 04:22:26 PM PDT 24 29156709 ps
T72 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4071512724 Jul 14 04:21:58 PM PDT 24 Jul 14 04:22:01 PM PDT 24 27312051 ps
T73 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3706124142 Jul 14 04:22:20 PM PDT 24 Jul 14 04:22:21 PM PDT 24 27253746 ps
T74 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.213775865 Jul 14 04:22:06 PM PDT 24 Jul 14 04:22:08 PM PDT 24 28007685 ps
T75 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1680863009 Jul 14 04:21:59 PM PDT 24 Jul 14 04:22:02 PM PDT 24 28034296 ps
T76 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1574707305 Jul 14 04:21:53 PM PDT 24 Jul 14 04:21:54 PM PDT 24 28457022 ps
T6 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3751488138 Jul 14 04:22:30 PM PDT 24 Jul 14 04:22:32 PM PDT 24 27580512 ps
T77 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1205678848 Jul 14 04:22:29 PM PDT 24 Jul 14 04:22:32 PM PDT 24 27187325 ps
T78 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.667874719 Jul 14 04:22:24 PM PDT 24 Jul 14 04:22:26 PM PDT 24 27240282 ps
T79 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1995755432 Jul 14 04:22:05 PM PDT 24 Jul 14 04:22:06 PM PDT 24 28017470 ps

Test location /workspace/coverage/default/6.prim_async_alert.520559552
Short name T7
Test name
Test status
Simulation time 12119268 ps
CPU time 0.44 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:21:56 PM PDT 24
Peak memory 144412 kb
Host smart-134f6b8b-f66d-4b38-9fba-ea87c1443b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520559552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.520559552
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.904622060
Short name T9
Test name
Test status
Simulation time 9602607 ps
CPU time 0.37 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 04:22:32 PM PDT 24
Peak memory 145140 kb
Host smart-fc9840d2-1115-4240-8733-e242f5a69dfd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=904622060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.904622060
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2666063478
Short name T11
Test name
Test status
Simulation time 12017306 ps
CPU time 0.41 seconds
Started Jul 14 04:21:54 PM PDT 24
Finished Jul 14 04:21:56 PM PDT 24
Peak memory 145340 kb
Host smart-c702992c-0e06-4d6d-8fa9-d122d3e29bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666063478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2666063478
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2265626959
Short name T45
Test name
Test status
Simulation time 28623340 ps
CPU time 0.42 seconds
Started Jul 14 05:59:00 PM PDT 24
Finished Jul 14 05:59:02 PM PDT 24
Peak memory 145220 kb
Host smart-4c0f1a28-b89c-4919-ba93-61180d2ec899
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2265626959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2265626959
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4122523064
Short name T4
Test name
Test status
Simulation time 28760932 ps
CPU time 0.4 seconds
Started Jul 14 05:59:07 PM PDT 24
Finished Jul 14 05:59:08 PM PDT 24
Peak memory 145328 kb
Host smart-6e65ea6e-64bb-4f95-bb34-67d5a49fa4b9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4122523064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.4122523064
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3343857367
Short name T25
Test name
Test status
Simulation time 10847410 ps
CPU time 0.38 seconds
Started Jul 14 04:22:07 PM PDT 24
Finished Jul 14 04:22:08 PM PDT 24
Peak memory 145596 kb
Host smart-ea90f919-8337-4de9-a4d5-07742bb2544f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343857367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3343857367
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2273129464
Short name T15
Test name
Test status
Simulation time 12000475 ps
CPU time 0.38 seconds
Started Jul 14 04:22:05 PM PDT 24
Finished Jul 14 04:22:06 PM PDT 24
Peak memory 145780 kb
Host smart-56dafd9a-3937-4cef-93dc-592820b6138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273129464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2273129464
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2489301198
Short name T52
Test name
Test status
Simulation time 10843424 ps
CPU time 0.4 seconds
Started Jul 14 04:20:08 PM PDT 24
Finished Jul 14 04:20:09 PM PDT 24
Peak memory 145676 kb
Host smart-3b3fd804-086e-4dbc-9929-f1a1e5c44062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489301198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2489301198
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.4274974478
Short name T19
Test name
Test status
Simulation time 10519053 ps
CPU time 0.38 seconds
Started Jul 14 04:21:45 PM PDT 24
Finished Jul 14 04:21:46 PM PDT 24
Peak memory 145672 kb
Host smart-dabc07d3-e8ea-4b35-94be-ffc0901fc465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274974478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4274974478
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.3331795961
Short name T23
Test name
Test status
Simulation time 11145135 ps
CPU time 0.43 seconds
Started Jul 14 04:21:50 PM PDT 24
Finished Jul 14 04:21:52 PM PDT 24
Peak memory 145244 kb
Host smart-905a4b04-8ee7-41c6-b6f2-a86b38ab2181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331795961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3331795961
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3731800144
Short name T14
Test name
Test status
Simulation time 11732958 ps
CPU time 0.38 seconds
Started Jul 14 04:18:42 PM PDT 24
Finished Jul 14 04:18:43 PM PDT 24
Peak memory 145768 kb
Host smart-9ce8e826-ee58-4272-8b10-c53898f247f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731800144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3731800144
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.233133207
Short name T22
Test name
Test status
Simulation time 10919764 ps
CPU time 0.41 seconds
Started Jul 14 04:22:24 PM PDT 24
Finished Jul 14 04:22:26 PM PDT 24
Peak memory 145252 kb
Host smart-26c5dfc0-efc1-45ee-9a74-3887a1741be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233133207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.233133207
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1455558588
Short name T1
Test name
Test status
Simulation time 11206527 ps
CPU time 0.36 seconds
Started Jul 14 04:22:25 PM PDT 24
Finished Jul 14 04:22:26 PM PDT 24
Peak memory 145612 kb
Host smart-0bbe687c-bc0d-4441-9afd-3119dcdad224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455558588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1455558588
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1342257486
Short name T51
Test name
Test status
Simulation time 10821939 ps
CPU time 0.37 seconds
Started Jul 14 04:22:25 PM PDT 24
Finished Jul 14 04:22:26 PM PDT 24
Peak memory 145440 kb
Host smart-c3ab0836-4ffd-4d9b-ac8c-b5974b9e4f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342257486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1342257486
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.588335465
Short name T8
Test name
Test status
Simulation time 10299403 ps
CPU time 0.38 seconds
Started Jul 14 04:22:25 PM PDT 24
Finished Jul 14 04:22:26 PM PDT 24
Peak memory 145444 kb
Host smart-e7ef39b0-cd4a-4262-82f4-ff8300656cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588335465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.588335465
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2747105680
Short name T18
Test name
Test status
Simulation time 11335477 ps
CPU time 0.39 seconds
Started Jul 14 04:22:26 PM PDT 24
Finished Jul 14 04:22:28 PM PDT 24
Peak memory 144348 kb
Host smart-9bfdb3ba-6c39-441a-8721-f4fa34a9dfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747105680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2747105680
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2487781964
Short name T26
Test name
Test status
Simulation time 10361408 ps
CPU time 0.45 seconds
Started Jul 14 04:22:26 PM PDT 24
Finished Jul 14 04:22:28 PM PDT 24
Peak memory 143440 kb
Host smart-b7b819db-d95d-4161-8ef6-814bda2ae02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487781964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2487781964
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3599964334
Short name T2
Test name
Test status
Simulation time 11558959 ps
CPU time 0.37 seconds
Started Jul 14 04:19:27 PM PDT 24
Finished Jul 14 04:19:28 PM PDT 24
Peak memory 145684 kb
Host smart-c01485ce-fe8e-446c-a3ae-2fb561125971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599964334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3599964334
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.819598546
Short name T20
Test name
Test status
Simulation time 11225294 ps
CPU time 0.4 seconds
Started Jul 14 04:21:54 PM PDT 24
Finished Jul 14 04:21:56 PM PDT 24
Peak memory 145372 kb
Host smart-9920b723-b143-4757-ab9e-577512eda2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819598546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.819598546
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3043061505
Short name T3
Test name
Test status
Simulation time 11916725 ps
CPU time 0.45 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:23:03 PM PDT 24
Peak memory 144044 kb
Host smart-4e251183-ef43-4683-9087-c65dff1eca9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043061505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3043061505
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3933387230
Short name T21
Test name
Test status
Simulation time 10726590 ps
CPU time 0.38 seconds
Started Jul 14 04:22:07 PM PDT 24
Finished Jul 14 04:22:08 PM PDT 24
Peak memory 145424 kb
Host smart-33d098a2-028d-4331-8a00-ccf3d5308c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933387230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3933387230
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3585202989
Short name T17
Test name
Test status
Simulation time 11438971 ps
CPU time 0.38 seconds
Started Jul 14 04:22:07 PM PDT 24
Finished Jul 14 04:22:08 PM PDT 24
Peak memory 145424 kb
Host smart-2e3857b8-8568-4412-9d51-ebab4098c78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585202989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3585202989
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1799266159
Short name T24
Test name
Test status
Simulation time 11610487 ps
CPU time 0.38 seconds
Started Jul 14 04:22:05 PM PDT 24
Finished Jul 14 04:22:06 PM PDT 24
Peak memory 145488 kb
Host smart-a6b8c639-56ae-428a-b142-5211d7e2fcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799266159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1799266159
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2364182000
Short name T58
Test name
Test status
Simulation time 29505064 ps
CPU time 0.4 seconds
Started Jul 14 05:59:06 PM PDT 24
Finished Jul 14 05:59:07 PM PDT 24
Peak memory 145328 kb
Host smart-5ae1def4-4e4e-4d55-ad1b-ee7ca4c6e5ef
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2364182000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2364182000
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2198652192
Short name T56
Test name
Test status
Simulation time 29521749 ps
CPU time 0.4 seconds
Started Jul 14 05:59:08 PM PDT 24
Finished Jul 14 05:59:09 PM PDT 24
Peak memory 145280 kb
Host smart-1b462661-79c3-41cb-bc9e-82844360d73e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2198652192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2198652192
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2060729371
Short name T13
Test name
Test status
Simulation time 31745334 ps
CPU time 0.4 seconds
Started Jul 14 05:59:09 PM PDT 24
Finished Jul 14 05:59:10 PM PDT 24
Peak memory 145296 kb
Host smart-e9d1be1e-878a-4571-8500-910bf4d63862
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2060729371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2060729371
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2871535454
Short name T12
Test name
Test status
Simulation time 31260028 ps
CPU time 0.4 seconds
Started Jul 14 05:59:03 PM PDT 24
Finished Jul 14 05:59:04 PM PDT 24
Peak memory 145344 kb
Host smart-05d1ea14-3ca1-495a-b144-ec45cb3719aa
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2871535454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2871535454
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.25806397
Short name T55
Test name
Test status
Simulation time 29040034 ps
CPU time 0.4 seconds
Started Jul 14 05:59:06 PM PDT 24
Finished Jul 14 05:59:06 PM PDT 24
Peak memory 145240 kb
Host smart-49924bbe-24d6-43c6-8bed-c1480c51c6fe
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=25806397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.25806397
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2371367877
Short name T49
Test name
Test status
Simulation time 29167534 ps
CPU time 0.41 seconds
Started Jul 14 05:59:07 PM PDT 24
Finished Jul 14 05:59:08 PM PDT 24
Peak memory 145116 kb
Host smart-72541851-2c57-475b-827b-dceb6cb4d4a0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2371367877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2371367877
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3373729170
Short name T50
Test name
Test status
Simulation time 28311315 ps
CPU time 0.39 seconds
Started Jul 14 05:59:10 PM PDT 24
Finished Jul 14 05:59:11 PM PDT 24
Peak memory 145304 kb
Host smart-2a6f8961-8cbc-47ec-a18c-136d92406de5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3373729170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3373729170
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3732158231
Short name T48
Test name
Test status
Simulation time 31024408 ps
CPU time 0.42 seconds
Started Jul 14 05:59:03 PM PDT 24
Finished Jul 14 05:59:04 PM PDT 24
Peak memory 145400 kb
Host smart-cfba6e87-3bc8-4b02-9eff-a5740c9d7453
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3732158231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3732158231
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1852746355
Short name T16
Test name
Test status
Simulation time 32042838 ps
CPU time 0.41 seconds
Started Jul 14 05:59:05 PM PDT 24
Finished Jul 14 05:59:05 PM PDT 24
Peak memory 145320 kb
Host smart-4e51416c-a10d-46c0-aaf8-189e5d5bf643
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1852746355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1852746355
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1658767109
Short name T54
Test name
Test status
Simulation time 30048705 ps
CPU time 0.44 seconds
Started Jul 14 05:59:07 PM PDT 24
Finished Jul 14 05:59:08 PM PDT 24
Peak memory 145248 kb
Host smart-2ce99275-274f-4e35-9b9c-5dc07ff0c707
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1658767109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1658767109
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1480911839
Short name T46
Test name
Test status
Simulation time 30105560 ps
CPU time 0.43 seconds
Started Jul 14 05:59:08 PM PDT 24
Finished Jul 14 05:59:09 PM PDT 24
Peak memory 145332 kb
Host smart-e4bc4aef-06e3-4373-9d12-2b5d2a8ee356
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1480911839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1480911839
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2760683226
Short name T47
Test name
Test status
Simulation time 28476911 ps
CPU time 0.4 seconds
Started Jul 14 05:59:07 PM PDT 24
Finished Jul 14 05:59:08 PM PDT 24
Peak memory 145220 kb
Host smart-e8142507-c85b-4528-a0c2-c82c767e25c7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2760683226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2760683226
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.942629278
Short name T53
Test name
Test status
Simulation time 27970700 ps
CPU time 0.41 seconds
Started Jul 14 05:59:05 PM PDT 24
Finished Jul 14 05:59:06 PM PDT 24
Peak memory 145304 kb
Host smart-13fdcc00-86a8-48a3-8e72-75740724e03b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=942629278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.942629278
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.462212302
Short name T44
Test name
Test status
Simulation time 28980192 ps
CPU time 0.41 seconds
Started Jul 14 05:59:07 PM PDT 24
Finished Jul 14 05:59:08 PM PDT 24
Peak memory 145260 kb
Host smart-0b0410b8-9f49-45c2-9f0a-7c819c469e51
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=462212302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.462212302
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3730402954
Short name T42
Test name
Test status
Simulation time 29870591 ps
CPU time 0.41 seconds
Started Jul 14 05:59:06 PM PDT 24
Finished Jul 14 05:59:07 PM PDT 24
Peak memory 145304 kb
Host smart-be4bd50b-94f8-4f48-a5e6-0a3d78ae8ea0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3730402954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3730402954
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1240603162
Short name T57
Test name
Test status
Simulation time 30215256 ps
CPU time 0.41 seconds
Started Jul 14 05:59:04 PM PDT 24
Finished Jul 14 05:59:05 PM PDT 24
Peak memory 145348 kb
Host smart-050fdd93-16b9-4851-82a0-93cbc05127f2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1240603162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1240603162
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2605342331
Short name T43
Test name
Test status
Simulation time 31176300 ps
CPU time 0.41 seconds
Started Jul 14 05:59:03 PM PDT 24
Finished Jul 14 05:59:04 PM PDT 24
Peak memory 145316 kb
Host smart-8f965959-eb46-4324-881a-58bf08a1f00f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2605342331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2605342331
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2877205151
Short name T31
Test name
Test status
Simulation time 10323621 ps
CPU time 0.42 seconds
Started Jul 14 04:22:49 PM PDT 24
Finished Jul 14 04:22:50 PM PDT 24
Peak memory 143336 kb
Host smart-8013d43c-cb5a-411a-b150-fd0afb54ed39
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2877205151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2877205151
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.336456017
Short name T41
Test name
Test status
Simulation time 8717771 ps
CPU time 0.42 seconds
Started Jul 14 04:21:44 PM PDT 24
Finished Jul 14 04:21:45 PM PDT 24
Peak memory 143984 kb
Host smart-7dccf892-7221-48a4-88a5-62a8cc3d3659
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=336456017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.336456017
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3065147650
Short name T10
Test name
Test status
Simulation time 8776835 ps
CPU time 0.42 seconds
Started Jul 14 04:21:44 PM PDT 24
Finished Jul 14 04:21:45 PM PDT 24
Peak memory 145052 kb
Host smart-c0badb60-6351-40b8-a16f-e402786c7b19
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3065147650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3065147650
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3763314137
Short name T30
Test name
Test status
Simulation time 9596205 ps
CPU time 0.37 seconds
Started Jul 14 04:22:40 PM PDT 24
Finished Jul 14 04:22:42 PM PDT 24
Peak memory 145428 kb
Host smart-5bad5c98-8101-473a-85f5-0edd0b708f0a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3763314137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3763314137
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1461700139
Short name T38
Test name
Test status
Simulation time 8022782 ps
CPU time 0.38 seconds
Started Jul 14 04:22:18 PM PDT 24
Finished Jul 14 04:22:19 PM PDT 24
Peak memory 145204 kb
Host smart-40e8c4de-2cc9-4451-8941-d4e6a166fed3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1461700139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1461700139
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2343137017
Short name T36
Test name
Test status
Simulation time 9719118 ps
CPU time 0.38 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:22:44 PM PDT 24
Peak memory 145176 kb
Host smart-d7bd9d96-0f99-44d1-a68f-5ac39f2001c2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2343137017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2343137017
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3417779519
Short name T40
Test name
Test status
Simulation time 9297382 ps
CPU time 0.38 seconds
Started Jul 14 04:22:27 PM PDT 24
Finished Jul 14 04:22:30 PM PDT 24
Peak memory 145236 kb
Host smart-c51f0d92-3071-4609-8c82-3dfa5b0f90f8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3417779519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3417779519
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2661752492
Short name T35
Test name
Test status
Simulation time 8643594 ps
CPU time 0.37 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:22:45 PM PDT 24
Peak memory 145344 kb
Host smart-95010355-73f0-437d-8115-790ddc45ae08
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2661752492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2661752492
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.494150918
Short name T60
Test name
Test status
Simulation time 8817371 ps
CPU time 0.39 seconds
Started Jul 14 04:20:20 PM PDT 24
Finished Jul 14 04:20:21 PM PDT 24
Peak memory 145560 kb
Host smart-fe229d4a-5f1d-4bbc-81fe-61888af32858
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=494150918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.494150918
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1933109694
Short name T32
Test name
Test status
Simulation time 10233390 ps
CPU time 0.42 seconds
Started Jul 14 04:22:27 PM PDT 24
Finished Jul 14 04:22:30 PM PDT 24
Peak memory 145280 kb
Host smart-7cf82504-0255-4819-b265-3c039fdef8d0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1933109694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1933109694
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.4130390885
Short name T29
Test name
Test status
Simulation time 9810186 ps
CPU time 0.45 seconds
Started Jul 14 04:21:54 PM PDT 24
Finished Jul 14 04:21:57 PM PDT 24
Peak memory 143740 kb
Host smart-9b62f22d-189d-4f03-8bac-6a721335ab5e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4130390885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.4130390885
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3241844281
Short name T39
Test name
Test status
Simulation time 9540453 ps
CPU time 0.38 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:22:44 PM PDT 24
Peak memory 145380 kb
Host smart-756cb525-99f1-47ab-b3bb-74a2096e9dc4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3241844281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3241844281
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1212266760
Short name T37
Test name
Test status
Simulation time 10252141 ps
CPU time 0.43 seconds
Started Jul 14 04:22:49 PM PDT 24
Finished Jul 14 04:22:50 PM PDT 24
Peak memory 143396 kb
Host smart-88ca0da7-82d1-4932-af29-1229dc865e73
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1212266760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1212266760
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2685730945
Short name T28
Test name
Test status
Simulation time 8653685 ps
CPU time 0.38 seconds
Started Jul 14 04:21:59 PM PDT 24
Finished Jul 14 04:22:02 PM PDT 24
Peak memory 145424 kb
Host smart-34d70a5d-53c8-4874-a4e2-bc424d8b971d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2685730945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2685730945
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2808572855
Short name T59
Test name
Test status
Simulation time 9775011 ps
CPU time 0.37 seconds
Started Jul 14 04:23:17 PM PDT 24
Finished Jul 14 04:23:18 PM PDT 24
Peak memory 145432 kb
Host smart-b3dc102d-dfef-4506-b512-95874265ccde
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2808572855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2808572855
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.299861751
Short name T33
Test name
Test status
Simulation time 8413501 ps
CPU time 0.43 seconds
Started Jul 14 04:23:02 PM PDT 24
Finished Jul 14 04:23:04 PM PDT 24
Peak memory 143104 kb
Host smart-daa447e5-a7c4-4c88-86ba-66ffbfdb6703
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=299861751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.299861751
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3434459160
Short name T61
Test name
Test status
Simulation time 9365682 ps
CPU time 0.36 seconds
Started Jul 14 04:20:40 PM PDT 24
Finished Jul 14 04:20:41 PM PDT 24
Peak memory 145480 kb
Host smart-79911b4b-e7e0-4177-99e9-fc763f603589
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3434459160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3434459160
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.4009819451
Short name T34
Test name
Test status
Simulation time 8634018 ps
CPU time 0.38 seconds
Started Jul 14 04:18:55 PM PDT 24
Finished Jul 14 04:18:56 PM PDT 24
Peak memory 145448 kb
Host smart-a8a6b73a-b806-4f2f-9a31-3a0efe9d4f7c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4009819451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.4009819451
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2535934734
Short name T27
Test name
Test status
Simulation time 9519028 ps
CPU time 0.43 seconds
Started Jul 14 04:23:02 PM PDT 24
Finished Jul 14 04:23:04 PM PDT 24
Peak memory 143000 kb
Host smart-85fde262-3f19-48ad-bc14-6e9716e63505
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2535934734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2535934734
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2711045641
Short name T68
Test name
Test status
Simulation time 28064419 ps
CPU time 0.42 seconds
Started Jul 14 04:21:50 PM PDT 24
Finished Jul 14 04:21:51 PM PDT 24
Peak memory 145832 kb
Host smart-ef6bf104-4c41-4f08-9646-78181b8a33e0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2711045641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2711045641
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3798244086
Short name T64
Test name
Test status
Simulation time 26831930 ps
CPU time 0.38 seconds
Started Jul 14 04:23:16 PM PDT 24
Finished Jul 14 04:23:17 PM PDT 24
Peak memory 145428 kb
Host smart-b3f4b6d8-9273-452f-b2f6-a9487d351113
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3798244086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3798244086
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.213775865
Short name T74
Test name
Test status
Simulation time 28007685 ps
CPU time 0.38 seconds
Started Jul 14 04:22:06 PM PDT 24
Finished Jul 14 04:22:08 PM PDT 24
Peak memory 145436 kb
Host smart-4315308e-0e73-4dc9-ac76-b2b2840ae7c2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=213775865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.213775865
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4271062485
Short name T5
Test name
Test status
Simulation time 29156709 ps
CPU time 0.42 seconds
Started Jul 14 04:22:24 PM PDT 24
Finished Jul 14 04:22:26 PM PDT 24
Peak memory 144852 kb
Host smart-eb825de5-c1ee-4518-b04a-fd4ec9217f17
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4271062485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.4271062485
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3698471654
Short name T70
Test name
Test status
Simulation time 28978327 ps
CPU time 0.39 seconds
Started Jul 14 04:22:25 PM PDT 24
Finished Jul 14 04:22:26 PM PDT 24
Peak memory 145152 kb
Host smart-e70841f0-ba8b-4672-8e8a-057d9f930400
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3698471654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3698471654
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3706124142
Short name T73
Test name
Test status
Simulation time 27253746 ps
CPU time 0.39 seconds
Started Jul 14 04:22:20 PM PDT 24
Finished Jul 14 04:22:21 PM PDT 24
Peak memory 145180 kb
Host smart-2f14c3e3-2683-45b5-a624-e4730be7e241
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3706124142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3706124142
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.667874719
Short name T78
Test name
Test status
Simulation time 27240282 ps
CPU time 0.43 seconds
Started Jul 14 04:22:24 PM PDT 24
Finished Jul 14 04:22:26 PM PDT 24
Peak memory 144836 kb
Host smart-50f79a1b-8cbc-4f51-922b-b6ec80fde0e1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=667874719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.667874719
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1254933309
Short name T63
Test name
Test status
Simulation time 28394528 ps
CPU time 0.39 seconds
Started Jul 14 04:22:21 PM PDT 24
Finished Jul 14 04:22:22 PM PDT 24
Peak memory 145284 kb
Host smart-9f13c2f1-525a-4206-ab87-19b7d6a6a887
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1254933309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1254933309
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.965137319
Short name T71
Test name
Test status
Simulation time 28439405 ps
CPU time 0.44 seconds
Started Jul 14 04:22:26 PM PDT 24
Finished Jul 14 04:22:28 PM PDT 24
Peak memory 143392 kb
Host smart-a0f03c76-8ca5-4e64-9f56-28b6bfcb9e52
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=965137319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.965137319
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1205678848
Short name T77
Test name
Test status
Simulation time 27187325 ps
CPU time 0.41 seconds
Started Jul 14 04:22:29 PM PDT 24
Finished Jul 14 04:22:32 PM PDT 24
Peak memory 145200 kb
Host smart-d98a7d23-ae54-4a68-b5cd-54705817c3de
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1205678848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1205678848
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3751488138
Short name T6
Test name
Test status
Simulation time 27580512 ps
CPU time 0.38 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 04:22:32 PM PDT 24
Peak memory 145200 kb
Host smart-285e6dad-a318-4685-a228-031db706a400
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3751488138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3751488138
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3580025046
Short name T66
Test name
Test status
Simulation time 25566711 ps
CPU time 0.47 seconds
Started Jul 14 04:22:26 PM PDT 24
Finished Jul 14 04:22:28 PM PDT 24
Peak memory 143508 kb
Host smart-0ee6f0b9-4775-4c3e-80f0-5104f2f9640e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3580025046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3580025046
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1479474415
Short name T67
Test name
Test status
Simulation time 28066469 ps
CPU time 0.39 seconds
Started Jul 14 04:20:07 PM PDT 24
Finished Jul 14 04:20:08 PM PDT 24
Peak memory 145432 kb
Host smart-a78244bd-49d1-49e8-afc9-a90e85635321
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1479474415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1479474415
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2523937664
Short name T65
Test name
Test status
Simulation time 27929648 ps
CPU time 0.41 seconds
Started Jul 14 04:17:55 PM PDT 24
Finished Jul 14 04:17:56 PM PDT 24
Peak memory 145528 kb
Host smart-14dc5b2c-9ec6-4d57-8419-115452f798d5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2523937664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2523937664
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1680863009
Short name T75
Test name
Test status
Simulation time 28034296 ps
CPU time 0.42 seconds
Started Jul 14 04:21:59 PM PDT 24
Finished Jul 14 04:22:02 PM PDT 24
Peak memory 145220 kb
Host smart-f5b6ce05-7602-4570-b1bf-989620989a21
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1680863009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1680863009
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1574707305
Short name T76
Test name
Test status
Simulation time 28457022 ps
CPU time 0.45 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:21:54 PM PDT 24
Peak memory 143888 kb
Host smart-9049dedc-433f-47a0-8d66-99362efa9baf
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1574707305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1574707305
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.357146678
Short name T69
Test name
Test status
Simulation time 26537302 ps
CPU time 0.4 seconds
Started Jul 14 04:22:05 PM PDT 24
Finished Jul 14 04:22:07 PM PDT 24
Peak memory 145252 kb
Host smart-163940ea-8f90-47a1-8330-9a6f33cfc81a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=357146678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.357146678
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.405420337
Short name T62
Test name
Test status
Simulation time 27963141 ps
CPU time 0.38 seconds
Started Jul 14 04:21:46 PM PDT 24
Finished Jul 14 04:21:47 PM PDT 24
Peak memory 145192 kb
Host smart-a12917cd-ebc2-43cd-bf38-3260c573d98b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=405420337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.405420337
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4071512724
Short name T72
Test name
Test status
Simulation time 27312051 ps
CPU time 0.38 seconds
Started Jul 14 04:21:58 PM PDT 24
Finished Jul 14 04:22:01 PM PDT 24
Peak memory 145408 kb
Host smart-e6806031-0ab3-4a8c-84fd-b47c31b29882
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4071512724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.4071512724
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1995755432
Short name T79
Test name
Test status
Simulation time 28017470 ps
CPU time 0.41 seconds
Started Jul 14 04:22:05 PM PDT 24
Finished Jul 14 04:22:06 PM PDT 24
Peak memory 145212 kb
Host smart-1d14d406-9327-478c-9998-2166cbed31e2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1995755432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1995755432
Directory /workspace/9.prim_sync_fatal_alert/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%