| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 89.27 | 89.27 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/10.prim_async_alert.2347818101 |
| 92.99 | 3.72 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 89.29 | 10.71 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/1.prim_sync_alert.3941625820 |
| 94.50 | 1.51 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.5688622 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2848999520 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2348135003 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.382764658 |
| /workspace/coverage/default/1.prim_async_alert.2737303985 |
| /workspace/coverage/default/11.prim_async_alert.1887347696 |
| /workspace/coverage/default/12.prim_async_alert.2187481374 |
| /workspace/coverage/default/13.prim_async_alert.938488258 |
| /workspace/coverage/default/14.prim_async_alert.551512431 |
| /workspace/coverage/default/15.prim_async_alert.2362421011 |
| /workspace/coverage/default/16.prim_async_alert.1268986913 |
| /workspace/coverage/default/18.prim_async_alert.1656913638 |
| /workspace/coverage/default/19.prim_async_alert.557349632 |
| /workspace/coverage/default/2.prim_async_alert.3086052960 |
| /workspace/coverage/default/3.prim_async_alert.381645196 |
| /workspace/coverage/default/4.prim_async_alert.982193224 |
| /workspace/coverage/default/5.prim_async_alert.3658974474 |
| /workspace/coverage/default/6.prim_async_alert.2136197546 |
| /workspace/coverage/default/7.prim_async_alert.340466302 |
| /workspace/coverage/default/8.prim_async_alert.2430627472 |
| /workspace/coverage/default/9.prim_async_alert.4181852745 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.362185240 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3633070984 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1172301774 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3039285113 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1488955213 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4188580568 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2561552099 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3841190441 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1588632066 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1735187788 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1404798314 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.287671896 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2615014631 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3031925531 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.988439921 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.1827020458 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.3662697549 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3804192312 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.3389769130 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.2694510850 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.1118608510 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.1735832143 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.1241200731 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.377148972 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.4034498863 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.3289499313 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.161929501 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.2472151293 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.1210204634 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.2044437931 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.3962731740 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.1294144333 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.1764443638 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1732913411 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2847274377 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1733885513 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1686567135 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1628955329 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4187139367 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.549413927 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1568063053 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4121491617 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.230124470 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4104915989 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2448589147 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3272174900 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1608021394 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1376096422 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.717599411 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3486410359 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4059334811 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.327702225 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/10.prim_async_alert.2347818101 | Jul 15 06:13:21 PM PDT 24 | Jul 15 06:13:21 PM PDT 24 | 12447710 ps | ||
| T2 | /workspace/coverage/default/12.prim_async_alert.2187481374 | Jul 15 06:13:17 PM PDT 24 | Jul 15 06:13:18 PM PDT 24 | 11488591 ps | ||
| T3 | /workspace/coverage/default/19.prim_async_alert.557349632 | Jul 15 06:13:29 PM PDT 24 | Jul 15 06:13:30 PM PDT 24 | 11466052 ps | ||
| T7 | /workspace/coverage/default/1.prim_async_alert.2737303985 | Jul 15 06:13:15 PM PDT 24 | Jul 15 06:13:16 PM PDT 24 | 10003227 ps | ||
| T8 | /workspace/coverage/default/6.prim_async_alert.2136197546 | Jul 15 06:13:16 PM PDT 24 | Jul 15 06:13:16 PM PDT 24 | 10998512 ps | ||
| T13 | /workspace/coverage/default/4.prim_async_alert.982193224 | Jul 15 06:13:16 PM PDT 24 | Jul 15 06:13:17 PM PDT 24 | 12188488 ps | ||
| T19 | /workspace/coverage/default/13.prim_async_alert.938488258 | Jul 15 06:13:16 PM PDT 24 | Jul 15 06:13:17 PM PDT 24 | 11444367 ps | ||
| T9 | /workspace/coverage/default/0.prim_async_alert.382764658 | Jul 15 06:13:15 PM PDT 24 | Jul 15 06:13:16 PM PDT 24 | 11316501 ps | ||
| T18 | /workspace/coverage/default/15.prim_async_alert.2362421011 | Jul 15 06:13:18 PM PDT 24 | Jul 15 06:13:19 PM PDT 24 | 10530945 ps | ||
| T10 | /workspace/coverage/default/8.prim_async_alert.2430627472 | Jul 15 06:13:17 PM PDT 24 | Jul 15 06:13:18 PM PDT 24 | 10457193 ps | ||
| T14 | /workspace/coverage/default/16.prim_async_alert.1268986913 | Jul 15 06:13:17 PM PDT 24 | Jul 15 06:13:18 PM PDT 24 | 11320186 ps | ||
| T47 | /workspace/coverage/default/5.prim_async_alert.3658974474 | Jul 15 06:13:17 PM PDT 24 | Jul 15 06:13:18 PM PDT 24 | 11787484 ps | ||
| T16 | /workspace/coverage/default/14.prim_async_alert.551512431 | Jul 15 06:13:18 PM PDT 24 | Jul 15 06:13:19 PM PDT 24 | 11322626 ps | ||
| T20 | /workspace/coverage/default/7.prim_async_alert.340466302 | Jul 15 06:13:16 PM PDT 24 | Jul 15 06:13:17 PM PDT 24 | 12885374 ps | ||
| T21 | /workspace/coverage/default/11.prim_async_alert.1887347696 | Jul 15 06:13:18 PM PDT 24 | Jul 15 06:13:19 PM PDT 24 | 12012141 ps | ||
| T11 | /workspace/coverage/default/3.prim_async_alert.381645196 | Jul 15 06:13:18 PM PDT 24 | Jul 15 06:13:19 PM PDT 24 | 10849839 ps | ||
| T22 | /workspace/coverage/default/18.prim_async_alert.1656913638 | Jul 15 06:13:18 PM PDT 24 | Jul 15 06:13:19 PM PDT 24 | 10777227 ps | ||
| T17 | /workspace/coverage/default/9.prim_async_alert.4181852745 | Jul 15 06:13:20 PM PDT 24 | Jul 15 06:13:21 PM PDT 24 | 10887654 ps | ||
| T15 | /workspace/coverage/default/2.prim_async_alert.3086052960 | Jul 15 06:13:15 PM PDT 24 | Jul 15 06:13:16 PM PDT 24 | 11877860 ps | ||
| T38 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.5688622 | Jul 15 05:32:01 PM PDT 24 | Jul 15 05:32:03 PM PDT 24 | 31024003 ps | ||
| T39 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2615014631 | Jul 15 05:31:55 PM PDT 24 | Jul 15 05:31:57 PM PDT 24 | 29714139 ps | ||
| T4 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2848999520 | Jul 15 05:32:06 PM PDT 24 | Jul 15 05:32:08 PM PDT 24 | 30610843 ps | ||
| T40 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1735187788 | Jul 15 05:32:01 PM PDT 24 | Jul 15 05:32:03 PM PDT 24 | 29364293 ps | ||
| T41 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2561552099 | Jul 15 05:32:02 PM PDT 24 | Jul 15 05:32:04 PM PDT 24 | 29601510 ps | ||
| T42 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4188580568 | Jul 15 05:32:04 PM PDT 24 | Jul 15 05:32:06 PM PDT 24 | 28999123 ps | ||
| T43 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1404798314 | Jul 15 05:31:57 PM PDT 24 | Jul 15 05:31:58 PM PDT 24 | 30941616 ps | ||
| T44 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1172301774 | Jul 15 05:32:01 PM PDT 24 | Jul 15 05:32:03 PM PDT 24 | 30455272 ps | ||
| T45 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.362185240 | Jul 15 05:31:56 PM PDT 24 | Jul 15 05:31:57 PM PDT 24 | 29227095 ps | ||
| T46 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.287671896 | Jul 15 05:31:58 PM PDT 24 | Jul 15 05:32:00 PM PDT 24 | 29732603 ps | ||
| T48 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1588632066 | Jul 15 05:31:57 PM PDT 24 | Jul 15 05:31:59 PM PDT 24 | 29117762 ps | ||
| T49 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3633070984 | Jul 15 05:31:57 PM PDT 24 | Jul 15 05:31:59 PM PDT 24 | 29891163 ps | ||
| T50 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1488955213 | Jul 15 05:32:01 PM PDT 24 | Jul 15 05:32:02 PM PDT 24 | 29422337 ps | ||
| T51 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3841190441 | Jul 15 05:32:00 PM PDT 24 | Jul 15 05:32:01 PM PDT 24 | 30735335 ps | ||
| T52 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3039285113 | Jul 15 05:32:00 PM PDT 24 | Jul 15 05:32:02 PM PDT 24 | 32336351 ps | ||
| T53 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3031925531 | Jul 15 05:32:03 PM PDT 24 | Jul 15 05:32:05 PM PDT 24 | 30019694 ps | ||
| T32 | /workspace/coverage/sync_alert/7.prim_sync_alert.3962731740 | Jul 15 06:13:25 PM PDT 24 | Jul 15 06:13:26 PM PDT 24 | 10089672 ps | ||
| T33 | /workspace/coverage/sync_alert/5.prim_sync_alert.1210204634 | Jul 15 06:13:29 PM PDT 24 | Jul 15 06:13:30 PM PDT 24 | 8959404 ps | ||
| T23 | /workspace/coverage/sync_alert/1.prim_sync_alert.3941625820 | Jul 15 06:13:24 PM PDT 24 | Jul 15 06:13:25 PM PDT 24 | 9581926 ps | ||
| T34 | /workspace/coverage/sync_alert/10.prim_sync_alert.1827020458 | Jul 15 06:13:28 PM PDT 24 | Jul 15 06:13:30 PM PDT 24 | 9852156 ps | ||
| T24 | /workspace/coverage/sync_alert/13.prim_sync_alert.3389769130 | Jul 15 06:13:23 PM PDT 24 | Jul 15 06:13:24 PM PDT 24 | 10140742 ps | ||
| T25 | /workspace/coverage/sync_alert/12.prim_sync_alert.3804192312 | Jul 15 06:13:27 PM PDT 24 | Jul 15 06:13:28 PM PDT 24 | 8533152 ps | ||
| T35 | /workspace/coverage/sync_alert/8.prim_sync_alert.1294144333 | Jul 15 06:13:27 PM PDT 24 | Jul 15 06:13:28 PM PDT 24 | 9090030 ps | ||
| T26 | /workspace/coverage/sync_alert/2.prim_sync_alert.3289499313 | Jul 15 06:13:26 PM PDT 24 | Jul 15 06:13:28 PM PDT 24 | 8814357 ps | ||
| T36 | /workspace/coverage/sync_alert/9.prim_sync_alert.1764443638 | Jul 15 06:13:26 PM PDT 24 | Jul 15 06:13:27 PM PDT 24 | 9755852 ps | ||
| T37 | /workspace/coverage/sync_alert/6.prim_sync_alert.2044437931 | Jul 15 06:13:25 PM PDT 24 | Jul 15 06:13:27 PM PDT 24 | 9331894 ps | ||
| T27 | /workspace/coverage/sync_alert/18.prim_sync_alert.377148972 | Jul 15 06:13:28 PM PDT 24 | Jul 15 06:13:29 PM PDT 24 | 9976034 ps | ||
| T28 | /workspace/coverage/sync_alert/11.prim_sync_alert.3662697549 | Jul 15 06:13:27 PM PDT 24 | Jul 15 06:13:28 PM PDT 24 | 8912718 ps | ||
| T54 | /workspace/coverage/sync_alert/0.prim_sync_alert.988439921 | Jul 15 06:13:27 PM PDT 24 | Jul 15 06:13:28 PM PDT 24 | 8638949 ps | ||
| T29 | /workspace/coverage/sync_alert/3.prim_sync_alert.161929501 | Jul 15 06:13:27 PM PDT 24 | Jul 15 06:13:28 PM PDT 24 | 9875821 ps | ||
| T30 | /workspace/coverage/sync_alert/14.prim_sync_alert.2694510850 | Jul 15 06:13:25 PM PDT 24 | Jul 15 06:13:27 PM PDT 24 | 8987064 ps | ||
| T31 | /workspace/coverage/sync_alert/15.prim_sync_alert.1118608510 | Jul 15 06:13:28 PM PDT 24 | Jul 15 06:13:29 PM PDT 24 | 8961756 ps | ||
| T55 | /workspace/coverage/sync_alert/4.prim_sync_alert.2472151293 | Jul 15 06:13:27 PM PDT 24 | Jul 15 06:13:29 PM PDT 24 | 8605731 ps | ||
| T56 | /workspace/coverage/sync_alert/17.prim_sync_alert.1241200731 | Jul 15 06:13:27 PM PDT 24 | Jul 15 06:13:28 PM PDT 24 | 8722329 ps | ||
| T57 | /workspace/coverage/sync_alert/19.prim_sync_alert.4034498863 | Jul 15 06:13:26 PM PDT 24 | Jul 15 06:13:27 PM PDT 24 | 10266374 ps | ||
| T58 | /workspace/coverage/sync_alert/16.prim_sync_alert.1735832143 | Jul 15 06:13:26 PM PDT 24 | Jul 15 06:13:27 PM PDT 24 | 9084584 ps | ||
| T59 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1732913411 | Jul 15 06:13:24 PM PDT 24 | Jul 15 06:13:25 PM PDT 24 | 27509766 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1628955329 | Jul 15 06:13:29 PM PDT 24 | Jul 15 06:13:30 PM PDT 24 | 25765132 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2847274377 | Jul 15 06:13:22 PM PDT 24 | Jul 15 06:13:23 PM PDT 24 | 26695700 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2448589147 | Jul 15 06:13:26 PM PDT 24 | Jul 15 06:13:27 PM PDT 24 | 28692478 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1376096422 | Jul 15 06:13:24 PM PDT 24 | Jul 15 06:13:25 PM PDT 24 | 26767800 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3272174900 | Jul 15 06:13:27 PM PDT 24 | Jul 15 06:13:28 PM PDT 24 | 27796861 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.230124470 | Jul 15 06:13:28 PM PDT 24 | Jul 15 06:13:29 PM PDT 24 | 27387798 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4187139367 | Jul 15 06:13:25 PM PDT 24 | Jul 15 06:13:26 PM PDT 24 | 25924813 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.327702225 | Jul 15 06:13:22 PM PDT 24 | Jul 15 06:13:24 PM PDT 24 | 26806210 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3486410359 | Jul 15 06:13:26 PM PDT 24 | Jul 15 06:13:27 PM PDT 24 | 25452148 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4104915989 | Jul 15 06:13:24 PM PDT 24 | Jul 15 06:13:26 PM PDT 24 | 27373361 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1568063053 | Jul 15 06:13:28 PM PDT 24 | Jul 15 06:13:30 PM PDT 24 | 25750437 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1733885513 | Jul 15 06:13:26 PM PDT 24 | Jul 15 06:13:27 PM PDT 24 | 26561201 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1686567135 | Jul 15 06:13:23 PM PDT 24 | Jul 15 06:13:24 PM PDT 24 | 27400794 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1608021394 | Jul 15 06:13:24 PM PDT 24 | Jul 15 06:13:25 PM PDT 24 | 28621483 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.717599411 | Jul 15 06:13:28 PM PDT 24 | Jul 15 06:13:30 PM PDT 24 | 29049216 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4121491617 | Jul 15 06:13:25 PM PDT 24 | Jul 15 06:13:26 PM PDT 24 | 29743968 ps | ||
| T12 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2348135003 | Jul 15 06:13:25 PM PDT 24 | Jul 15 06:13:27 PM PDT 24 | 29226497 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.549413927 | Jul 15 06:13:22 PM PDT 24 | Jul 15 06:13:24 PM PDT 24 | 26963580 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4059334811 | Jul 15 06:13:26 PM PDT 24 | Jul 15 06:13:27 PM PDT 24 | 27300995 ps |
| Test location | /workspace/coverage/default/10.prim_async_alert.2347818101 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12447710 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:21 PM PDT 24 |
| Finished | Jul 15 06:13:21 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-5e2f3ed1-7627-435c-8990-733ca2996a86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2347818101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2347818101 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.3941625820 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9581926 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:24 PM PDT 24 |
| Finished | Jul 15 06:13:25 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-ab50b8da-9da8-4124-8b6c-4e283183ec0b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3941625820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3941625820 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.5688622 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 31024003 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 05:32:01 PM PDT 24 |
| Finished | Jul 15 05:32:03 PM PDT 24 |
| Peak memory | 145272 kb |
| Host | smart-ac54a3af-e1c6-4715-a29c-cb07446b05b9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=5688622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.5688622 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2848999520 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30610843 ps |
| CPU time | 0.41 seconds |
| Started | Jul 15 05:32:06 PM PDT 24 |
| Finished | Jul 15 05:32:08 PM PDT 24 |
| Peak memory | 145268 kb |
| Host | smart-5e54fd9b-572a-4e4f-add9-a12737353730 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2848999520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2848999520 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2348135003 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 29226497 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:25 PM PDT 24 |
| Finished | Jul 15 06:13:27 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-f413ddc6-5ea1-4f77-b8c0-d547849fefe3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2348135003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2348135003 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.382764658 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11316501 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 06:13:15 PM PDT 24 |
| Finished | Jul 15 06:13:16 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-68955cdd-0959-4565-9f09-49900226055b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=382764658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.382764658 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.2737303985 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10003227 ps |
| CPU time | 0.39 seconds |
| Started | Jul 15 06:13:15 PM PDT 24 |
| Finished | Jul 15 06:13:16 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-9cae0083-1ba6-42c7-aee9-984e1373ed22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737303985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2737303985 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.1887347696 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12012141 ps |
| CPU time | 0.43 seconds |
| Started | Jul 15 06:13:18 PM PDT 24 |
| Finished | Jul 15 06:13:19 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-9312f081-de2d-44f2-94de-045a46919a1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1887347696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1887347696 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.2187481374 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11488591 ps |
| CPU time | 0.39 seconds |
| Started | Jul 15 06:13:17 PM PDT 24 |
| Finished | Jul 15 06:13:18 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-a3104259-572a-45da-bc55-0b01ee5ab9e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2187481374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2187481374 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.938488258 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11444367 ps |
| CPU time | 0.39 seconds |
| Started | Jul 15 06:13:16 PM PDT 24 |
| Finished | Jul 15 06:13:17 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-ca08655c-139d-4ece-b963-84daedea666a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938488258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.938488258 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.551512431 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11322626 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:18 PM PDT 24 |
| Finished | Jul 15 06:13:19 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-1d6b9833-af2c-46b6-a962-8b120e05b692 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551512431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.551512431 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.2362421011 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10530945 ps |
| CPU time | 0.39 seconds |
| Started | Jul 15 06:13:18 PM PDT 24 |
| Finished | Jul 15 06:13:19 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-42816fce-5ef6-4960-a5ab-1eda94701ad5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362421011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2362421011 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.1268986913 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11320186 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:17 PM PDT 24 |
| Finished | Jul 15 06:13:18 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-793bc6c3-610d-439f-9f84-0ea7e91690ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268986913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1268986913 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.1656913638 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10777227 ps |
| CPU time | 0.43 seconds |
| Started | Jul 15 06:13:18 PM PDT 24 |
| Finished | Jul 15 06:13:19 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-ffa1ad70-d64a-4c3e-a2cb-fd2f528a6a0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1656913638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1656913638 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.557349632 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11466052 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:29 PM PDT 24 |
| Finished | Jul 15 06:13:30 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-75db428b-0761-491e-875a-2ed98a685a80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=557349632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.557349632 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3086052960 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11877860 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:15 PM PDT 24 |
| Finished | Jul 15 06:13:16 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-3c68eaf2-85ea-490c-a5d0-6e507300d602 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3086052960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3086052960 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.381645196 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10849839 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:18 PM PDT 24 |
| Finished | Jul 15 06:13:19 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-b5150c4e-fdc9-4b16-bd88-dc619e6d90de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=381645196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.381645196 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.982193224 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12188488 ps |
| CPU time | 0.39 seconds |
| Started | Jul 15 06:13:16 PM PDT 24 |
| Finished | Jul 15 06:13:17 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-a94b91af-49a7-4cc0-b4ee-3969ee39c60e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=982193224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.982193224 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3658974474 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11787484 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:17 PM PDT 24 |
| Finished | Jul 15 06:13:18 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-7715e9dc-756e-4caf-a1ad-73d836284496 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3658974474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3658974474 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2136197546 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10998512 ps |
| CPU time | 0.43 seconds |
| Started | Jul 15 06:13:16 PM PDT 24 |
| Finished | Jul 15 06:13:16 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-4cdd4459-003f-4a22-b434-d801b3b50c2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136197546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2136197546 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.340466302 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12885374 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 06:13:16 PM PDT 24 |
| Finished | Jul 15 06:13:17 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-b4915d3a-b003-4cf7-bf9c-8f56cbaed920 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340466302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.340466302 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.2430627472 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10457193 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:17 PM PDT 24 |
| Finished | Jul 15 06:13:18 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-28d5b65c-242a-45f8-b12d-0b42adb692a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2430627472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2430627472 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.4181852745 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10887654 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:20 PM PDT 24 |
| Finished | Jul 15 06:13:21 PM PDT 24 |
| Peak memory | 145748 kb |
| Host | smart-563e6c7d-0c00-4371-ae4e-c5691cfc2ac0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4181852745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.4181852745 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.362185240 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29227095 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 05:31:56 PM PDT 24 |
| Finished | Jul 15 05:31:57 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-cdb28348-e3c4-41d5-9528-b398f03f73b2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=362185240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.362185240 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3633070984 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29891163 ps |
| CPU time | 0.45 seconds |
| Started | Jul 15 05:31:57 PM PDT 24 |
| Finished | Jul 15 05:31:59 PM PDT 24 |
| Peak memory | 145364 kb |
| Host | smart-cf4538fd-d9a3-4e50-aff8-5ae3c48eaa81 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3633070984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3633070984 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1172301774 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30455272 ps |
| CPU time | 0.41 seconds |
| Started | Jul 15 05:32:01 PM PDT 24 |
| Finished | Jul 15 05:32:03 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-c7dcef7d-20eb-4938-9e93-ee34a136ab6a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1172301774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1172301774 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3039285113 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 32336351 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 05:32:00 PM PDT 24 |
| Finished | Jul 15 05:32:02 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-1e4cecac-c79d-4d53-8115-11303010531e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3039285113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3039285113 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1488955213 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 29422337 ps |
| CPU time | 0.45 seconds |
| Started | Jul 15 05:32:01 PM PDT 24 |
| Finished | Jul 15 05:32:02 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-527cd07e-0e4a-4d37-b8e9-08ebdfdf7317 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1488955213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1488955213 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4188580568 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 28999123 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 05:32:04 PM PDT 24 |
| Finished | Jul 15 05:32:06 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-eb8a4496-8d12-4980-b516-efd7f30a71cc |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4188580568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.4188580568 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2561552099 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29601510 ps |
| CPU time | 0.39 seconds |
| Started | Jul 15 05:32:02 PM PDT 24 |
| Finished | Jul 15 05:32:04 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-696614f0-b830-48e0-a75e-73051d55b5ff |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2561552099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2561552099 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3841190441 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30735335 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 05:32:00 PM PDT 24 |
| Finished | Jul 15 05:32:01 PM PDT 24 |
| Peak memory | 145292 kb |
| Host | smart-59470456-09ef-45c2-8016-2be9863b5277 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3841190441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3841190441 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1588632066 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 29117762 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 05:31:57 PM PDT 24 |
| Finished | Jul 15 05:31:59 PM PDT 24 |
| Peak memory | 145272 kb |
| Host | smart-c343df41-c17f-4322-9344-bdeaa724c0c5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1588632066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1588632066 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1735187788 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29364293 ps |
| CPU time | 0.44 seconds |
| Started | Jul 15 05:32:01 PM PDT 24 |
| Finished | Jul 15 05:32:03 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-0d57b1cf-3747-4516-be53-bbd667b87eaa |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1735187788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1735187788 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1404798314 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30941616 ps |
| CPU time | 0.41 seconds |
| Started | Jul 15 05:31:57 PM PDT 24 |
| Finished | Jul 15 05:31:58 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-fd9d9f16-0fd9-4ea8-a8db-122bfbdee4f5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1404798314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1404798314 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.287671896 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29732603 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 05:31:58 PM PDT 24 |
| Finished | Jul 15 05:32:00 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-167bb2fa-aa64-4a6c-ab91-cb086629c4c5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=287671896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.287671896 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2615014631 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 29714139 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 05:31:55 PM PDT 24 |
| Finished | Jul 15 05:31:57 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-1cd48a2d-7855-4e33-adff-4ab8a56cbdbd |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2615014631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2615014631 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3031925531 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30019694 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 05:32:03 PM PDT 24 |
| Finished | Jul 15 05:32:05 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-a94cb971-f0c8-44c5-a5e0-85f2ba937170 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3031925531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3031925531 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.988439921 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 8638949 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:27 PM PDT 24 |
| Finished | Jul 15 06:13:28 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-db8f4d93-3604-442f-b5c9-ac6eb44f2b76 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=988439921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.988439921 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.1827020458 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9852156 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:28 PM PDT 24 |
| Finished | Jul 15 06:13:30 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-23f9e84c-f788-4979-b38b-f95c28ffa8ee |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1827020458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1827020458 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.3662697549 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8912718 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:27 PM PDT 24 |
| Finished | Jul 15 06:13:28 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-a984344c-ccc5-47ba-b020-a703e1395dee |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3662697549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3662697549 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3804192312 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8533152 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 06:13:27 PM PDT 24 |
| Finished | Jul 15 06:13:28 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-9233abb4-6141-46ba-a57e-99b431708a9f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3804192312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3804192312 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.3389769130 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10140742 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:23 PM PDT 24 |
| Finished | Jul 15 06:13:24 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-043e9cb5-9ed8-47ce-936a-bfa1f303cc42 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3389769130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3389769130 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.2694510850 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8987064 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:25 PM PDT 24 |
| Finished | Jul 15 06:13:27 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-dc974858-b0f3-4ada-8fb7-e27b6e79755e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2694510850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2694510850 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.1118608510 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8961756 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:28 PM PDT 24 |
| Finished | Jul 15 06:13:29 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-38ccc8be-abf5-4423-934c-244837c940dd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1118608510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1118608510 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.1735832143 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9084584 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:26 PM PDT 24 |
| Finished | Jul 15 06:13:27 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-5607a682-1a28-4859-8343-636a4ec56fec |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1735832143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1735832143 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.1241200731 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8722329 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:27 PM PDT 24 |
| Finished | Jul 15 06:13:28 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-4a9a6c38-e5a2-4dd8-be47-275036900d8c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1241200731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1241200731 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.377148972 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9976034 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:28 PM PDT 24 |
| Finished | Jul 15 06:13:29 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-5557cc55-9a8a-41dc-9216-6e99cd237fe7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=377148972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.377148972 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.4034498863 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 10266374 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 06:13:26 PM PDT 24 |
| Finished | Jul 15 06:13:27 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-b5016fab-69ac-41bc-8d08-aab3c50de47b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4034498863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.4034498863 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.3289499313 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8814357 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:26 PM PDT 24 |
| Finished | Jul 15 06:13:28 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-847e0235-098f-4d05-9147-1a94a41b49b9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3289499313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3289499313 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.161929501 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9875821 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:27 PM PDT 24 |
| Finished | Jul 15 06:13:28 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-857eb124-26bd-423d-89b5-8933cc37cf1a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=161929501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.161929501 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.2472151293 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 8605731 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:27 PM PDT 24 |
| Finished | Jul 15 06:13:29 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-d9c8d856-484d-4a91-8522-936ef5e5bc1e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2472151293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2472151293 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1210204634 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8959404 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:29 PM PDT 24 |
| Finished | Jul 15 06:13:30 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-49f68f09-8306-43bd-8aa7-34e2f7aba0b1 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1210204634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1210204634 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.2044437931 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9331894 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:25 PM PDT 24 |
| Finished | Jul 15 06:13:27 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-13a24507-ba6a-4b9d-a556-9514679e1ab5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2044437931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2044437931 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.3962731740 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10089672 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 06:13:25 PM PDT 24 |
| Finished | Jul 15 06:13:26 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-33b5646d-007d-463b-ac62-6a3cf683c241 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3962731740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3962731740 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.1294144333 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9090030 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:27 PM PDT 24 |
| Finished | Jul 15 06:13:28 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-6a78c4de-3bce-4ab5-bde0-e211767aa203 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1294144333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1294144333 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.1764443638 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9755852 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:26 PM PDT 24 |
| Finished | Jul 15 06:13:27 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-c441dfd4-8c25-4418-8528-2901682cb6c3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1764443638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1764443638 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1732913411 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 27509766 ps |
| CPU time | 0.42 seconds |
| Started | Jul 15 06:13:24 PM PDT 24 |
| Finished | Jul 15 06:13:25 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-e539e36c-43c6-4480-b36f-7e599535e9d0 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1732913411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1732913411 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2847274377 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 26695700 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:22 PM PDT 24 |
| Finished | Jul 15 06:13:23 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-98234577-0559-4d7a-a32e-b68242443be8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2847274377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2847274377 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1733885513 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 26561201 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:26 PM PDT 24 |
| Finished | Jul 15 06:13:27 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-51add166-f85f-44df-8081-66aad17c8ce0 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1733885513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1733885513 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1686567135 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27400794 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 06:13:23 PM PDT 24 |
| Finished | Jul 15 06:13:24 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-6214706a-eb64-45d8-b7a0-3e2642a61690 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1686567135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1686567135 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1628955329 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 25765132 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:29 PM PDT 24 |
| Finished | Jul 15 06:13:30 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-bcb5ce55-e845-4114-b647-95ad619faabc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1628955329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1628955329 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4187139367 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 25924813 ps |
| CPU time | 0.39 seconds |
| Started | Jul 15 06:13:25 PM PDT 24 |
| Finished | Jul 15 06:13:26 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-d9d52975-58e2-4ff8-b569-55e2f5e79296 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4187139367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.4187139367 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.549413927 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26963580 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:22 PM PDT 24 |
| Finished | Jul 15 06:13:24 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-30440d35-a224-4cb7-89a6-19dfab3a68df |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=549413927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.549413927 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1568063053 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 25750437 ps |
| CPU time | 0.44 seconds |
| Started | Jul 15 06:13:28 PM PDT 24 |
| Finished | Jul 15 06:13:30 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-6da8c6c7-b051-421e-be55-fe46eaff34da |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1568063053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1568063053 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4121491617 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 29743968 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 06:13:25 PM PDT 24 |
| Finished | Jul 15 06:13:26 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-5a5d19ab-5be1-4495-a8c3-7dd0dbf40d54 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4121491617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.4121491617 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.230124470 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27387798 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:28 PM PDT 24 |
| Finished | Jul 15 06:13:29 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-7281a41c-839d-450b-aecc-9151466581e4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=230124470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.230124470 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4104915989 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27373361 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:24 PM PDT 24 |
| Finished | Jul 15 06:13:26 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-ad59b22f-200f-42bd-88aa-e4c1588bf8e1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4104915989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.4104915989 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2448589147 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 28692478 ps |
| CPU time | 0.39 seconds |
| Started | Jul 15 06:13:26 PM PDT 24 |
| Finished | Jul 15 06:13:27 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-23053c4b-d750-4e8d-ab2a-a960cc0f2142 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2448589147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2448589147 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3272174900 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27796861 ps |
| CPU time | 0.41 seconds |
| Started | Jul 15 06:13:27 PM PDT 24 |
| Finished | Jul 15 06:13:28 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-ffedeaa6-6f46-4e1d-8939-9905fc4eeb18 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3272174900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3272174900 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1608021394 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 28621483 ps |
| CPU time | 0.39 seconds |
| Started | Jul 15 06:13:24 PM PDT 24 |
| Finished | Jul 15 06:13:25 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-8aca82a1-d6a8-4cf5-9ded-171e00651a72 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1608021394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1608021394 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1376096422 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 26767800 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:24 PM PDT 24 |
| Finished | Jul 15 06:13:25 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-a0edbe92-0a63-445c-b97b-a33d610b6cc9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1376096422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1376096422 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.717599411 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 29049216 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 06:13:28 PM PDT 24 |
| Finished | Jul 15 06:13:30 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-9fd62c1f-8f88-4f9b-9290-3e88bc1fcc12 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=717599411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.717599411 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3486410359 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 25452148 ps |
| CPU time | 0.39 seconds |
| Started | Jul 15 06:13:26 PM PDT 24 |
| Finished | Jul 15 06:13:27 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-4f5ca7e9-d1b8-40a3-b630-6f36be205e93 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3486410359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3486410359 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4059334811 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27300995 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 06:13:26 PM PDT 24 |
| Finished | Jul 15 06:13:27 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-9cb009bb-f79c-4cce-a2ae-b1aecede625d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4059334811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.4059334811 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.327702225 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 26806210 ps |
| CPU time | 0.48 seconds |
| Started | Jul 15 06:13:22 PM PDT 24 |
| Finished | Jul 15 06:13:24 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-45325ab5-b745-44d7-b3fb-39f1d72e41a9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=327702225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.327702225 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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