Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 77
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.42 88.42 100.00 100.00 95.83 95.83 96.43 96.43 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/2.prim_async_alert.565080516
91.55 3.13 100.00 0.00 95.83 0.00 96.43 0.00 82.14 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/17.prim_sync_alert.3316071464
94.25 2.70 100.00 0.00 97.92 2.08 100.00 3.57 85.71 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.193391288
94.85 0.60 100.00 0.00 97.92 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/13.prim_async_alert.1475218557
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1646727521

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.43702429
/workspace/coverage/default/1.prim_async_alert.1076716875
/workspace/coverage/default/10.prim_async_alert.1658946819
/workspace/coverage/default/11.prim_async_alert.3259646128
/workspace/coverage/default/12.prim_async_alert.1943498848
/workspace/coverage/default/14.prim_async_alert.4165017230
/workspace/coverage/default/15.prim_async_alert.1679069922
/workspace/coverage/default/16.prim_async_alert.702536339
/workspace/coverage/default/17.prim_async_alert.3662019553
/workspace/coverage/default/18.prim_async_alert.2616857030
/workspace/coverage/default/19.prim_async_alert.1075414824
/workspace/coverage/default/3.prim_async_alert.2259222214
/workspace/coverage/default/4.prim_async_alert.1611816131
/workspace/coverage/default/5.prim_async_alert.2904315474
/workspace/coverage/default/6.prim_async_alert.1902165887
/workspace/coverage/default/7.prim_async_alert.1348288595
/workspace/coverage/default/8.prim_async_alert.2876716024
/workspace/coverage/default/9.prim_async_alert.722356861
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3593063594
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3601459674
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1821253248
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3534431534
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2440422482
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.731687003
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.585705693
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3190396148
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.840458542
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3589778178
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3659499967
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2586108767
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1107830147
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2217560926
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2167929083
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3811325295
/workspace/coverage/sync_alert/0.prim_sync_alert.668431898
/workspace/coverage/sync_alert/1.prim_sync_alert.2976441288
/workspace/coverage/sync_alert/10.prim_sync_alert.370579029
/workspace/coverage/sync_alert/11.prim_sync_alert.2657617687
/workspace/coverage/sync_alert/12.prim_sync_alert.2593160201
/workspace/coverage/sync_alert/13.prim_sync_alert.3617386153
/workspace/coverage/sync_alert/14.prim_sync_alert.154169642
/workspace/coverage/sync_alert/15.prim_sync_alert.1970100204
/workspace/coverage/sync_alert/16.prim_sync_alert.3830579360
/workspace/coverage/sync_alert/18.prim_sync_alert.1188947360
/workspace/coverage/sync_alert/19.prim_sync_alert.3146078893
/workspace/coverage/sync_alert/2.prim_sync_alert.225408502
/workspace/coverage/sync_alert/3.prim_sync_alert.18964161
/workspace/coverage/sync_alert/4.prim_sync_alert.3995115333
/workspace/coverage/sync_alert/5.prim_sync_alert.2845199724
/workspace/coverage/sync_alert/6.prim_sync_alert.2112781646
/workspace/coverage/sync_alert/7.prim_sync_alert.770012605
/workspace/coverage/sync_alert/8.prim_sync_alert.612420171
/workspace/coverage/sync_alert/9.prim_sync_alert.2174415423
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1972660296
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.331298868
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.791954375
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.20014350
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3616321004
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1992626549
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1147657963
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3387939518
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1150228407
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2579291445
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1621283899
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2881502323
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.998379283
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2478884803
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2011545238
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1820634325
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4203416962
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3732511183
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2734572212



Total test records in report: 77
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/19.prim_async_alert.1075414824 Jul 16 04:34:33 PM PDT 24 Jul 16 04:34:33 PM PDT 24 10967794 ps
T2 /workspace/coverage/default/8.prim_async_alert.2876716024 Jul 16 04:34:33 PM PDT 24 Jul 16 04:34:34 PM PDT 24 10692995 ps
T3 /workspace/coverage/default/9.prim_async_alert.722356861 Jul 16 04:34:34 PM PDT 24 Jul 16 04:34:35 PM PDT 24 11575891 ps
T7 /workspace/coverage/default/17.prim_async_alert.3662019553 Jul 16 04:34:37 PM PDT 24 Jul 16 04:34:38 PM PDT 24 10258031 ps
T10 /workspace/coverage/default/15.prim_async_alert.1679069922 Jul 16 04:34:23 PM PDT 24 Jul 16 04:34:24 PM PDT 24 10422585 ps
T14 /workspace/coverage/default/4.prim_async_alert.1611816131 Jul 16 04:34:35 PM PDT 24 Jul 16 04:34:37 PM PDT 24 10778869 ps
T8 /workspace/coverage/default/2.prim_async_alert.565080516 Jul 16 04:34:28 PM PDT 24 Jul 16 04:34:29 PM PDT 24 10769328 ps
T19 /workspace/coverage/default/6.prim_async_alert.1902165887 Jul 16 04:35:33 PM PDT 24 Jul 16 04:35:34 PM PDT 24 11074600 ps
T20 /workspace/coverage/default/1.prim_async_alert.1076716875 Jul 16 04:34:34 PM PDT 24 Jul 16 04:34:35 PM PDT 24 11416416 ps
T21 /workspace/coverage/default/5.prim_async_alert.2904315474 Jul 16 04:34:35 PM PDT 24 Jul 16 04:34:37 PM PDT 24 10133436 ps
T9 /workspace/coverage/default/10.prim_async_alert.1658946819 Jul 16 04:34:27 PM PDT 24 Jul 16 04:34:28 PM PDT 24 12057148 ps
T13 /workspace/coverage/default/12.prim_async_alert.1943498848 Jul 16 04:34:31 PM PDT 24 Jul 16 04:34:32 PM PDT 24 11839659 ps
T16 /workspace/coverage/default/13.prim_async_alert.1475218557 Jul 16 04:34:21 PM PDT 24 Jul 16 04:34:23 PM PDT 24 11365705 ps
T22 /workspace/coverage/default/16.prim_async_alert.702536339 Jul 16 04:35:42 PM PDT 24 Jul 16 04:35:43 PM PDT 24 11052968 ps
T23 /workspace/coverage/default/18.prim_async_alert.2616857030 Jul 16 04:34:32 PM PDT 24 Jul 16 04:34:33 PM PDT 24 11407789 ps
T46 /workspace/coverage/default/14.prim_async_alert.4165017230 Jul 16 04:34:35 PM PDT 24 Jul 16 04:34:37 PM PDT 24 10343801 ps
T47 /workspace/coverage/default/3.prim_async_alert.2259222214 Jul 16 04:34:27 PM PDT 24 Jul 16 04:34:28 PM PDT 24 10775947 ps
T15 /workspace/coverage/default/0.prim_async_alert.43702429 Jul 16 04:34:24 PM PDT 24 Jul 16 04:34:25 PM PDT 24 12885033 ps
T48 /workspace/coverage/default/7.prim_async_alert.1348288595 Jul 16 04:34:35 PM PDT 24 Jul 16 04:34:37 PM PDT 24 10866343 ps
T38 /workspace/coverage/default/11.prim_async_alert.3259646128 Jul 16 04:34:34 PM PDT 24 Jul 16 04:34:35 PM PDT 24 11070372 ps
T39 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2440422482 Jul 16 04:34:35 PM PDT 24 Jul 16 04:34:37 PM PDT 24 28156282 ps
T4 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2167929083 Jul 16 04:34:29 PM PDT 24 Jul 16 04:34:30 PM PDT 24 28694070 ps
T5 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.193391288 Jul 16 04:34:34 PM PDT 24 Jul 16 04:34:35 PM PDT 24 30166794 ps
T40 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.585705693 Jul 16 04:35:50 PM PDT 24 Jul 16 04:35:50 PM PDT 24 31268572 ps
T41 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3190396148 Jul 16 04:34:34 PM PDT 24 Jul 16 04:34:35 PM PDT 24 32013441 ps
T42 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3601459674 Jul 16 04:34:35 PM PDT 24 Jul 16 04:34:37 PM PDT 24 30487417 ps
T43 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3811325295 Jul 16 04:34:27 PM PDT 24 Jul 16 04:34:27 PM PDT 24 29264728 ps
T44 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3534431534 Jul 16 04:34:21 PM PDT 24 Jul 16 04:34:23 PM PDT 24 30383838 ps
T17 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1821253248 Jul 16 04:34:33 PM PDT 24 Jul 16 04:34:34 PM PDT 24 30214153 ps
T45 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.731687003 Jul 16 04:35:42 PM PDT 24 Jul 16 04:35:43 PM PDT 24 30037478 ps
T49 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.840458542 Jul 16 04:34:32 PM PDT 24 Jul 16 04:34:33 PM PDT 24 31143027 ps
T50 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1107830147 Jul 16 04:35:41 PM PDT 24 Jul 16 04:35:42 PM PDT 24 29555997 ps
T51 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3659499967 Jul 16 04:34:34 PM PDT 24 Jul 16 04:34:36 PM PDT 24 30149049 ps
T52 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2217560926 Jul 16 04:34:37 PM PDT 24 Jul 16 04:34:38 PM PDT 24 29768188 ps
T53 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3593063594 Jul 16 04:34:33 PM PDT 24 Jul 16 04:34:35 PM PDT 24 31494341 ps
T18 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3589778178 Jul 16 04:35:42 PM PDT 24 Jul 16 04:35:43 PM PDT 24 29702103 ps
T54 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2586108767 Jul 16 04:34:34 PM PDT 24 Jul 16 04:34:35 PM PDT 24 28815409 ps
T24 /workspace/coverage/sync_alert/1.prim_sync_alert.2976441288 Jul 16 05:07:31 PM PDT 24 Jul 16 05:07:32 PM PDT 24 8969976 ps
T25 /workspace/coverage/sync_alert/14.prim_sync_alert.154169642 Jul 16 05:07:42 PM PDT 24 Jul 16 05:07:43 PM PDT 24 9319083 ps
T26 /workspace/coverage/sync_alert/19.prim_sync_alert.3146078893 Jul 16 05:07:45 PM PDT 24 Jul 16 05:07:45 PM PDT 24 9094728 ps
T34 /workspace/coverage/sync_alert/10.prim_sync_alert.370579029 Jul 16 05:07:43 PM PDT 24 Jul 16 05:07:43 PM PDT 24 9296569 ps
T35 /workspace/coverage/sync_alert/17.prim_sync_alert.3316071464 Jul 16 05:07:37 PM PDT 24 Jul 16 05:07:38 PM PDT 24 9778447 ps
T27 /workspace/coverage/sync_alert/7.prim_sync_alert.770012605 Jul 16 05:07:34 PM PDT 24 Jul 16 05:07:34 PM PDT 24 8705360 ps
T28 /workspace/coverage/sync_alert/18.prim_sync_alert.1188947360 Jul 16 05:07:38 PM PDT 24 Jul 16 05:07:39 PM PDT 24 9609900 ps
T36 /workspace/coverage/sync_alert/12.prim_sync_alert.2593160201 Jul 16 05:07:41 PM PDT 24 Jul 16 05:07:42 PM PDT 24 9971865 ps
T29 /workspace/coverage/sync_alert/9.prim_sync_alert.2174415423 Jul 16 05:07:37 PM PDT 24 Jul 16 05:07:38 PM PDT 24 9194569 ps
T37 /workspace/coverage/sync_alert/5.prim_sync_alert.2845199724 Jul 16 05:07:30 PM PDT 24 Jul 16 05:07:30 PM PDT 24 8827279 ps
T30 /workspace/coverage/sync_alert/0.prim_sync_alert.668431898 Jul 16 05:07:45 PM PDT 24 Jul 16 05:07:45 PM PDT 24 8982135 ps
T55 /workspace/coverage/sync_alert/11.prim_sync_alert.2657617687 Jul 16 05:07:31 PM PDT 24 Jul 16 05:07:31 PM PDT 24 9050916 ps
T31 /workspace/coverage/sync_alert/2.prim_sync_alert.225408502 Jul 16 05:07:42 PM PDT 24 Jul 16 05:07:43 PM PDT 24 10747727 ps
T56 /workspace/coverage/sync_alert/8.prim_sync_alert.612420171 Jul 16 05:07:50 PM PDT 24 Jul 16 05:07:51 PM PDT 24 8903498 ps
T32 /workspace/coverage/sync_alert/15.prim_sync_alert.1970100204 Jul 16 05:07:49 PM PDT 24 Jul 16 05:07:50 PM PDT 24 9130166 ps
T33 /workspace/coverage/sync_alert/3.prim_sync_alert.18964161 Jul 16 05:07:36 PM PDT 24 Jul 16 05:07:37 PM PDT 24 9028208 ps
T57 /workspace/coverage/sync_alert/6.prim_sync_alert.2112781646 Jul 16 05:07:29 PM PDT 24 Jul 16 05:07:30 PM PDT 24 9555666 ps
T58 /workspace/coverage/sync_alert/16.prim_sync_alert.3830579360 Jul 16 05:07:49 PM PDT 24 Jul 16 05:07:49 PM PDT 24 8251007 ps
T59 /workspace/coverage/sync_alert/4.prim_sync_alert.3995115333 Jul 16 05:07:35 PM PDT 24 Jul 16 05:07:36 PM PDT 24 8054639 ps
T60 /workspace/coverage/sync_alert/13.prim_sync_alert.3617386153 Jul 16 05:07:37 PM PDT 24 Jul 16 05:07:38 PM PDT 24 9671127 ps
T61 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2478884803 Jul 16 04:34:33 PM PDT 24 Jul 16 04:34:35 PM PDT 24 27945247 ps
T62 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2881502323 Jul 16 04:34:33 PM PDT 24 Jul 16 04:34:34 PM PDT 24 26376894 ps
T6 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1150228407 Jul 16 04:34:32 PM PDT 24 Jul 16 04:34:33 PM PDT 24 27863415 ps
T63 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3387939518 Jul 16 04:34:41 PM PDT 24 Jul 16 04:34:42 PM PDT 24 28084978 ps
T11 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2011545238 Jul 16 04:34:35 PM PDT 24 Jul 16 04:34:37 PM PDT 24 26865778 ps
T64 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2734572212 Jul 16 04:35:55 PM PDT 24 Jul 16 04:35:56 PM PDT 24 26615825 ps
T65 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.20014350 Jul 16 04:34:22 PM PDT 24 Jul 16 04:34:23 PM PDT 24 27529353 ps
T66 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.331298868 Jul 16 04:35:55 PM PDT 24 Jul 16 04:35:56 PM PDT 24 27485635 ps
T67 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2579291445 Jul 16 04:34:34 PM PDT 24 Jul 16 04:34:36 PM PDT 24 27433293 ps
T68 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.998379283 Jul 16 04:34:27 PM PDT 24 Jul 16 04:34:27 PM PDT 24 26067516 ps
T69 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3732511183 Jul 16 04:34:31 PM PDT 24 Jul 16 04:34:32 PM PDT 24 26582557 ps
T12 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1646727521 Jul 16 04:35:49 PM PDT 24 Jul 16 04:35:50 PM PDT 24 28450662 ps
T70 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.791954375 Jul 16 04:34:33 PM PDT 24 Jul 16 04:34:34 PM PDT 24 27398638 ps
T71 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1621283899 Jul 16 04:35:41 PM PDT 24 Jul 16 04:35:42 PM PDT 24 27518371 ps
T72 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1992626549 Jul 16 04:34:34 PM PDT 24 Jul 16 04:34:35 PM PDT 24 27850700 ps
T73 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1972660296 Jul 16 04:34:22 PM PDT 24 Jul 16 04:34:23 PM PDT 24 27763917 ps
T74 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3616321004 Jul 16 04:34:28 PM PDT 24 Jul 16 04:34:29 PM PDT 24 25717617 ps
T75 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4203416962 Jul 16 04:34:34 PM PDT 24 Jul 16 04:34:36 PM PDT 24 26019178 ps
T76 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1147657963 Jul 16 04:35:55 PM PDT 24 Jul 16 04:35:56 PM PDT 24 28832893 ps
T77 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1820634325 Jul 16 04:35:42 PM PDT 24 Jul 16 04:35:43 PM PDT 24 28314445 ps

Test location /workspace/coverage/default/2.prim_async_alert.565080516
Short name T8
Test name
Test status
Simulation time 10769328 ps
CPU time 0.41 seconds
Started Jul 16 04:34:28 PM PDT 24
Finished Jul 16 04:34:29 PM PDT 24
Peak memory 145164 kb
Host smart-41848189-5252-4a4c-bbe0-0d9abffc014c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565080516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.565080516
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3316071464
Short name T35
Test name
Test status
Simulation time 9778447 ps
CPU time 0.39 seconds
Started Jul 16 05:07:37 PM PDT 24
Finished Jul 16 05:07:38 PM PDT 24
Peak memory 145576 kb
Host smart-ad730d7e-177c-41e2-97e5-b7e18ce37dec
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3316071464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3316071464
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.193391288
Short name T5
Test name
Test status
Simulation time 30166794 ps
CPU time 0.4 seconds
Started Jul 16 04:34:34 PM PDT 24
Finished Jul 16 04:34:35 PM PDT 24
Peak memory 145740 kb
Host smart-5e1076eb-a56a-4fc4-88b2-a65161862f63
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=193391288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.193391288
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1475218557
Short name T16
Test name
Test status
Simulation time 11365705 ps
CPU time 0.44 seconds
Started Jul 16 04:34:21 PM PDT 24
Finished Jul 16 04:34:23 PM PDT 24
Peak memory 144492 kb
Host smart-8e731fb5-e136-4416-b458-253a0a40b732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475218557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1475218557
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1646727521
Short name T12
Test name
Test status
Simulation time 28450662 ps
CPU time 0.4 seconds
Started Jul 16 04:35:49 PM PDT 24
Finished Jul 16 04:35:50 PM PDT 24
Peak memory 145248 kb
Host smart-f890633f-c614-45af-98fe-3442e4bc5924
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1646727521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1646727521
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.43702429
Short name T15
Test name
Test status
Simulation time 12885033 ps
CPU time 0.39 seconds
Started Jul 16 04:34:24 PM PDT 24
Finished Jul 16 04:34:25 PM PDT 24
Peak memory 145840 kb
Host smart-77b24c91-3729-4156-a815-0f5a7a03d622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43702429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.43702429
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1076716875
Short name T20
Test name
Test status
Simulation time 11416416 ps
CPU time 0.42 seconds
Started Jul 16 04:34:34 PM PDT 24
Finished Jul 16 04:34:35 PM PDT 24
Peak memory 145640 kb
Host smart-0e65cc17-f727-4459-80f9-ac22141101e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076716875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1076716875
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1658946819
Short name T9
Test name
Test status
Simulation time 12057148 ps
CPU time 0.39 seconds
Started Jul 16 04:34:27 PM PDT 24
Finished Jul 16 04:34:28 PM PDT 24
Peak memory 145804 kb
Host smart-459961c7-1c18-4513-8cf5-c81983b29ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658946819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1658946819
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3259646128
Short name T38
Test name
Test status
Simulation time 11070372 ps
CPU time 0.39 seconds
Started Jul 16 04:34:34 PM PDT 24
Finished Jul 16 04:34:35 PM PDT 24
Peak memory 145788 kb
Host smart-01384195-f5f7-436a-a740-d2ee4e14f1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259646128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3259646128
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1943498848
Short name T13
Test name
Test status
Simulation time 11839659 ps
CPU time 0.38 seconds
Started Jul 16 04:34:31 PM PDT 24
Finished Jul 16 04:34:32 PM PDT 24
Peak memory 145648 kb
Host smart-23082497-dd5f-4e04-a86b-495822704a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943498848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1943498848
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.4165017230
Short name T46
Test name
Test status
Simulation time 10343801 ps
CPU time 0.38 seconds
Started Jul 16 04:34:35 PM PDT 24
Finished Jul 16 04:34:37 PM PDT 24
Peak memory 146608 kb
Host smart-740c51fd-3355-4a74-a924-dd5b1fc042c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165017230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.4165017230
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1679069922
Short name T10
Test name
Test status
Simulation time 10422585 ps
CPU time 0.39 seconds
Started Jul 16 04:34:23 PM PDT 24
Finished Jul 16 04:34:24 PM PDT 24
Peak memory 145836 kb
Host smart-ece269ff-63b9-4700-9ff9-7de243991e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679069922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1679069922
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.702536339
Short name T22
Test name
Test status
Simulation time 11052968 ps
CPU time 0.37 seconds
Started Jul 16 04:35:42 PM PDT 24
Finished Jul 16 04:35:43 PM PDT 24
Peak memory 145080 kb
Host smart-c4ac8874-5a13-46ec-91f0-9171b132940d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702536339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.702536339
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3662019553
Short name T7
Test name
Test status
Simulation time 10258031 ps
CPU time 0.38 seconds
Started Jul 16 04:34:37 PM PDT 24
Finished Jul 16 04:34:38 PM PDT 24
Peak memory 145724 kb
Host smart-685c5174-608a-4e81-8364-abc5815db781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662019553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3662019553
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2616857030
Short name T23
Test name
Test status
Simulation time 11407789 ps
CPU time 0.38 seconds
Started Jul 16 04:34:32 PM PDT 24
Finished Jul 16 04:34:33 PM PDT 24
Peak memory 145728 kb
Host smart-e2c0ba89-393e-4353-8615-12b07172c9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616857030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2616857030
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1075414824
Short name T1
Test name
Test status
Simulation time 10967794 ps
CPU time 0.4 seconds
Started Jul 16 04:34:33 PM PDT 24
Finished Jul 16 04:34:33 PM PDT 24
Peak memory 145732 kb
Host smart-7dc3110a-26c8-46d8-8993-665d9ecfada5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075414824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1075414824
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2259222214
Short name T47
Test name
Test status
Simulation time 10775947 ps
CPU time 0.45 seconds
Started Jul 16 04:34:27 PM PDT 24
Finished Jul 16 04:34:28 PM PDT 24
Peak memory 145828 kb
Host smart-42b67407-1170-4e23-8e0c-0dc447ffa3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259222214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2259222214
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1611816131
Short name T14
Test name
Test status
Simulation time 10778869 ps
CPU time 0.37 seconds
Started Jul 16 04:34:35 PM PDT 24
Finished Jul 16 04:34:37 PM PDT 24
Peak memory 145208 kb
Host smart-1abd5d29-b7be-4612-83db-6f0b0d46dc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611816131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1611816131
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2904315474
Short name T21
Test name
Test status
Simulation time 10133436 ps
CPU time 0.38 seconds
Started Jul 16 04:34:35 PM PDT 24
Finished Jul 16 04:34:37 PM PDT 24
Peak memory 146668 kb
Host smart-a7f74ee3-5374-41c2-bb27-7367d1bd1a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904315474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2904315474
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1902165887
Short name T19
Test name
Test status
Simulation time 11074600 ps
CPU time 0.42 seconds
Started Jul 16 04:35:33 PM PDT 24
Finished Jul 16 04:35:34 PM PDT 24
Peak memory 145348 kb
Host smart-0d51aef5-ffb4-4f34-91fe-193a90e1ab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902165887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1902165887
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1348288595
Short name T48
Test name
Test status
Simulation time 10866343 ps
CPU time 0.4 seconds
Started Jul 16 04:34:35 PM PDT 24
Finished Jul 16 04:34:37 PM PDT 24
Peak memory 145876 kb
Host smart-5559f017-efda-4111-9acb-0addfda7d0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348288595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1348288595
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2876716024
Short name T2
Test name
Test status
Simulation time 10692995 ps
CPU time 0.4 seconds
Started Jul 16 04:34:33 PM PDT 24
Finished Jul 16 04:34:34 PM PDT 24
Peak memory 145876 kb
Host smart-d8e443a4-4579-4dea-9213-e35427333b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876716024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2876716024
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.722356861
Short name T3
Test name
Test status
Simulation time 11575891 ps
CPU time 0.42 seconds
Started Jul 16 04:34:34 PM PDT 24
Finished Jul 16 04:34:35 PM PDT 24
Peak memory 146248 kb
Host smart-c60952fe-d1a9-4994-808e-ea0050ea1ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722356861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.722356861
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3593063594
Short name T53
Test name
Test status
Simulation time 31494341 ps
CPU time 0.4 seconds
Started Jul 16 04:34:33 PM PDT 24
Finished Jul 16 04:34:35 PM PDT 24
Peak memory 145400 kb
Host smart-d277fc02-3fdf-41c6-9239-4cce8f12ef14
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3593063594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3593063594
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3601459674
Short name T42
Test name
Test status
Simulation time 30487417 ps
CPU time 0.4 seconds
Started Jul 16 04:34:35 PM PDT 24
Finished Jul 16 04:34:37 PM PDT 24
Peak memory 144912 kb
Host smart-2f597d5f-4962-4f3f-a958-a6af2cca4c23
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3601459674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3601459674
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1821253248
Short name T17
Test name
Test status
Simulation time 30214153 ps
CPU time 0.43 seconds
Started Jul 16 04:34:33 PM PDT 24
Finished Jul 16 04:34:34 PM PDT 24
Peak memory 145292 kb
Host smart-9d89c159-3e9a-4407-b2d2-e2bfe17a1771
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1821253248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1821253248
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3534431534
Short name T44
Test name
Test status
Simulation time 30383838 ps
CPU time 0.44 seconds
Started Jul 16 04:34:21 PM PDT 24
Finished Jul 16 04:34:23 PM PDT 24
Peak memory 144124 kb
Host smart-91068cbc-a1b5-40a1-adda-d06e66f532c7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3534431534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3534431534
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2440422482
Short name T39
Test name
Test status
Simulation time 28156282 ps
CPU time 0.41 seconds
Started Jul 16 04:34:35 PM PDT 24
Finished Jul 16 04:34:37 PM PDT 24
Peak memory 144752 kb
Host smart-9d34e854-8c55-4543-89ff-068708d1d46f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2440422482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2440422482
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.731687003
Short name T45
Test name
Test status
Simulation time 30037478 ps
CPU time 0.4 seconds
Started Jul 16 04:35:42 PM PDT 24
Finished Jul 16 04:35:43 PM PDT 24
Peak memory 144772 kb
Host smart-4e89dcaa-f301-4ecf-af28-2c6dc5c68ae0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=731687003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.731687003
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.585705693
Short name T40
Test name
Test status
Simulation time 31268572 ps
CPU time 0.4 seconds
Started Jul 16 04:35:50 PM PDT 24
Finished Jul 16 04:35:50 PM PDT 24
Peak memory 145032 kb
Host smart-5b461243-dc21-4fa5-ac40-ca715d41ac77
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=585705693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.585705693
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3190396148
Short name T41
Test name
Test status
Simulation time 32013441 ps
CPU time 0.42 seconds
Started Jul 16 04:34:34 PM PDT 24
Finished Jul 16 04:34:35 PM PDT 24
Peak memory 145404 kb
Host smart-d8d158fc-46d5-4134-a851-c24591391998
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3190396148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3190396148
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.840458542
Short name T49
Test name
Test status
Simulation time 31143027 ps
CPU time 0.4 seconds
Started Jul 16 04:34:32 PM PDT 24
Finished Jul 16 04:34:33 PM PDT 24
Peak memory 145272 kb
Host smart-0e04f8c0-8f70-474b-a196-fb288a95c5bd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=840458542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.840458542
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3589778178
Short name T18
Test name
Test status
Simulation time 29702103 ps
CPU time 0.4 seconds
Started Jul 16 04:35:42 PM PDT 24
Finished Jul 16 04:35:43 PM PDT 24
Peak memory 144744 kb
Host smart-9dee7434-6fc6-4d43-be29-90970107392f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3589778178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3589778178
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3659499967
Short name T51
Test name
Test status
Simulation time 30149049 ps
CPU time 0.39 seconds
Started Jul 16 04:34:34 PM PDT 24
Finished Jul 16 04:34:36 PM PDT 24
Peak memory 144724 kb
Host smart-c7963b5e-063c-4872-9f5e-274e71be3dd4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3659499967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3659499967
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2586108767
Short name T54
Test name
Test status
Simulation time 28815409 ps
CPU time 0.44 seconds
Started Jul 16 04:34:34 PM PDT 24
Finished Jul 16 04:34:35 PM PDT 24
Peak memory 145468 kb
Host smart-d2315417-5b39-41d2-841e-cc30f4529603
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2586108767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2586108767
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1107830147
Short name T50
Test name
Test status
Simulation time 29555997 ps
CPU time 0.41 seconds
Started Jul 16 04:35:41 PM PDT 24
Finished Jul 16 04:35:42 PM PDT 24
Peak memory 143872 kb
Host smart-24709659-573d-4353-aa72-a640b01ec9bc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1107830147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1107830147
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2217560926
Short name T52
Test name
Test status
Simulation time 29768188 ps
CPU time 0.4 seconds
Started Jul 16 04:34:37 PM PDT 24
Finished Jul 16 04:34:38 PM PDT 24
Peak memory 145276 kb
Host smart-80822098-0a06-4861-881e-8a625dd46358
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2217560926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2217560926
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2167929083
Short name T4
Test name
Test status
Simulation time 28694070 ps
CPU time 0.45 seconds
Started Jul 16 04:34:29 PM PDT 24
Finished Jul 16 04:34:30 PM PDT 24
Peak memory 144996 kb
Host smart-e082a657-fdae-432e-92a1-8f4b810f113d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2167929083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2167929083
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3811325295
Short name T43
Test name
Test status
Simulation time 29264728 ps
CPU time 0.39 seconds
Started Jul 16 04:34:27 PM PDT 24
Finished Jul 16 04:34:27 PM PDT 24
Peak memory 145364 kb
Host smart-c691513c-a6d3-4e9d-8065-624503da3420
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3811325295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3811325295
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.668431898
Short name T30
Test name
Test status
Simulation time 8982135 ps
CPU time 0.4 seconds
Started Jul 16 05:07:45 PM PDT 24
Finished Jul 16 05:07:45 PM PDT 24
Peak memory 145456 kb
Host smart-46622872-062c-40aa-8027-bda6fcc5510d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=668431898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.668431898
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2976441288
Short name T24
Test name
Test status
Simulation time 8969976 ps
CPU time 0.4 seconds
Started Jul 16 05:07:31 PM PDT 24
Finished Jul 16 05:07:32 PM PDT 24
Peak memory 145580 kb
Host smart-5bd10298-b80b-42fa-8252-363e3c035765
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2976441288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2976441288
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.370579029
Short name T34
Test name
Test status
Simulation time 9296569 ps
CPU time 0.38 seconds
Started Jul 16 05:07:43 PM PDT 24
Finished Jul 16 05:07:43 PM PDT 24
Peak memory 145496 kb
Host smart-f155b72f-3777-44ab-a86d-0afebe010414
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=370579029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.370579029
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2657617687
Short name T55
Test name
Test status
Simulation time 9050916 ps
CPU time 0.38 seconds
Started Jul 16 05:07:31 PM PDT 24
Finished Jul 16 05:07:31 PM PDT 24
Peak memory 145476 kb
Host smart-6f3db601-0e23-42f8-856a-c767572ba1ef
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2657617687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2657617687
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2593160201
Short name T36
Test name
Test status
Simulation time 9971865 ps
CPU time 0.37 seconds
Started Jul 16 05:07:41 PM PDT 24
Finished Jul 16 05:07:42 PM PDT 24
Peak memory 145424 kb
Host smart-8cb5fc04-64c6-4918-8ccd-b60e01f9864f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2593160201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2593160201
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3617386153
Short name T60
Test name
Test status
Simulation time 9671127 ps
CPU time 0.39 seconds
Started Jul 16 05:07:37 PM PDT 24
Finished Jul 16 05:07:38 PM PDT 24
Peak memory 145456 kb
Host smart-10a04c54-7970-41e6-b330-5176f5a463db
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3617386153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3617386153
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.154169642
Short name T25
Test name
Test status
Simulation time 9319083 ps
CPU time 0.36 seconds
Started Jul 16 05:07:42 PM PDT 24
Finished Jul 16 05:07:43 PM PDT 24
Peak memory 145492 kb
Host smart-d4f9b9a2-1498-4a87-90e5-ab1f3c93a4b7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=154169642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.154169642
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1970100204
Short name T32
Test name
Test status
Simulation time 9130166 ps
CPU time 0.39 seconds
Started Jul 16 05:07:49 PM PDT 24
Finished Jul 16 05:07:50 PM PDT 24
Peak memory 145588 kb
Host smart-56cec4b7-9941-47c3-a5b8-dc58d006e297
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1970100204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1970100204
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3830579360
Short name T58
Test name
Test status
Simulation time 8251007 ps
CPU time 0.38 seconds
Started Jul 16 05:07:49 PM PDT 24
Finished Jul 16 05:07:49 PM PDT 24
Peak memory 145600 kb
Host smart-b8d08fde-993d-4cda-b532-fcd32d91eb9a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3830579360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3830579360
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1188947360
Short name T28
Test name
Test status
Simulation time 9609900 ps
CPU time 0.4 seconds
Started Jul 16 05:07:38 PM PDT 24
Finished Jul 16 05:07:39 PM PDT 24
Peak memory 145600 kb
Host smart-afe16ef9-2e7e-4322-b349-ea6c501d04a8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1188947360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1188947360
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3146078893
Short name T26
Test name
Test status
Simulation time 9094728 ps
CPU time 0.43 seconds
Started Jul 16 05:07:45 PM PDT 24
Finished Jul 16 05:07:45 PM PDT 24
Peak memory 145596 kb
Host smart-13b073e7-6e67-4556-87b5-5b3c31ede133
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3146078893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3146078893
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.225408502
Short name T31
Test name
Test status
Simulation time 10747727 ps
CPU time 0.38 seconds
Started Jul 16 05:07:42 PM PDT 24
Finished Jul 16 05:07:43 PM PDT 24
Peak memory 145588 kb
Host smart-02ff9f6e-3fa5-48e5-a43f-da27aaa9f510
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=225408502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.225408502
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.18964161
Short name T33
Test name
Test status
Simulation time 9028208 ps
CPU time 0.38 seconds
Started Jul 16 05:07:36 PM PDT 24
Finished Jul 16 05:07:37 PM PDT 24
Peak memory 145584 kb
Host smart-9682dffa-6c07-4c9d-8503-afba3328a1dd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=18964161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.18964161
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3995115333
Short name T59
Test name
Test status
Simulation time 8054639 ps
CPU time 0.41 seconds
Started Jul 16 05:07:35 PM PDT 24
Finished Jul 16 05:07:36 PM PDT 24
Peak memory 145488 kb
Host smart-cfff4e7b-3553-45f9-a769-09947b4e6a32
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3995115333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3995115333
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2845199724
Short name T37
Test name
Test status
Simulation time 8827279 ps
CPU time 0.38 seconds
Started Jul 16 05:07:30 PM PDT 24
Finished Jul 16 05:07:30 PM PDT 24
Peak memory 145576 kb
Host smart-f7af87c2-faeb-437d-a627-d358d27fbe0a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2845199724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2845199724
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2112781646
Short name T57
Test name
Test status
Simulation time 9555666 ps
CPU time 0.37 seconds
Started Jul 16 05:07:29 PM PDT 24
Finished Jul 16 05:07:30 PM PDT 24
Peak memory 145524 kb
Host smart-79b31da6-7b72-42de-85ab-c432cb82222b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2112781646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2112781646
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.770012605
Short name T27
Test name
Test status
Simulation time 8705360 ps
CPU time 0.38 seconds
Started Jul 16 05:07:34 PM PDT 24
Finished Jul 16 05:07:34 PM PDT 24
Peak memory 145564 kb
Host smart-757d7136-68ca-4dc9-85d9-7815e5eb2acb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=770012605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.770012605
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.612420171
Short name T56
Test name
Test status
Simulation time 8903498 ps
CPU time 0.39 seconds
Started Jul 16 05:07:50 PM PDT 24
Finished Jul 16 05:07:51 PM PDT 24
Peak memory 145456 kb
Host smart-ba82f1c9-5d99-4273-8025-b87703d494d7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=612420171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.612420171
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2174415423
Short name T29
Test name
Test status
Simulation time 9194569 ps
CPU time 0.37 seconds
Started Jul 16 05:07:37 PM PDT 24
Finished Jul 16 05:07:38 PM PDT 24
Peak memory 145424 kb
Host smart-ac45226f-677d-4fa9-a9ea-4bd2c89c4206
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2174415423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2174415423
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1972660296
Short name T73
Test name
Test status
Simulation time 27763917 ps
CPU time 0.39 seconds
Started Jul 16 04:34:22 PM PDT 24
Finished Jul 16 04:34:23 PM PDT 24
Peak memory 145664 kb
Host smart-46880261-f616-4948-820f-55a766668ddc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1972660296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1972660296
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.331298868
Short name T66
Test name
Test status
Simulation time 27485635 ps
CPU time 0.4 seconds
Started Jul 16 04:35:55 PM PDT 24
Finished Jul 16 04:35:56 PM PDT 24
Peak memory 144992 kb
Host smart-a3a4ab60-2f96-4d26-b9c5-9d8a11ca6326
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=331298868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.331298868
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.791954375
Short name T70
Test name
Test status
Simulation time 27398638 ps
CPU time 0.39 seconds
Started Jul 16 04:34:33 PM PDT 24
Finished Jul 16 04:34:34 PM PDT 24
Peak memory 145680 kb
Host smart-7b975c22-dd23-4ffe-9ffa-3e830acfd2f5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=791954375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.791954375
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.20014350
Short name T65
Test name
Test status
Simulation time 27529353 ps
CPU time 0.4 seconds
Started Jul 16 04:34:22 PM PDT 24
Finished Jul 16 04:34:23 PM PDT 24
Peak memory 145036 kb
Host smart-06b58112-39d8-4433-b3b8-d4934864bce3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=20014350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.20014350
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3616321004
Short name T74
Test name
Test status
Simulation time 25717617 ps
CPU time 0.4 seconds
Started Jul 16 04:34:28 PM PDT 24
Finished Jul 16 04:34:29 PM PDT 24
Peak memory 144996 kb
Host smart-1d7e45b7-8b0a-4403-bf56-70edf1e4a061
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3616321004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3616321004
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1992626549
Short name T72
Test name
Test status
Simulation time 27850700 ps
CPU time 0.38 seconds
Started Jul 16 04:34:34 PM PDT 24
Finished Jul 16 04:34:35 PM PDT 24
Peak memory 145784 kb
Host smart-9c17196d-48fe-4d20-bc61-4beedb9fce88
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1992626549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1992626549
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1147657963
Short name T76
Test name
Test status
Simulation time 28832893 ps
CPU time 0.39 seconds
Started Jul 16 04:35:55 PM PDT 24
Finished Jul 16 04:35:56 PM PDT 24
Peak memory 145140 kb
Host smart-0b2fac9e-948f-419d-a1ac-233c7124c79a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1147657963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1147657963
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3387939518
Short name T63
Test name
Test status
Simulation time 28084978 ps
CPU time 0.44 seconds
Started Jul 16 04:34:41 PM PDT 24
Finished Jul 16 04:34:42 PM PDT 24
Peak memory 145680 kb
Host smart-9ef1f1de-29b1-4058-b84e-56a3cfc191d6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3387939518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3387939518
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1150228407
Short name T6
Test name
Test status
Simulation time 27863415 ps
CPU time 0.4 seconds
Started Jul 16 04:34:32 PM PDT 24
Finished Jul 16 04:34:33 PM PDT 24
Peak memory 145524 kb
Host smart-addd8758-90e1-4bcd-8d5c-8734b91e9bb3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1150228407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1150228407
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2579291445
Short name T67
Test name
Test status
Simulation time 27433293 ps
CPU time 0.39 seconds
Started Jul 16 04:34:34 PM PDT 24
Finished Jul 16 04:34:36 PM PDT 24
Peak memory 145004 kb
Host smart-4e0e57d1-0450-4d18-aa59-3ccf92be6ba8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2579291445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2579291445
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1621283899
Short name T71
Test name
Test status
Simulation time 27518371 ps
CPU time 0.45 seconds
Started Jul 16 04:35:41 PM PDT 24
Finished Jul 16 04:35:42 PM PDT 24
Peak memory 145152 kb
Host smart-2a7ce371-2afa-4617-91e9-15f530d4c64e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1621283899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1621283899
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2881502323
Short name T62
Test name
Test status
Simulation time 26376894 ps
CPU time 0.4 seconds
Started Jul 16 04:34:33 PM PDT 24
Finished Jul 16 04:34:34 PM PDT 24
Peak memory 145680 kb
Host smart-8d530b00-8d4f-4db8-8330-1b32c2a5fd88
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2881502323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2881502323
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.998379283
Short name T68
Test name
Test status
Simulation time 26067516 ps
CPU time 0.39 seconds
Started Jul 16 04:34:27 PM PDT 24
Finished Jul 16 04:34:27 PM PDT 24
Peak memory 145660 kb
Host smart-64e6498a-993e-4061-9347-89661bd34625
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=998379283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.998379283
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2478884803
Short name T61
Test name
Test status
Simulation time 27945247 ps
CPU time 0.4 seconds
Started Jul 16 04:34:33 PM PDT 24
Finished Jul 16 04:34:35 PM PDT 24
Peak memory 145672 kb
Host smart-acc5c638-784e-436c-b4e4-daba0f14139a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2478884803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2478884803
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2011545238
Short name T11
Test name
Test status
Simulation time 26865778 ps
CPU time 0.39 seconds
Started Jul 16 04:34:35 PM PDT 24
Finished Jul 16 04:34:37 PM PDT 24
Peak memory 145052 kb
Host smart-6868ba52-c443-4263-bd3d-16c728866783
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2011545238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2011545238
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1820634325
Short name T77
Test name
Test status
Simulation time 28314445 ps
CPU time 0.4 seconds
Started Jul 16 04:35:42 PM PDT 24
Finished Jul 16 04:35:43 PM PDT 24
Peak memory 144856 kb
Host smart-4c3e4b9f-5b66-4a30-bde4-0b1f1b2af6dc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1820634325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1820634325
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4203416962
Short name T75
Test name
Test status
Simulation time 26019178 ps
CPU time 0.39 seconds
Started Jul 16 04:34:34 PM PDT 24
Finished Jul 16 04:34:36 PM PDT 24
Peak memory 145008 kb
Host smart-1d7692b0-38d6-4f9b-8fd7-17804d11b7b1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4203416962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.4203416962
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3732511183
Short name T69
Test name
Test status
Simulation time 26582557 ps
CPU time 0.42 seconds
Started Jul 16 04:34:31 PM PDT 24
Finished Jul 16 04:34:32 PM PDT 24
Peak memory 145516 kb
Host smart-ecf6bb7c-7aa8-4a0d-b7a5-613c0430b460
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3732511183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3732511183
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2734572212
Short name T64
Test name
Test status
Simulation time 26615825 ps
CPU time 0.4 seconds
Started Jul 16 04:35:55 PM PDT 24
Finished Jul 16 04:35:56 PM PDT 24
Peak memory 145008 kb
Host smart-d1cf4fc8-d8a8-4aca-ba2c-947cc5d7caa1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2734572212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2734572212
Directory /workspace/9.prim_sync_fatal_alert/latest
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