Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.08 88.08 100.00 100.00 93.75 93.75 96.43 96.43 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/12.prim_async_alert.2064680261
91.20 3.13 100.00 0.00 93.75 0.00 96.43 0.00 82.14 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/1.prim_sync_alert.2502274058
93.90 2.70 100.00 0.00 95.83 2.08 100.00 3.57 85.71 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2105768164
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/14.prim_async_alert.3852331295
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/13.prim_sync_alert.2725014094
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3817731540

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1535326247
/workspace/coverage/default/1.prim_async_alert.1255313792
/workspace/coverage/default/10.prim_async_alert.3838717338
/workspace/coverage/default/11.prim_async_alert.2407944285
/workspace/coverage/default/13.prim_async_alert.3094050617
/workspace/coverage/default/15.prim_async_alert.1572331634
/workspace/coverage/default/16.prim_async_alert.2733756957
/workspace/coverage/default/17.prim_async_alert.2529583498
/workspace/coverage/default/18.prim_async_alert.2210770868
/workspace/coverage/default/19.prim_async_alert.3164249114
/workspace/coverage/default/2.prim_async_alert.3694222667
/workspace/coverage/default/3.prim_async_alert.3036306238
/workspace/coverage/default/4.prim_async_alert.2058624364
/workspace/coverage/default/5.prim_async_alert.1028491595
/workspace/coverage/default/6.prim_async_alert.2416682767
/workspace/coverage/default/7.prim_async_alert.3453683062
/workspace/coverage/default/8.prim_async_alert.4065279356
/workspace/coverage/default/9.prim_async_alert.364686918
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1980607144
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2071620739
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1541078801
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3597751913
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.5933399
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.143359552
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1348034972
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1595612480
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1397768498
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.880493923
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3589481263
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3954662312
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2943885298
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3482964938
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3866761832
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4229191861
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.887581183
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2235106563
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.757627224
/workspace/coverage/sync_alert/0.prim_sync_alert.1227762655
/workspace/coverage/sync_alert/10.prim_sync_alert.3534304670
/workspace/coverage/sync_alert/11.prim_sync_alert.1053364982
/workspace/coverage/sync_alert/12.prim_sync_alert.976382063
/workspace/coverage/sync_alert/14.prim_sync_alert.4167173974
/workspace/coverage/sync_alert/15.prim_sync_alert.2917387902
/workspace/coverage/sync_alert/16.prim_sync_alert.3028672904
/workspace/coverage/sync_alert/17.prim_sync_alert.841249431
/workspace/coverage/sync_alert/18.prim_sync_alert.416127274
/workspace/coverage/sync_alert/19.prim_sync_alert.967347990
/workspace/coverage/sync_alert/2.prim_sync_alert.1310448587
/workspace/coverage/sync_alert/3.prim_sync_alert.516967190
/workspace/coverage/sync_alert/4.prim_sync_alert.4281740234
/workspace/coverage/sync_alert/5.prim_sync_alert.1102575372
/workspace/coverage/sync_alert/6.prim_sync_alert.2682071307
/workspace/coverage/sync_alert/7.prim_sync_alert.2698063742
/workspace/coverage/sync_alert/8.prim_sync_alert.4070998526
/workspace/coverage/sync_alert/9.prim_sync_alert.2958015547
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.597691157
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3170542206
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3316378834
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3968765852
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1578138121
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2026320639
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.994941614
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3018578912
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4123071811
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1363651561
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4070349795
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1860282117
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1079111138
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1106676971
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3693623604
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2024844386
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.79637300
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1455698835
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1283024449



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/12.prim_async_alert.2064680261 Jul 17 04:17:04 PM PDT 24 Jul 17 04:17:05 PM PDT 24 11490657 ps
T2 /workspace/coverage/default/15.prim_async_alert.1572331634 Jul 17 04:17:10 PM PDT 24 Jul 17 04:17:12 PM PDT 24 12236566 ps
T3 /workspace/coverage/default/17.prim_async_alert.2529583498 Jul 17 04:17:06 PM PDT 24 Jul 17 04:17:09 PM PDT 24 10418936 ps
T8 /workspace/coverage/default/14.prim_async_alert.3852331295 Jul 17 04:17:11 PM PDT 24 Jul 17 04:17:13 PM PDT 24 11709289 ps
T18 /workspace/coverage/default/5.prim_async_alert.1028491595 Jul 17 04:17:04 PM PDT 24 Jul 17 04:17:06 PM PDT 24 10857039 ps
T15 /workspace/coverage/default/1.prim_async_alert.1255313792 Jul 17 04:17:10 PM PDT 24 Jul 17 04:17:13 PM PDT 24 10192144 ps
T19 /workspace/coverage/default/8.prim_async_alert.4065279356 Jul 17 04:17:12 PM PDT 24 Jul 17 04:17:14 PM PDT 24 11077176 ps
T7 /workspace/coverage/default/19.prim_async_alert.3164249114 Jul 17 04:17:57 PM PDT 24 Jul 17 04:17:58 PM PDT 24 11583319 ps
T20 /workspace/coverage/default/10.prim_async_alert.3838717338 Jul 17 04:17:09 PM PDT 24 Jul 17 04:17:10 PM PDT 24 11016531 ps
T21 /workspace/coverage/default/4.prim_async_alert.2058624364 Jul 17 04:17:52 PM PDT 24 Jul 17 04:17:53 PM PDT 24 11035471 ps
T22 /workspace/coverage/default/11.prim_async_alert.2407944285 Jul 17 04:17:15 PM PDT 24 Jul 17 04:17:18 PM PDT 24 11633847 ps
T12 /workspace/coverage/default/9.prim_async_alert.364686918 Jul 17 04:17:10 PM PDT 24 Jul 17 04:17:12 PM PDT 24 13079995 ps
T16 /workspace/coverage/default/13.prim_async_alert.3094050617 Jul 17 04:17:06 PM PDT 24 Jul 17 04:17:09 PM PDT 24 12420258 ps
T47 /workspace/coverage/default/6.prim_async_alert.2416682767 Jul 17 04:17:17 PM PDT 24 Jul 17 04:17:19 PM PDT 24 10967815 ps
T13 /workspace/coverage/default/18.prim_async_alert.2210770868 Jul 17 04:17:17 PM PDT 24 Jul 17 04:17:19 PM PDT 24 11499679 ps
T23 /workspace/coverage/default/7.prim_async_alert.3453683062 Jul 17 04:17:06 PM PDT 24 Jul 17 04:17:09 PM PDT 24 10278095 ps
T48 /workspace/coverage/default/0.prim_async_alert.1535326247 Jul 17 04:17:11 PM PDT 24 Jul 17 04:17:13 PM PDT 24 11245603 ps
T17 /workspace/coverage/default/2.prim_async_alert.3694222667 Jul 17 04:17:05 PM PDT 24 Jul 17 04:17:06 PM PDT 24 10775769 ps
T49 /workspace/coverage/default/16.prim_async_alert.2733756957 Jul 17 04:17:20 PM PDT 24 Jul 17 04:17:21 PM PDT 24 11597992 ps
T50 /workspace/coverage/default/3.prim_async_alert.3036306238 Jul 17 04:17:20 PM PDT 24 Jul 17 04:17:21 PM PDT 24 11266669 ps
T14 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3597751913 Jul 17 04:19:02 PM PDT 24 Jul 17 04:19:03 PM PDT 24 30197350 ps
T39 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.887581183 Jul 17 04:17:10 PM PDT 24 Jul 17 04:17:11 PM PDT 24 28515660 ps
T24 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3866761832 Jul 17 04:17:50 PM PDT 24 Jul 17 04:17:51 PM PDT 24 31609316 ps
T40 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2105768164 Jul 17 04:17:18 PM PDT 24 Jul 17 04:17:20 PM PDT 24 31562030 ps
T41 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1595612480 Jul 17 04:17:11 PM PDT 24 Jul 17 04:17:13 PM PDT 24 29916222 ps
T42 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2235106563 Jul 17 04:17:10 PM PDT 24 Jul 17 04:17:12 PM PDT 24 30501114 ps
T43 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2071620739 Jul 17 04:17:16 PM PDT 24 Jul 17 04:17:18 PM PDT 24 28739593 ps
T44 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.143359552 Jul 17 04:17:17 PM PDT 24 Jul 17 04:17:19 PM PDT 24 28674715 ps
T45 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.757627224 Jul 17 04:18:15 PM PDT 24 Jul 17 04:18:17 PM PDT 24 28079030 ps
T46 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3589481263 Jul 17 04:19:14 PM PDT 24 Jul 17 04:19:15 PM PDT 24 30103485 ps
T51 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1980607144 Jul 17 04:17:10 PM PDT 24 Jul 17 04:17:13 PM PDT 24 30352996 ps
T52 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1541078801 Jul 17 04:17:10 PM PDT 24 Jul 17 04:17:12 PM PDT 24 30219553 ps
T53 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2943885298 Jul 17 04:17:55 PM PDT 24 Jul 17 04:17:56 PM PDT 24 28286240 ps
T54 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3482964938 Jul 17 04:17:11 PM PDT 24 Jul 17 04:17:13 PM PDT 24 30661239 ps
T38 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1348034972 Jul 17 04:17:04 PM PDT 24 Jul 17 04:17:05 PM PDT 24 29596245 ps
T55 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4229191861 Jul 17 04:17:20 PM PDT 24 Jul 17 04:17:21 PM PDT 24 29039969 ps
T56 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.5933399 Jul 17 04:16:59 PM PDT 24 Jul 17 04:17:01 PM PDT 24 27989803 ps
T57 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3954662312 Jul 17 04:17:55 PM PDT 24 Jul 17 04:17:56 PM PDT 24 30586229 ps
T58 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.880493923 Jul 17 04:17:10 PM PDT 24 Jul 17 04:17:11 PM PDT 24 29951567 ps
T59 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1397768498 Jul 17 04:17:12 PM PDT 24 Jul 17 04:17:14 PM PDT 24 32508282 ps
T33 /workspace/coverage/sync_alert/6.prim_sync_alert.2682071307 Jul 17 04:17:06 PM PDT 24 Jul 17 04:17:09 PM PDT 24 8747407 ps
T9 /workspace/coverage/sync_alert/15.prim_sync_alert.2917387902 Jul 17 04:18:06 PM PDT 24 Jul 17 04:18:08 PM PDT 24 9267208 ps
T25 /workspace/coverage/sync_alert/8.prim_sync_alert.4070998526 Jul 17 04:17:06 PM PDT 24 Jul 17 04:17:09 PM PDT 24 9369865 ps
T34 /workspace/coverage/sync_alert/16.prim_sync_alert.3028672904 Jul 17 04:17:09 PM PDT 24 Jul 17 04:17:11 PM PDT 24 9345023 ps
T35 /workspace/coverage/sync_alert/1.prim_sync_alert.2502274058 Jul 17 04:17:15 PM PDT 24 Jul 17 04:17:18 PM PDT 24 10467093 ps
T26 /workspace/coverage/sync_alert/14.prim_sync_alert.4167173974 Jul 17 04:17:06 PM PDT 24 Jul 17 04:17:09 PM PDT 24 9225304 ps
T36 /workspace/coverage/sync_alert/17.prim_sync_alert.841249431 Jul 17 04:17:06 PM PDT 24 Jul 17 04:17:09 PM PDT 24 9350724 ps
T37 /workspace/coverage/sync_alert/4.prim_sync_alert.4281740234 Jul 17 04:17:10 PM PDT 24 Jul 17 04:17:12 PM PDT 24 10670913 ps
T27 /workspace/coverage/sync_alert/10.prim_sync_alert.3534304670 Jul 17 04:17:12 PM PDT 24 Jul 17 04:17:14 PM PDT 24 9470578 ps
T28 /workspace/coverage/sync_alert/0.prim_sync_alert.1227762655 Jul 17 04:17:16 PM PDT 24 Jul 17 04:17:18 PM PDT 24 9609175 ps
T60 /workspace/coverage/sync_alert/2.prim_sync_alert.1310448587 Jul 17 04:17:17 PM PDT 24 Jul 17 04:17:19 PM PDT 24 10110443 ps
T61 /workspace/coverage/sync_alert/7.prim_sync_alert.2698063742 Jul 17 04:17:16 PM PDT 24 Jul 17 04:17:18 PM PDT 24 9380301 ps
T29 /workspace/coverage/sync_alert/5.prim_sync_alert.1102575372 Jul 17 04:17:19 PM PDT 24 Jul 17 04:17:21 PM PDT 24 8532570 ps
T62 /workspace/coverage/sync_alert/18.prim_sync_alert.416127274 Jul 17 04:17:05 PM PDT 24 Jul 17 04:17:07 PM PDT 24 8680764 ps
T63 /workspace/coverage/sync_alert/12.prim_sync_alert.976382063 Jul 17 04:17:05 PM PDT 24 Jul 17 04:17:06 PM PDT 24 8814277 ps
T30 /workspace/coverage/sync_alert/9.prim_sync_alert.2958015547 Jul 17 04:17:11 PM PDT 24 Jul 17 04:17:14 PM PDT 24 9876895 ps
T10 /workspace/coverage/sync_alert/3.prim_sync_alert.516967190 Jul 17 04:18:15 PM PDT 24 Jul 17 04:18:17 PM PDT 24 9205008 ps
T64 /workspace/coverage/sync_alert/19.prim_sync_alert.967347990 Jul 17 04:17:15 PM PDT 24 Jul 17 04:17:17 PM PDT 24 9211585 ps
T65 /workspace/coverage/sync_alert/11.prim_sync_alert.1053364982 Jul 17 04:17:17 PM PDT 24 Jul 17 04:17:19 PM PDT 24 10647745 ps
T11 /workspace/coverage/sync_alert/13.prim_sync_alert.2725014094 Jul 17 04:17:57 PM PDT 24 Jul 17 04:17:58 PM PDT 24 10083407 ps
T66 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1106676971 Jul 17 04:22:41 PM PDT 24 Jul 17 04:22:42 PM PDT 24 29010775 ps
T67 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3170542206 Jul 17 04:18:06 PM PDT 24 Jul 17 04:18:07 PM PDT 24 26668859 ps
T68 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.597691157 Jul 17 04:18:12 PM PDT 24 Jul 17 04:18:14 PM PDT 24 27021467 ps
T4 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.79637300 Jul 17 04:21:38 PM PDT 24 Jul 17 04:21:39 PM PDT 24 26022990 ps
T31 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1283024449 Jul 17 04:18:04 PM PDT 24 Jul 17 04:18:05 PM PDT 24 29000354 ps
T32 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.994941614 Jul 17 04:18:13 PM PDT 24 Jul 17 04:18:14 PM PDT 24 27636402 ps
T69 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2026320639 Jul 17 04:19:06 PM PDT 24 Jul 17 04:19:07 PM PDT 24 26755889 ps
T70 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2024844386 Jul 17 04:19:14 PM PDT 24 Jul 17 04:19:15 PM PDT 24 29306707 ps
T71 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1860282117 Jul 17 04:24:35 PM PDT 24 Jul 17 04:24:37 PM PDT 24 26173910 ps
T72 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1363651561 Jul 17 04:18:15 PM PDT 24 Jul 17 04:18:18 PM PDT 24 28399243 ps
T73 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3316378834 Jul 17 04:19:30 PM PDT 24 Jul 17 04:19:31 PM PDT 24 28348714 ps
T5 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4123071811 Jul 17 04:18:11 PM PDT 24 Jul 17 04:18:12 PM PDT 24 28349011 ps
T6 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4070349795 Jul 17 04:19:48 PM PDT 24 Jul 17 04:19:49 PM PDT 24 27614178 ps
T74 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3968765852 Jul 17 04:19:36 PM PDT 24 Jul 17 04:19:37 PM PDT 24 27381214 ps
T75 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3693623604 Jul 17 04:19:04 PM PDT 24 Jul 17 04:19:05 PM PDT 24 29826942 ps
T76 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3018578912 Jul 17 04:18:04 PM PDT 24 Jul 17 04:18:05 PM PDT 24 27039346 ps
T77 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1578138121 Jul 17 04:21:15 PM PDT 24 Jul 17 04:21:16 PM PDT 24 28150423 ps
T78 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1079111138 Jul 17 04:17:51 PM PDT 24 Jul 17 04:17:52 PM PDT 24 26057068 ps
T79 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1455698835 Jul 17 04:18:15 PM PDT 24 Jul 17 04:18:17 PM PDT 24 28370961 ps
T80 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3817731540 Jul 17 04:18:14 PM PDT 24 Jul 17 04:18:16 PM PDT 24 28059837 ps

Test location /workspace/coverage/default/12.prim_async_alert.2064680261
Short name T1
Test name
Test status
Simulation time 11490657 ps
CPU time 0.45 seconds
Started Jul 17 04:17:04 PM PDT 24
Finished Jul 17 04:17:05 PM PDT 24
Peak memory 145288 kb
Host smart-3fe163b0-32c2-4ac1-9d69-464bd5272f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064680261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2064680261
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2502274058
Short name T35
Test name
Test status
Simulation time 10467093 ps
CPU time 0.37 seconds
Started Jul 17 04:17:15 PM PDT 24
Finished Jul 17 04:17:18 PM PDT 24
Peak memory 145636 kb
Host smart-62b6517a-916a-46ad-9e1e-c8de84d11a0f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2502274058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2502274058
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2105768164
Short name T40
Test name
Test status
Simulation time 31562030 ps
CPU time 0.4 seconds
Started Jul 17 04:17:18 PM PDT 24
Finished Jul 17 04:17:20 PM PDT 24
Peak memory 145000 kb
Host smart-ee1a9ede-8eab-4f45-b134-a7fc24e01b26
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2105768164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2105768164
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.3852331295
Short name T8
Test name
Test status
Simulation time 11709289 ps
CPU time 0.38 seconds
Started Jul 17 04:17:11 PM PDT 24
Finished Jul 17 04:17:13 PM PDT 24
Peak memory 145856 kb
Host smart-a95756d2-3d87-4c83-9e50-19269449b2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852331295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3852331295
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2725014094
Short name T11
Test name
Test status
Simulation time 10083407 ps
CPU time 0.42 seconds
Started Jul 17 04:17:57 PM PDT 24
Finished Jul 17 04:17:58 PM PDT 24
Peak memory 145176 kb
Host smart-ad5dfdd2-8535-4ca1-bb59-f1f0a91faa92
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2725014094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2725014094
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3817731540
Short name T80
Test name
Test status
Simulation time 28059837 ps
CPU time 0.41 seconds
Started Jul 17 04:18:14 PM PDT 24
Finished Jul 17 04:18:16 PM PDT 24
Peak memory 145644 kb
Host smart-7a8e1a1e-1b17-428e-a515-88995f7a38e7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3817731540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3817731540
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1535326247
Short name T48
Test name
Test status
Simulation time 11245603 ps
CPU time 0.37 seconds
Started Jul 17 04:17:11 PM PDT 24
Finished Jul 17 04:17:13 PM PDT 24
Peak memory 145856 kb
Host smart-fad0395b-7e8c-4dde-84e5-3011918db37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535326247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1535326247
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1255313792
Short name T15
Test name
Test status
Simulation time 10192144 ps
CPU time 0.43 seconds
Started Jul 17 04:17:10 PM PDT 24
Finished Jul 17 04:17:13 PM PDT 24
Peak memory 144780 kb
Host smart-44af34bc-c8ef-4cc8-8955-c67ad1f2c552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255313792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1255313792
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3838717338
Short name T20
Test name
Test status
Simulation time 11016531 ps
CPU time 0.4 seconds
Started Jul 17 04:17:09 PM PDT 24
Finished Jul 17 04:17:10 PM PDT 24
Peak memory 145840 kb
Host smart-6af14f36-cd1f-4b37-9d6d-f4749cd86179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838717338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3838717338
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2407944285
Short name T22
Test name
Test status
Simulation time 11633847 ps
CPU time 0.38 seconds
Started Jul 17 04:17:15 PM PDT 24
Finished Jul 17 04:17:18 PM PDT 24
Peak memory 145840 kb
Host smart-641fc1b2-da31-47f2-98e6-38596a671e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407944285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2407944285
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3094050617
Short name T16
Test name
Test status
Simulation time 12420258 ps
CPU time 0.4 seconds
Started Jul 17 04:17:06 PM PDT 24
Finished Jul 17 04:17:09 PM PDT 24
Peak memory 145156 kb
Host smart-7e853ad1-1d1e-4e53-b7df-9c0b8e8045f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094050617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3094050617
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1572331634
Short name T2
Test name
Test status
Simulation time 12236566 ps
CPU time 0.41 seconds
Started Jul 17 04:17:10 PM PDT 24
Finished Jul 17 04:17:12 PM PDT 24
Peak memory 144724 kb
Host smart-54fac326-bfd8-40f9-8199-fffe3df9159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572331634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1572331634
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2733756957
Short name T49
Test name
Test status
Simulation time 11597992 ps
CPU time 0.4 seconds
Started Jul 17 04:17:20 PM PDT 24
Finished Jul 17 04:17:21 PM PDT 24
Peak memory 145532 kb
Host smart-27457b75-372c-42ed-856f-5d1ef4bd6ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733756957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2733756957
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2529583498
Short name T3
Test name
Test status
Simulation time 10418936 ps
CPU time 0.45 seconds
Started Jul 17 04:17:06 PM PDT 24
Finished Jul 17 04:17:09 PM PDT 24
Peak memory 145084 kb
Host smart-308d897c-a3c1-40f1-8231-bb1f7e370f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529583498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2529583498
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2210770868
Short name T13
Test name
Test status
Simulation time 11499679 ps
CPU time 0.39 seconds
Started Jul 17 04:17:17 PM PDT 24
Finished Jul 17 04:17:19 PM PDT 24
Peak memory 147164 kb
Host smart-7c90a70e-efa4-4579-bf09-eea189dbd4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210770868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2210770868
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3164249114
Short name T7
Test name
Test status
Simulation time 11583319 ps
CPU time 0.49 seconds
Started Jul 17 04:17:57 PM PDT 24
Finished Jul 17 04:17:58 PM PDT 24
Peak memory 145432 kb
Host smart-4957302e-a0fc-45fe-86ef-7fc0095dc2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164249114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3164249114
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3694222667
Short name T17
Test name
Test status
Simulation time 10775769 ps
CPU time 0.41 seconds
Started Jul 17 04:17:05 PM PDT 24
Finished Jul 17 04:17:06 PM PDT 24
Peak memory 145428 kb
Host smart-23bac537-fd7b-4fe3-81f7-8b715f059118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694222667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3694222667
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3036306238
Short name T50
Test name
Test status
Simulation time 11266669 ps
CPU time 0.42 seconds
Started Jul 17 04:17:20 PM PDT 24
Finished Jul 17 04:17:21 PM PDT 24
Peak memory 145528 kb
Host smart-b8f40904-a6dd-4f35-bcee-defd6ef9b56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036306238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3036306238
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2058624364
Short name T21
Test name
Test status
Simulation time 11035471 ps
CPU time 0.38 seconds
Started Jul 17 04:17:52 PM PDT 24
Finished Jul 17 04:17:53 PM PDT 24
Peak memory 145420 kb
Host smart-2f6e3942-bf15-4b2a-bc18-ce122c383b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058624364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2058624364
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1028491595
Short name T18
Test name
Test status
Simulation time 10857039 ps
CPU time 0.49 seconds
Started Jul 17 04:17:04 PM PDT 24
Finished Jul 17 04:17:06 PM PDT 24
Peak memory 145008 kb
Host smart-f8a38a25-03ce-4f5b-be57-d859f36ee0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028491595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1028491595
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.2416682767
Short name T47
Test name
Test status
Simulation time 10967815 ps
CPU time 0.39 seconds
Started Jul 17 04:17:17 PM PDT 24
Finished Jul 17 04:17:19 PM PDT 24
Peak memory 147276 kb
Host smart-63f12c32-bc73-4aa6-ab98-772d01f023f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416682767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2416682767
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3453683062
Short name T23
Test name
Test status
Simulation time 10278095 ps
CPU time 0.4 seconds
Started Jul 17 04:17:06 PM PDT 24
Finished Jul 17 04:17:09 PM PDT 24
Peak memory 145136 kb
Host smart-570540ff-4c63-4650-8dae-9d7cdf92721a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453683062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3453683062
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.4065279356
Short name T19
Test name
Test status
Simulation time 11077176 ps
CPU time 0.38 seconds
Started Jul 17 04:17:12 PM PDT 24
Finished Jul 17 04:17:14 PM PDT 24
Peak memory 145856 kb
Host smart-5811a51a-862f-4496-9b17-bca8e17c0813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065279356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.4065279356
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.364686918
Short name T12
Test name
Test status
Simulation time 13079995 ps
CPU time 0.39 seconds
Started Jul 17 04:17:10 PM PDT 24
Finished Jul 17 04:17:12 PM PDT 24
Peak memory 145896 kb
Host smart-1236cc0a-ef32-45d1-a5a1-7cd3930904fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364686918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.364686918
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1980607144
Short name T51
Test name
Test status
Simulation time 30352996 ps
CPU time 0.42 seconds
Started Jul 17 04:17:10 PM PDT 24
Finished Jul 17 04:17:13 PM PDT 24
Peak memory 145408 kb
Host smart-7dc8daf2-1408-40fe-9207-3bc1c8360daf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1980607144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1980607144
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2071620739
Short name T43
Test name
Test status
Simulation time 28739593 ps
CPU time 0.4 seconds
Started Jul 17 04:17:16 PM PDT 24
Finished Jul 17 04:17:18 PM PDT 24
Peak memory 145368 kb
Host smart-282de019-d1ec-43bc-8885-742ce84f6b08
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2071620739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2071620739
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1541078801
Short name T52
Test name
Test status
Simulation time 30219553 ps
CPU time 0.4 seconds
Started Jul 17 04:17:10 PM PDT 24
Finished Jul 17 04:17:12 PM PDT 24
Peak memory 145376 kb
Host smart-7f3b2b6c-cddb-4e32-93df-b88740808e3d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1541078801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1541078801
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3597751913
Short name T14
Test name
Test status
Simulation time 30197350 ps
CPU time 0.49 seconds
Started Jul 17 04:19:02 PM PDT 24
Finished Jul 17 04:19:03 PM PDT 24
Peak memory 145408 kb
Host smart-8d0cf33f-51da-4fc6-9c49-a64765219c14
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3597751913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3597751913
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.5933399
Short name T56
Test name
Test status
Simulation time 27989803 ps
CPU time 0.47 seconds
Started Jul 17 04:16:59 PM PDT 24
Finished Jul 17 04:17:01 PM PDT 24
Peak memory 144836 kb
Host smart-bf51c7b4-a317-4640-8b2e-b71ac6282806
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=5933399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.5933399
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.143359552
Short name T44
Test name
Test status
Simulation time 28674715 ps
CPU time 0.41 seconds
Started Jul 17 04:17:17 PM PDT 24
Finished Jul 17 04:17:19 PM PDT 24
Peak memory 146856 kb
Host smart-63e94223-2c5a-4a89-bece-e30a8af8a9d9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=143359552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.143359552
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1348034972
Short name T38
Test name
Test status
Simulation time 29596245 ps
CPU time 0.5 seconds
Started Jul 17 04:17:04 PM PDT 24
Finished Jul 17 04:17:05 PM PDT 24
Peak memory 145104 kb
Host smart-fa193f58-01fb-4012-933b-07a406c8f35e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1348034972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1348034972
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1595612480
Short name T41
Test name
Test status
Simulation time 29916222 ps
CPU time 0.4 seconds
Started Jul 17 04:17:11 PM PDT 24
Finished Jul 17 04:17:13 PM PDT 24
Peak memory 145352 kb
Host smart-7de4c0f5-9821-466b-9327-54c096fb0d79
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1595612480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1595612480
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1397768498
Short name T59
Test name
Test status
Simulation time 32508282 ps
CPU time 0.4 seconds
Started Jul 17 04:17:12 PM PDT 24
Finished Jul 17 04:17:14 PM PDT 24
Peak memory 145352 kb
Host smart-0e5ee16c-2f6a-45bd-80c6-06b623934317
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1397768498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1397768498
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.880493923
Short name T58
Test name
Test status
Simulation time 29951567 ps
CPU time 0.39 seconds
Started Jul 17 04:17:10 PM PDT 24
Finished Jul 17 04:17:11 PM PDT 24
Peak memory 145068 kb
Host smart-108b1b22-f4c4-4e76-a58f-a54bcfb0192d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=880493923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.880493923
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3589481263
Short name T46
Test name
Test status
Simulation time 30103485 ps
CPU time 0.42 seconds
Started Jul 17 04:19:14 PM PDT 24
Finished Jul 17 04:19:15 PM PDT 24
Peak memory 145108 kb
Host smart-276bd1fa-0256-4046-b920-6a71c13d67df
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3589481263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3589481263
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3954662312
Short name T57
Test name
Test status
Simulation time 30586229 ps
CPU time 0.42 seconds
Started Jul 17 04:17:55 PM PDT 24
Finished Jul 17 04:17:56 PM PDT 24
Peak memory 145084 kb
Host smart-54d731ee-5c65-46df-af01-dfcf388897d7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3954662312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3954662312
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2943885298
Short name T53
Test name
Test status
Simulation time 28286240 ps
CPU time 0.47 seconds
Started Jul 17 04:17:55 PM PDT 24
Finished Jul 17 04:17:56 PM PDT 24
Peak memory 145084 kb
Host smart-f587ecae-11cc-4d3a-83b6-7fd2429ab006
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2943885298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2943885298
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3482964938
Short name T54
Test name
Test status
Simulation time 30661239 ps
CPU time 0.4 seconds
Started Jul 17 04:17:11 PM PDT 24
Finished Jul 17 04:17:13 PM PDT 24
Peak memory 145368 kb
Host smart-a0a25f94-9282-48fe-849f-92d4d1650bc5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3482964938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3482964938
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3866761832
Short name T24
Test name
Test status
Simulation time 31609316 ps
CPU time 0.41 seconds
Started Jul 17 04:17:50 PM PDT 24
Finished Jul 17 04:17:51 PM PDT 24
Peak memory 145060 kb
Host smart-caadc1c6-3455-49a8-8454-ede4dfa37191
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3866761832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3866761832
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4229191861
Short name T55
Test name
Test status
Simulation time 29039969 ps
CPU time 0.4 seconds
Started Jul 17 04:17:20 PM PDT 24
Finished Jul 17 04:17:21 PM PDT 24
Peak memory 144988 kb
Host smart-4f42669b-6da8-49d6-b034-e9d5849cea76
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4229191861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.4229191861
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.887581183
Short name T39
Test name
Test status
Simulation time 28515660 ps
CPU time 0.41 seconds
Started Jul 17 04:17:10 PM PDT 24
Finished Jul 17 04:17:11 PM PDT 24
Peak memory 145416 kb
Host smart-3f1ce0e3-3166-4423-9114-e25e4d8b5226
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=887581183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.887581183
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2235106563
Short name T42
Test name
Test status
Simulation time 30501114 ps
CPU time 0.41 seconds
Started Jul 17 04:17:10 PM PDT 24
Finished Jul 17 04:17:12 PM PDT 24
Peak memory 145408 kb
Host smart-c0b76a0b-38a5-4f2a-a5d1-d4baec732a70
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2235106563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2235106563
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.757627224
Short name T45
Test name
Test status
Simulation time 28079030 ps
CPU time 0.41 seconds
Started Jul 17 04:18:15 PM PDT 24
Finished Jul 17 04:18:17 PM PDT 24
Peak memory 145068 kb
Host smart-d94097f2-8db9-4cd0-a7eb-1e5cf59cadc2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=757627224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.757627224
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1227762655
Short name T28
Test name
Test status
Simulation time 9609175 ps
CPU time 0.38 seconds
Started Jul 17 04:17:16 PM PDT 24
Finished Jul 17 04:17:18 PM PDT 24
Peak memory 145608 kb
Host smart-d1b50def-736b-435b-b44c-81c983cf8bca
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1227762655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1227762655
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3534304670
Short name T27
Test name
Test status
Simulation time 9470578 ps
CPU time 0.38 seconds
Started Jul 17 04:17:12 PM PDT 24
Finished Jul 17 04:17:14 PM PDT 24
Peak memory 145636 kb
Host smart-c49c8e1c-4a4d-4a62-b978-7a2d33956941
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3534304670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3534304670
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1053364982
Short name T65
Test name
Test status
Simulation time 10647745 ps
CPU time 0.38 seconds
Started Jul 17 04:17:17 PM PDT 24
Finished Jul 17 04:17:19 PM PDT 24
Peak memory 145644 kb
Host smart-2d6c0210-8841-4646-8696-37a780b9b128
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1053364982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1053364982
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.976382063
Short name T63
Test name
Test status
Simulation time 8814277 ps
CPU time 0.41 seconds
Started Jul 17 04:17:05 PM PDT 24
Finished Jul 17 04:17:06 PM PDT 24
Peak memory 144916 kb
Host smart-03417269-4c70-42d4-855d-f5f603c69b7a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=976382063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.976382063
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.4167173974
Short name T26
Test name
Test status
Simulation time 9225304 ps
CPU time 0.48 seconds
Started Jul 17 04:17:06 PM PDT 24
Finished Jul 17 04:17:09 PM PDT 24
Peak memory 144152 kb
Host smart-85398bd0-84ea-41a5-ba27-d38dc2e7bdf0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4167173974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.4167173974
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2917387902
Short name T9
Test name
Test status
Simulation time 9267208 ps
CPU time 0.4 seconds
Started Jul 17 04:18:06 PM PDT 24
Finished Jul 17 04:18:08 PM PDT 24
Peak memory 145692 kb
Host smart-bc433414-73f4-4b0a-a36a-b8227e6a283c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2917387902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2917387902
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3028672904
Short name T34
Test name
Test status
Simulation time 9345023 ps
CPU time 0.38 seconds
Started Jul 17 04:17:09 PM PDT 24
Finished Jul 17 04:17:11 PM PDT 24
Peak memory 145160 kb
Host smart-ef76f694-abca-40e1-a5e1-787b548e0b0e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3028672904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3028672904
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.841249431
Short name T36
Test name
Test status
Simulation time 9350724 ps
CPU time 0.39 seconds
Started Jul 17 04:17:06 PM PDT 24
Finished Jul 17 04:17:09 PM PDT 24
Peak memory 144972 kb
Host smart-9d4a3cc7-6933-46b9-8fc5-d0b1005c936e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=841249431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.841249431
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.416127274
Short name T62
Test name
Test status
Simulation time 8680764 ps
CPU time 0.4 seconds
Started Jul 17 04:17:05 PM PDT 24
Finished Jul 17 04:17:07 PM PDT 24
Peak memory 144980 kb
Host smart-46a33ad3-5f4b-4671-b802-be93813a7352
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=416127274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.416127274
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.967347990
Short name T64
Test name
Test status
Simulation time 9211585 ps
CPU time 0.38 seconds
Started Jul 17 04:17:15 PM PDT 24
Finished Jul 17 04:17:17 PM PDT 24
Peak memory 145636 kb
Host smart-96159293-b292-47c6-91eb-d6a90ac50f47
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=967347990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.967347990
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1310448587
Short name T60
Test name
Test status
Simulation time 10110443 ps
CPU time 0.38 seconds
Started Jul 17 04:17:17 PM PDT 24
Finished Jul 17 04:17:19 PM PDT 24
Peak memory 145632 kb
Host smart-20679310-3ff4-486b-a22f-7c4c4d2a65a2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1310448587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1310448587
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.516967190
Short name T10
Test name
Test status
Simulation time 9205008 ps
CPU time 0.39 seconds
Started Jul 17 04:18:15 PM PDT 24
Finished Jul 17 04:18:17 PM PDT 24
Peak memory 145640 kb
Host smart-4a25ee72-4dbc-4e88-9146-223191bad47c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=516967190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.516967190
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.4281740234
Short name T37
Test name
Test status
Simulation time 10670913 ps
CPU time 0.41 seconds
Started Jul 17 04:17:10 PM PDT 24
Finished Jul 17 04:17:12 PM PDT 24
Peak memory 145652 kb
Host smart-6d2168be-513a-451e-99e5-1f9ef250a8c9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4281740234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.4281740234
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1102575372
Short name T29
Test name
Test status
Simulation time 8532570 ps
CPU time 0.39 seconds
Started Jul 17 04:17:19 PM PDT 24
Finished Jul 17 04:17:21 PM PDT 24
Peak memory 145276 kb
Host smart-32354c76-371c-460e-bff3-982092f8134c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1102575372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1102575372
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2682071307
Short name T33
Test name
Test status
Simulation time 8747407 ps
CPU time 0.44 seconds
Started Jul 17 04:17:06 PM PDT 24
Finished Jul 17 04:17:09 PM PDT 24
Peak memory 145840 kb
Host smart-c2aedeb0-c0b2-4b06-bb90-60b84760d82d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2682071307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2682071307
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2698063742
Short name T61
Test name
Test status
Simulation time 9380301 ps
CPU time 0.38 seconds
Started Jul 17 04:17:16 PM PDT 24
Finished Jul 17 04:17:18 PM PDT 24
Peak memory 145576 kb
Host smart-86c85c23-8dd9-47e2-81d4-aaabe924c1ed
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2698063742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2698063742
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.4070998526
Short name T25
Test name
Test status
Simulation time 9369865 ps
CPU time 0.47 seconds
Started Jul 17 04:17:06 PM PDT 24
Finished Jul 17 04:17:09 PM PDT 24
Peak memory 144100 kb
Host smart-f13094cf-3aec-4da1-9f06-f756f83d1c26
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4070998526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.4070998526
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2958015547
Short name T30
Test name
Test status
Simulation time 9876895 ps
CPU time 0.38 seconds
Started Jul 17 04:17:11 PM PDT 24
Finished Jul 17 04:17:14 PM PDT 24
Peak memory 145636 kb
Host smart-6e4f46b5-6609-4cb9-91be-31fcdb4eff37
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2958015547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2958015547
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.597691157
Short name T68
Test name
Test status
Simulation time 27021467 ps
CPU time 0.43 seconds
Started Jul 17 04:18:12 PM PDT 24
Finished Jul 17 04:18:14 PM PDT 24
Peak memory 145260 kb
Host smart-0c0b44f1-94b8-4189-9ac9-2230a9fbf322
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=597691157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.597691157
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3170542206
Short name T67
Test name
Test status
Simulation time 26668859 ps
CPU time 0.42 seconds
Started Jul 17 04:18:06 PM PDT 24
Finished Jul 17 04:18:07 PM PDT 24
Peak memory 145708 kb
Host smart-0726faec-221a-4ee6-be9d-fe363eb16d8b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3170542206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3170542206
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3316378834
Short name T73
Test name
Test status
Simulation time 28348714 ps
CPU time 0.41 seconds
Started Jul 17 04:19:30 PM PDT 24
Finished Jul 17 04:19:31 PM PDT 24
Peak memory 145288 kb
Host smart-048cbb92-7981-4ee7-9a9c-19a97e0ae17f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3316378834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3316378834
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3968765852
Short name T74
Test name
Test status
Simulation time 27381214 ps
CPU time 0.39 seconds
Started Jul 17 04:19:36 PM PDT 24
Finished Jul 17 04:19:37 PM PDT 24
Peak memory 145292 kb
Host smart-6cf827f0-03cc-4a10-8421-c6f6aa3c60a2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3968765852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3968765852
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1578138121
Short name T77
Test name
Test status
Simulation time 28150423 ps
CPU time 0.44 seconds
Started Jul 17 04:21:15 PM PDT 24
Finished Jul 17 04:21:16 PM PDT 24
Peak memory 145260 kb
Host smart-70775dc1-63a9-462c-acf4-49f36def3630
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1578138121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1578138121
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2026320639
Short name T69
Test name
Test status
Simulation time 26755889 ps
CPU time 0.39 seconds
Started Jul 17 04:19:06 PM PDT 24
Finished Jul 17 04:19:07 PM PDT 24
Peak memory 145652 kb
Host smart-81682ca6-80f4-418b-a017-c03ac493c0ad
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2026320639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2026320639
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.994941614
Short name T32
Test name
Test status
Simulation time 27636402 ps
CPU time 0.42 seconds
Started Jul 17 04:18:13 PM PDT 24
Finished Jul 17 04:18:14 PM PDT 24
Peak memory 145272 kb
Host smart-6c666d4d-3e5a-4f20-8f83-cf7f57e92790
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=994941614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.994941614
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3018578912
Short name T76
Test name
Test status
Simulation time 27039346 ps
CPU time 0.4 seconds
Started Jul 17 04:18:04 PM PDT 24
Finished Jul 17 04:18:05 PM PDT 24
Peak memory 145292 kb
Host smart-eb411785-0eac-48c0-b6b5-0ce4bf426eda
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3018578912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3018578912
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4123071811
Short name T5
Test name
Test status
Simulation time 28349011 ps
CPU time 0.43 seconds
Started Jul 17 04:18:11 PM PDT 24
Finished Jul 17 04:18:12 PM PDT 24
Peak memory 145280 kb
Host smart-c130055a-329b-4ab4-b159-5fd755efbed4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4123071811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.4123071811
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1363651561
Short name T72
Test name
Test status
Simulation time 28399243 ps
CPU time 0.41 seconds
Started Jul 17 04:18:15 PM PDT 24
Finished Jul 17 04:18:18 PM PDT 24
Peak memory 145648 kb
Host smart-42549c44-28bf-4a93-8f4f-bfa54ddc4f8f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1363651561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1363651561
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4070349795
Short name T6
Test name
Test status
Simulation time 27614178 ps
CPU time 0.41 seconds
Started Jul 17 04:19:48 PM PDT 24
Finished Jul 17 04:19:49 PM PDT 24
Peak memory 145292 kb
Host smart-dee62532-eb6e-46d9-add0-4e7f92ebf606
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4070349795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.4070349795
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1860282117
Short name T71
Test name
Test status
Simulation time 26173910 ps
CPU time 0.44 seconds
Started Jul 17 04:24:35 PM PDT 24
Finished Jul 17 04:24:37 PM PDT 24
Peak memory 145252 kb
Host smart-f4dee2f1-9883-492d-b1e0-c5fc372abe27
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1860282117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1860282117
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1079111138
Short name T78
Test name
Test status
Simulation time 26057068 ps
CPU time 0.4 seconds
Started Jul 17 04:17:51 PM PDT 24
Finished Jul 17 04:17:52 PM PDT 24
Peak memory 145292 kb
Host smart-ff3d4bc6-baa5-446c-a2d1-8405a30b511e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1079111138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1079111138
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1106676971
Short name T66
Test name
Test status
Simulation time 29010775 ps
CPU time 0.39 seconds
Started Jul 17 04:22:41 PM PDT 24
Finished Jul 17 04:22:42 PM PDT 24
Peak memory 145480 kb
Host smart-5d8bea1c-a639-4ae0-a597-99cf92bb553d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1106676971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1106676971
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3693623604
Short name T75
Test name
Test status
Simulation time 29826942 ps
CPU time 0.39 seconds
Started Jul 17 04:19:04 PM PDT 24
Finished Jul 17 04:19:05 PM PDT 24
Peak memory 145668 kb
Host smart-95062828-34a2-43f3-9d5c-e5c57efc42d3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3693623604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3693623604
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2024844386
Short name T70
Test name
Test status
Simulation time 29306707 ps
CPU time 0.45 seconds
Started Jul 17 04:19:14 PM PDT 24
Finished Jul 17 04:19:15 PM PDT 24
Peak memory 145316 kb
Host smart-8b7a43b4-ca60-4668-af6b-dbb1e9f5172e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2024844386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2024844386
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.79637300
Short name T4
Test name
Test status
Simulation time 26022990 ps
CPU time 0.45 seconds
Started Jul 17 04:21:38 PM PDT 24
Finished Jul 17 04:21:39 PM PDT 24
Peak memory 145656 kb
Host smart-df2aae46-1159-4622-80bc-59e7a99d41fa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=79637300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.79637300
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1455698835
Short name T79
Test name
Test status
Simulation time 28370961 ps
CPU time 0.39 seconds
Started Jul 17 04:18:15 PM PDT 24
Finished Jul 17 04:18:17 PM PDT 24
Peak memory 145256 kb
Host smart-ed184a14-2568-486d-9bbf-dffa0c5c31de
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1455698835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1455698835
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1283024449
Short name T31
Test name
Test status
Simulation time 29000354 ps
CPU time 0.41 seconds
Started Jul 17 04:18:04 PM PDT 24
Finished Jul 17 04:18:05 PM PDT 24
Peak memory 145288 kb
Host smart-d3a5149e-29d7-40d5-8b9f-bca41da3ea35
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1283024449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1283024449
Directory /workspace/9.prim_sync_fatal_alert/latest
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