Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 100.00 100.00 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/2.prim_async_alert.1963052507
91.20 2.53 100.00 0.00 93.75 0.00 100.00 0.00 78.57 3.57 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/4.prim_sync_alert.3319042956
93.31 2.11 100.00 0.00 95.83 2.08 100.00 0.00 82.14 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.635285309
94.50 1.19 100.00 0.00 95.83 0.00 100.00 0.00 89.29 7.14 95.83 0.00 86.05 0.00 /workspace/coverage/default/19.prim_async_alert.2718236188
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/10.prim_sync_alert.3928179493
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1718210642

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2762276887
/workspace/coverage/default/1.prim_async_alert.2156250436
/workspace/coverage/default/10.prim_async_alert.3247866782
/workspace/coverage/default/11.prim_async_alert.1169126461
/workspace/coverage/default/12.prim_async_alert.651776943
/workspace/coverage/default/13.prim_async_alert.427413368
/workspace/coverage/default/14.prim_async_alert.3593473826
/workspace/coverage/default/15.prim_async_alert.467180607
/workspace/coverage/default/16.prim_async_alert.3872685065
/workspace/coverage/default/17.prim_async_alert.2070746364
/workspace/coverage/default/18.prim_async_alert.3659552880
/workspace/coverage/default/3.prim_async_alert.1321947986
/workspace/coverage/default/4.prim_async_alert.1695869597
/workspace/coverage/default/5.prim_async_alert.2170467438
/workspace/coverage/default/6.prim_async_alert.3372399171
/workspace/coverage/default/7.prim_async_alert.2506432946
/workspace/coverage/default/8.prim_async_alert.2546313559
/workspace/coverage/default/9.prim_async_alert.2865310014
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4016215777
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.295352144
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2110160964
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3966132652
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2430091156
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1074679202
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2276378395
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.546218680
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2653789732
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2840297157
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.45478159
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.591446597
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1832406438
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2930759275
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.183531444
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.242324603
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1563866308
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.409742174
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1135325122
/workspace/coverage/sync_alert/0.prim_sync_alert.2146021373
/workspace/coverage/sync_alert/1.prim_sync_alert.2448474839
/workspace/coverage/sync_alert/11.prim_sync_alert.658537676
/workspace/coverage/sync_alert/12.prim_sync_alert.3065789062
/workspace/coverage/sync_alert/13.prim_sync_alert.2690298861
/workspace/coverage/sync_alert/14.prim_sync_alert.2357924002
/workspace/coverage/sync_alert/15.prim_sync_alert.952486234
/workspace/coverage/sync_alert/16.prim_sync_alert.4124508672
/workspace/coverage/sync_alert/17.prim_sync_alert.4270444693
/workspace/coverage/sync_alert/18.prim_sync_alert.4212824941
/workspace/coverage/sync_alert/19.prim_sync_alert.2810281041
/workspace/coverage/sync_alert/2.prim_sync_alert.617508910
/workspace/coverage/sync_alert/3.prim_sync_alert.1299252329
/workspace/coverage/sync_alert/5.prim_sync_alert.3969611705
/workspace/coverage/sync_alert/6.prim_sync_alert.3235449146
/workspace/coverage/sync_alert/7.prim_sync_alert.2988553177
/workspace/coverage/sync_alert/8.prim_sync_alert.2166543254
/workspace/coverage/sync_alert/9.prim_sync_alert.29528980
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.773507269
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3925140851
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3045901036
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3026052661
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.947904354
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.691461318
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3338658467
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.965918753
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3986569644
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3335685033
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.141302183
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1427388160
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3840628969
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.332205804
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1492780569
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3520879464
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1581249090
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2792032528
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1009389970



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/4.prim_async_alert.1695869597 Jul 18 05:16:33 PM PDT 24 Jul 18 05:16:39 PM PDT 24 11193475 ps
T2 /workspace/coverage/default/2.prim_async_alert.1963052507 Jul 18 05:16:38 PM PDT 24 Jul 18 05:16:43 PM PDT 24 11748194 ps
T3 /workspace/coverage/default/7.prim_async_alert.2506432946 Jul 18 05:16:35 PM PDT 24 Jul 18 05:16:41 PM PDT 24 11740844 ps
T7 /workspace/coverage/default/9.prim_async_alert.2865310014 Jul 18 05:16:38 PM PDT 24 Jul 18 05:16:43 PM PDT 24 9921573 ps
T13 /workspace/coverage/default/19.prim_async_alert.2718236188 Jul 18 05:16:32 PM PDT 24 Jul 18 05:16:38 PM PDT 24 12130792 ps
T19 /workspace/coverage/default/0.prim_async_alert.2762276887 Jul 18 05:16:33 PM PDT 24 Jul 18 05:16:39 PM PDT 24 11557700 ps
T8 /workspace/coverage/default/5.prim_async_alert.2170467438 Jul 18 05:16:39 PM PDT 24 Jul 18 05:16:43 PM PDT 24 12180420 ps
T20 /workspace/coverage/default/13.prim_async_alert.427413368 Jul 18 05:16:37 PM PDT 24 Jul 18 05:16:42 PM PDT 24 12594484 ps
T21 /workspace/coverage/default/10.prim_async_alert.3247866782 Jul 18 05:16:35 PM PDT 24 Jul 18 05:16:42 PM PDT 24 10935848 ps
T9 /workspace/coverage/default/17.prim_async_alert.2070746364 Jul 18 05:16:37 PM PDT 24 Jul 18 05:16:42 PM PDT 24 11376117 ps
T47 /workspace/coverage/default/16.prim_async_alert.3872685065 Jul 18 05:16:32 PM PDT 24 Jul 18 05:16:37 PM PDT 24 11701893 ps
T48 /workspace/coverage/default/1.prim_async_alert.2156250436 Jul 18 05:16:30 PM PDT 24 Jul 18 05:16:34 PM PDT 24 11760542 ps
T15 /workspace/coverage/default/3.prim_async_alert.1321947986 Jul 18 05:16:32 PM PDT 24 Jul 18 05:16:37 PM PDT 24 11520443 ps
T49 /workspace/coverage/default/14.prim_async_alert.3593473826 Jul 18 05:16:44 PM PDT 24 Jul 18 05:16:46 PM PDT 24 12001323 ps
T17 /workspace/coverage/default/8.prim_async_alert.2546313559 Jul 18 05:16:34 PM PDT 24 Jul 18 05:16:40 PM PDT 24 11520279 ps
T50 /workspace/coverage/default/6.prim_async_alert.3372399171 Jul 18 05:16:37 PM PDT 24 Jul 18 05:16:42 PM PDT 24 10783246 ps
T10 /workspace/coverage/default/18.prim_async_alert.3659552880 Jul 18 05:16:43 PM PDT 24 Jul 18 05:16:45 PM PDT 24 11258901 ps
T16 /workspace/coverage/default/11.prim_async_alert.1169126461 Jul 18 05:16:37 PM PDT 24 Jul 18 05:16:42 PM PDT 24 12324009 ps
T22 /workspace/coverage/default/15.prim_async_alert.467180607 Jul 18 05:16:43 PM PDT 24 Jul 18 05:16:45 PM PDT 24 11106114 ps
T23 /workspace/coverage/default/12.prim_async_alert.651776943 Jul 18 05:16:37 PM PDT 24 Jul 18 05:16:42 PM PDT 24 11709277 ps
T40 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1135325122 Jul 18 05:35:55 PM PDT 24 Jul 18 05:36:01 PM PDT 24 29977863 ps
T24 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2930759275 Jul 18 05:35:52 PM PDT 24 Jul 18 05:35:57 PM PDT 24 26527246 ps
T18 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.635285309 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:00 PM PDT 24 31168367 ps
T41 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.183531444 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:01 PM PDT 24 30186334 ps
T42 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.242324603 Jul 18 05:35:53 PM PDT 24 Jul 18 05:35:58 PM PDT 24 28089260 ps
T43 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.591446597 Jul 18 05:35:56 PM PDT 24 Jul 18 05:36:02 PM PDT 24 29049418 ps
T39 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4016215777 Jul 18 05:35:52 PM PDT 24 Jul 18 05:35:58 PM PDT 24 30740872 ps
T44 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.45478159 Jul 18 05:36:08 PM PDT 24 Jul 18 05:36:15 PM PDT 24 31518662 ps
T45 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3966132652 Jul 18 05:35:53 PM PDT 24 Jul 18 05:35:59 PM PDT 24 30198614 ps
T46 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2276378395 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:00 PM PDT 24 30694568 ps
T51 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1074679202 Jul 18 05:35:52 PM PDT 24 Jul 18 05:35:57 PM PDT 24 30268035 ps
T52 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2110160964 Jul 18 05:35:56 PM PDT 24 Jul 18 05:36:02 PM PDT 24 31421617 ps
T53 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.546218680 Jul 18 05:35:49 PM PDT 24 Jul 18 05:35:53 PM PDT 24 29036318 ps
T14 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2653789732 Jul 18 05:36:12 PM PDT 24 Jul 18 05:36:20 PM PDT 24 31108904 ps
T54 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.409742174 Jul 18 05:35:55 PM PDT 24 Jul 18 05:36:02 PM PDT 24 30307204 ps
T55 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1832406438 Jul 18 05:35:52 PM PDT 24 Jul 18 05:35:58 PM PDT 24 31023381 ps
T56 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2430091156 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:01 PM PDT 24 34124982 ps
T57 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2840297157 Jul 18 05:36:09 PM PDT 24 Jul 18 05:36:15 PM PDT 24 31711965 ps
T58 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1563866308 Jul 18 05:35:52 PM PDT 24 Jul 18 05:35:57 PM PDT 24 30401626 ps
T59 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.295352144 Jul 18 05:35:58 PM PDT 24 Jul 18 05:36:03 PM PDT 24 31234117 ps
T25 /workspace/coverage/sync_alert/2.prim_sync_alert.617508910 Jul 18 04:44:26 PM PDT 24 Jul 18 04:44:29 PM PDT 24 8802960 ps
T34 /workspace/coverage/sync_alert/6.prim_sync_alert.3235449146 Jul 18 04:44:30 PM PDT 24 Jul 18 04:44:32 PM PDT 24 9788996 ps
T35 /workspace/coverage/sync_alert/9.prim_sync_alert.29528980 Jul 18 04:44:29 PM PDT 24 Jul 18 04:44:31 PM PDT 24 9002078 ps
T11 /workspace/coverage/sync_alert/15.prim_sync_alert.952486234 Jul 18 04:44:25 PM PDT 24 Jul 18 04:44:26 PM PDT 24 8614785 ps
T26 /workspace/coverage/sync_alert/16.prim_sync_alert.4124508672 Jul 18 04:45:35 PM PDT 24 Jul 18 04:45:40 PM PDT 24 8731178 ps
T36 /workspace/coverage/sync_alert/4.prim_sync_alert.3319042956 Jul 18 04:44:30 PM PDT 24 Jul 18 04:44:33 PM PDT 24 9436043 ps
T27 /workspace/coverage/sync_alert/12.prim_sync_alert.3065789062 Jul 18 04:44:33 PM PDT 24 Jul 18 04:44:34 PM PDT 24 9592352 ps
T37 /workspace/coverage/sync_alert/14.prim_sync_alert.2357924002 Jul 18 04:44:26 PM PDT 24 Jul 18 04:44:29 PM PDT 24 10162811 ps
T38 /workspace/coverage/sync_alert/18.prim_sync_alert.4212824941 Jul 18 04:45:40 PM PDT 24 Jul 18 04:45:47 PM PDT 24 9350894 ps
T28 /workspace/coverage/sync_alert/3.prim_sync_alert.1299252329 Jul 18 04:44:28 PM PDT 24 Jul 18 04:44:30 PM PDT 24 8719822 ps
T60 /workspace/coverage/sync_alert/7.prim_sync_alert.2988553177 Jul 18 04:44:27 PM PDT 24 Jul 18 04:44:30 PM PDT 24 9060296 ps
T29 /workspace/coverage/sync_alert/8.prim_sync_alert.2166543254 Jul 18 04:44:25 PM PDT 24 Jul 18 04:44:26 PM PDT 24 10020437 ps
T61 /workspace/coverage/sync_alert/11.prim_sync_alert.658537676 Jul 18 04:44:26 PM PDT 24 Jul 18 04:44:28 PM PDT 24 9041915 ps
T62 /workspace/coverage/sync_alert/19.prim_sync_alert.2810281041 Jul 18 04:45:38 PM PDT 24 Jul 18 04:45:44 PM PDT 24 9728936 ps
T30 /workspace/coverage/sync_alert/0.prim_sync_alert.2146021373 Jul 18 04:44:27 PM PDT 24 Jul 18 04:44:29 PM PDT 24 9867001 ps
T63 /workspace/coverage/sync_alert/13.prim_sync_alert.2690298861 Jul 18 04:44:30 PM PDT 24 Jul 18 04:44:33 PM PDT 24 9355711 ps
T64 /workspace/coverage/sync_alert/1.prim_sync_alert.2448474839 Jul 18 04:56:39 PM PDT 24 Jul 18 04:56:40 PM PDT 24 9210127 ps
T65 /workspace/coverage/sync_alert/5.prim_sync_alert.3969611705 Jul 18 04:44:28 PM PDT 24 Jul 18 04:44:31 PM PDT 24 9565152 ps
T12 /workspace/coverage/sync_alert/10.prim_sync_alert.3928179493 Jul 18 04:44:32 PM PDT 24 Jul 18 04:44:34 PM PDT 24 9491147 ps
T31 /workspace/coverage/sync_alert/17.prim_sync_alert.4270444693 Jul 18 04:45:38 PM PDT 24 Jul 18 04:45:45 PM PDT 24 9657049 ps
T66 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3925140851 Jul 18 04:35:45 PM PDT 24 Jul 18 04:35:47 PM PDT 24 28938749 ps
T67 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1427388160 Jul 18 04:35:42 PM PDT 24 Jul 18 04:35:44 PM PDT 24 29578976 ps
T68 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.965918753 Jul 18 04:35:48 PM PDT 24 Jul 18 04:35:49 PM PDT 24 29106848 ps
T32 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3045901036 Jul 18 04:37:03 PM PDT 24 Jul 18 04:37:04 PM PDT 24 28507849 ps
T69 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.947904354 Jul 18 04:35:52 PM PDT 24 Jul 18 04:35:53 PM PDT 24 27690438 ps
T33 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.141302183 Jul 18 04:35:44 PM PDT 24 Jul 18 04:35:45 PM PDT 24 27212794 ps
T70 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3335685033 Jul 18 04:35:52 PM PDT 24 Jul 18 04:35:53 PM PDT 24 28497038 ps
T71 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.691461318 Jul 18 04:35:52 PM PDT 24 Jul 18 04:35:53 PM PDT 24 26928032 ps
T72 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.773507269 Jul 18 04:35:45 PM PDT 24 Jul 18 04:35:46 PM PDT 24 28036344 ps
T73 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3026052661 Jul 18 04:35:45 PM PDT 24 Jul 18 04:35:47 PM PDT 24 28215194 ps
T74 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.332205804 Jul 18 04:35:44 PM PDT 24 Jul 18 04:35:46 PM PDT 24 27470164 ps
T4 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3520879464 Jul 18 04:37:03 PM PDT 24 Jul 18 04:37:04 PM PDT 24 29271436 ps
T75 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1009389970 Jul 18 04:35:42 PM PDT 24 Jul 18 04:35:44 PM PDT 24 28731647 ps
T76 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1492780569 Jul 18 04:35:44 PM PDT 24 Jul 18 04:35:47 PM PDT 24 27681622 ps
T77 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3986569644 Jul 18 04:36:20 PM PDT 24 Jul 18 04:36:22 PM PDT 24 25433989 ps
T5 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3338658467 Jul 18 04:35:52 PM PDT 24 Jul 18 04:35:53 PM PDT 24 27568877 ps
T78 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2792032528 Jul 18 04:35:42 PM PDT 24 Jul 18 04:35:43 PM PDT 24 27943879 ps
T79 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3840628969 Jul 18 04:35:45 PM PDT 24 Jul 18 04:35:47 PM PDT 24 27081577 ps
T6 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1718210642 Jul 18 04:37:03 PM PDT 24 Jul 18 04:37:04 PM PDT 24 26595567 ps
T80 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1581249090 Jul 18 04:35:52 PM PDT 24 Jul 18 04:35:54 PM PDT 24 24916724 ps

Test location /workspace/coverage/default/2.prim_async_alert.1963052507
Short name T2
Test name
Test status
Simulation time 11748194 ps
CPU time 0.4 seconds
Started Jul 18 05:16:38 PM PDT 24
Finished Jul 18 05:16:43 PM PDT 24
Peak memory 145744 kb
Host smart-aed1ae13-dfe9-42fb-8534-bafc2175e63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963052507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1963052507
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3319042956
Short name T36
Test name
Test status
Simulation time 9436043 ps
CPU time 0.37 seconds
Started Jul 18 04:44:30 PM PDT 24
Finished Jul 18 04:44:33 PM PDT 24
Peak memory 146500 kb
Host smart-cacf8931-8a68-41fd-b7b4-e49dd433e886
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3319042956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3319042956
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.635285309
Short name T18
Test name
Test status
Simulation time 31168367 ps
CPU time 0.42 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:00 PM PDT 24
Peak memory 145244 kb
Host smart-6c89a42e-33a5-49fb-9494-1bf50be472cc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=635285309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.635285309
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2718236188
Short name T13
Test name
Test status
Simulation time 12130792 ps
CPU time 0.39 seconds
Started Jul 18 05:16:32 PM PDT 24
Finished Jul 18 05:16:38 PM PDT 24
Peak memory 145800 kb
Host smart-1967743f-bdbe-44e2-ab25-48934cc86df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718236188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2718236188
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3928179493
Short name T12
Test name
Test status
Simulation time 9491147 ps
CPU time 0.39 seconds
Started Jul 18 04:44:32 PM PDT 24
Finished Jul 18 04:44:34 PM PDT 24
Peak memory 146328 kb
Host smart-56ad97cc-839a-485a-9a61-bbd627115715
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3928179493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3928179493
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1718210642
Short name T6
Test name
Test status
Simulation time 26595567 ps
CPU time 0.44 seconds
Started Jul 18 04:37:03 PM PDT 24
Finished Jul 18 04:37:04 PM PDT 24
Peak memory 144116 kb
Host smart-53acbb5c-7a93-4980-9b31-f4f408c6514d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1718210642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1718210642
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2762276887
Short name T19
Test name
Test status
Simulation time 11557700 ps
CPU time 0.4 seconds
Started Jul 18 05:16:33 PM PDT 24
Finished Jul 18 05:16:39 PM PDT 24
Peak memory 145712 kb
Host smart-9cdf386e-3439-4f55-81cc-443c20d92171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762276887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2762276887
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2156250436
Short name T48
Test name
Test status
Simulation time 11760542 ps
CPU time 0.39 seconds
Started Jul 18 05:16:30 PM PDT 24
Finished Jul 18 05:16:34 PM PDT 24
Peak memory 145788 kb
Host smart-7be4c598-3b44-415a-99cc-a65d1f5c23e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156250436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2156250436
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3247866782
Short name T21
Test name
Test status
Simulation time 10935848 ps
CPU time 0.38 seconds
Started Jul 18 05:16:35 PM PDT 24
Finished Jul 18 05:16:42 PM PDT 24
Peak memory 145732 kb
Host smart-49d7fd78-dd8a-4a22-9c50-bd42dffe42e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247866782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3247866782
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1169126461
Short name T16
Test name
Test status
Simulation time 12324009 ps
CPU time 0.4 seconds
Started Jul 18 05:16:37 PM PDT 24
Finished Jul 18 05:16:42 PM PDT 24
Peak memory 145744 kb
Host smart-d8d9ad2b-c998-4328-8fb2-50a0e9ca9ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169126461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1169126461
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.651776943
Short name T23
Test name
Test status
Simulation time 11709277 ps
CPU time 0.4 seconds
Started Jul 18 05:16:37 PM PDT 24
Finished Jul 18 05:16:42 PM PDT 24
Peak memory 145740 kb
Host smart-1511c3e9-e292-4e31-85bc-e7350fdbda7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651776943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.651776943
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.427413368
Short name T20
Test name
Test status
Simulation time 12594484 ps
CPU time 0.41 seconds
Started Jul 18 05:16:37 PM PDT 24
Finished Jul 18 05:16:42 PM PDT 24
Peak memory 145740 kb
Host smart-867054ee-e059-4cd5-a0bb-2b69254d7f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427413368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.427413368
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.3593473826
Short name T49
Test name
Test status
Simulation time 12001323 ps
CPU time 0.39 seconds
Started Jul 18 05:16:44 PM PDT 24
Finished Jul 18 05:16:46 PM PDT 24
Peak memory 145792 kb
Host smart-e3f2c4cd-03a7-4793-a1f9-1ff2364cd2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593473826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3593473826
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.467180607
Short name T22
Test name
Test status
Simulation time 11106114 ps
CPU time 0.39 seconds
Started Jul 18 05:16:43 PM PDT 24
Finished Jul 18 05:16:45 PM PDT 24
Peak memory 145724 kb
Host smart-a504c3dd-3eff-4854-9fa9-54ff06c62495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467180607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.467180607
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3872685065
Short name T47
Test name
Test status
Simulation time 11701893 ps
CPU time 0.4 seconds
Started Jul 18 05:16:32 PM PDT 24
Finished Jul 18 05:16:37 PM PDT 24
Peak memory 145776 kb
Host smart-6150ea31-b467-44f3-86d9-32ac104f2d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872685065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3872685065
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2070746364
Short name T9
Test name
Test status
Simulation time 11376117 ps
CPU time 0.38 seconds
Started Jul 18 05:16:37 PM PDT 24
Finished Jul 18 05:16:42 PM PDT 24
Peak memory 145732 kb
Host smart-2a45c5ab-a4e5-471a-b122-5cb19fd186c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070746364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2070746364
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3659552880
Short name T10
Test name
Test status
Simulation time 11258901 ps
CPU time 0.39 seconds
Started Jul 18 05:16:43 PM PDT 24
Finished Jul 18 05:16:45 PM PDT 24
Peak memory 145724 kb
Host smart-00235958-71d7-4f8b-9396-5f433210b80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659552880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3659552880
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1321947986
Short name T15
Test name
Test status
Simulation time 11520443 ps
CPU time 0.39 seconds
Started Jul 18 05:16:32 PM PDT 24
Finished Jul 18 05:16:37 PM PDT 24
Peak memory 145760 kb
Host smart-4231866d-df22-4f7a-80ce-d455e44c32af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321947986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1321947986
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1695869597
Short name T1
Test name
Test status
Simulation time 11193475 ps
CPU time 0.38 seconds
Started Jul 18 05:16:33 PM PDT 24
Finished Jul 18 05:16:39 PM PDT 24
Peak memory 145720 kb
Host smart-a712fa96-5607-4ca3-9f85-fa02329a1b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695869597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1695869597
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2170467438
Short name T8
Test name
Test status
Simulation time 12180420 ps
CPU time 0.4 seconds
Started Jul 18 05:16:39 PM PDT 24
Finished Jul 18 05:16:43 PM PDT 24
Peak memory 145736 kb
Host smart-9f1651ec-7067-4f41-9f5f-f72c5074e127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170467438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2170467438
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3372399171
Short name T50
Test name
Test status
Simulation time 10783246 ps
CPU time 0.38 seconds
Started Jul 18 05:16:37 PM PDT 24
Finished Jul 18 05:16:42 PM PDT 24
Peak memory 145728 kb
Host smart-2027594b-5f89-4d02-ab14-f94b9b29c568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372399171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3372399171
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2506432946
Short name T3
Test name
Test status
Simulation time 11740844 ps
CPU time 0.4 seconds
Started Jul 18 05:16:35 PM PDT 24
Finished Jul 18 05:16:41 PM PDT 24
Peak memory 145796 kb
Host smart-071f7407-3f72-4bc0-9268-733c061c3db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506432946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2506432946
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2546313559
Short name T17
Test name
Test status
Simulation time 11520279 ps
CPU time 0.41 seconds
Started Jul 18 05:16:34 PM PDT 24
Finished Jul 18 05:16:40 PM PDT 24
Peak memory 145728 kb
Host smart-7f713386-e304-45b5-bf85-f8a5566974c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546313559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2546313559
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2865310014
Short name T7
Test name
Test status
Simulation time 9921573 ps
CPU time 0.39 seconds
Started Jul 18 05:16:38 PM PDT 24
Finished Jul 18 05:16:43 PM PDT 24
Peak memory 145740 kb
Host smart-a5afc1cd-b0b2-4634-af2b-9334a11560fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865310014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2865310014
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4016215777
Short name T39
Test name
Test status
Simulation time 30740872 ps
CPU time 0.42 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:58 PM PDT 24
Peak memory 145252 kb
Host smart-6d0913a1-9f43-436e-9f04-ddb2fc8cbfd8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4016215777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4016215777
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.295352144
Short name T59
Test name
Test status
Simulation time 31234117 ps
CPU time 0.42 seconds
Started Jul 18 05:35:58 PM PDT 24
Finished Jul 18 05:36:03 PM PDT 24
Peak memory 145336 kb
Host smart-50d0bdee-e979-414e-baf6-e19dfcbd2196
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=295352144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.295352144
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2110160964
Short name T52
Test name
Test status
Simulation time 31421617 ps
CPU time 0.42 seconds
Started Jul 18 05:35:56 PM PDT 24
Finished Jul 18 05:36:02 PM PDT 24
Peak memory 145256 kb
Host smart-3e2c4feb-e5b8-414e-91e3-1154b095db91
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2110160964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2110160964
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3966132652
Short name T45
Test name
Test status
Simulation time 30198614 ps
CPU time 0.41 seconds
Started Jul 18 05:35:53 PM PDT 24
Finished Jul 18 05:35:59 PM PDT 24
Peak memory 145244 kb
Host smart-8df17889-d8a4-4a0f-8983-9a3561146806
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3966132652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3966132652
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2430091156
Short name T56
Test name
Test status
Simulation time 34124982 ps
CPU time 0.41 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 145300 kb
Host smart-d946f246-a446-495d-a5e8-91b1cec8a9e7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2430091156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2430091156
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1074679202
Short name T51
Test name
Test status
Simulation time 30268035 ps
CPU time 0.43 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:57 PM PDT 24
Peak memory 145340 kb
Host smart-d44a55fd-9d3a-4b05-a37d-185b390029b9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1074679202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1074679202
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2276378395
Short name T46
Test name
Test status
Simulation time 30694568 ps
CPU time 0.43 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:00 PM PDT 24
Peak memory 145300 kb
Host smart-f769ea88-cdb4-44a9-a963-35702588a779
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2276378395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2276378395
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.546218680
Short name T53
Test name
Test status
Simulation time 29036318 ps
CPU time 0.4 seconds
Started Jul 18 05:35:49 PM PDT 24
Finished Jul 18 05:35:53 PM PDT 24
Peak memory 145332 kb
Host smart-cbda359e-31b4-42dc-b3e7-fee79b452335
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=546218680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.546218680
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2653789732
Short name T14
Test name
Test status
Simulation time 31108904 ps
CPU time 0.39 seconds
Started Jul 18 05:36:12 PM PDT 24
Finished Jul 18 05:36:20 PM PDT 24
Peak memory 145216 kb
Host smart-cbf8e92e-e31a-47eb-9e4d-b1ecb742276f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2653789732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2653789732
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2840297157
Short name T57
Test name
Test status
Simulation time 31711965 ps
CPU time 0.41 seconds
Started Jul 18 05:36:09 PM PDT 24
Finished Jul 18 05:36:15 PM PDT 24
Peak memory 145240 kb
Host smart-fc6084e9-d97c-4dc7-91e5-04f0799a93d3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2840297157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2840297157
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.45478159
Short name T44
Test name
Test status
Simulation time 31518662 ps
CPU time 0.41 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:36:15 PM PDT 24
Peak memory 145232 kb
Host smart-3012ee19-bf8c-4b7e-8dd6-7af35e29f9cc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=45478159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.45478159
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.591446597
Short name T43
Test name
Test status
Simulation time 29049418 ps
CPU time 0.4 seconds
Started Jul 18 05:35:56 PM PDT 24
Finished Jul 18 05:36:02 PM PDT 24
Peak memory 145316 kb
Host smart-28e51c6d-62d2-481e-8e99-81e6012dfafc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=591446597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.591446597
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1832406438
Short name T55
Test name
Test status
Simulation time 31023381 ps
CPU time 0.41 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:58 PM PDT 24
Peak memory 145264 kb
Host smart-9463e01c-ff61-4363-a556-23b1425bdf06
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1832406438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1832406438
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2930759275
Short name T24
Test name
Test status
Simulation time 26527246 ps
CPU time 0.41 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:57 PM PDT 24
Peak memory 145244 kb
Host smart-eaaffe07-cb24-4158-b1c7-2152ac3b209e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2930759275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2930759275
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.183531444
Short name T41
Test name
Test status
Simulation time 30186334 ps
CPU time 0.44 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 145336 kb
Host smart-9424fc9b-c6c0-4cd3-b280-81784043974a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=183531444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.183531444
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.242324603
Short name T42
Test name
Test status
Simulation time 28089260 ps
CPU time 0.41 seconds
Started Jul 18 05:35:53 PM PDT 24
Finished Jul 18 05:35:58 PM PDT 24
Peak memory 145260 kb
Host smart-03260d7f-e000-4bd7-91cd-d21939baab3d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=242324603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.242324603
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1563866308
Short name T58
Test name
Test status
Simulation time 30401626 ps
CPU time 0.46 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:57 PM PDT 24
Peak memory 145240 kb
Host smart-0f1c97f1-a4be-41e4-89f4-4983b01ef0d8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1563866308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1563866308
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.409742174
Short name T54
Test name
Test status
Simulation time 30307204 ps
CPU time 0.43 seconds
Started Jul 18 05:35:55 PM PDT 24
Finished Jul 18 05:36:02 PM PDT 24
Peak memory 145256 kb
Host smart-88891f16-6e69-4607-a309-ad53012803ee
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=409742174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.409742174
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1135325122
Short name T40
Test name
Test status
Simulation time 29977863 ps
CPU time 0.45 seconds
Started Jul 18 05:35:55 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 145264 kb
Host smart-38ad07a2-1868-40ba-a287-7cc9a7d2842a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1135325122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1135325122
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2146021373
Short name T30
Test name
Test status
Simulation time 9867001 ps
CPU time 0.38 seconds
Started Jul 18 04:44:27 PM PDT 24
Finished Jul 18 04:44:29 PM PDT 24
Peak memory 145440 kb
Host smart-930868d2-4bea-4b0a-86fa-7fd4cb4fd977
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2146021373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2146021373
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2448474839
Short name T64
Test name
Test status
Simulation time 9210127 ps
CPU time 0.38 seconds
Started Jul 18 04:56:39 PM PDT 24
Finished Jul 18 04:56:40 PM PDT 24
Peak memory 145468 kb
Host smart-8055ce3d-3494-46cb-9ffd-f180b0d1f4df
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2448474839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2448474839
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.658537676
Short name T61
Test name
Test status
Simulation time 9041915 ps
CPU time 0.36 seconds
Started Jul 18 04:44:26 PM PDT 24
Finished Jul 18 04:44:28 PM PDT 24
Peak memory 145476 kb
Host smart-58c00d75-1d8e-4f68-ac76-9cea6056f856
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=658537676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.658537676
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3065789062
Short name T27
Test name
Test status
Simulation time 9592352 ps
CPU time 0.4 seconds
Started Jul 18 04:44:33 PM PDT 24
Finished Jul 18 04:44:34 PM PDT 24
Peak memory 145100 kb
Host smart-cbbea5f1-caa6-46eb-9334-9031f743427a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3065789062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3065789062
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2690298861
Short name T63
Test name
Test status
Simulation time 9355711 ps
CPU time 0.37 seconds
Started Jul 18 04:44:30 PM PDT 24
Finished Jul 18 04:44:33 PM PDT 24
Peak memory 146608 kb
Host smart-8d88e1a4-addf-49b3-a5f0-0b078f5aa5ce
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2690298861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2690298861
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2357924002
Short name T37
Test name
Test status
Simulation time 10162811 ps
CPU time 0.38 seconds
Started Jul 18 04:44:26 PM PDT 24
Finished Jul 18 04:44:29 PM PDT 24
Peak memory 145488 kb
Host smart-007c20f5-7ed9-4ed0-8cc5-14c37fa919af
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2357924002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2357924002
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.952486234
Short name T11
Test name
Test status
Simulation time 8614785 ps
CPU time 0.37 seconds
Started Jul 18 04:44:25 PM PDT 24
Finished Jul 18 04:44:26 PM PDT 24
Peak memory 145484 kb
Host smart-c8a2d36a-3a41-481b-a12d-f414eaddcf0b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=952486234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.952486234
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.4124508672
Short name T26
Test name
Test status
Simulation time 8731178 ps
CPU time 0.37 seconds
Started Jul 18 04:45:35 PM PDT 24
Finished Jul 18 04:45:40 PM PDT 24
Peak memory 145452 kb
Host smart-24bcfbcb-37ab-469f-9937-2ff81b20c139
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4124508672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.4124508672
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.4270444693
Short name T31
Test name
Test status
Simulation time 9657049 ps
CPU time 0.38 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 04:45:45 PM PDT 24
Peak memory 145664 kb
Host smart-a23d5049-bd71-4ff8-a21a-70a0fd4333a8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4270444693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.4270444693
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.4212824941
Short name T38
Test name
Test status
Simulation time 9350894 ps
CPU time 0.39 seconds
Started Jul 18 04:45:40 PM PDT 24
Finished Jul 18 04:45:47 PM PDT 24
Peak memory 145436 kb
Host smart-d558faef-52c1-4ac5-90b8-8502bbe21ece
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4212824941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.4212824941
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2810281041
Short name T62
Test name
Test status
Simulation time 9728936 ps
CPU time 0.39 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 04:45:44 PM PDT 24
Peak memory 145472 kb
Host smart-645a2bde-b31f-419f-b633-ad1834b829ea
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2810281041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2810281041
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.617508910
Short name T25
Test name
Test status
Simulation time 8802960 ps
CPU time 0.38 seconds
Started Jul 18 04:44:26 PM PDT 24
Finished Jul 18 04:44:29 PM PDT 24
Peak memory 145484 kb
Host smart-c8cb2e2d-55de-4d24-b512-c6054b33e49c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=617508910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.617508910
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1299252329
Short name T28
Test name
Test status
Simulation time 8719822 ps
CPU time 0.38 seconds
Started Jul 18 04:44:28 PM PDT 24
Finished Jul 18 04:44:30 PM PDT 24
Peak memory 145436 kb
Host smart-b65bfc65-edbd-42c3-b6fe-76070a46947b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1299252329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1299252329
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3969611705
Short name T65
Test name
Test status
Simulation time 9565152 ps
CPU time 0.37 seconds
Started Jul 18 04:44:28 PM PDT 24
Finished Jul 18 04:44:31 PM PDT 24
Peak memory 145436 kb
Host smart-15aa6321-b670-49a5-a6f8-3430d2e0f53f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3969611705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3969611705
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3235449146
Short name T34
Test name
Test status
Simulation time 9788996 ps
CPU time 0.39 seconds
Started Jul 18 04:44:30 PM PDT 24
Finished Jul 18 04:44:32 PM PDT 24
Peak memory 145436 kb
Host smart-ae7751d9-5d3f-4f91-9ea8-899b15835987
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3235449146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3235449146
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2988553177
Short name T60
Test name
Test status
Simulation time 9060296 ps
CPU time 0.38 seconds
Started Jul 18 04:44:27 PM PDT 24
Finished Jul 18 04:44:30 PM PDT 24
Peak memory 145436 kb
Host smart-caf4a17c-3515-42e5-b346-5f743df45cbc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2988553177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2988553177
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2166543254
Short name T29
Test name
Test status
Simulation time 10020437 ps
CPU time 0.38 seconds
Started Jul 18 04:44:25 PM PDT 24
Finished Jul 18 04:44:26 PM PDT 24
Peak memory 145664 kb
Host smart-508c0377-996c-4fa0-b730-d4738052f3e7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2166543254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2166543254
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.29528980
Short name T35
Test name
Test status
Simulation time 9002078 ps
CPU time 0.37 seconds
Started Jul 18 04:44:29 PM PDT 24
Finished Jul 18 04:44:31 PM PDT 24
Peak memory 145468 kb
Host smart-3eab314e-56ba-4fc4-9911-f775e3b4d4f2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=29528980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.29528980
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.773507269
Short name T72
Test name
Test status
Simulation time 28036344 ps
CPU time 0.42 seconds
Started Jul 18 04:35:45 PM PDT 24
Finished Jul 18 04:35:46 PM PDT 24
Peak memory 145216 kb
Host smart-09912ffc-4eac-4904-9882-0cec7f872c00
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=773507269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.773507269
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3925140851
Short name T66
Test name
Test status
Simulation time 28938749 ps
CPU time 0.46 seconds
Started Jul 18 04:35:45 PM PDT 24
Finished Jul 18 04:35:47 PM PDT 24
Peak memory 145860 kb
Host smart-76215310-74b7-45a9-a806-86c4b2eacc11
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3925140851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3925140851
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3045901036
Short name T32
Test name
Test status
Simulation time 28507849 ps
CPU time 0.42 seconds
Started Jul 18 04:37:03 PM PDT 24
Finished Jul 18 04:37:04 PM PDT 24
Peak memory 144372 kb
Host smart-e9c8c4f6-68ab-4f2f-9062-cd740c52c1e7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3045901036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3045901036
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3026052661
Short name T73
Test name
Test status
Simulation time 28215194 ps
CPU time 0.49 seconds
Started Jul 18 04:35:45 PM PDT 24
Finished Jul 18 04:35:47 PM PDT 24
Peak memory 145848 kb
Host smart-e530b008-6bfa-44ac-9401-3fcdfe70e287
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3026052661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3026052661
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.947904354
Short name T69
Test name
Test status
Simulation time 27690438 ps
CPU time 0.41 seconds
Started Jul 18 04:35:52 PM PDT 24
Finished Jul 18 04:35:53 PM PDT 24
Peak memory 144988 kb
Host smart-77118617-d6fd-4c25-957e-edd97abd2025
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=947904354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.947904354
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.691461318
Short name T71
Test name
Test status
Simulation time 26928032 ps
CPU time 0.44 seconds
Started Jul 18 04:35:52 PM PDT 24
Finished Jul 18 04:35:53 PM PDT 24
Peak memory 144356 kb
Host smart-00b38bcf-7c11-477e-97b6-fedffb85d6d8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=691461318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.691461318
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3338658467
Short name T5
Test name
Test status
Simulation time 27568877 ps
CPU time 0.4 seconds
Started Jul 18 04:35:52 PM PDT 24
Finished Jul 18 04:35:53 PM PDT 24
Peak memory 145032 kb
Host smart-54adea6e-18f0-48fa-8af0-8c02496ad876
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3338658467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3338658467
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.965918753
Short name T68
Test name
Test status
Simulation time 29106848 ps
CPU time 0.49 seconds
Started Jul 18 04:35:48 PM PDT 24
Finished Jul 18 04:35:49 PM PDT 24
Peak memory 145856 kb
Host smart-7366c2ad-8a98-4655-b7ee-7249160f6549
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=965918753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.965918753
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3986569644
Short name T77
Test name
Test status
Simulation time 25433989 ps
CPU time 0.45 seconds
Started Jul 18 04:36:20 PM PDT 24
Finished Jul 18 04:36:22 PM PDT 24
Peak memory 145848 kb
Host smart-ca27a76e-5302-4613-96e5-55d4dbc31543
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3986569644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3986569644
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3335685033
Short name T70
Test name
Test status
Simulation time 28497038 ps
CPU time 0.46 seconds
Started Jul 18 04:35:52 PM PDT 24
Finished Jul 18 04:35:53 PM PDT 24
Peak memory 144504 kb
Host smart-49c65a89-6db0-4958-a8da-a74bf5763ac6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3335685033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3335685033
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.141302183
Short name T33
Test name
Test status
Simulation time 27212794 ps
CPU time 0.39 seconds
Started Jul 18 04:35:44 PM PDT 24
Finished Jul 18 04:35:45 PM PDT 24
Peak memory 145188 kb
Host smart-3ff6d9da-8554-4587-bdef-b680e996cfd5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=141302183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.141302183
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1427388160
Short name T67
Test name
Test status
Simulation time 29578976 ps
CPU time 0.4 seconds
Started Jul 18 04:35:42 PM PDT 24
Finished Jul 18 04:35:44 PM PDT 24
Peak memory 145204 kb
Host smart-09db249b-cdb0-4fea-a2ba-bd194b5189ec
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1427388160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1427388160
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3840628969
Short name T79
Test name
Test status
Simulation time 27081577 ps
CPU time 0.47 seconds
Started Jul 18 04:35:45 PM PDT 24
Finished Jul 18 04:35:47 PM PDT 24
Peak memory 145824 kb
Host smart-4cc2019b-07f8-4d8e-ba2a-ee129de751ac
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3840628969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3840628969
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.332205804
Short name T74
Test name
Test status
Simulation time 27470164 ps
CPU time 0.4 seconds
Started Jul 18 04:35:44 PM PDT 24
Finished Jul 18 04:35:46 PM PDT 24
Peak memory 145256 kb
Host smart-828f918e-5f43-40d5-94ec-df9f99962484
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=332205804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.332205804
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1492780569
Short name T76
Test name
Test status
Simulation time 27681622 ps
CPU time 0.44 seconds
Started Jul 18 04:35:44 PM PDT 24
Finished Jul 18 04:35:47 PM PDT 24
Peak memory 145856 kb
Host smart-bd9e9aa7-849b-49c9-932c-11c2168c92ea
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1492780569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1492780569
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3520879464
Short name T4
Test name
Test status
Simulation time 29271436 ps
CPU time 0.44 seconds
Started Jul 18 04:37:03 PM PDT 24
Finished Jul 18 04:37:04 PM PDT 24
Peak memory 143392 kb
Host smart-8fd0fcf0-8c5b-4980-a5bf-0f699c4fa4b1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3520879464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3520879464
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1581249090
Short name T80
Test name
Test status
Simulation time 24916724 ps
CPU time 0.41 seconds
Started Jul 18 04:35:52 PM PDT 24
Finished Jul 18 04:35:54 PM PDT 24
Peak memory 145224 kb
Host smart-1d6068b5-729b-4cae-b752-bd374ceeff4c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1581249090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1581249090
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2792032528
Short name T78
Test name
Test status
Simulation time 27943879 ps
CPU time 0.42 seconds
Started Jul 18 04:35:42 PM PDT 24
Finished Jul 18 04:35:43 PM PDT 24
Peak memory 145232 kb
Host smart-ab2f02c0-7182-4951-bbff-8ddcb5ed5e76
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2792032528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2792032528
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1009389970
Short name T75
Test name
Test status
Simulation time 28731647 ps
CPU time 0.4 seconds
Started Jul 18 04:35:42 PM PDT 24
Finished Jul 18 04:35:44 PM PDT 24
Peak memory 145208 kb
Host smart-0508ab24-1e1e-4d27-837a-5b1b28c2fa04
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1009389970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1009389970
Directory /workspace/9.prim_sync_fatal_alert/latest
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