Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 78
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 96.43 96.43 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/15.prim_async_alert.363817998
91.80 3.13 100.00 0.00 93.75 0.00 96.43 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/13.prim_sync_alert.2419018911
93.56 1.76 100.00 0.00 93.75 0.00 100.00 3.57 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4091739528
94.50 0.94 100.00 0.00 95.83 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/8.prim_async_alert.3274784747
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3036660288

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1579312508
/workspace/coverage/default/1.prim_async_alert.3805414014
/workspace/coverage/default/10.prim_async_alert.468145095
/workspace/coverage/default/11.prim_async_alert.1364089850
/workspace/coverage/default/13.prim_async_alert.2070905911
/workspace/coverage/default/14.prim_async_alert.61672688
/workspace/coverage/default/16.prim_async_alert.3458317693
/workspace/coverage/default/17.prim_async_alert.2483468895
/workspace/coverage/default/18.prim_async_alert.244821319
/workspace/coverage/default/19.prim_async_alert.3240856312
/workspace/coverage/default/2.prim_async_alert.521213093
/workspace/coverage/default/3.prim_async_alert.1359171989
/workspace/coverage/default/4.prim_async_alert.1748283995
/workspace/coverage/default/5.prim_async_alert.1361945489
/workspace/coverage/default/6.prim_async_alert.147311517
/workspace/coverage/default/7.prim_async_alert.2802077661
/workspace/coverage/default/9.prim_async_alert.3818996339
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2527101032
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1760181609
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1527115660
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.850874743
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.203411245
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4026118864
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3860171535
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1894313848
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3041527421
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1395325651
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4060828718
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2281654773
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3987389839
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3338205919
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1419664686
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1461577817
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.908359622
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2770696091
/workspace/coverage/sync_alert/0.prim_sync_alert.4046679052
/workspace/coverage/sync_alert/1.prim_sync_alert.1237266726
/workspace/coverage/sync_alert/10.prim_sync_alert.1793926798
/workspace/coverage/sync_alert/11.prim_sync_alert.178832620
/workspace/coverage/sync_alert/12.prim_sync_alert.3609809192
/workspace/coverage/sync_alert/14.prim_sync_alert.3190476319
/workspace/coverage/sync_alert/15.prim_sync_alert.1332688086
/workspace/coverage/sync_alert/16.prim_sync_alert.10258903
/workspace/coverage/sync_alert/17.prim_sync_alert.1777149551
/workspace/coverage/sync_alert/18.prim_sync_alert.2099547954
/workspace/coverage/sync_alert/19.prim_sync_alert.4206317376
/workspace/coverage/sync_alert/2.prim_sync_alert.3126977934
/workspace/coverage/sync_alert/3.prim_sync_alert.2420084535
/workspace/coverage/sync_alert/4.prim_sync_alert.3407404843
/workspace/coverage/sync_alert/5.prim_sync_alert.1164016159
/workspace/coverage/sync_alert/6.prim_sync_alert.2399344076
/workspace/coverage/sync_alert/7.prim_sync_alert.2536220091
/workspace/coverage/sync_alert/8.prim_sync_alert.1490024181
/workspace/coverage/sync_alert/9.prim_sync_alert.3091119437
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2623593402
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.961474737
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3109260048
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.138481886
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2461297985
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.82942422
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3993593422
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2717453782
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2113385369
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2960127367
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3204303947
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4224991308
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.426928738
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2427648211
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.623580110
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1668347242
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3336582316
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.370515132
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1239718911



Total test records in report: 78
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/6.prim_async_alert.147311517 Jul 19 04:17:08 PM PDT 24 Jul 19 04:17:09 PM PDT 24 11197818 ps
T2 /workspace/coverage/default/5.prim_async_alert.1361945489 Jul 19 04:21:03 PM PDT 24 Jul 19 04:21:04 PM PDT 24 11767568 ps
T3 /workspace/coverage/default/11.prim_async_alert.1364089850 Jul 19 04:22:43 PM PDT 24 Jul 19 04:22:46 PM PDT 24 12212409 ps
T6 /workspace/coverage/default/16.prim_async_alert.3458317693 Jul 19 04:17:24 PM PDT 24 Jul 19 04:17:25 PM PDT 24 11702352 ps
T13 /workspace/coverage/default/14.prim_async_alert.61672688 Jul 19 04:23:07 PM PDT 24 Jul 19 04:23:19 PM PDT 24 10736367 ps
T9 /workspace/coverage/default/17.prim_async_alert.2483468895 Jul 19 04:23:08 PM PDT 24 Jul 19 04:23:21 PM PDT 24 11737237 ps
T10 /workspace/coverage/default/1.prim_async_alert.3805414014 Jul 19 04:23:07 PM PDT 24 Jul 19 04:23:18 PM PDT 24 11525252 ps
T11 /workspace/coverage/default/7.prim_async_alert.2802077661 Jul 19 04:22:39 PM PDT 24 Jul 19 04:22:41 PM PDT 24 12303803 ps
T7 /workspace/coverage/default/15.prim_async_alert.363817998 Jul 19 04:23:08 PM PDT 24 Jul 19 04:23:21 PM PDT 24 11230516 ps
T14 /workspace/coverage/default/4.prim_async_alert.1748283995 Jul 19 04:22:42 PM PDT 24 Jul 19 04:22:45 PM PDT 24 10888646 ps
T8 /workspace/coverage/default/10.prim_async_alert.468145095 Jul 19 04:22:52 PM PDT 24 Jul 19 04:22:53 PM PDT 24 11944450 ps
T15 /workspace/coverage/default/3.prim_async_alert.1359171989 Jul 19 04:21:18 PM PDT 24 Jul 19 04:21:19 PM PDT 24 12248689 ps
T16 /workspace/coverage/default/0.prim_async_alert.1579312508 Jul 19 04:22:59 PM PDT 24 Jul 19 04:23:02 PM PDT 24 11113895 ps
T41 /workspace/coverage/default/2.prim_async_alert.521213093 Jul 19 04:21:12 PM PDT 24 Jul 19 04:21:13 PM PDT 24 11342072 ps
T42 /workspace/coverage/default/9.prim_async_alert.3818996339 Jul 19 04:22:51 PM PDT 24 Jul 19 04:22:53 PM PDT 24 11325243 ps
T17 /workspace/coverage/default/13.prim_async_alert.2070905911 Jul 19 04:21:33 PM PDT 24 Jul 19 04:21:34 PM PDT 24 10889734 ps
T43 /workspace/coverage/default/8.prim_async_alert.3274784747 Jul 19 04:21:29 PM PDT 24 Jul 19 04:21:30 PM PDT 24 12450419 ps
T44 /workspace/coverage/default/18.prim_async_alert.244821319 Jul 19 04:22:40 PM PDT 24 Jul 19 04:22:43 PM PDT 24 10730847 ps
T45 /workspace/coverage/default/19.prim_async_alert.3240856312 Jul 19 04:23:00 PM PDT 24 Jul 19 04:23:04 PM PDT 24 12033632 ps
T32 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1419664686 Jul 19 04:23:07 PM PDT 24 Jul 19 04:23:16 PM PDT 24 33889823 ps
T33 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.908359622 Jul 19 04:17:03 PM PDT 24 Jul 19 04:17:04 PM PDT 24 29301783 ps
T34 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4091739528 Jul 19 04:23:08 PM PDT 24 Jul 19 04:23:21 PM PDT 24 32194672 ps
T35 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2281654773 Jul 19 04:23:00 PM PDT 24 Jul 19 04:23:04 PM PDT 24 27743799 ps
T36 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3860171535 Jul 19 04:23:07 PM PDT 24 Jul 19 04:23:19 PM PDT 24 29536165 ps
T12 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3041527421 Jul 19 04:23:00 PM PDT 24 Jul 19 04:23:04 PM PDT 24 30424201 ps
T37 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4060828718 Jul 19 04:17:08 PM PDT 24 Jul 19 04:17:09 PM PDT 24 28656965 ps
T38 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.203411245 Jul 19 04:23:00 PM PDT 24 Jul 19 04:23:03 PM PDT 24 28431510 ps
T39 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3987389839 Jul 19 04:23:00 PM PDT 24 Jul 19 04:23:04 PM PDT 24 29992831 ps
T40 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2527101032 Jul 19 04:21:01 PM PDT 24 Jul 19 04:21:02 PM PDT 24 28904739 ps
T46 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1527115660 Jul 19 04:22:53 PM PDT 24 Jul 19 04:22:55 PM PDT 24 30659582 ps
T47 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1894313848 Jul 19 04:23:08 PM PDT 24 Jul 19 04:23:21 PM PDT 24 30658852 ps
T48 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1760181609 Jul 19 04:22:37 PM PDT 24 Jul 19 04:22:38 PM PDT 24 30455990 ps
T49 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1461577817 Jul 19 04:21:02 PM PDT 24 Jul 19 04:21:03 PM PDT 24 29503600 ps
T50 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.850874743 Jul 19 04:20:53 PM PDT 24 Jul 19 04:20:54 PM PDT 24 29379402 ps
T51 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3338205919 Jul 19 04:22:39 PM PDT 24 Jul 19 04:22:41 PM PDT 24 30304195 ps
T52 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2770696091 Jul 19 04:22:58 PM PDT 24 Jul 19 04:23:01 PM PDT 24 31226213 ps
T53 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4026118864 Jul 19 04:21:18 PM PDT 24 Jul 19 04:21:19 PM PDT 24 29464662 ps
T54 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1395325651 Jul 19 04:23:00 PM PDT 24 Jul 19 04:23:03 PM PDT 24 31133790 ps
T27 /workspace/coverage/sync_alert/19.prim_sync_alert.4206317376 Jul 19 04:22:58 PM PDT 24 Jul 19 04:23:02 PM PDT 24 7762264 ps
T18 /workspace/coverage/sync_alert/11.prim_sync_alert.178832620 Jul 19 04:20:57 PM PDT 24 Jul 19 04:20:58 PM PDT 24 10194604 ps
T19 /workspace/coverage/sync_alert/2.prim_sync_alert.3126977934 Jul 19 04:22:27 PM PDT 24 Jul 19 04:22:29 PM PDT 24 9377633 ps
T28 /workspace/coverage/sync_alert/10.prim_sync_alert.1793926798 Jul 19 04:23:08 PM PDT 24 Jul 19 04:23:20 PM PDT 24 9741515 ps
T20 /workspace/coverage/sync_alert/13.prim_sync_alert.2419018911 Jul 19 04:23:00 PM PDT 24 Jul 19 04:23:04 PM PDT 24 8793732 ps
T29 /workspace/coverage/sync_alert/18.prim_sync_alert.2099547954 Jul 19 04:23:00 PM PDT 24 Jul 19 04:23:04 PM PDT 24 9242993 ps
T30 /workspace/coverage/sync_alert/14.prim_sync_alert.3190476319 Jul 19 04:22:40 PM PDT 24 Jul 19 04:22:43 PM PDT 24 9797812 ps
T31 /workspace/coverage/sync_alert/5.prim_sync_alert.1164016159 Jul 19 04:20:52 PM PDT 24 Jul 19 04:20:53 PM PDT 24 10130784 ps
T21 /workspace/coverage/sync_alert/0.prim_sync_alert.4046679052 Jul 19 04:23:00 PM PDT 24 Jul 19 04:23:04 PM PDT 24 8810464 ps
T22 /workspace/coverage/sync_alert/9.prim_sync_alert.3091119437 Jul 19 04:23:00 PM PDT 24 Jul 19 04:23:03 PM PDT 24 8952250 ps
T55 /workspace/coverage/sync_alert/15.prim_sync_alert.1332688086 Jul 19 04:17:24 PM PDT 24 Jul 19 04:17:25 PM PDT 24 9481317 ps
T23 /workspace/coverage/sync_alert/7.prim_sync_alert.2536220091 Jul 19 04:23:12 PM PDT 24 Jul 19 04:23:37 PM PDT 24 8963108 ps
T24 /workspace/coverage/sync_alert/16.prim_sync_alert.10258903 Jul 19 04:22:27 PM PDT 24 Jul 19 04:22:29 PM PDT 24 9583560 ps
T56 /workspace/coverage/sync_alert/6.prim_sync_alert.2399344076 Jul 19 04:22:40 PM PDT 24 Jul 19 04:22:42 PM PDT 24 9704471 ps
T25 /workspace/coverage/sync_alert/3.prim_sync_alert.2420084535 Jul 19 04:22:44 PM PDT 24 Jul 19 04:22:47 PM PDT 24 9445176 ps
T57 /workspace/coverage/sync_alert/17.prim_sync_alert.1777149551 Jul 19 04:23:00 PM PDT 24 Jul 19 04:23:04 PM PDT 24 9076600 ps
T26 /workspace/coverage/sync_alert/8.prim_sync_alert.1490024181 Jul 19 04:22:39 PM PDT 24 Jul 19 04:22:41 PM PDT 24 10026791 ps
T58 /workspace/coverage/sync_alert/12.prim_sync_alert.3609809192 Jul 19 04:23:08 PM PDT 24 Jul 19 04:23:20 PM PDT 24 8819328 ps
T59 /workspace/coverage/sync_alert/1.prim_sync_alert.1237266726 Jul 19 04:22:52 PM PDT 24 Jul 19 04:22:54 PM PDT 24 9825747 ps
T60 /workspace/coverage/sync_alert/4.prim_sync_alert.3407404843 Jul 19 04:23:08 PM PDT 24 Jul 19 04:23:20 PM PDT 24 8429185 ps
T4 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3036660288 Jul 19 04:23:00 PM PDT 24 Jul 19 04:23:03 PM PDT 24 28098765 ps
T61 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2427648211 Jul 19 04:23:07 PM PDT 24 Jul 19 04:23:18 PM PDT 24 27118574 ps
T62 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1668347242 Jul 19 04:22:55 PM PDT 24 Jul 19 04:22:57 PM PDT 24 26940040 ps
T63 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.370515132 Jul 19 04:19:16 PM PDT 24 Jul 19 04:19:17 PM PDT 24 28456707 ps
T64 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.623580110 Jul 19 04:23:07 PM PDT 24 Jul 19 04:23:18 PM PDT 24 27392395 ps
T65 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2960127367 Jul 19 04:22:44 PM PDT 24 Jul 19 04:22:47 PM PDT 24 26265400 ps
T66 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4224991308 Jul 19 04:20:35 PM PDT 24 Jul 19 04:20:36 PM PDT 24 27363334 ps
T67 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.961474737 Jul 19 04:23:08 PM PDT 24 Jul 19 04:23:19 PM PDT 24 25871732 ps
T68 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2461297985 Jul 19 04:20:27 PM PDT 24 Jul 19 04:20:28 PM PDT 24 26014468 ps
T69 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1239718911 Jul 19 04:21:45 PM PDT 24 Jul 19 04:21:47 PM PDT 24 27846684 ps
T70 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3993593422 Jul 19 04:23:01 PM PDT 24 Jul 19 04:23:05 PM PDT 24 28388109 ps
T71 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.138481886 Jul 19 04:23:04 PM PDT 24 Jul 19 04:23:10 PM PDT 24 27434457 ps
T72 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2623593402 Jul 19 04:21:07 PM PDT 24 Jul 19 04:21:08 PM PDT 24 27294507 ps
T73 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.426928738 Jul 19 04:22:55 PM PDT 24 Jul 19 04:22:57 PM PDT 24 24695667 ps
T5 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3336582316 Jul 19 04:22:39 PM PDT 24 Jul 19 04:22:42 PM PDT 24 27401048 ps
T74 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3109260048 Jul 19 04:21:46 PM PDT 24 Jul 19 04:21:47 PM PDT 24 28141503 ps
T75 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2717453782 Jul 19 04:23:03 PM PDT 24 Jul 19 04:23:08 PM PDT 24 26796366 ps
T76 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.82942422 Jul 19 04:21:45 PM PDT 24 Jul 19 04:21:46 PM PDT 24 27690656 ps
T77 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2113385369 Jul 19 04:22:56 PM PDT 24 Jul 19 04:23:00 PM PDT 24 26118614 ps
T78 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3204303947 Jul 19 04:23:10 PM PDT 24 Jul 19 04:23:28 PM PDT 24 27694060 ps

Test location /workspace/coverage/default/15.prim_async_alert.363817998
Short name T7
Test name
Test status
Simulation time 11230516 ps
CPU time 0.38 seconds
Started Jul 19 04:23:08 PM PDT 24
Finished Jul 19 04:23:21 PM PDT 24
Peak memory 145556 kb
Host smart-7c520666-5755-498b-89ec-454ffe3d02f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363817998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.363817998
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2419018911
Short name T20
Test name
Test status
Simulation time 8793732 ps
CPU time 0.39 seconds
Started Jul 19 04:23:00 PM PDT 24
Finished Jul 19 04:23:04 PM PDT 24
Peak memory 145176 kb
Host smart-6f24592d-1535-40ca-997d-10803d317cac
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2419018911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2419018911
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4091739528
Short name T34
Test name
Test status
Simulation time 32194672 ps
CPU time 0.4 seconds
Started Jul 19 04:23:08 PM PDT 24
Finished Jul 19 04:23:21 PM PDT 24
Peak memory 145124 kb
Host smart-53ceaa31-f975-45b9-a2be-d965f8fc982a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4091739528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.4091739528
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3274784747
Short name T43
Test name
Test status
Simulation time 12450419 ps
CPU time 0.38 seconds
Started Jul 19 04:21:29 PM PDT 24
Finished Jul 19 04:21:30 PM PDT 24
Peak memory 145608 kb
Host smart-7aca2e6b-cf63-4075-879f-f981f70a64e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274784747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3274784747
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3036660288
Short name T4
Test name
Test status
Simulation time 28098765 ps
CPU time 0.39 seconds
Started Jul 19 04:23:00 PM PDT 24
Finished Jul 19 04:23:03 PM PDT 24
Peak memory 145184 kb
Host smart-44a333e6-47cb-4bd3-b0ef-f744397b7ce4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3036660288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3036660288
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1579312508
Short name T16
Test name
Test status
Simulation time 11113895 ps
CPU time 0.37 seconds
Started Jul 19 04:22:59 PM PDT 24
Finished Jul 19 04:23:02 PM PDT 24
Peak memory 145372 kb
Host smart-486cc86a-65b5-40dd-9c31-3115a1fdb50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579312508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1579312508
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3805414014
Short name T10
Test name
Test status
Simulation time 11525252 ps
CPU time 0.39 seconds
Started Jul 19 04:23:07 PM PDT 24
Finished Jul 19 04:23:18 PM PDT 24
Peak memory 145552 kb
Host smart-2c072730-3b4e-43b6-8000-f4a0b84d4adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805414014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3805414014
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.468145095
Short name T8
Test name
Test status
Simulation time 11944450 ps
CPU time 0.37 seconds
Started Jul 19 04:22:52 PM PDT 24
Finished Jul 19 04:22:53 PM PDT 24
Peak memory 145644 kb
Host smart-65611bac-174d-49bc-bf11-6a6d0713d731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468145095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.468145095
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1364089850
Short name T3
Test name
Test status
Simulation time 12212409 ps
CPU time 0.42 seconds
Started Jul 19 04:22:43 PM PDT 24
Finished Jul 19 04:22:46 PM PDT 24
Peak memory 145248 kb
Host smart-3c7d476a-8576-4d1d-8b99-d601c2c3d75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364089850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1364089850
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2070905911
Short name T17
Test name
Test status
Simulation time 10889734 ps
CPU time 0.39 seconds
Started Jul 19 04:21:33 PM PDT 24
Finished Jul 19 04:21:34 PM PDT 24
Peak memory 145652 kb
Host smart-5024152d-f391-4b1f-ba77-40baddf25360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070905911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2070905911
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.61672688
Short name T13
Test name
Test status
Simulation time 10736367 ps
CPU time 0.38 seconds
Started Jul 19 04:23:07 PM PDT 24
Finished Jul 19 04:23:19 PM PDT 24
Peak memory 145572 kb
Host smart-8192826a-3733-453e-bde7-c6c05c8e2800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61672688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.61672688
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3458317693
Short name T6
Test name
Test status
Simulation time 11702352 ps
CPU time 0.4 seconds
Started Jul 19 04:17:24 PM PDT 24
Finished Jul 19 04:17:25 PM PDT 24
Peak memory 145880 kb
Host smart-8b9d4c79-ca87-448e-904f-2f67c143b28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458317693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3458317693
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2483468895
Short name T9
Test name
Test status
Simulation time 11737237 ps
CPU time 0.37 seconds
Started Jul 19 04:23:08 PM PDT 24
Finished Jul 19 04:23:21 PM PDT 24
Peak memory 145560 kb
Host smart-7d6f5508-82d9-49b2-ae13-493c4d4ebd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483468895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2483468895
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.244821319
Short name T44
Test name
Test status
Simulation time 10730847 ps
CPU time 0.37 seconds
Started Jul 19 04:22:40 PM PDT 24
Finished Jul 19 04:22:43 PM PDT 24
Peak memory 145124 kb
Host smart-5fb7342e-1aa2-4df0-bd36-a942a79249ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244821319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.244821319
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3240856312
Short name T45
Test name
Test status
Simulation time 12033632 ps
CPU time 0.38 seconds
Started Jul 19 04:23:00 PM PDT 24
Finished Jul 19 04:23:04 PM PDT 24
Peak memory 145376 kb
Host smart-f950ca05-c8ea-4195-9d9a-dce0944b6433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240856312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3240856312
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.521213093
Short name T41
Test name
Test status
Simulation time 11342072 ps
CPU time 0.41 seconds
Started Jul 19 04:21:12 PM PDT 24
Finished Jul 19 04:21:13 PM PDT 24
Peak memory 145608 kb
Host smart-1c5e787a-992a-4e9c-998f-6a6ca99dc944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521213093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.521213093
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1359171989
Short name T15
Test name
Test status
Simulation time 12248689 ps
CPU time 0.41 seconds
Started Jul 19 04:21:18 PM PDT 24
Finished Jul 19 04:21:19 PM PDT 24
Peak memory 145876 kb
Host smart-bb718584-839e-4795-9919-f0a1f173a099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359171989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1359171989
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1748283995
Short name T14
Test name
Test status
Simulation time 10888646 ps
CPU time 0.39 seconds
Started Jul 19 04:22:42 PM PDT 24
Finished Jul 19 04:22:45 PM PDT 24
Peak memory 144776 kb
Host smart-a28ca81c-cb36-4442-b809-1ed45dcbc6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748283995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1748283995
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1361945489
Short name T2
Test name
Test status
Simulation time 11767568 ps
CPU time 0.39 seconds
Started Jul 19 04:21:03 PM PDT 24
Finished Jul 19 04:21:04 PM PDT 24
Peak memory 145824 kb
Host smart-3dae1446-2c82-446b-a6cc-63a473354f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361945489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1361945489
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.147311517
Short name T1
Test name
Test status
Simulation time 11197818 ps
CPU time 0.41 seconds
Started Jul 19 04:17:08 PM PDT 24
Finished Jul 19 04:17:09 PM PDT 24
Peak memory 145880 kb
Host smart-14628cad-2ba1-4f13-b69d-9723f13c2189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147311517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.147311517
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2802077661
Short name T11
Test name
Test status
Simulation time 12303803 ps
CPU time 0.4 seconds
Started Jul 19 04:22:39 PM PDT 24
Finished Jul 19 04:22:41 PM PDT 24
Peak memory 144852 kb
Host smart-389d374e-4ca3-4ce0-94b3-a895fbe85dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802077661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2802077661
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3818996339
Short name T42
Test name
Test status
Simulation time 11325243 ps
CPU time 0.43 seconds
Started Jul 19 04:22:51 PM PDT 24
Finished Jul 19 04:22:53 PM PDT 24
Peak memory 145156 kb
Host smart-5088fdbe-c9b8-4d1c-8571-6c722bf15440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818996339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3818996339
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2527101032
Short name T40
Test name
Test status
Simulation time 28904739 ps
CPU time 0.41 seconds
Started Jul 19 04:21:01 PM PDT 24
Finished Jul 19 04:21:02 PM PDT 24
Peak memory 145172 kb
Host smart-2891cfe8-792e-40ff-b143-1201cb6cf6dd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2527101032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2527101032
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1760181609
Short name T48
Test name
Test status
Simulation time 30455990 ps
CPU time 0.38 seconds
Started Jul 19 04:22:37 PM PDT 24
Finished Jul 19 04:22:38 PM PDT 24
Peak memory 144824 kb
Host smart-07bd98ab-c66b-4732-a0a6-0f6d09c89764
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1760181609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1760181609
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1527115660
Short name T46
Test name
Test status
Simulation time 30659582 ps
CPU time 0.4 seconds
Started Jul 19 04:22:53 PM PDT 24
Finished Jul 19 04:22:55 PM PDT 24
Peak memory 144932 kb
Host smart-18a5839c-7f06-40a2-9731-73bd2d770a0b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1527115660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1527115660
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.850874743
Short name T50
Test name
Test status
Simulation time 29379402 ps
CPU time 0.42 seconds
Started Jul 19 04:20:53 PM PDT 24
Finished Jul 19 04:20:54 PM PDT 24
Peak memory 145364 kb
Host smart-306f0c95-62d9-4cf6-a104-34314668adfd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=850874743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.850874743
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.203411245
Short name T38
Test name
Test status
Simulation time 28431510 ps
CPU time 0.39 seconds
Started Jul 19 04:23:00 PM PDT 24
Finished Jul 19 04:23:03 PM PDT 24
Peak memory 145012 kb
Host smart-03ca22f5-93ad-4dca-bc95-409464a80d4f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=203411245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.203411245
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4026118864
Short name T53
Test name
Test status
Simulation time 29464662 ps
CPU time 0.43 seconds
Started Jul 19 04:21:18 PM PDT 24
Finished Jul 19 04:21:19 PM PDT 24
Peak memory 145396 kb
Host smart-5f276dbc-c6b7-40d2-9a9d-256591b0e2f4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4026118864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.4026118864
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3860171535
Short name T36
Test name
Test status
Simulation time 29536165 ps
CPU time 0.39 seconds
Started Jul 19 04:23:07 PM PDT 24
Finished Jul 19 04:23:19 PM PDT 24
Peak memory 145180 kb
Host smart-a0b6390c-54ac-4d50-8ad5-a4224b868504
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3860171535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3860171535
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1894313848
Short name T47
Test name
Test status
Simulation time 30658852 ps
CPU time 0.44 seconds
Started Jul 19 04:23:08 PM PDT 24
Finished Jul 19 04:23:21 PM PDT 24
Peak memory 145112 kb
Host smart-1a7a7f8d-105f-4031-9f9c-a8e40a3a1ebe
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1894313848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1894313848
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3041527421
Short name T12
Test name
Test status
Simulation time 30424201 ps
CPU time 0.4 seconds
Started Jul 19 04:23:00 PM PDT 24
Finished Jul 19 04:23:04 PM PDT 24
Peak memory 144916 kb
Host smart-5fe29ce9-4e08-4d29-bc3f-d3af833e074d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3041527421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3041527421
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1395325651
Short name T54
Test name
Test status
Simulation time 31133790 ps
CPU time 0.4 seconds
Started Jul 19 04:23:00 PM PDT 24
Finished Jul 19 04:23:03 PM PDT 24
Peak memory 144948 kb
Host smart-b3cf111f-66c8-4d85-86fd-eaab768305c5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1395325651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1395325651
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4060828718
Short name T37
Test name
Test status
Simulation time 28656965 ps
CPU time 0.41 seconds
Started Jul 19 04:17:08 PM PDT 24
Finished Jul 19 04:17:09 PM PDT 24
Peak memory 145332 kb
Host smart-0276ade9-c2f9-47ec-93dd-72efb5ee238d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4060828718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4060828718
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2281654773
Short name T35
Test name
Test status
Simulation time 27743799 ps
CPU time 0.39 seconds
Started Jul 19 04:23:00 PM PDT 24
Finished Jul 19 04:23:04 PM PDT 24
Peak memory 144952 kb
Host smart-3fdc24b8-a92d-4d22-adb1-1127c64783b9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2281654773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2281654773
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3987389839
Short name T39
Test name
Test status
Simulation time 29992831 ps
CPU time 0.4 seconds
Started Jul 19 04:23:00 PM PDT 24
Finished Jul 19 04:23:04 PM PDT 24
Peak memory 145012 kb
Host smart-948158f4-fa07-4707-a6b9-e3c4d7508b75
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3987389839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3987389839
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3338205919
Short name T51
Test name
Test status
Simulation time 30304195 ps
CPU time 0.41 seconds
Started Jul 19 04:22:39 PM PDT 24
Finished Jul 19 04:22:41 PM PDT 24
Peak memory 144064 kb
Host smart-74e0bccd-e7c7-4597-85e1-6438eeec551e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3338205919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3338205919
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1419664686
Short name T32
Test name
Test status
Simulation time 33889823 ps
CPU time 0.39 seconds
Started Jul 19 04:23:07 PM PDT 24
Finished Jul 19 04:23:16 PM PDT 24
Peak memory 145108 kb
Host smart-3967117d-6a9f-4e37-a90a-72b560d3cd67
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1419664686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1419664686
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1461577817
Short name T49
Test name
Test status
Simulation time 29503600 ps
CPU time 0.42 seconds
Started Jul 19 04:21:02 PM PDT 24
Finished Jul 19 04:21:03 PM PDT 24
Peak memory 145332 kb
Host smart-7c14f8d7-b38e-4937-9790-b6f2fac5c4db
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1461577817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1461577817
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.908359622
Short name T33
Test name
Test status
Simulation time 29301783 ps
CPU time 0.4 seconds
Started Jul 19 04:17:03 PM PDT 24
Finished Jul 19 04:17:04 PM PDT 24
Peak memory 145388 kb
Host smart-a58f5aa1-48d7-45dc-a129-0b8410c6a6a9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=908359622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.908359622
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2770696091
Short name T52
Test name
Test status
Simulation time 31226213 ps
CPU time 0.42 seconds
Started Jul 19 04:22:58 PM PDT 24
Finished Jul 19 04:23:01 PM PDT 24
Peak memory 145200 kb
Host smart-ad71d413-1e17-450c-a562-07fe1a9ed763
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2770696091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2770696091
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.4046679052
Short name T21
Test name
Test status
Simulation time 8810464 ps
CPU time 0.38 seconds
Started Jul 19 04:23:00 PM PDT 24
Finished Jul 19 04:23:04 PM PDT 24
Peak memory 144972 kb
Host smart-3c844649-3a45-4dab-8fda-e88458c16421
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4046679052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.4046679052
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1237266726
Short name T59
Test name
Test status
Simulation time 9825747 ps
CPU time 0.41 seconds
Started Jul 19 04:22:52 PM PDT 24
Finished Jul 19 04:22:54 PM PDT 24
Peak memory 145848 kb
Host smart-e4e80bc9-bfaf-4eea-b2d2-ddfdbd5243ee
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1237266726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1237266726
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1793926798
Short name T28
Test name
Test status
Simulation time 9741515 ps
CPU time 0.37 seconds
Started Jul 19 04:23:08 PM PDT 24
Finished Jul 19 04:23:20 PM PDT 24
Peak memory 145380 kb
Host smart-4c6e8959-7da8-4f67-be54-35cad848a172
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1793926798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1793926798
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.178832620
Short name T18
Test name
Test status
Simulation time 10194604 ps
CPU time 0.38 seconds
Started Jul 19 04:20:57 PM PDT 24
Finished Jul 19 04:20:58 PM PDT 24
Peak memory 145664 kb
Host smart-0df67d23-daf7-4c3f-bc82-70bd254e8740
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=178832620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.178832620
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3609809192
Short name T58
Test name
Test status
Simulation time 8819328 ps
CPU time 0.37 seconds
Started Jul 19 04:23:08 PM PDT 24
Finished Jul 19 04:23:20 PM PDT 24
Peak memory 145388 kb
Host smart-33236fd3-95ae-41e1-a444-2362dc8006b5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3609809192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3609809192
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3190476319
Short name T30
Test name
Test status
Simulation time 9797812 ps
CPU time 0.37 seconds
Started Jul 19 04:22:40 PM PDT 24
Finished Jul 19 04:22:43 PM PDT 24
Peak memory 144980 kb
Host smart-73f313c6-c5d4-4ff8-8403-745abbe720a4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3190476319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3190476319
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1332688086
Short name T55
Test name
Test status
Simulation time 9481317 ps
CPU time 0.39 seconds
Started Jul 19 04:17:24 PM PDT 24
Finished Jul 19 04:17:25 PM PDT 24
Peak memory 145672 kb
Host smart-1c0f62fe-8742-4d83-8a00-a511cf072e3d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1332688086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1332688086
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.10258903
Short name T24
Test name
Test status
Simulation time 9583560 ps
CPU time 0.36 seconds
Started Jul 19 04:22:27 PM PDT 24
Finished Jul 19 04:22:29 PM PDT 24
Peak memory 145044 kb
Host smart-a8f62116-6f8c-4d04-95db-16054c125214
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=10258903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.10258903
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1777149551
Short name T57
Test name
Test status
Simulation time 9076600 ps
CPU time 0.39 seconds
Started Jul 19 04:23:00 PM PDT 24
Finished Jul 19 04:23:04 PM PDT 24
Peak memory 145032 kb
Host smart-32e23a6f-1807-4c83-8357-c9bea1efb765
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1777149551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1777149551
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2099547954
Short name T29
Test name
Test status
Simulation time 9242993 ps
CPU time 0.37 seconds
Started Jul 19 04:23:00 PM PDT 24
Finished Jul 19 04:23:04 PM PDT 24
Peak memory 145176 kb
Host smart-fb251269-f35f-4850-83f4-ee93a4274216
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2099547954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2099547954
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.4206317376
Short name T27
Test name
Test status
Simulation time 7762264 ps
CPU time 0.37 seconds
Started Jul 19 04:22:58 PM PDT 24
Finished Jul 19 04:23:02 PM PDT 24
Peak memory 145396 kb
Host smart-de8523cd-409c-452c-a70f-f6c197e91cf9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4206317376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.4206317376
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3126977934
Short name T19
Test name
Test status
Simulation time 9377633 ps
CPU time 0.42 seconds
Started Jul 19 04:22:27 PM PDT 24
Finished Jul 19 04:22:29 PM PDT 24
Peak memory 144172 kb
Host smart-11286948-1a90-4634-b242-760a98cb5a81
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3126977934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3126977934
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2420084535
Short name T25
Test name
Test status
Simulation time 9445176 ps
CPU time 0.4 seconds
Started Jul 19 04:22:44 PM PDT 24
Finished Jul 19 04:22:47 PM PDT 24
Peak memory 145132 kb
Host smart-64f9ed79-3245-4130-9119-07ed4dbfe7a3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2420084535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2420084535
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3407404843
Short name T60
Test name
Test status
Simulation time 8429185 ps
CPU time 0.37 seconds
Started Jul 19 04:23:08 PM PDT 24
Finished Jul 19 04:23:20 PM PDT 24
Peak memory 145388 kb
Host smart-55258b47-99fc-42ef-87d3-270f590cba7e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3407404843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3407404843
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1164016159
Short name T31
Test name
Test status
Simulation time 10130784 ps
CPU time 0.4 seconds
Started Jul 19 04:20:52 PM PDT 24
Finished Jul 19 04:20:53 PM PDT 24
Peak memory 145656 kb
Host smart-8a85b66a-cf30-400d-b918-8781ac92721f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1164016159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1164016159
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2399344076
Short name T56
Test name
Test status
Simulation time 9704471 ps
CPU time 0.41 seconds
Started Jul 19 04:22:40 PM PDT 24
Finished Jul 19 04:22:42 PM PDT 24
Peak memory 144988 kb
Host smart-bae899a3-87f0-4dfc-b7bc-4ba031f2321d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2399344076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2399344076
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2536220091
Short name T23
Test name
Test status
Simulation time 8963108 ps
CPU time 0.38 seconds
Started Jul 19 04:23:12 PM PDT 24
Finished Jul 19 04:23:37 PM PDT 24
Peak memory 145440 kb
Host smart-a1bfb964-57ed-41be-98fe-014c20f0c6a2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2536220091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2536220091
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1490024181
Short name T26
Test name
Test status
Simulation time 10026791 ps
CPU time 0.4 seconds
Started Jul 19 04:22:39 PM PDT 24
Finished Jul 19 04:22:41 PM PDT 24
Peak memory 144648 kb
Host smart-2c947224-b55b-4878-ab35-1da00e286aa8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1490024181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1490024181
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3091119437
Short name T22
Test name
Test status
Simulation time 8952250 ps
CPU time 0.38 seconds
Started Jul 19 04:23:00 PM PDT 24
Finished Jul 19 04:23:03 PM PDT 24
Peak memory 145152 kb
Host smart-144515cf-6546-4b58-be08-821b3d61c5db
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3091119437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3091119437
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2623593402
Short name T72
Test name
Test status
Simulation time 27294507 ps
CPU time 0.39 seconds
Started Jul 19 04:21:07 PM PDT 24
Finished Jul 19 04:21:08 PM PDT 24
Peak memory 145432 kb
Host smart-c1310a72-3c26-4179-8cc6-24cc5e1dbc8a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2623593402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2623593402
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.961474737
Short name T67
Test name
Test status
Simulation time 25871732 ps
CPU time 0.38 seconds
Started Jul 19 04:23:08 PM PDT 24
Finished Jul 19 04:23:19 PM PDT 24
Peak memory 145392 kb
Host smart-64f84d0f-e24b-40f0-a9f8-a12bfd94ec77
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=961474737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.961474737
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3109260048
Short name T74
Test name
Test status
Simulation time 28141503 ps
CPU time 0.4 seconds
Started Jul 19 04:21:46 PM PDT 24
Finished Jul 19 04:21:47 PM PDT 24
Peak memory 145448 kb
Host smart-977046b6-13ba-4953-ac73-7fce832ef5b3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3109260048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3109260048
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.138481886
Short name T71
Test name
Test status
Simulation time 27434457 ps
CPU time 0.38 seconds
Started Jul 19 04:23:04 PM PDT 24
Finished Jul 19 04:23:10 PM PDT 24
Peak memory 145296 kb
Host smart-879d1f25-3b41-45ff-b42a-ace5a4dfe03f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=138481886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.138481886
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2461297985
Short name T68
Test name
Test status
Simulation time 26014468 ps
CPU time 0.48 seconds
Started Jul 19 04:20:27 PM PDT 24
Finished Jul 19 04:20:28 PM PDT 24
Peak memory 145448 kb
Host smart-4d6ab49d-6fa0-4e10-9ebb-6c2d60ae8387
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2461297985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2461297985
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.82942422
Short name T76
Test name
Test status
Simulation time 27690656 ps
CPU time 0.39 seconds
Started Jul 19 04:21:45 PM PDT 24
Finished Jul 19 04:21:46 PM PDT 24
Peak memory 145444 kb
Host smart-c092cf44-5ee7-4740-9e41-8289a7994c57
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=82942422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.82942422
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3993593422
Short name T70
Test name
Test status
Simulation time 28388109 ps
CPU time 0.4 seconds
Started Jul 19 04:23:01 PM PDT 24
Finished Jul 19 04:23:05 PM PDT 24
Peak memory 145192 kb
Host smart-bee41b2b-7453-477e-a415-9886e4ea278d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3993593422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3993593422
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2717453782
Short name T75
Test name
Test status
Simulation time 26796366 ps
CPU time 0.38 seconds
Started Jul 19 04:23:03 PM PDT 24
Finished Jul 19 04:23:08 PM PDT 24
Peak memory 145180 kb
Host smart-50ece8af-9342-4869-b3ae-e9b50cb6464c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2717453782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2717453782
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2113385369
Short name T77
Test name
Test status
Simulation time 26118614 ps
CPU time 0.43 seconds
Started Jul 19 04:22:56 PM PDT 24
Finished Jul 19 04:23:00 PM PDT 24
Peak memory 144364 kb
Host smart-6f0839c3-9321-4938-a7b2-7aeb5d8f7924
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2113385369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2113385369
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2960127367
Short name T65
Test name
Test status
Simulation time 26265400 ps
CPU time 0.45 seconds
Started Jul 19 04:22:44 PM PDT 24
Finished Jul 19 04:22:47 PM PDT 24
Peak memory 145276 kb
Host smart-8fc83720-f901-4d90-9118-7cda9e10b16f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2960127367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2960127367
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3204303947
Short name T78
Test name
Test status
Simulation time 27694060 ps
CPU time 0.39 seconds
Started Jul 19 04:23:10 PM PDT 24
Finished Jul 19 04:23:28 PM PDT 24
Peak memory 145412 kb
Host smart-9e422b8d-6c91-4b94-9329-d4fa6bfe0984
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3204303947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3204303947
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4224991308
Short name T66
Test name
Test status
Simulation time 27363334 ps
CPU time 0.4 seconds
Started Jul 19 04:20:35 PM PDT 24
Finished Jul 19 04:20:36 PM PDT 24
Peak memory 145440 kb
Host smart-b7bb3d48-88cd-4a34-b7e9-f2cb324394cf
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4224991308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.4224991308
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.426928738
Short name T73
Test name
Test status
Simulation time 24695667 ps
CPU time 0.39 seconds
Started Jul 19 04:22:55 PM PDT 24
Finished Jul 19 04:22:57 PM PDT 24
Peak memory 145160 kb
Host smart-e3851f27-34f5-4ef3-aaa1-7f894c111d2f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=426928738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.426928738
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2427648211
Short name T61
Test name
Test status
Simulation time 27118574 ps
CPU time 0.4 seconds
Started Jul 19 04:23:07 PM PDT 24
Finished Jul 19 04:23:18 PM PDT 24
Peak memory 145368 kb
Host smart-796154b5-8c0e-4b53-a06c-4eee1190831c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2427648211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2427648211
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.623580110
Short name T64
Test name
Test status
Simulation time 27392395 ps
CPU time 0.41 seconds
Started Jul 19 04:23:07 PM PDT 24
Finished Jul 19 04:23:18 PM PDT 24
Peak memory 145404 kb
Host smart-f958609d-6979-4c76-bb52-a43205d56b2d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=623580110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.623580110
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1668347242
Short name T62
Test name
Test status
Simulation time 26940040 ps
CPU time 0.4 seconds
Started Jul 19 04:22:55 PM PDT 24
Finished Jul 19 04:22:57 PM PDT 24
Peak memory 145136 kb
Host smart-d41b6d88-3b62-4ca8-bd70-3c3e204bc2f6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1668347242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1668347242
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3336582316
Short name T5
Test name
Test status
Simulation time 27401048 ps
CPU time 0.37 seconds
Started Jul 19 04:22:39 PM PDT 24
Finished Jul 19 04:22:42 PM PDT 24
Peak memory 144960 kb
Host smart-108d7025-372c-4679-a781-72c73503814c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3336582316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3336582316
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.370515132
Short name T63
Test name
Test status
Simulation time 28456707 ps
CPU time 0.43 seconds
Started Jul 19 04:19:16 PM PDT 24
Finished Jul 19 04:19:17 PM PDT 24
Peak memory 145636 kb
Host smart-975d80db-f6cd-4789-bf79-9fcad9ed0076
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=370515132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.370515132
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1239718911
Short name T69
Test name
Test status
Simulation time 27846684 ps
CPU time 0.39 seconds
Started Jul 19 04:21:45 PM PDT 24
Finished Jul 19 04:21:47 PM PDT 24
Peak memory 145444 kb
Host smart-95deb512-d870-4142-b635-809c09e4f46e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1239718911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1239718911
Directory /workspace/9.prim_sync_fatal_alert/latest
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