Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.88 88.88 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/3.prim_async_alert.893793919
92.60 3.72 100.00 0.00 93.75 0.00 100.00 0.00 89.29 10.71 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/18.prim_sync_alert.1534548450
94.15 1.55 100.00 0.00 93.75 0.00 100.00 0.00 89.29 0.00 95.83 0.00 86.05 9.30 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3114675188
94.50 0.35 100.00 0.00 95.83 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/10.prim_async_alert.2728144986
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3245065600
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/0.prim_sync_alert.3985199350

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1641779474
/workspace/coverage/default/1.prim_async_alert.2737617857
/workspace/coverage/default/11.prim_async_alert.3440030572
/workspace/coverage/default/12.prim_async_alert.2930046834
/workspace/coverage/default/13.prim_async_alert.644502654
/workspace/coverage/default/14.prim_async_alert.1412238959
/workspace/coverage/default/15.prim_async_alert.821805778
/workspace/coverage/default/16.prim_async_alert.3923686258
/workspace/coverage/default/17.prim_async_alert.4004848408
/workspace/coverage/default/18.prim_async_alert.3422336838
/workspace/coverage/default/19.prim_async_alert.813584439
/workspace/coverage/default/2.prim_async_alert.1163489985
/workspace/coverage/default/4.prim_async_alert.2258826803
/workspace/coverage/default/5.prim_async_alert.3936391132
/workspace/coverage/default/6.prim_async_alert.1631556348
/workspace/coverage/default/7.prim_async_alert.1004083853
/workspace/coverage/default/8.prim_async_alert.1869233171
/workspace/coverage/default/9.prim_async_alert.47070258
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2098003151
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2383822149
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2337389469
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3948639518
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1610034711
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2236610753
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.656915183
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.504350583
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3468627326
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1768258352
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3764984273
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.335876856
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.509035690
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1652494288
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3213529964
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2552429440
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1234456374
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2080142143
/workspace/coverage/sync_alert/1.prim_sync_alert.486850665
/workspace/coverage/sync_alert/10.prim_sync_alert.2087687373
/workspace/coverage/sync_alert/11.prim_sync_alert.2503673841
/workspace/coverage/sync_alert/12.prim_sync_alert.2601345394
/workspace/coverage/sync_alert/13.prim_sync_alert.61546813
/workspace/coverage/sync_alert/14.prim_sync_alert.2717386246
/workspace/coverage/sync_alert/15.prim_sync_alert.141841789
/workspace/coverage/sync_alert/16.prim_sync_alert.3054824241
/workspace/coverage/sync_alert/17.prim_sync_alert.922504423
/workspace/coverage/sync_alert/19.prim_sync_alert.850392335
/workspace/coverage/sync_alert/2.prim_sync_alert.1302508796
/workspace/coverage/sync_alert/3.prim_sync_alert.3629021539
/workspace/coverage/sync_alert/4.prim_sync_alert.655572258
/workspace/coverage/sync_alert/5.prim_sync_alert.3796965100
/workspace/coverage/sync_alert/6.prim_sync_alert.578083299
/workspace/coverage/sync_alert/7.prim_sync_alert.1606550098
/workspace/coverage/sync_alert/8.prim_sync_alert.2483293134
/workspace/coverage/sync_alert/9.prim_sync_alert.1406839943
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4152655392
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4262910343
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1100361809
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2725428427
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2053813348
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2210779960
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2796504586
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.525936204
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3292226726
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2034518461
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4159570950
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3559832997
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3185033237
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.492426553
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3516756239
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3767436321
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3813169592
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.393428315
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.711392622
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1537358797



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/2.prim_async_alert.1163489985 Jul 22 06:21:57 PM PDT 24 Jul 22 06:21:58 PM PDT 24 10684984 ps
T2 /workspace/coverage/default/11.prim_async_alert.3440030572 Jul 22 06:22:04 PM PDT 24 Jul 22 06:22:05 PM PDT 24 11127100 ps
T3 /workspace/coverage/default/10.prim_async_alert.2728144986 Jul 22 06:22:01 PM PDT 24 Jul 22 06:22:02 PM PDT 24 11576273 ps
T9 /workspace/coverage/default/6.prim_async_alert.1631556348 Jul 22 06:21:58 PM PDT 24 Jul 22 06:21:59 PM PDT 24 11316053 ps
T19 /workspace/coverage/default/16.prim_async_alert.3923686258 Jul 22 06:21:56 PM PDT 24 Jul 22 06:21:57 PM PDT 24 11109432 ps
T7 /workspace/coverage/default/18.prim_async_alert.3422336838 Jul 22 06:21:57 PM PDT 24 Jul 22 06:21:58 PM PDT 24 11783587 ps
T10 /workspace/coverage/default/3.prim_async_alert.893793919 Jul 22 06:21:54 PM PDT 24 Jul 22 06:21:54 PM PDT 24 12765591 ps
T12 /workspace/coverage/default/19.prim_async_alert.813584439 Jul 22 06:21:58 PM PDT 24 Jul 22 06:21:59 PM PDT 24 12092790 ps
T20 /workspace/coverage/default/1.prim_async_alert.2737617857 Jul 22 06:21:58 PM PDT 24 Jul 22 06:21:59 PM PDT 24 11062918 ps
T21 /workspace/coverage/default/0.prim_async_alert.1641779474 Jul 22 06:21:51 PM PDT 24 Jul 22 06:21:52 PM PDT 24 10141467 ps
T8 /workspace/coverage/default/17.prim_async_alert.4004848408 Jul 22 06:21:56 PM PDT 24 Jul 22 06:21:57 PM PDT 24 11254886 ps
T13 /workspace/coverage/default/8.prim_async_alert.1869233171 Jul 22 06:21:55 PM PDT 24 Jul 22 06:21:56 PM PDT 24 11843788 ps
T44 /workspace/coverage/default/5.prim_async_alert.3936391132 Jul 22 06:21:50 PM PDT 24 Jul 22 06:21:51 PM PDT 24 10740585 ps
T18 /workspace/coverage/default/14.prim_async_alert.1412238959 Jul 22 06:21:59 PM PDT 24 Jul 22 06:22:00 PM PDT 24 10671741 ps
T45 /workspace/coverage/default/15.prim_async_alert.821805778 Jul 22 06:21:55 PM PDT 24 Jul 22 06:21:56 PM PDT 24 10782702 ps
T15 /workspace/coverage/default/4.prim_async_alert.2258826803 Jul 22 06:21:52 PM PDT 24 Jul 22 06:21:53 PM PDT 24 11105092 ps
T22 /workspace/coverage/default/12.prim_async_alert.2930046834 Jul 22 06:22:25 PM PDT 24 Jul 22 06:22:27 PM PDT 24 11289329 ps
T16 /workspace/coverage/default/13.prim_async_alert.644502654 Jul 22 06:22:00 PM PDT 24 Jul 22 06:22:01 PM PDT 24 12301684 ps
T46 /workspace/coverage/default/7.prim_async_alert.1004083853 Jul 22 06:21:58 PM PDT 24 Jul 22 06:21:59 PM PDT 24 11535595 ps
T47 /workspace/coverage/default/9.prim_async_alert.47070258 Jul 22 06:21:59 PM PDT 24 Jul 22 06:22:00 PM PDT 24 10423024 ps
T4 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3245065600 Jul 22 06:23:57 PM PDT 24 Jul 22 06:23:58 PM PDT 24 30194651 ps
T23 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1768258352 Jul 22 06:23:09 PM PDT 24 Jul 22 06:23:10 PM PDT 24 30111022 ps
T5 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1652494288 Jul 22 06:23:01 PM PDT 24 Jul 22 06:23:02 PM PDT 24 28892237 ps
T24 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3114675188 Jul 22 06:22:56 PM PDT 24 Jul 22 06:22:57 PM PDT 24 29310019 ps
T25 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.656915183 Jul 22 06:22:56 PM PDT 24 Jul 22 06:22:58 PM PDT 24 29942139 ps
T40 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1234456374 Jul 22 06:24:01 PM PDT 24 Jul 22 06:24:01 PM PDT 24 31061468 ps
T41 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2098003151 Jul 22 06:22:47 PM PDT 24 Jul 22 06:22:48 PM PDT 24 30871372 ps
T42 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.509035690 Jul 22 06:22:57 PM PDT 24 Jul 22 06:22:58 PM PDT 24 30139546 ps
T14 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2236610753 Jul 22 06:22:57 PM PDT 24 Jul 22 06:22:59 PM PDT 24 31485877 ps
T43 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.504350583 Jul 22 06:24:13 PM PDT 24 Jul 22 06:24:14 PM PDT 24 29575783 ps
T48 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2337389469 Jul 22 06:22:56 PM PDT 24 Jul 22 06:22:58 PM PDT 24 29694340 ps
T49 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3948639518 Jul 22 06:23:00 PM PDT 24 Jul 22 06:23:01 PM PDT 24 30611792 ps
T50 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2383822149 Jul 22 06:23:29 PM PDT 24 Jul 22 06:23:29 PM PDT 24 29922154 ps
T51 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3213529964 Jul 22 06:22:58 PM PDT 24 Jul 22 06:22:59 PM PDT 24 30188829 ps
T17 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.335876856 Jul 22 06:22:48 PM PDT 24 Jul 22 06:22:49 PM PDT 24 31898818 ps
T52 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2552429440 Jul 22 06:22:57 PM PDT 24 Jul 22 06:22:59 PM PDT 24 30424450 ps
T53 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1610034711 Jul 22 06:22:55 PM PDT 24 Jul 22 06:22:56 PM PDT 24 30488734 ps
T54 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3764984273 Jul 22 06:22:46 PM PDT 24 Jul 22 06:22:47 PM PDT 24 30450860 ps
T55 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3468627326 Jul 22 06:24:13 PM PDT 24 Jul 22 06:24:14 PM PDT 24 28555247 ps
T56 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2080142143 Jul 22 06:22:55 PM PDT 24 Jul 22 06:22:57 PM PDT 24 30968851 ps
T26 /workspace/coverage/sync_alert/12.prim_sync_alert.2601345394 Jul 22 06:22:56 PM PDT 24 Jul 22 06:22:58 PM PDT 24 9546220 ps
T27 /workspace/coverage/sync_alert/1.prim_sync_alert.486850665 Jul 22 06:22:57 PM PDT 24 Jul 22 06:22:59 PM PDT 24 9140334 ps
T36 /workspace/coverage/sync_alert/7.prim_sync_alert.1606550098 Jul 22 06:23:47 PM PDT 24 Jul 22 06:23:48 PM PDT 24 8821223 ps
T28 /workspace/coverage/sync_alert/14.prim_sync_alert.2717386246 Jul 22 06:22:58 PM PDT 24 Jul 22 06:22:59 PM PDT 24 8728969 ps
T29 /workspace/coverage/sync_alert/5.prim_sync_alert.3796965100 Jul 22 06:23:47 PM PDT 24 Jul 22 06:23:48 PM PDT 24 9694798 ps
T30 /workspace/coverage/sync_alert/4.prim_sync_alert.655572258 Jul 22 06:22:57 PM PDT 24 Jul 22 06:22:59 PM PDT 24 8095874 ps
T37 /workspace/coverage/sync_alert/18.prim_sync_alert.1534548450 Jul 22 06:23:06 PM PDT 24 Jul 22 06:23:07 PM PDT 24 9311364 ps
T38 /workspace/coverage/sync_alert/2.prim_sync_alert.1302508796 Jul 22 06:22:57 PM PDT 24 Jul 22 06:22:59 PM PDT 24 8457242 ps
T39 /workspace/coverage/sync_alert/3.prim_sync_alert.3629021539 Jul 22 06:22:57 PM PDT 24 Jul 22 06:22:59 PM PDT 24 7776908 ps
T31 /workspace/coverage/sync_alert/17.prim_sync_alert.922504423 Jul 22 06:23:57 PM PDT 24 Jul 22 06:23:58 PM PDT 24 10065525 ps
T57 /workspace/coverage/sync_alert/6.prim_sync_alert.578083299 Jul 22 06:22:55 PM PDT 24 Jul 22 06:22:57 PM PDT 24 9235893 ps
T58 /workspace/coverage/sync_alert/11.prim_sync_alert.2503673841 Jul 22 06:22:55 PM PDT 24 Jul 22 06:22:56 PM PDT 24 9929185 ps
T32 /workspace/coverage/sync_alert/13.prim_sync_alert.61546813 Jul 22 06:22:55 PM PDT 24 Jul 22 06:22:57 PM PDT 24 10212716 ps
T59 /workspace/coverage/sync_alert/19.prim_sync_alert.850392335 Jul 22 06:23:09 PM PDT 24 Jul 22 06:23:10 PM PDT 24 9137522 ps
T60 /workspace/coverage/sync_alert/8.prim_sync_alert.2483293134 Jul 22 06:22:56 PM PDT 24 Jul 22 06:22:57 PM PDT 24 8721924 ps
T11 /workspace/coverage/sync_alert/0.prim_sync_alert.3985199350 Jul 22 06:22:57 PM PDT 24 Jul 22 06:22:59 PM PDT 24 9902249 ps
T33 /workspace/coverage/sync_alert/10.prim_sync_alert.2087687373 Jul 22 06:22:59 PM PDT 24 Jul 22 06:23:00 PM PDT 24 8824152 ps
T34 /workspace/coverage/sync_alert/16.prim_sync_alert.3054824241 Jul 22 06:22:59 PM PDT 24 Jul 22 06:23:00 PM PDT 24 9823052 ps
T35 /workspace/coverage/sync_alert/15.prim_sync_alert.141841789 Jul 22 06:22:56 PM PDT 24 Jul 22 06:22:57 PM PDT 24 10770480 ps
T61 /workspace/coverage/sync_alert/9.prim_sync_alert.1406839943 Jul 22 06:22:59 PM PDT 24 Jul 22 06:23:01 PM PDT 24 9221519 ps
T6 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3185033237 Jul 22 05:11:12 PM PDT 24 Jul 22 05:11:13 PM PDT 24 31316512 ps
T62 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.492426553 Jul 22 05:13:45 PM PDT 24 Jul 22 05:13:46 PM PDT 24 27634174 ps
T63 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3813169592 Jul 22 05:11:22 PM PDT 24 Jul 22 05:11:23 PM PDT 24 26552465 ps
T64 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1100361809 Jul 22 05:11:20 PM PDT 24 Jul 22 05:11:21 PM PDT 24 28236589 ps
T65 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.525936204 Jul 22 05:11:29 PM PDT 24 Jul 22 05:11:30 PM PDT 24 27473644 ps
T66 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4152655392 Jul 22 05:15:57 PM PDT 24 Jul 22 05:15:58 PM PDT 24 26214068 ps
T67 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1537358797 Jul 22 05:11:20 PM PDT 24 Jul 22 05:11:21 PM PDT 24 26932813 ps
T68 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2034518461 Jul 22 05:13:07 PM PDT 24 Jul 22 05:13:08 PM PDT 24 29002055 ps
T69 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2053813348 Jul 22 05:11:20 PM PDT 24 Jul 22 05:11:21 PM PDT 24 29456842 ps
T70 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.393428315 Jul 22 05:11:19 PM PDT 24 Jul 22 05:11:19 PM PDT 24 25146276 ps
T71 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4159570950 Jul 22 05:11:30 PM PDT 24 Jul 22 05:11:30 PM PDT 24 26934681 ps
T72 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3292226726 Jul 22 05:11:31 PM PDT 24 Jul 22 05:11:32 PM PDT 24 28326881 ps
T73 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.711392622 Jul 22 05:14:48 PM PDT 24 Jul 22 05:14:49 PM PDT 24 25664255 ps
T74 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3559832997 Jul 22 05:11:28 PM PDT 24 Jul 22 05:11:29 PM PDT 24 28209198 ps
T75 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2725428427 Jul 22 05:11:20 PM PDT 24 Jul 22 05:11:21 PM PDT 24 27753970 ps
T76 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2796504586 Jul 22 05:11:22 PM PDT 24 Jul 22 05:11:23 PM PDT 24 28418738 ps
T77 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3767436321 Jul 22 05:11:22 PM PDT 24 Jul 22 05:11:22 PM PDT 24 25763324 ps
T78 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2210779960 Jul 22 05:11:20 PM PDT 24 Jul 22 05:11:21 PM PDT 24 26667349 ps
T79 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3516756239 Jul 22 05:16:10 PM PDT 24 Jul 22 05:16:11 PM PDT 24 29492941 ps
T80 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4262910343 Jul 22 05:11:11 PM PDT 24 Jul 22 05:11:12 PM PDT 24 28805189 ps

Test location /workspace/coverage/default/3.prim_async_alert.893793919
Short name T10
Test name
Test status
Simulation time 12765591 ps
CPU time 0.4 seconds
Started Jul 22 06:21:54 PM PDT 24
Finished Jul 22 06:21:54 PM PDT 24
Peak memory 145808 kb
Host smart-110d43a0-eed2-4aff-943f-979e9f0d8d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893793919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.893793919
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1534548450
Short name T37
Test name
Test status
Simulation time 9311364 ps
CPU time 0.38 seconds
Started Jul 22 06:23:06 PM PDT 24
Finished Jul 22 06:23:07 PM PDT 24
Peak memory 145636 kb
Host smart-00abf29f-7457-492e-bcc8-1642e7a5eb3d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1534548450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1534548450
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3114675188
Short name T24
Test name
Test status
Simulation time 29310019 ps
CPU time 0.4 seconds
Started Jul 22 06:22:56 PM PDT 24
Finished Jul 22 06:22:57 PM PDT 24
Peak memory 145320 kb
Host smart-47a5675a-6375-4048-aa91-be90df1d3377
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3114675188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3114675188
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2728144986
Short name T3
Test name
Test status
Simulation time 11576273 ps
CPU time 0.4 seconds
Started Jul 22 06:22:01 PM PDT 24
Finished Jul 22 06:22:02 PM PDT 24
Peak memory 145804 kb
Host smart-5f4c9776-5b8d-421a-bc45-e40b947da798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728144986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2728144986
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3245065600
Short name T4
Test name
Test status
Simulation time 30194651 ps
CPU time 0.4 seconds
Started Jul 22 06:23:57 PM PDT 24
Finished Jul 22 06:23:58 PM PDT 24
Peak memory 145252 kb
Host smart-8dc26a7c-fa57-406e-9316-7fc221d859c6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3245065600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3245065600
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3985199350
Short name T11
Test name
Test status
Simulation time 9902249 ps
CPU time 0.38 seconds
Started Jul 22 06:22:57 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 145624 kb
Host smart-83f38bb9-acd2-42e3-96e9-d2b8638039d6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3985199350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3985199350
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1641779474
Short name T21
Test name
Test status
Simulation time 10141467 ps
CPU time 0.43 seconds
Started Jul 22 06:21:51 PM PDT 24
Finished Jul 22 06:21:52 PM PDT 24
Peak memory 145780 kb
Host smart-32e34d40-865e-45a6-9f29-6a3b4c6f5ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641779474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1641779474
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2737617857
Short name T20
Test name
Test status
Simulation time 11062918 ps
CPU time 0.4 seconds
Started Jul 22 06:21:58 PM PDT 24
Finished Jul 22 06:21:59 PM PDT 24
Peak memory 145836 kb
Host smart-cf8d41d4-eb2c-4559-806e-2d637a85817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737617857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2737617857
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3440030572
Short name T2
Test name
Test status
Simulation time 11127100 ps
CPU time 0.38 seconds
Started Jul 22 06:22:04 PM PDT 24
Finished Jul 22 06:22:05 PM PDT 24
Peak memory 145720 kb
Host smart-d06d7988-cec8-4b3f-9eff-2b22832b4ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440030572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3440030572
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2930046834
Short name T22
Test name
Test status
Simulation time 11289329 ps
CPU time 0.39 seconds
Started Jul 22 06:22:25 PM PDT 24
Finished Jul 22 06:22:27 PM PDT 24
Peak memory 145756 kb
Host smart-957f8371-ffba-4753-b972-7d0b1ba018c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930046834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2930046834
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.644502654
Short name T16
Test name
Test status
Simulation time 12301684 ps
CPU time 0.39 seconds
Started Jul 22 06:22:00 PM PDT 24
Finished Jul 22 06:22:01 PM PDT 24
Peak memory 145740 kb
Host smart-919e30a3-17e7-4849-8656-a1a7015eda41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644502654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.644502654
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1412238959
Short name T18
Test name
Test status
Simulation time 10671741 ps
CPU time 0.38 seconds
Started Jul 22 06:21:59 PM PDT 24
Finished Jul 22 06:22:00 PM PDT 24
Peak memory 145748 kb
Host smart-53429348-8f51-4278-a8c5-6cd97a52a08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412238959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1412238959
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.821805778
Short name T45
Test name
Test status
Simulation time 10782702 ps
CPU time 0.41 seconds
Started Jul 22 06:21:55 PM PDT 24
Finished Jul 22 06:21:56 PM PDT 24
Peak memory 145760 kb
Host smart-e28e3de7-f383-4df1-a976-d12c0995228b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821805778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.821805778
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3923686258
Short name T19
Test name
Test status
Simulation time 11109432 ps
CPU time 0.39 seconds
Started Jul 22 06:21:56 PM PDT 24
Finished Jul 22 06:21:57 PM PDT 24
Peak memory 145788 kb
Host smart-4c548f31-cbee-4c8d-b786-67fca9f8d1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923686258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3923686258
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.4004848408
Short name T8
Test name
Test status
Simulation time 11254886 ps
CPU time 0.39 seconds
Started Jul 22 06:21:56 PM PDT 24
Finished Jul 22 06:21:57 PM PDT 24
Peak memory 145780 kb
Host smart-2b3aff13-f164-43ae-9907-e898c07eceab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004848408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.4004848408
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3422336838
Short name T7
Test name
Test status
Simulation time 11783587 ps
CPU time 0.39 seconds
Started Jul 22 06:21:57 PM PDT 24
Finished Jul 22 06:21:58 PM PDT 24
Peak memory 145784 kb
Host smart-d24710df-abf0-4515-80b4-9310e1f80330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422336838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3422336838
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.813584439
Short name T12
Test name
Test status
Simulation time 12092790 ps
CPU time 0.4 seconds
Started Jul 22 06:21:58 PM PDT 24
Finished Jul 22 06:21:59 PM PDT 24
Peak memory 145760 kb
Host smart-c047dfad-dddf-483e-980e-bf03ec1fe25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813584439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.813584439
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.1163489985
Short name T1
Test name
Test status
Simulation time 10684984 ps
CPU time 0.44 seconds
Started Jul 22 06:21:57 PM PDT 24
Finished Jul 22 06:21:58 PM PDT 24
Peak memory 145792 kb
Host smart-521f9408-1c89-4f3c-8bb2-9a5552fd173b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163489985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1163489985
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2258826803
Short name T15
Test name
Test status
Simulation time 11105092 ps
CPU time 0.39 seconds
Started Jul 22 06:21:52 PM PDT 24
Finished Jul 22 06:21:53 PM PDT 24
Peak memory 145840 kb
Host smart-4326859f-049f-4d8f-a8fb-900e632332f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258826803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2258826803
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3936391132
Short name T44
Test name
Test status
Simulation time 10740585 ps
CPU time 0.39 seconds
Started Jul 22 06:21:50 PM PDT 24
Finished Jul 22 06:21:51 PM PDT 24
Peak memory 145780 kb
Host smart-b4e32f33-68f9-4f68-b01f-41f151cfc938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936391132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3936391132
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1631556348
Short name T9
Test name
Test status
Simulation time 11316053 ps
CPU time 0.41 seconds
Started Jul 22 06:21:58 PM PDT 24
Finished Jul 22 06:21:59 PM PDT 24
Peak memory 145836 kb
Host smart-c07cfaa1-3d23-42c8-8fa9-9ca140a2f140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631556348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1631556348
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1004083853
Short name T46
Test name
Test status
Simulation time 11535595 ps
CPU time 0.41 seconds
Started Jul 22 06:21:58 PM PDT 24
Finished Jul 22 06:21:59 PM PDT 24
Peak memory 145800 kb
Host smart-b516d12c-e847-4fb3-b287-172593bdd8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004083853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1004083853
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1869233171
Short name T13
Test name
Test status
Simulation time 11843788 ps
CPU time 0.38 seconds
Started Jul 22 06:21:55 PM PDT 24
Finished Jul 22 06:21:56 PM PDT 24
Peak memory 145780 kb
Host smart-48dac15e-3501-4b2f-a291-9574725ac005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869233171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1869233171
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.47070258
Short name T47
Test name
Test status
Simulation time 10423024 ps
CPU time 0.4 seconds
Started Jul 22 06:21:59 PM PDT 24
Finished Jul 22 06:22:00 PM PDT 24
Peak memory 145820 kb
Host smart-a8365833-b8d1-4fda-ac37-eae59fc0e1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47070258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.47070258
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2098003151
Short name T41
Test name
Test status
Simulation time 30871372 ps
CPU time 0.39 seconds
Started Jul 22 06:22:47 PM PDT 24
Finished Jul 22 06:22:48 PM PDT 24
Peak memory 145316 kb
Host smart-06ea0dd7-283e-4281-9043-542197122c9a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2098003151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2098003151
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2383822149
Short name T50
Test name
Test status
Simulation time 29922154 ps
CPU time 0.39 seconds
Started Jul 22 06:23:29 PM PDT 24
Finished Jul 22 06:23:29 PM PDT 24
Peak memory 145320 kb
Host smart-a53d5806-b738-45ae-866f-cd98ef2055a0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2383822149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2383822149
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2337389469
Short name T48
Test name
Test status
Simulation time 29694340 ps
CPU time 0.39 seconds
Started Jul 22 06:22:56 PM PDT 24
Finished Jul 22 06:22:58 PM PDT 24
Peak memory 145324 kb
Host smart-22c0f103-d535-4046-b067-aeff9029b9be
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2337389469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2337389469
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3948639518
Short name T49
Test name
Test status
Simulation time 30611792 ps
CPU time 0.42 seconds
Started Jul 22 06:23:00 PM PDT 24
Finished Jul 22 06:23:01 PM PDT 24
Peak memory 145300 kb
Host smart-42b7f043-c2a0-4615-ac5d-1fbd20ea7f5a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3948639518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3948639518
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1610034711
Short name T53
Test name
Test status
Simulation time 30488734 ps
CPU time 0.39 seconds
Started Jul 22 06:22:55 PM PDT 24
Finished Jul 22 06:22:56 PM PDT 24
Peak memory 145312 kb
Host smart-4c786150-f3cc-4878-8b4d-d40f0b546307
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1610034711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1610034711
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2236610753
Short name T14
Test name
Test status
Simulation time 31485877 ps
CPU time 0.41 seconds
Started Jul 22 06:22:57 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 145332 kb
Host smart-57872ecc-0224-46fb-8d2b-0454a6697ce2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2236610753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2236610753
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.656915183
Short name T25
Test name
Test status
Simulation time 29942139 ps
CPU time 0.41 seconds
Started Jul 22 06:22:56 PM PDT 24
Finished Jul 22 06:22:58 PM PDT 24
Peak memory 145296 kb
Host smart-e249200f-569b-43c5-818f-50423fe176a5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=656915183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.656915183
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.504350583
Short name T43
Test name
Test status
Simulation time 29575783 ps
CPU time 0.42 seconds
Started Jul 22 06:24:13 PM PDT 24
Finished Jul 22 06:24:14 PM PDT 24
Peak memory 145300 kb
Host smart-a27a619f-b213-4b07-962c-bed242e7e463
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=504350583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.504350583
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3468627326
Short name T55
Test name
Test status
Simulation time 28555247 ps
CPU time 0.45 seconds
Started Jul 22 06:24:13 PM PDT 24
Finished Jul 22 06:24:14 PM PDT 24
Peak memory 145288 kb
Host smart-f6846697-507e-4ef4-a744-bad74fc91c8e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3468627326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3468627326
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1768258352
Short name T23
Test name
Test status
Simulation time 30111022 ps
CPU time 0.39 seconds
Started Jul 22 06:23:09 PM PDT 24
Finished Jul 22 06:23:10 PM PDT 24
Peak memory 145296 kb
Host smart-daa1c212-d80f-499a-984d-db4399587356
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1768258352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1768258352
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3764984273
Short name T54
Test name
Test status
Simulation time 30450860 ps
CPU time 0.39 seconds
Started Jul 22 06:22:46 PM PDT 24
Finished Jul 22 06:22:47 PM PDT 24
Peak memory 145308 kb
Host smart-32ac4d0a-3a5d-44d7-b546-a6959708c1ad
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3764984273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3764984273
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.335876856
Short name T17
Test name
Test status
Simulation time 31898818 ps
CPU time 0.4 seconds
Started Jul 22 06:22:48 PM PDT 24
Finished Jul 22 06:22:49 PM PDT 24
Peak memory 145268 kb
Host smart-8faa92ea-1444-41f7-97c3-2a8b1a83ba23
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=335876856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.335876856
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.509035690
Short name T42
Test name
Test status
Simulation time 30139546 ps
CPU time 0.38 seconds
Started Jul 22 06:22:57 PM PDT 24
Finished Jul 22 06:22:58 PM PDT 24
Peak memory 145244 kb
Host smart-ba20d2cb-1b5a-4e19-b1fe-90a8ee0abeb5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=509035690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.509035690
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1652494288
Short name T5
Test name
Test status
Simulation time 28892237 ps
CPU time 0.44 seconds
Started Jul 22 06:23:01 PM PDT 24
Finished Jul 22 06:23:02 PM PDT 24
Peak memory 145160 kb
Host smart-6a945553-d1c5-4db4-9352-d18b6a010ef2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1652494288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1652494288
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3213529964
Short name T51
Test name
Test status
Simulation time 30188829 ps
CPU time 0.4 seconds
Started Jul 22 06:22:58 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 145332 kb
Host smart-f8a5f77e-7f4c-4c94-a2af-1488527ddd0a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3213529964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3213529964
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2552429440
Short name T52
Test name
Test status
Simulation time 30424450 ps
CPU time 0.4 seconds
Started Jul 22 06:22:57 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 145384 kb
Host smart-c62dc5fc-4bf6-4729-82ba-12dbb2350b50
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2552429440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2552429440
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1234456374
Short name T40
Test name
Test status
Simulation time 31061468 ps
CPU time 0.42 seconds
Started Jul 22 06:24:01 PM PDT 24
Finished Jul 22 06:24:01 PM PDT 24
Peak memory 145252 kb
Host smart-d7fa45e3-65b4-4796-a76d-ae388061d40a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1234456374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1234456374
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2080142143
Short name T56
Test name
Test status
Simulation time 30968851 ps
CPU time 0.4 seconds
Started Jul 22 06:22:55 PM PDT 24
Finished Jul 22 06:22:57 PM PDT 24
Peak memory 145292 kb
Host smart-618b701b-6918-49d1-8b44-5a7ef01d14e0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2080142143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2080142143
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.486850665
Short name T27
Test name
Test status
Simulation time 9140334 ps
CPU time 0.37 seconds
Started Jul 22 06:22:57 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 145528 kb
Host smart-f702133e-40cd-4426-8f0b-87d102cc3742
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=486850665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.486850665
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2087687373
Short name T33
Test name
Test status
Simulation time 8824152 ps
CPU time 0.4 seconds
Started Jul 22 06:22:59 PM PDT 24
Finished Jul 22 06:23:00 PM PDT 24
Peak memory 145560 kb
Host smart-0bc699ef-7f05-42f4-8f23-19cc165a3c99
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2087687373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2087687373
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2503673841
Short name T58
Test name
Test status
Simulation time 9929185 ps
CPU time 0.37 seconds
Started Jul 22 06:22:55 PM PDT 24
Finished Jul 22 06:22:56 PM PDT 24
Peak memory 145600 kb
Host smart-fb56ffaa-d617-4db3-9c33-f3130c1065c2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2503673841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2503673841
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2601345394
Short name T26
Test name
Test status
Simulation time 9546220 ps
CPU time 0.36 seconds
Started Jul 22 06:22:56 PM PDT 24
Finished Jul 22 06:22:58 PM PDT 24
Peak memory 145500 kb
Host smart-414826ae-529e-4954-a997-dd50d4f5bb1b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2601345394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2601345394
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.61546813
Short name T32
Test name
Test status
Simulation time 10212716 ps
CPU time 0.37 seconds
Started Jul 22 06:22:55 PM PDT 24
Finished Jul 22 06:22:57 PM PDT 24
Peak memory 145596 kb
Host smart-48571324-148c-44ff-beb5-76be32065b24
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=61546813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.61546813
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2717386246
Short name T28
Test name
Test status
Simulation time 8728969 ps
CPU time 0.39 seconds
Started Jul 22 06:22:58 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 145560 kb
Host smart-8ae63ab9-033b-4706-b270-d8fe6b586b88
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2717386246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2717386246
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.141841789
Short name T35
Test name
Test status
Simulation time 10770480 ps
CPU time 0.39 seconds
Started Jul 22 06:22:56 PM PDT 24
Finished Jul 22 06:22:57 PM PDT 24
Peak memory 145592 kb
Host smart-995f4bcc-c485-47e9-9ed1-c2bccc19c5ac
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=141841789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.141841789
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3054824241
Short name T34
Test name
Test status
Simulation time 9823052 ps
CPU time 0.4 seconds
Started Jul 22 06:22:59 PM PDT 24
Finished Jul 22 06:23:00 PM PDT 24
Peak memory 145456 kb
Host smart-6888f629-0de8-4b41-b963-0008b5daa470
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3054824241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3054824241
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.922504423
Short name T31
Test name
Test status
Simulation time 10065525 ps
CPU time 0.39 seconds
Started Jul 22 06:23:57 PM PDT 24
Finished Jul 22 06:23:58 PM PDT 24
Peak memory 145552 kb
Host smart-7110a645-ff71-4c9c-a2a0-c8dd73f97930
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=922504423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.922504423
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.850392335
Short name T59
Test name
Test status
Simulation time 9137522 ps
CPU time 0.41 seconds
Started Jul 22 06:23:09 PM PDT 24
Finished Jul 22 06:23:10 PM PDT 24
Peak memory 145644 kb
Host smart-01f4a84f-2e3f-4cd1-b16e-0a538109487c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=850392335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.850392335
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1302508796
Short name T38
Test name
Test status
Simulation time 8457242 ps
CPU time 0.41 seconds
Started Jul 22 06:22:57 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 145500 kb
Host smart-cab4ce2d-0fc0-4aa2-b1c7-7997d1673698
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1302508796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1302508796
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3629021539
Short name T39
Test name
Test status
Simulation time 7776908 ps
CPU time 0.39 seconds
Started Jul 22 06:22:57 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 145500 kb
Host smart-09768447-4d1b-4ee6-976f-ab287cd6293c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3629021539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3629021539
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.655572258
Short name T30
Test name
Test status
Simulation time 8095874 ps
CPU time 0.4 seconds
Started Jul 22 06:22:57 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 145584 kb
Host smart-7af43186-2d6d-437d-8a60-b6e28a2439a4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=655572258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.655572258
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3796965100
Short name T29
Test name
Test status
Simulation time 9694798 ps
CPU time 0.37 seconds
Started Jul 22 06:23:47 PM PDT 24
Finished Jul 22 06:23:48 PM PDT 24
Peak memory 145512 kb
Host smart-83d6658d-f6ec-4b06-aeaa-3268e097d698
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3796965100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3796965100
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.578083299
Short name T57
Test name
Test status
Simulation time 9235893 ps
CPU time 0.42 seconds
Started Jul 22 06:22:55 PM PDT 24
Finished Jul 22 06:22:57 PM PDT 24
Peak memory 145588 kb
Host smart-5ef15e61-4ac4-4960-ae87-3e3de103c051
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=578083299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.578083299
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1606550098
Short name T36
Test name
Test status
Simulation time 8821223 ps
CPU time 0.39 seconds
Started Jul 22 06:23:47 PM PDT 24
Finished Jul 22 06:23:48 PM PDT 24
Peak memory 145512 kb
Host smart-051a2942-75fc-427e-9275-401a2e4e8d27
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1606550098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1606550098
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2483293134
Short name T60
Test name
Test status
Simulation time 8721924 ps
CPU time 0.4 seconds
Started Jul 22 06:22:56 PM PDT 24
Finished Jul 22 06:22:57 PM PDT 24
Peak memory 145592 kb
Host smart-c8473ed5-9fa3-45d0-8bd0-b6c78d3daf65
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2483293134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2483293134
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1406839943
Short name T61
Test name
Test status
Simulation time 9221519 ps
CPU time 0.39 seconds
Started Jul 22 06:22:59 PM PDT 24
Finished Jul 22 06:23:01 PM PDT 24
Peak memory 145468 kb
Host smart-c2c72f1d-aa71-4416-9809-21a65cb025af
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1406839943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1406839943
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4152655392
Short name T66
Test name
Test status
Simulation time 26214068 ps
CPU time 0.39 seconds
Started Jul 22 05:15:57 PM PDT 24
Finished Jul 22 05:15:58 PM PDT 24
Peak memory 145604 kb
Host smart-4d1b87d7-6f6c-4917-b532-7d2838836bb7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4152655392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4152655392
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4262910343
Short name T80
Test name
Test status
Simulation time 28805189 ps
CPU time 0.39 seconds
Started Jul 22 05:11:11 PM PDT 24
Finished Jul 22 05:11:12 PM PDT 24
Peak memory 145476 kb
Host smart-1d32502b-c05a-4892-9294-5c5584190bce
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4262910343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.4262910343
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1100361809
Short name T64
Test name
Test status
Simulation time 28236589 ps
CPU time 0.4 seconds
Started Jul 22 05:11:20 PM PDT 24
Finished Jul 22 05:11:21 PM PDT 24
Peak memory 145504 kb
Host smart-885c646b-6f6c-4427-96fb-9ba25142d0b8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1100361809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1100361809
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2725428427
Short name T75
Test name
Test status
Simulation time 27753970 ps
CPU time 0.41 seconds
Started Jul 22 05:11:20 PM PDT 24
Finished Jul 22 05:11:21 PM PDT 24
Peak memory 145600 kb
Host smart-4842fe1f-8aa2-4e8c-9b05-6a05c49688d1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2725428427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2725428427
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2053813348
Short name T69
Test name
Test status
Simulation time 29456842 ps
CPU time 0.38 seconds
Started Jul 22 05:11:20 PM PDT 24
Finished Jul 22 05:11:21 PM PDT 24
Peak memory 145472 kb
Host smart-ce278bd5-f8f4-4bb0-bd1d-58bcc82703ce
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2053813348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2053813348
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2210779960
Short name T78
Test name
Test status
Simulation time 26667349 ps
CPU time 0.4 seconds
Started Jul 22 05:11:20 PM PDT 24
Finished Jul 22 05:11:21 PM PDT 24
Peak memory 145576 kb
Host smart-574020bf-50d9-4c2a-bbf1-6c4854e41066
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2210779960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2210779960
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2796504586
Short name T76
Test name
Test status
Simulation time 28418738 ps
CPU time 0.39 seconds
Started Jul 22 05:11:22 PM PDT 24
Finished Jul 22 05:11:23 PM PDT 24
Peak memory 145588 kb
Host smart-548d8635-5630-4444-aa6e-5dec57d8a17f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2796504586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2796504586
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.525936204
Short name T65
Test name
Test status
Simulation time 27473644 ps
CPU time 0.38 seconds
Started Jul 22 05:11:29 PM PDT 24
Finished Jul 22 05:11:30 PM PDT 24
Peak memory 145436 kb
Host smart-bc94f235-683f-4c89-ba4c-f5ba36fd0447
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=525936204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.525936204
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3292226726
Short name T72
Test name
Test status
Simulation time 28326881 ps
CPU time 0.4 seconds
Started Jul 22 05:11:31 PM PDT 24
Finished Jul 22 05:11:32 PM PDT 24
Peak memory 145580 kb
Host smart-c670d052-e068-487b-abe3-65be1e6f7289
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3292226726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3292226726
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2034518461
Short name T68
Test name
Test status
Simulation time 29002055 ps
CPU time 0.4 seconds
Started Jul 22 05:13:07 PM PDT 24
Finished Jul 22 05:13:08 PM PDT 24
Peak memory 145584 kb
Host smart-f91b2ade-e681-454e-bce0-a2d27dc9a73e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2034518461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2034518461
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4159570950
Short name T71
Test name
Test status
Simulation time 26934681 ps
CPU time 0.39 seconds
Started Jul 22 05:11:30 PM PDT 24
Finished Jul 22 05:11:30 PM PDT 24
Peak memory 145496 kb
Host smart-62b574b3-d5a6-4cb3-abc2-5799730d904c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4159570950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.4159570950
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3559832997
Short name T74
Test name
Test status
Simulation time 28209198 ps
CPU time 0.38 seconds
Started Jul 22 05:11:28 PM PDT 24
Finished Jul 22 05:11:29 PM PDT 24
Peak memory 145524 kb
Host smart-64dd3237-83ea-4710-a7b4-886908b0b597
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3559832997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3559832997
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3185033237
Short name T6
Test name
Test status
Simulation time 31316512 ps
CPU time 0.4 seconds
Started Jul 22 05:11:12 PM PDT 24
Finished Jul 22 05:11:13 PM PDT 24
Peak memory 145448 kb
Host smart-0f4039c1-67a0-4927-993b-99b6e9c859cf
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3185033237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3185033237
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.492426553
Short name T62
Test name
Test status
Simulation time 27634174 ps
CPU time 0.39 seconds
Started Jul 22 05:13:45 PM PDT 24
Finished Jul 22 05:13:46 PM PDT 24
Peak memory 145568 kb
Host smart-55eec345-23df-46e9-ab44-ccd0fdbc1980
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=492426553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.492426553
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3516756239
Short name T79
Test name
Test status
Simulation time 29492941 ps
CPU time 0.39 seconds
Started Jul 22 05:16:10 PM PDT 24
Finished Jul 22 05:16:11 PM PDT 24
Peak memory 145604 kb
Host smart-411f7e40-26e2-46d1-980a-6edb85ed4299
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3516756239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3516756239
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3767436321
Short name T77
Test name
Test status
Simulation time 25763324 ps
CPU time 0.38 seconds
Started Jul 22 05:11:22 PM PDT 24
Finished Jul 22 05:11:22 PM PDT 24
Peak memory 145584 kb
Host smart-b0589b71-1d16-40fe-925e-7cf5e861883e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3767436321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3767436321
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3813169592
Short name T63
Test name
Test status
Simulation time 26552465 ps
CPU time 0.41 seconds
Started Jul 22 05:11:22 PM PDT 24
Finished Jul 22 05:11:23 PM PDT 24
Peak memory 145584 kb
Host smart-59f50451-a437-4fb1-99ea-bfe5d36c7e6d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3813169592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3813169592
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.393428315
Short name T70
Test name
Test status
Simulation time 25146276 ps
CPU time 0.38 seconds
Started Jul 22 05:11:19 PM PDT 24
Finished Jul 22 05:11:19 PM PDT 24
Peak memory 145488 kb
Host smart-780e669d-6c24-463e-b5b8-870449af5a10
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=393428315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.393428315
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.711392622
Short name T73
Test name
Test status
Simulation time 25664255 ps
CPU time 0.37 seconds
Started Jul 22 05:14:48 PM PDT 24
Finished Jul 22 05:14:49 PM PDT 24
Peak memory 145496 kb
Host smart-b32773ba-5dbc-465c-817f-f9c2770b7626
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=711392622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.711392622
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1537358797
Short name T67
Test name
Test status
Simulation time 26932813 ps
CPU time 0.4 seconds
Started Jul 22 05:11:20 PM PDT 24
Finished Jul 22 05:11:21 PM PDT 24
Peak memory 145568 kb
Host smart-40a6ec8e-6684-41da-b8de-594b6bc606af
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1537358797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1537358797
Directory /workspace/9.prim_sync_fatal_alert/latest
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