Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.92 88.92 100.00 100.00 91.67 91.67 100.00 100.00 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/5.prim_async_alert.2956118433
91.45 2.53 100.00 0.00 91.67 0.00 100.00 0.00 82.14 3.57 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/1.prim_sync_alert.2680835591
93.81 2.35 100.00 0.00 91.67 0.00 100.00 0.00 89.29 7.14 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1018635370
94.50 0.69 100.00 0.00 95.83 4.17 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/0.prim_async_alert.3376879679
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2124184616

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.3492027130
/workspace/coverage/default/10.prim_async_alert.2986870313
/workspace/coverage/default/11.prim_async_alert.1477009551
/workspace/coverage/default/12.prim_async_alert.1728715926
/workspace/coverage/default/13.prim_async_alert.3859097593
/workspace/coverage/default/14.prim_async_alert.2847779954
/workspace/coverage/default/15.prim_async_alert.2380760422
/workspace/coverage/default/17.prim_async_alert.2305571699
/workspace/coverage/default/18.prim_async_alert.919572212
/workspace/coverage/default/19.prim_async_alert.3687158598
/workspace/coverage/default/2.prim_async_alert.1013011063
/workspace/coverage/default/3.prim_async_alert.1256922959
/workspace/coverage/default/4.prim_async_alert.1759829834
/workspace/coverage/default/6.prim_async_alert.1484082879
/workspace/coverage/default/7.prim_async_alert.4189996848
/workspace/coverage/default/8.prim_async_alert.4110648308
/workspace/coverage/default/9.prim_async_alert.2967217858
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3788910575
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2863095760
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.826650942
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3640140858
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1141546074
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2339096079
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.748419312
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4079829027
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1639580639
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.179258697
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2956042906
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4221664956
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2171479058
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.770248783
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3490688426
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3350728022
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.294679271
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.758069710
/workspace/coverage/sync_alert/0.prim_sync_alert.3446464796
/workspace/coverage/sync_alert/10.prim_sync_alert.3010075101
/workspace/coverage/sync_alert/11.prim_sync_alert.3710149876
/workspace/coverage/sync_alert/12.prim_sync_alert.3298064214
/workspace/coverage/sync_alert/13.prim_sync_alert.1280874208
/workspace/coverage/sync_alert/14.prim_sync_alert.3550831096
/workspace/coverage/sync_alert/15.prim_sync_alert.672495348
/workspace/coverage/sync_alert/16.prim_sync_alert.1405702384
/workspace/coverage/sync_alert/17.prim_sync_alert.2553534079
/workspace/coverage/sync_alert/18.prim_sync_alert.3183694274
/workspace/coverage/sync_alert/19.prim_sync_alert.315873470
/workspace/coverage/sync_alert/2.prim_sync_alert.3740297021
/workspace/coverage/sync_alert/3.prim_sync_alert.855033047
/workspace/coverage/sync_alert/4.prim_sync_alert.2241288340
/workspace/coverage/sync_alert/5.prim_sync_alert.4082183052
/workspace/coverage/sync_alert/6.prim_sync_alert.2852685220
/workspace/coverage/sync_alert/7.prim_sync_alert.1299391943
/workspace/coverage/sync_alert/8.prim_sync_alert.1626673807
/workspace/coverage/sync_alert/9.prim_sync_alert.1884750868
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.723840781
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1477577508
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1397118939
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.991396753
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4003456879
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2229363201
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.991449636
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2382409874
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.209227080
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2257684308
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.762051742
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.644472019
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.890526404
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2674420769
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4061269091
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2637572879
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1707080125
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2777750993
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2171018350
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3227902942



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/5.prim_async_alert.2956118433 Jul 23 05:18:29 PM PDT 24 Jul 23 05:18:31 PM PDT 24 13291391 ps
T2 /workspace/coverage/default/18.prim_async_alert.919572212 Jul 23 05:18:58 PM PDT 24 Jul 23 05:19:00 PM PDT 24 10826445 ps
T3 /workspace/coverage/default/9.prim_async_alert.2967217858 Jul 23 05:18:29 PM PDT 24 Jul 23 05:18:30 PM PDT 24 12576674 ps
T10 /workspace/coverage/default/2.prim_async_alert.1013011063 Jul 23 05:18:30 PM PDT 24 Jul 23 05:18:31 PM PDT 24 12338265 ps
T17 /workspace/coverage/default/15.prim_async_alert.2380760422 Jul 23 05:18:57 PM PDT 24 Jul 23 05:18:58 PM PDT 24 9733577 ps
T12 /workspace/coverage/default/3.prim_async_alert.1256922959 Jul 23 05:18:29 PM PDT 24 Jul 23 05:18:31 PM PDT 24 12142041 ps
T18 /workspace/coverage/default/6.prim_async_alert.1484082879 Jul 23 05:18:29 PM PDT 24 Jul 23 05:18:31 PM PDT 24 10768755 ps
T7 /workspace/coverage/default/10.prim_async_alert.2986870313 Jul 23 05:18:38 PM PDT 24 Jul 23 05:18:40 PM PDT 24 10712253 ps
T11 /workspace/coverage/default/17.prim_async_alert.2305571699 Jul 23 05:18:58 PM PDT 24 Jul 23 05:19:00 PM PDT 24 10836270 ps
T19 /workspace/coverage/default/1.prim_async_alert.3492027130 Jul 23 05:18:20 PM PDT 24 Jul 23 05:18:21 PM PDT 24 11076340 ps
T15 /workspace/coverage/default/7.prim_async_alert.4189996848 Jul 23 05:18:28 PM PDT 24 Jul 23 05:18:29 PM PDT 24 11256837 ps
T8 /workspace/coverage/default/4.prim_async_alert.1759829834 Jul 23 05:18:30 PM PDT 24 Jul 23 05:18:31 PM PDT 24 10863610 ps
T46 /workspace/coverage/default/14.prim_async_alert.2847779954 Jul 23 05:18:50 PM PDT 24 Jul 23 05:18:51 PM PDT 24 10885435 ps
T47 /workspace/coverage/default/12.prim_async_alert.1728715926 Jul 23 05:18:38 PM PDT 24 Jul 23 05:18:39 PM PDT 24 10457410 ps
T9 /workspace/coverage/default/13.prim_async_alert.3859097593 Jul 23 05:18:40 PM PDT 24 Jul 23 05:18:41 PM PDT 24 11344013 ps
T48 /workspace/coverage/default/0.prim_async_alert.3376879679 Jul 23 05:18:22 PM PDT 24 Jul 23 05:18:23 PM PDT 24 11109499 ps
T20 /workspace/coverage/default/11.prim_async_alert.1477009551 Jul 23 05:18:40 PM PDT 24 Jul 23 05:18:41 PM PDT 24 11345875 ps
T16 /workspace/coverage/default/19.prim_async_alert.3687158598 Jul 23 05:18:58 PM PDT 24 Jul 23 05:19:00 PM PDT 24 11068071 ps
T49 /workspace/coverage/default/8.prim_async_alert.4110648308 Jul 23 05:18:32 PM PDT 24 Jul 23 05:18:33 PM PDT 24 10674070 ps
T21 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2863095760 Jul 23 05:19:00 PM PDT 24 Jul 23 05:19:02 PM PDT 24 30573357 ps
T42 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3490688426 Jul 23 05:19:01 PM PDT 24 Jul 23 05:19:03 PM PDT 24 29255575 ps
T22 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.770248783 Jul 23 05:18:57 PM PDT 24 Jul 23 05:18:58 PM PDT 24 29703686 ps
T41 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4221664956 Jul 23 05:19:08 PM PDT 24 Jul 23 05:19:12 PM PDT 24 30654429 ps
T43 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.179258697 Jul 23 05:19:07 PM PDT 24 Jul 23 05:19:09 PM PDT 24 29997440 ps
T13 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1018635370 Jul 23 05:18:57 PM PDT 24 Jul 23 05:18:59 PM PDT 24 30629647 ps
T4 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2124184616 Jul 23 05:18:58 PM PDT 24 Jul 23 05:19:00 PM PDT 24 29510926 ps
T44 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2339096079 Jul 23 05:19:10 PM PDT 24 Jul 23 05:19:13 PM PDT 24 28749803 ps
T45 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1639580639 Jul 23 05:19:09 PM PDT 24 Jul 23 05:19:12 PM PDT 24 32157671 ps
T23 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4079829027 Jul 23 05:19:08 PM PDT 24 Jul 23 05:19:11 PM PDT 24 28724406 ps
T50 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1141546074 Jul 23 05:19:08 PM PDT 24 Jul 23 05:19:11 PM PDT 24 31746129 ps
T51 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2956042906 Jul 23 05:19:11 PM PDT 24 Jul 23 05:19:14 PM PDT 24 31952153 ps
T52 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2171479058 Jul 23 05:19:01 PM PDT 24 Jul 23 05:19:03 PM PDT 24 28784289 ps
T53 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3788910575 Jul 23 05:18:59 PM PDT 24 Jul 23 05:19:01 PM PDT 24 27861819 ps
T54 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3350728022 Jul 23 05:18:57 PM PDT 24 Jul 23 05:18:59 PM PDT 24 29910031 ps
T55 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3640140858 Jul 23 05:19:09 PM PDT 24 Jul 23 05:19:12 PM PDT 24 32395935 ps
T40 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.826650942 Jul 23 05:19:08 PM PDT 24 Jul 23 05:19:11 PM PDT 24 28629275 ps
T56 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.748419312 Jul 23 05:19:09 PM PDT 24 Jul 23 05:19:12 PM PDT 24 31178437 ps
T57 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.758069710 Jul 23 05:18:58 PM PDT 24 Jul 23 05:19:00 PM PDT 24 29062314 ps
T58 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.294679271 Jul 23 05:18:58 PM PDT 24 Jul 23 05:19:00 PM PDT 24 31941557 ps
T24 /workspace/coverage/sync_alert/12.prim_sync_alert.3298064214 Jul 23 04:29:25 PM PDT 24 Jul 23 04:30:10 PM PDT 24 9764913 ps
T34 /workspace/coverage/sync_alert/10.prim_sync_alert.3010075101 Jul 23 04:29:17 PM PDT 24 Jul 23 04:29:18 PM PDT 24 9911184 ps
T25 /workspace/coverage/sync_alert/19.prim_sync_alert.315873470 Jul 23 04:29:19 PM PDT 24 Jul 23 04:29:56 PM PDT 24 10126372 ps
T26 /workspace/coverage/sync_alert/1.prim_sync_alert.2680835591 Jul 23 04:29:22 PM PDT 24 Jul 23 04:30:10 PM PDT 24 9007207 ps
T35 /workspace/coverage/sync_alert/4.prim_sync_alert.2241288340 Jul 23 04:29:26 PM PDT 24 Jul 23 04:30:11 PM PDT 24 10001712 ps
T36 /workspace/coverage/sync_alert/15.prim_sync_alert.672495348 Jul 23 04:29:17 PM PDT 24 Jul 23 04:29:19 PM PDT 24 8338158 ps
T37 /workspace/coverage/sync_alert/17.prim_sync_alert.2553534079 Jul 23 04:29:17 PM PDT 24 Jul 23 04:29:30 PM PDT 24 9129516 ps
T38 /workspace/coverage/sync_alert/0.prim_sync_alert.3446464796 Jul 23 04:29:21 PM PDT 24 Jul 23 04:30:11 PM PDT 24 9363813 ps
T14 /workspace/coverage/sync_alert/7.prim_sync_alert.1299391943 Jul 23 04:29:27 PM PDT 24 Jul 23 04:30:11 PM PDT 24 9886061 ps
T39 /workspace/coverage/sync_alert/8.prim_sync_alert.1626673807 Jul 23 04:29:16 PM PDT 24 Jul 23 04:29:18 PM PDT 24 9103407 ps
T27 /workspace/coverage/sync_alert/3.prim_sync_alert.855033047 Jul 23 04:29:23 PM PDT 24 Jul 23 04:30:11 PM PDT 24 9460171 ps
T28 /workspace/coverage/sync_alert/16.prim_sync_alert.1405702384 Jul 23 04:29:17 PM PDT 24 Jul 23 04:29:20 PM PDT 24 8431038 ps
T59 /workspace/coverage/sync_alert/11.prim_sync_alert.3710149876 Jul 23 04:29:15 PM PDT 24 Jul 23 04:29:16 PM PDT 24 9164849 ps
T29 /workspace/coverage/sync_alert/2.prim_sync_alert.3740297021 Jul 23 04:29:19 PM PDT 24 Jul 23 04:30:07 PM PDT 24 9563654 ps
T30 /workspace/coverage/sync_alert/9.prim_sync_alert.1884750868 Jul 23 04:29:26 PM PDT 24 Jul 23 04:30:11 PM PDT 24 9042495 ps
T31 /workspace/coverage/sync_alert/5.prim_sync_alert.4082183052 Jul 23 04:29:27 PM PDT 24 Jul 23 04:30:11 PM PDT 24 9294915 ps
T60 /workspace/coverage/sync_alert/13.prim_sync_alert.1280874208 Jul 23 04:29:21 PM PDT 24 Jul 23 04:30:10 PM PDT 24 9108498 ps
T61 /workspace/coverage/sync_alert/6.prim_sync_alert.2852685220 Jul 23 04:29:23 PM PDT 24 Jul 23 04:30:10 PM PDT 24 10244696 ps
T62 /workspace/coverage/sync_alert/14.prim_sync_alert.3550831096 Jul 23 04:29:23 PM PDT 24 Jul 23 04:30:11 PM PDT 24 10044270 ps
T32 /workspace/coverage/sync_alert/18.prim_sync_alert.3183694274 Jul 23 04:29:29 PM PDT 24 Jul 23 04:30:11 PM PDT 24 10241420 ps
T63 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2637572879 Jul 23 05:33:18 PM PDT 24 Jul 23 05:33:21 PM PDT 24 28524918 ps
T33 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.991449636 Jul 23 05:33:18 PM PDT 24 Jul 23 05:33:21 PM PDT 24 28611940 ps
T64 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2674420769 Jul 23 05:33:17 PM PDT 24 Jul 23 05:33:19 PM PDT 24 27844649 ps
T65 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.209227080 Jul 23 05:33:18 PM PDT 24 Jul 23 05:33:21 PM PDT 24 26944555 ps
T66 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.890526404 Jul 23 05:33:17 PM PDT 24 Jul 23 05:33:18 PM PDT 24 28227870 ps
T67 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2171018350 Jul 23 05:33:17 PM PDT 24 Jul 23 05:33:20 PM PDT 24 26682476 ps
T68 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1397118939 Jul 23 05:33:19 PM PDT 24 Jul 23 05:33:22 PM PDT 24 27056678 ps
T5 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2229363201 Jul 23 05:33:19 PM PDT 24 Jul 23 05:33:22 PM PDT 24 28283566 ps
T69 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.723840781 Jul 23 05:33:18 PM PDT 24 Jul 23 05:33:21 PM PDT 24 28118461 ps
T70 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4061269091 Jul 23 05:33:20 PM PDT 24 Jul 23 05:33:22 PM PDT 24 24756437 ps
T6 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4003456879 Jul 23 05:33:17 PM PDT 24 Jul 23 05:33:18 PM PDT 24 27571310 ps
T71 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1707080125 Jul 23 05:33:16 PM PDT 24 Jul 23 05:33:17 PM PDT 24 25348010 ps
T72 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2382409874 Jul 23 05:33:17 PM PDT 24 Jul 23 05:33:19 PM PDT 24 30148216 ps
T73 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3227902942 Jul 23 05:33:17 PM PDT 24 Jul 23 05:33:19 PM PDT 24 25756250 ps
T74 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.991396753 Jul 23 05:33:19 PM PDT 24 Jul 23 05:33:22 PM PDT 24 26176235 ps
T75 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2777750993 Jul 23 05:33:18 PM PDT 24 Jul 23 05:33:21 PM PDT 24 29106415 ps
T76 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1477577508 Jul 23 05:33:16 PM PDT 24 Jul 23 05:33:18 PM PDT 24 26033020 ps
T77 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.644472019 Jul 23 05:33:19 PM PDT 24 Jul 23 05:33:22 PM PDT 24 26257252 ps
T78 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.762051742 Jul 23 05:33:17 PM PDT 24 Jul 23 05:33:19 PM PDT 24 27776669 ps
T79 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2257684308 Jul 23 05:33:16 PM PDT 24 Jul 23 05:33:17 PM PDT 24 28256448 ps

Test location /workspace/coverage/default/5.prim_async_alert.2956118433
Short name T1
Test name
Test status
Simulation time 13291391 ps
CPU time 0.44 seconds
Started Jul 23 05:18:29 PM PDT 24
Finished Jul 23 05:18:31 PM PDT 24
Peak memory 145732 kb
Host smart-a242f5a3-3bc8-42ff-bb86-ad68bb13443b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956118433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2956118433
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2680835591
Short name T26
Test name
Test status
Simulation time 9007207 ps
CPU time 0.39 seconds
Started Jul 23 04:29:22 PM PDT 24
Finished Jul 23 04:30:10 PM PDT 24
Peak memory 145368 kb
Host smart-65b9629b-a349-4ca0-baa3-2c5ea38202d6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2680835591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2680835591
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1018635370
Short name T13
Test name
Test status
Simulation time 30629647 ps
CPU time 0.39 seconds
Started Jul 23 05:18:57 PM PDT 24
Finished Jul 23 05:18:59 PM PDT 24
Peak memory 145252 kb
Host smart-6c3d35a6-1902-4b66-a457-91b4c55fb4a1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1018635370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1018635370
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3376879679
Short name T48
Test name
Test status
Simulation time 11109499 ps
CPU time 0.39 seconds
Started Jul 23 05:18:22 PM PDT 24
Finished Jul 23 05:18:23 PM PDT 24
Peak memory 145800 kb
Host smart-bfa1b407-0846-48c7-86cb-c4205a8e9324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376879679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3376879679
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2124184616
Short name T4
Test name
Test status
Simulation time 29510926 ps
CPU time 0.44 seconds
Started Jul 23 05:18:58 PM PDT 24
Finished Jul 23 05:19:00 PM PDT 24
Peak memory 145264 kb
Host smart-97a155a8-c882-4b7a-81ca-914fc834fc2f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2124184616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2124184616
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3492027130
Short name T19
Test name
Test status
Simulation time 11076340 ps
CPU time 0.39 seconds
Started Jul 23 05:18:20 PM PDT 24
Finished Jul 23 05:18:21 PM PDT 24
Peak memory 145792 kb
Host smart-50ce2d8a-8dcb-4e89-b5bb-e98333e5311b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492027130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3492027130
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2986870313
Short name T7
Test name
Test status
Simulation time 10712253 ps
CPU time 0.37 seconds
Started Jul 23 05:18:38 PM PDT 24
Finished Jul 23 05:18:40 PM PDT 24
Peak memory 145804 kb
Host smart-86a2704d-7ba9-4a28-8d9f-b5cc2aa55a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986870313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2986870313
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1477009551
Short name T20
Test name
Test status
Simulation time 11345875 ps
CPU time 0.39 seconds
Started Jul 23 05:18:40 PM PDT 24
Finished Jul 23 05:18:41 PM PDT 24
Peak memory 145716 kb
Host smart-6132648c-bd8b-4361-ae6d-dbe8893fa55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477009551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1477009551
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1728715926
Short name T47
Test name
Test status
Simulation time 10457410 ps
CPU time 0.38 seconds
Started Jul 23 05:18:38 PM PDT 24
Finished Jul 23 05:18:39 PM PDT 24
Peak memory 145804 kb
Host smart-70c6550a-7628-4178-a657-b6ef08d66e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728715926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1728715926
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3859097593
Short name T9
Test name
Test status
Simulation time 11344013 ps
CPU time 0.39 seconds
Started Jul 23 05:18:40 PM PDT 24
Finished Jul 23 05:18:41 PM PDT 24
Peak memory 145716 kb
Host smart-d12ed844-36ca-46c8-92e4-c0539935a81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859097593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3859097593
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2847779954
Short name T46
Test name
Test status
Simulation time 10885435 ps
CPU time 0.4 seconds
Started Jul 23 05:18:50 PM PDT 24
Finished Jul 23 05:18:51 PM PDT 24
Peak memory 145736 kb
Host smart-ceaffed3-3b2f-44fc-bf5e-2aab9a2d973b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847779954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2847779954
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.2380760422
Short name T17
Test name
Test status
Simulation time 9733577 ps
CPU time 0.39 seconds
Started Jul 23 05:18:57 PM PDT 24
Finished Jul 23 05:18:58 PM PDT 24
Peak memory 145720 kb
Host smart-358eb90c-3245-451b-87d8-b8336899a991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380760422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2380760422
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2305571699
Short name T11
Test name
Test status
Simulation time 10836270 ps
CPU time 0.38 seconds
Started Jul 23 05:18:58 PM PDT 24
Finished Jul 23 05:19:00 PM PDT 24
Peak memory 145804 kb
Host smart-213e47a1-40b1-4749-9469-47c2d1e204a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305571699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2305571699
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.919572212
Short name T2
Test name
Test status
Simulation time 10826445 ps
CPU time 0.39 seconds
Started Jul 23 05:18:58 PM PDT 24
Finished Jul 23 05:19:00 PM PDT 24
Peak memory 145800 kb
Host smart-1302bcc5-aeb4-4136-acf4-699cf785a586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919572212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.919572212
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3687158598
Short name T16
Test name
Test status
Simulation time 11068071 ps
CPU time 0.39 seconds
Started Jul 23 05:18:58 PM PDT 24
Finished Jul 23 05:19:00 PM PDT 24
Peak memory 145816 kb
Host smart-72eba32f-5f52-4de2-b351-3acddcc1988b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687158598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3687158598
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.1013011063
Short name T10
Test name
Test status
Simulation time 12338265 ps
CPU time 0.4 seconds
Started Jul 23 05:18:30 PM PDT 24
Finished Jul 23 05:18:31 PM PDT 24
Peak memory 145696 kb
Host smart-32352f5f-db45-4639-bb50-f6f9fb42cc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013011063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1013011063
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1256922959
Short name T12
Test name
Test status
Simulation time 12142041 ps
CPU time 0.4 seconds
Started Jul 23 05:18:29 PM PDT 24
Finished Jul 23 05:18:31 PM PDT 24
Peak memory 145808 kb
Host smart-511a23ad-bd9b-4f9c-94f5-3248e7476853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256922959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1256922959
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1759829834
Short name T8
Test name
Test status
Simulation time 10863610 ps
CPU time 0.39 seconds
Started Jul 23 05:18:30 PM PDT 24
Finished Jul 23 05:18:31 PM PDT 24
Peak memory 145800 kb
Host smart-28179f57-0558-41dd-a2ba-ce958fd45d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759829834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1759829834
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1484082879
Short name T18
Test name
Test status
Simulation time 10768755 ps
CPU time 0.39 seconds
Started Jul 23 05:18:29 PM PDT 24
Finished Jul 23 05:18:31 PM PDT 24
Peak memory 145800 kb
Host smart-45d416e6-91ef-4a01-9419-0f690b43af90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484082879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1484082879
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.4189996848
Short name T15
Test name
Test status
Simulation time 11256837 ps
CPU time 0.39 seconds
Started Jul 23 05:18:28 PM PDT 24
Finished Jul 23 05:18:29 PM PDT 24
Peak memory 145796 kb
Host smart-7b9e91d6-a43b-457d-82a1-46117901d6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189996848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.4189996848
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.4110648308
Short name T49
Test name
Test status
Simulation time 10674070 ps
CPU time 0.38 seconds
Started Jul 23 05:18:32 PM PDT 24
Finished Jul 23 05:18:33 PM PDT 24
Peak memory 145704 kb
Host smart-b0503822-8c3f-4343-a6d0-314d8f76c9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110648308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.4110648308
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2967217858
Short name T3
Test name
Test status
Simulation time 12576674 ps
CPU time 0.39 seconds
Started Jul 23 05:18:29 PM PDT 24
Finished Jul 23 05:18:30 PM PDT 24
Peak memory 145740 kb
Host smart-1cbb5d3b-936b-4dbf-9a71-3b7c581d15f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967217858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2967217858
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3788910575
Short name T53
Test name
Test status
Simulation time 27861819 ps
CPU time 0.4 seconds
Started Jul 23 05:18:59 PM PDT 24
Finished Jul 23 05:19:01 PM PDT 24
Peak memory 145308 kb
Host smart-617f3e78-97ec-4821-9b16-d728eeca2bff
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3788910575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3788910575
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2863095760
Short name T21
Test name
Test status
Simulation time 30573357 ps
CPU time 0.41 seconds
Started Jul 23 05:19:00 PM PDT 24
Finished Jul 23 05:19:02 PM PDT 24
Peak memory 145264 kb
Host smart-8b38a357-3275-4cd3-9ff7-2d8deec2ebed
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2863095760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2863095760
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.826650942
Short name T40
Test name
Test status
Simulation time 28629275 ps
CPU time 0.43 seconds
Started Jul 23 05:19:08 PM PDT 24
Finished Jul 23 05:19:11 PM PDT 24
Peak memory 145308 kb
Host smart-49849b5c-782e-4926-b818-92a1584e4ef1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=826650942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.826650942
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3640140858
Short name T55
Test name
Test status
Simulation time 32395935 ps
CPU time 0.4 seconds
Started Jul 23 05:19:09 PM PDT 24
Finished Jul 23 05:19:12 PM PDT 24
Peak memory 145252 kb
Host smart-be0893a8-4f6a-4917-8c1b-c71b520620e5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3640140858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3640140858
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1141546074
Short name T50
Test name
Test status
Simulation time 31746129 ps
CPU time 0.4 seconds
Started Jul 23 05:19:08 PM PDT 24
Finished Jul 23 05:19:11 PM PDT 24
Peak memory 145220 kb
Host smart-c4195de7-a030-494c-9820-6391e2c3ecb6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1141546074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1141546074
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2339096079
Short name T44
Test name
Test status
Simulation time 28749803 ps
CPU time 0.4 seconds
Started Jul 23 05:19:10 PM PDT 24
Finished Jul 23 05:19:13 PM PDT 24
Peak memory 145264 kb
Host smart-8feee6b0-4bea-43d2-8b68-efc6c4a34e76
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2339096079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2339096079
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.748419312
Short name T56
Test name
Test status
Simulation time 31178437 ps
CPU time 0.39 seconds
Started Jul 23 05:19:09 PM PDT 24
Finished Jul 23 05:19:12 PM PDT 24
Peak memory 145308 kb
Host smart-e5bee24e-22a8-4b00-a622-2f3ac6779896
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=748419312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.748419312
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4079829027
Short name T23
Test name
Test status
Simulation time 28724406 ps
CPU time 0.41 seconds
Started Jul 23 05:19:08 PM PDT 24
Finished Jul 23 05:19:11 PM PDT 24
Peak memory 145320 kb
Host smart-a5e815c1-da6e-44dd-88d8-4f60ee839435
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4079829027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.4079829027
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1639580639
Short name T45
Test name
Test status
Simulation time 32157671 ps
CPU time 0.4 seconds
Started Jul 23 05:19:09 PM PDT 24
Finished Jul 23 05:19:12 PM PDT 24
Peak memory 145260 kb
Host smart-eace40f2-381b-4b59-8e8c-1a5844929193
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1639580639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1639580639
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.179258697
Short name T43
Test name
Test status
Simulation time 29997440 ps
CPU time 0.41 seconds
Started Jul 23 05:19:07 PM PDT 24
Finished Jul 23 05:19:09 PM PDT 24
Peak memory 145236 kb
Host smart-3a6f46b4-f9c8-406c-9e4a-5a818137b43e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=179258697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.179258697
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2956042906
Short name T51
Test name
Test status
Simulation time 31952153 ps
CPU time 0.41 seconds
Started Jul 23 05:19:11 PM PDT 24
Finished Jul 23 05:19:14 PM PDT 24
Peak memory 145280 kb
Host smart-dbb414de-fd18-4142-bf3e-f943552beeb4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2956042906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2956042906
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4221664956
Short name T41
Test name
Test status
Simulation time 30654429 ps
CPU time 0.39 seconds
Started Jul 23 05:19:08 PM PDT 24
Finished Jul 23 05:19:12 PM PDT 24
Peak memory 145316 kb
Host smart-743bec6e-eb66-410f-b448-0f023de2bc74
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4221664956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.4221664956
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2171479058
Short name T52
Test name
Test status
Simulation time 28784289 ps
CPU time 0.41 seconds
Started Jul 23 05:19:01 PM PDT 24
Finished Jul 23 05:19:03 PM PDT 24
Peak memory 145296 kb
Host smart-77e8b754-9b2f-465b-9016-74e79c1bacb2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2171479058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2171479058
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.770248783
Short name T22
Test name
Test status
Simulation time 29703686 ps
CPU time 0.4 seconds
Started Jul 23 05:18:57 PM PDT 24
Finished Jul 23 05:18:58 PM PDT 24
Peak memory 145284 kb
Host smart-29d4a0a0-5913-497b-b1d1-a5e2cf2a1ec3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=770248783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.770248783
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3490688426
Short name T42
Test name
Test status
Simulation time 29255575 ps
CPU time 0.4 seconds
Started Jul 23 05:19:01 PM PDT 24
Finished Jul 23 05:19:03 PM PDT 24
Peak memory 145296 kb
Host smart-cc0c2d02-91c4-4044-99bd-a2a7ba645688
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3490688426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3490688426
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3350728022
Short name T54
Test name
Test status
Simulation time 29910031 ps
CPU time 0.43 seconds
Started Jul 23 05:18:57 PM PDT 24
Finished Jul 23 05:18:59 PM PDT 24
Peak memory 145252 kb
Host smart-0c54a543-7351-48f5-b0b2-6158ef20a1c5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3350728022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3350728022
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.294679271
Short name T58
Test name
Test status
Simulation time 31941557 ps
CPU time 0.4 seconds
Started Jul 23 05:18:58 PM PDT 24
Finished Jul 23 05:19:00 PM PDT 24
Peak memory 145236 kb
Host smart-299ec6a6-45b6-4fd6-9554-0cdecedbcd70
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=294679271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.294679271
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.758069710
Short name T57
Test name
Test status
Simulation time 29062314 ps
CPU time 0.44 seconds
Started Jul 23 05:18:58 PM PDT 24
Finished Jul 23 05:19:00 PM PDT 24
Peak memory 145272 kb
Host smart-d614cde2-7c98-4317-979b-781695069e4a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=758069710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.758069710
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3446464796
Short name T38
Test name
Test status
Simulation time 9363813 ps
CPU time 0.38 seconds
Started Jul 23 04:29:21 PM PDT 24
Finished Jul 23 04:30:11 PM PDT 24
Peak memory 145436 kb
Host smart-4d167e10-53d3-4391-b541-bd785e5f1207
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3446464796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3446464796
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3010075101
Short name T34
Test name
Test status
Simulation time 9911184 ps
CPU time 0.38 seconds
Started Jul 23 04:29:17 PM PDT 24
Finished Jul 23 04:29:18 PM PDT 24
Peak memory 145440 kb
Host smart-197e3fab-7a90-4554-b380-aab347ac9fe6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3010075101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3010075101
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3710149876
Short name T59
Test name
Test status
Simulation time 9164849 ps
CPU time 0.38 seconds
Started Jul 23 04:29:15 PM PDT 24
Finished Jul 23 04:29:16 PM PDT 24
Peak memory 145428 kb
Host smart-2fd5bd00-0bbf-4dfd-af5a-58bbd4f78886
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3710149876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3710149876
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3298064214
Short name T24
Test name
Test status
Simulation time 9764913 ps
CPU time 0.42 seconds
Started Jul 23 04:29:25 PM PDT 24
Finished Jul 23 04:30:10 PM PDT 24
Peak memory 145388 kb
Host smart-2b3765b9-99e8-400d-ba00-9a6f1a408b6c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3298064214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3298064214
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1280874208
Short name T60
Test name
Test status
Simulation time 9108498 ps
CPU time 0.39 seconds
Started Jul 23 04:29:21 PM PDT 24
Finished Jul 23 04:30:10 PM PDT 24
Peak memory 145424 kb
Host smart-4c224673-8659-4f8b-8091-2d1af3105f9b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1280874208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1280874208
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3550831096
Short name T62
Test name
Test status
Simulation time 10044270 ps
CPU time 0.38 seconds
Started Jul 23 04:29:23 PM PDT 24
Finished Jul 23 04:30:11 PM PDT 24
Peak memory 145392 kb
Host smart-5a436f42-3473-4475-a5f0-b5bd3056bd0d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3550831096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3550831096
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.672495348
Short name T36
Test name
Test status
Simulation time 8338158 ps
CPU time 0.37 seconds
Started Jul 23 04:29:17 PM PDT 24
Finished Jul 23 04:29:19 PM PDT 24
Peak memory 145440 kb
Host smart-a3f847a0-19ab-424b-a079-a6ca9fa3fc52
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=672495348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.672495348
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1405702384
Short name T28
Test name
Test status
Simulation time 8431038 ps
CPU time 0.42 seconds
Started Jul 23 04:29:17 PM PDT 24
Finished Jul 23 04:29:20 PM PDT 24
Peak memory 145440 kb
Host smart-7b3a0980-1030-4326-80fb-0daf6cb7d45b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1405702384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1405702384
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2553534079
Short name T37
Test name
Test status
Simulation time 9129516 ps
CPU time 0.38 seconds
Started Jul 23 04:29:17 PM PDT 24
Finished Jul 23 04:29:30 PM PDT 24
Peak memory 145440 kb
Host smart-c0301c9c-fbb3-470a-8001-f0c5b4952465
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2553534079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2553534079
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3183694274
Short name T32
Test name
Test status
Simulation time 10241420 ps
CPU time 0.37 seconds
Started Jul 23 04:29:29 PM PDT 24
Finished Jul 23 04:30:11 PM PDT 24
Peak memory 145416 kb
Host smart-5220b9bc-9603-463d-87a1-f00c6dc5e473
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3183694274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3183694274
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.315873470
Short name T25
Test name
Test status
Simulation time 10126372 ps
CPU time 0.38 seconds
Started Jul 23 04:29:19 PM PDT 24
Finished Jul 23 04:29:56 PM PDT 24
Peak memory 145428 kb
Host smart-1d32f3b2-1bbe-46de-944e-e895d9dd6b8a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=315873470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.315873470
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3740297021
Short name T29
Test name
Test status
Simulation time 9563654 ps
CPU time 0.38 seconds
Started Jul 23 04:29:19 PM PDT 24
Finished Jul 23 04:30:07 PM PDT 24
Peak memory 145448 kb
Host smart-0de511fa-255d-46df-a891-ddc9d2471482
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3740297021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3740297021
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.855033047
Short name T27
Test name
Test status
Simulation time 9460171 ps
CPU time 0.39 seconds
Started Jul 23 04:29:23 PM PDT 24
Finished Jul 23 04:30:11 PM PDT 24
Peak memory 145396 kb
Host smart-1f01efce-3a40-4697-9bb6-276699b2dea7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=855033047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.855033047
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2241288340
Short name T35
Test name
Test status
Simulation time 10001712 ps
CPU time 0.37 seconds
Started Jul 23 04:29:26 PM PDT 24
Finished Jul 23 04:30:11 PM PDT 24
Peak memory 145392 kb
Host smart-f51b74f8-1ad5-4690-a320-80ed6f1c741a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2241288340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2241288340
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.4082183052
Short name T31
Test name
Test status
Simulation time 9294915 ps
CPU time 0.39 seconds
Started Jul 23 04:29:27 PM PDT 24
Finished Jul 23 04:30:11 PM PDT 24
Peak memory 145416 kb
Host smart-c060e40a-acba-4cf0-bd78-702f5969819e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4082183052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.4082183052
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2852685220
Short name T61
Test name
Test status
Simulation time 10244696 ps
CPU time 0.41 seconds
Started Jul 23 04:29:23 PM PDT 24
Finished Jul 23 04:30:10 PM PDT 24
Peak memory 145408 kb
Host smart-7aa6cb6b-af62-4650-b696-cff4def058b5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2852685220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2852685220
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1299391943
Short name T14
Test name
Test status
Simulation time 9886061 ps
CPU time 0.37 seconds
Started Jul 23 04:29:27 PM PDT 24
Finished Jul 23 04:30:11 PM PDT 24
Peak memory 145420 kb
Host smart-a1409ab8-ebfd-4747-8c52-5923edf28e7f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1299391943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1299391943
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1626673807
Short name T39
Test name
Test status
Simulation time 9103407 ps
CPU time 0.37 seconds
Started Jul 23 04:29:16 PM PDT 24
Finished Jul 23 04:29:18 PM PDT 24
Peak memory 145440 kb
Host smart-8418f9ae-daea-45a5-8003-34a9e0b9d6fc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1626673807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1626673807
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1884750868
Short name T30
Test name
Test status
Simulation time 9042495 ps
CPU time 0.38 seconds
Started Jul 23 04:29:26 PM PDT 24
Finished Jul 23 04:30:11 PM PDT 24
Peak memory 145420 kb
Host smart-7e8c2ce5-7ddb-4695-9ba7-eccd12e16000
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1884750868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1884750868
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.723840781
Short name T69
Test name
Test status
Simulation time 28118461 ps
CPU time 0.4 seconds
Started Jul 23 05:33:18 PM PDT 24
Finished Jul 23 05:33:21 PM PDT 24
Peak memory 145576 kb
Host smart-b5e0e359-9d8b-4ff8-ae63-4fd3fc08f7a3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=723840781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.723840781
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1477577508
Short name T76
Test name
Test status
Simulation time 26033020 ps
CPU time 0.39 seconds
Started Jul 23 05:33:16 PM PDT 24
Finished Jul 23 05:33:18 PM PDT 24
Peak memory 145560 kb
Host smart-1983979f-51ae-4564-9795-6852ad1665d7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1477577508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1477577508
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1397118939
Short name T68
Test name
Test status
Simulation time 27056678 ps
CPU time 0.39 seconds
Started Jul 23 05:33:19 PM PDT 24
Finished Jul 23 05:33:22 PM PDT 24
Peak memory 145612 kb
Host smart-e2e60f14-475a-414a-93d8-ee63e7687d20
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1397118939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1397118939
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.991396753
Short name T74
Test name
Test status
Simulation time 26176235 ps
CPU time 0.39 seconds
Started Jul 23 05:33:19 PM PDT 24
Finished Jul 23 05:33:22 PM PDT 24
Peak memory 145608 kb
Host smart-72523f9a-1294-45d7-a881-3cb1034ec263
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=991396753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.991396753
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4003456879
Short name T6
Test name
Test status
Simulation time 27571310 ps
CPU time 0.39 seconds
Started Jul 23 05:33:17 PM PDT 24
Finished Jul 23 05:33:18 PM PDT 24
Peak memory 145584 kb
Host smart-bdd28943-58a2-4752-ae13-7a3ca92dcd14
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4003456879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.4003456879
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2229363201
Short name T5
Test name
Test status
Simulation time 28283566 ps
CPU time 0.4 seconds
Started Jul 23 05:33:19 PM PDT 24
Finished Jul 23 05:33:22 PM PDT 24
Peak memory 145612 kb
Host smart-5df8534e-152d-423f-92a5-8617e96aa3f9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2229363201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2229363201
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.991449636
Short name T33
Test name
Test status
Simulation time 28611940 ps
CPU time 0.45 seconds
Started Jul 23 05:33:18 PM PDT 24
Finished Jul 23 05:33:21 PM PDT 24
Peak memory 145548 kb
Host smart-b0b6c94d-5bf6-48c2-990f-5929a8203644
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=991449636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.991449636
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2382409874
Short name T72
Test name
Test status
Simulation time 30148216 ps
CPU time 0.4 seconds
Started Jul 23 05:33:17 PM PDT 24
Finished Jul 23 05:33:19 PM PDT 24
Peak memory 145552 kb
Host smart-5dbe4e54-6fe0-4a90-ba3b-fafeba78f0fb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2382409874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2382409874
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.209227080
Short name T65
Test name
Test status
Simulation time 26944555 ps
CPU time 0.4 seconds
Started Jul 23 05:33:18 PM PDT 24
Finished Jul 23 05:33:21 PM PDT 24
Peak memory 145572 kb
Host smart-402163b5-1e9e-4839-b255-465ca0c6a38d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=209227080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.209227080
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2257684308
Short name T79
Test name
Test status
Simulation time 28256448 ps
CPU time 0.4 seconds
Started Jul 23 05:33:16 PM PDT 24
Finished Jul 23 05:33:17 PM PDT 24
Peak memory 145636 kb
Host smart-4d6d11c7-d58d-486f-8c4f-1d682e144782
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2257684308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2257684308
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.762051742
Short name T78
Test name
Test status
Simulation time 27776669 ps
CPU time 0.4 seconds
Started Jul 23 05:33:17 PM PDT 24
Finished Jul 23 05:33:19 PM PDT 24
Peak memory 145576 kb
Host smart-f3c124ba-95d6-4607-8286-1c070f634cf2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=762051742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.762051742
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.644472019
Short name T77
Test name
Test status
Simulation time 26257252 ps
CPU time 0.41 seconds
Started Jul 23 05:33:19 PM PDT 24
Finished Jul 23 05:33:22 PM PDT 24
Peak memory 145468 kb
Host smart-30d72afe-9484-49d5-ac48-f7028f7597f1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=644472019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.644472019
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.890526404
Short name T66
Test name
Test status
Simulation time 28227870 ps
CPU time 0.4 seconds
Started Jul 23 05:33:17 PM PDT 24
Finished Jul 23 05:33:18 PM PDT 24
Peak memory 145616 kb
Host smart-a52297bc-bec2-443b-bebb-ac47be5b59ff
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=890526404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.890526404
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2674420769
Short name T64
Test name
Test status
Simulation time 27844649 ps
CPU time 0.4 seconds
Started Jul 23 05:33:17 PM PDT 24
Finished Jul 23 05:33:19 PM PDT 24
Peak memory 145552 kb
Host smart-c07230c3-5809-41ac-ba69-afad05366998
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2674420769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2674420769
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4061269091
Short name T70
Test name
Test status
Simulation time 24756437 ps
CPU time 0.39 seconds
Started Jul 23 05:33:20 PM PDT 24
Finished Jul 23 05:33:22 PM PDT 24
Peak memory 145564 kb
Host smart-65ea268f-3bc6-4c6f-88c6-4973a1d8facc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4061269091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.4061269091
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2637572879
Short name T63
Test name
Test status
Simulation time 28524918 ps
CPU time 0.42 seconds
Started Jul 23 05:33:18 PM PDT 24
Finished Jul 23 05:33:21 PM PDT 24
Peak memory 145564 kb
Host smart-212497ad-0d18-4693-9584-046c3b906185
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2637572879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2637572879
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1707080125
Short name T71
Test name
Test status
Simulation time 25348010 ps
CPU time 0.4 seconds
Started Jul 23 05:33:16 PM PDT 24
Finished Jul 23 05:33:17 PM PDT 24
Peak memory 145632 kb
Host smart-2da0cf4c-6772-4eb9-a2a0-a5812aff1c29
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1707080125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1707080125
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2777750993
Short name T75
Test name
Test status
Simulation time 29106415 ps
CPU time 0.41 seconds
Started Jul 23 05:33:18 PM PDT 24
Finished Jul 23 05:33:21 PM PDT 24
Peak memory 145552 kb
Host smart-58352292-28f5-4b91-a5a8-50a4fd6df681
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2777750993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2777750993
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2171018350
Short name T67
Test name
Test status
Simulation time 26682476 ps
CPU time 0.4 seconds
Started Jul 23 05:33:17 PM PDT 24
Finished Jul 23 05:33:20 PM PDT 24
Peak memory 145504 kb
Host smart-2c036309-d7ec-4e87-bcad-c8663a4b5218
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2171018350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2171018350
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3227902942
Short name T73
Test name
Test status
Simulation time 25756250 ps
CPU time 0.45 seconds
Started Jul 23 05:33:17 PM PDT 24
Finished Jul 23 05:33:19 PM PDT 24
Peak memory 145572 kb
Host smart-9c003255-1d81-4cc6-a6e5-885165e670fc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3227902942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3227902942
Directory /workspace/9.prim_sync_fatal_alert/latest
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