Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.88 88.88 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/11.prim_async_alert.500054527
92.01 3.13 100.00 0.00 93.75 0.00 100.00 0.00 85.71 7.14 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/12.prim_sync_alert.3311032382
93.56 1.55 100.00 0.00 93.75 0.00 100.00 0.00 85.71 0.00 95.83 0.00 86.05 9.30 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2017633828
94.50 0.94 100.00 0.00 95.83 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/4.prim_async_alert.2579132102
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3002774044

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.953502233
/workspace/coverage/default/1.prim_async_alert.1202171343
/workspace/coverage/default/10.prim_async_alert.3955689482
/workspace/coverage/default/12.prim_async_alert.2036568596
/workspace/coverage/default/13.prim_async_alert.1547816828
/workspace/coverage/default/14.prim_async_alert.19073301
/workspace/coverage/default/15.prim_async_alert.4165501179
/workspace/coverage/default/16.prim_async_alert.2513403214
/workspace/coverage/default/17.prim_async_alert.1715173704
/workspace/coverage/default/18.prim_async_alert.2445775817
/workspace/coverage/default/19.prim_async_alert.2794039570
/workspace/coverage/default/2.prim_async_alert.2809835133
/workspace/coverage/default/3.prim_async_alert.3383342926
/workspace/coverage/default/5.prim_async_alert.3513810999
/workspace/coverage/default/6.prim_async_alert.1424867566
/workspace/coverage/default/7.prim_async_alert.3078236708
/workspace/coverage/default/8.prim_async_alert.1878661698
/workspace/coverage/default/9.prim_async_alert.2090166445
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1280979385
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.277459651
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3156487856
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.994981407
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2530983304
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.756616744
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.501613730
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.961110237
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1296811151
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1164353725
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1499810051
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2683147479
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2370244682
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2140323278
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1815187922
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3018874217
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2714310479
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3492939817
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4108944030
/workspace/coverage/sync_alert/0.prim_sync_alert.1421291277
/workspace/coverage/sync_alert/1.prim_sync_alert.2858856755
/workspace/coverage/sync_alert/10.prim_sync_alert.1721831163
/workspace/coverage/sync_alert/11.prim_sync_alert.1992099600
/workspace/coverage/sync_alert/13.prim_sync_alert.365945462
/workspace/coverage/sync_alert/14.prim_sync_alert.3308049398
/workspace/coverage/sync_alert/15.prim_sync_alert.2956228043
/workspace/coverage/sync_alert/16.prim_sync_alert.685054949
/workspace/coverage/sync_alert/17.prim_sync_alert.399497423
/workspace/coverage/sync_alert/18.prim_sync_alert.2187047464
/workspace/coverage/sync_alert/19.prim_sync_alert.116095622
/workspace/coverage/sync_alert/2.prim_sync_alert.2641308188
/workspace/coverage/sync_alert/3.prim_sync_alert.3192140474
/workspace/coverage/sync_alert/4.prim_sync_alert.730394536
/workspace/coverage/sync_alert/5.prim_sync_alert.2981347445
/workspace/coverage/sync_alert/6.prim_sync_alert.3589057234
/workspace/coverage/sync_alert/7.prim_sync_alert.955395781
/workspace/coverage/sync_alert/8.prim_sync_alert.495073327
/workspace/coverage/sync_alert/9.prim_sync_alert.2394381033
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4137187470
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3052320293
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3853918822
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1783640470
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.571279511
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1064211448
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2848712386
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1010359387
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1099899318
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2374383223
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1330865999
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2001701585
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1149132616
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3090674310
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3479595166
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3533197641
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1689498160
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3502479793
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1093351278



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/2.prim_async_alert.2809835133 Jul 24 04:43:22 PM PDT 24 Jul 24 04:43:23 PM PDT 24 11371583 ps
T2 /workspace/coverage/default/6.prim_async_alert.1424867566 Jul 24 04:43:23 PM PDT 24 Jul 24 04:43:23 PM PDT 24 11294666 ps
T3 /workspace/coverage/default/12.prim_async_alert.2036568596 Jul 24 04:43:24 PM PDT 24 Jul 24 04:43:25 PM PDT 24 11396886 ps
T6 /workspace/coverage/default/11.prim_async_alert.500054527 Jul 24 04:43:24 PM PDT 24 Jul 24 04:43:25 PM PDT 24 11553961 ps
T15 /workspace/coverage/default/9.prim_async_alert.2090166445 Jul 24 04:43:21 PM PDT 24 Jul 24 04:43:22 PM PDT 24 12258391 ps
T11 /workspace/coverage/default/14.prim_async_alert.19073301 Jul 24 04:43:22 PM PDT 24 Jul 24 04:43:23 PM PDT 24 12726522 ps
T18 /workspace/coverage/default/16.prim_async_alert.2513403214 Jul 24 04:43:22 PM PDT 24 Jul 24 04:43:23 PM PDT 24 10997009 ps
T16 /workspace/coverage/default/15.prim_async_alert.4165501179 Jul 24 04:43:24 PM PDT 24 Jul 24 04:43:24 PM PDT 24 12294501 ps
T8 /workspace/coverage/default/17.prim_async_alert.1715173704 Jul 24 04:43:22 PM PDT 24 Jul 24 04:43:23 PM PDT 24 11672999 ps
T19 /workspace/coverage/default/0.prim_async_alert.953502233 Jul 24 04:43:33 PM PDT 24 Jul 24 04:43:34 PM PDT 24 11610810 ps
T7 /workspace/coverage/default/7.prim_async_alert.3078236708 Jul 24 04:43:22 PM PDT 24 Jul 24 04:43:22 PM PDT 24 10984694 ps
T9 /workspace/coverage/default/10.prim_async_alert.3955689482 Jul 24 04:43:20 PM PDT 24 Jul 24 04:43:21 PM PDT 24 11962064 ps
T47 /workspace/coverage/default/19.prim_async_alert.2794039570 Jul 24 04:43:25 PM PDT 24 Jul 24 04:43:26 PM PDT 24 10118667 ps
T10 /workspace/coverage/default/5.prim_async_alert.3513810999 Jul 24 04:43:25 PM PDT 24 Jul 24 04:43:25 PM PDT 24 11569911 ps
T48 /workspace/coverage/default/18.prim_async_alert.2445775817 Jul 24 04:43:25 PM PDT 24 Jul 24 04:43:25 PM PDT 24 11935898 ps
T20 /workspace/coverage/default/13.prim_async_alert.1547816828 Jul 24 04:43:24 PM PDT 24 Jul 24 04:43:25 PM PDT 24 11466012 ps
T13 /workspace/coverage/default/1.prim_async_alert.1202171343 Jul 24 04:43:25 PM PDT 24 Jul 24 04:43:26 PM PDT 24 11182689 ps
T17 /workspace/coverage/default/4.prim_async_alert.2579132102 Jul 24 04:43:22 PM PDT 24 Jul 24 04:43:23 PM PDT 24 11978564 ps
T14 /workspace/coverage/default/3.prim_async_alert.3383342926 Jul 24 04:43:22 PM PDT 24 Jul 24 04:43:23 PM PDT 24 11265299 ps
T21 /workspace/coverage/default/8.prim_async_alert.1878661698 Jul 24 04:43:24 PM PDT 24 Jul 24 04:43:25 PM PDT 24 10407027 ps
T39 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2140323278 Jul 24 04:48:31 PM PDT 24 Jul 24 04:48:32 PM PDT 24 30700957 ps
T40 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.994981407 Jul 24 04:48:29 PM PDT 24 Jul 24 04:48:30 PM PDT 24 29216384 ps
T41 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1296811151 Jul 24 04:48:43 PM PDT 24 Jul 24 04:48:44 PM PDT 24 32468154 ps
T42 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3156487856 Jul 24 04:48:27 PM PDT 24 Jul 24 04:48:27 PM PDT 24 30589226 ps
T43 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3492939817 Jul 24 04:48:23 PM PDT 24 Jul 24 04:48:24 PM PDT 24 29769107 ps
T22 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2017633828 Jul 24 04:48:16 PM PDT 24 Jul 24 04:48:17 PM PDT 24 30404541 ps
T44 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.277459651 Jul 24 04:48:38 PM PDT 24 Jul 24 04:48:39 PM PDT 24 29685366 ps
T12 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.961110237 Jul 24 04:48:25 PM PDT 24 Jul 24 04:48:26 PM PDT 24 31658829 ps
T45 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.501613730 Jul 24 04:48:26 PM PDT 24 Jul 24 04:48:27 PM PDT 24 30191415 ps
T46 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4108944030 Jul 24 04:48:49 PM PDT 24 Jul 24 04:48:50 PM PDT 24 30209049 ps
T37 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1815187922 Jul 24 04:48:45 PM PDT 24 Jul 24 04:48:46 PM PDT 24 31464542 ps
T49 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2714310479 Jul 24 04:48:20 PM PDT 24 Jul 24 04:48:21 PM PDT 24 30569628 ps
T50 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1499810051 Jul 24 04:48:56 PM PDT 24 Jul 24 04:48:56 PM PDT 24 30240024 ps
T51 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1280979385 Jul 24 04:48:16 PM PDT 24 Jul 24 04:48:17 PM PDT 24 30278736 ps
T52 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1164353725 Jul 24 04:48:29 PM PDT 24 Jul 24 04:48:30 PM PDT 24 30039575 ps
T53 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2370244682 Jul 24 04:48:26 PM PDT 24 Jul 24 04:48:26 PM PDT 24 30140156 ps
T54 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.756616744 Jul 24 04:48:53 PM PDT 24 Jul 24 04:48:53 PM PDT 24 31012942 ps
T38 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2530983304 Jul 24 04:48:43 PM PDT 24 Jul 24 04:48:44 PM PDT 24 30197298 ps
T55 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2683147479 Jul 24 04:48:53 PM PDT 24 Jul 24 04:48:53 PM PDT 24 27691183 ps
T56 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3018874217 Jul 24 04:48:19 PM PDT 24 Jul 24 04:48:20 PM PDT 24 31787590 ps
T32 /workspace/coverage/sync_alert/0.prim_sync_alert.1421291277 Jul 24 04:50:06 PM PDT 24 Jul 24 04:50:06 PM PDT 24 9594506 ps
T23 /workspace/coverage/sync_alert/10.prim_sync_alert.1721831163 Jul 24 04:50:27 PM PDT 24 Jul 24 04:50:28 PM PDT 24 8867826 ps
T24 /workspace/coverage/sync_alert/12.prim_sync_alert.3311032382 Jul 24 04:50:11 PM PDT 24 Jul 24 04:50:12 PM PDT 24 8955723 ps
T25 /workspace/coverage/sync_alert/7.prim_sync_alert.955395781 Jul 24 04:50:07 PM PDT 24 Jul 24 04:50:08 PM PDT 24 8739180 ps
T26 /workspace/coverage/sync_alert/16.prim_sync_alert.685054949 Jul 24 04:50:06 PM PDT 24 Jul 24 04:50:06 PM PDT 24 9772719 ps
T33 /workspace/coverage/sync_alert/8.prim_sync_alert.495073327 Jul 24 04:50:25 PM PDT 24 Jul 24 04:50:26 PM PDT 24 9235314 ps
T34 /workspace/coverage/sync_alert/14.prim_sync_alert.3308049398 Jul 24 04:50:18 PM PDT 24 Jul 24 04:50:19 PM PDT 24 9632905 ps
T35 /workspace/coverage/sync_alert/9.prim_sync_alert.2394381033 Jul 24 04:50:09 PM PDT 24 Jul 24 04:50:10 PM PDT 24 8886996 ps
T27 /workspace/coverage/sync_alert/4.prim_sync_alert.730394536 Jul 24 04:50:06 PM PDT 24 Jul 24 04:50:06 PM PDT 24 9469001 ps
T36 /workspace/coverage/sync_alert/19.prim_sync_alert.116095622 Jul 24 04:50:15 PM PDT 24 Jul 24 04:50:16 PM PDT 24 9407851 ps
T57 /workspace/coverage/sync_alert/5.prim_sync_alert.2981347445 Jul 24 04:50:13 PM PDT 24 Jul 24 04:50:13 PM PDT 24 7790430 ps
T58 /workspace/coverage/sync_alert/2.prim_sync_alert.2641308188 Jul 24 04:50:04 PM PDT 24 Jul 24 04:50:04 PM PDT 24 10509580 ps
T59 /workspace/coverage/sync_alert/11.prim_sync_alert.1992099600 Jul 24 04:50:25 PM PDT 24 Jul 24 04:50:26 PM PDT 24 9214313 ps
T60 /workspace/coverage/sync_alert/18.prim_sync_alert.2187047464 Jul 24 04:50:12 PM PDT 24 Jul 24 04:50:13 PM PDT 24 8700540 ps
T61 /workspace/coverage/sync_alert/3.prim_sync_alert.3192140474 Jul 24 04:50:07 PM PDT 24 Jul 24 04:50:07 PM PDT 24 9222419 ps
T62 /workspace/coverage/sync_alert/6.prim_sync_alert.3589057234 Jul 24 04:50:08 PM PDT 24 Jul 24 04:50:08 PM PDT 24 9041764 ps
T63 /workspace/coverage/sync_alert/15.prim_sync_alert.2956228043 Jul 24 04:50:13 PM PDT 24 Jul 24 04:50:14 PM PDT 24 9082070 ps
T28 /workspace/coverage/sync_alert/13.prim_sync_alert.365945462 Jul 24 04:50:28 PM PDT 24 Jul 24 04:50:28 PM PDT 24 10139831 ps
T29 /workspace/coverage/sync_alert/1.prim_sync_alert.2858856755 Jul 24 04:50:05 PM PDT 24 Jul 24 04:50:06 PM PDT 24 9083569 ps
T30 /workspace/coverage/sync_alert/17.prim_sync_alert.399497423 Jul 24 04:50:13 PM PDT 24 Jul 24 04:50:14 PM PDT 24 9613494 ps
T31 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2848712386 Jul 24 04:50:07 PM PDT 24 Jul 24 04:50:08 PM PDT 24 28366489 ps
T64 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3479595166 Jul 24 04:50:18 PM PDT 24 Jul 24 04:50:18 PM PDT 24 27567057 ps
T65 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4137187470 Jul 24 04:50:28 PM PDT 24 Jul 24 04:50:29 PM PDT 24 27189561 ps
T66 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3090674310 Jul 24 04:50:08 PM PDT 24 Jul 24 04:50:08 PM PDT 24 26969106 ps
T67 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3052320293 Jul 24 04:50:16 PM PDT 24 Jul 24 04:50:16 PM PDT 24 27120426 ps
T68 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3502479793 Jul 24 04:50:21 PM PDT 24 Jul 24 04:50:22 PM PDT 24 26719664 ps
T69 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1330865999 Jul 24 04:50:18 PM PDT 24 Jul 24 04:50:19 PM PDT 24 26335219 ps
T4 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3002774044 Jul 24 04:50:11 PM PDT 24 Jul 24 04:50:12 PM PDT 24 30574980 ps
T70 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1099899318 Jul 24 04:50:12 PM PDT 24 Jul 24 04:50:12 PM PDT 24 27410428 ps
T71 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3533197641 Jul 24 04:50:29 PM PDT 24 Jul 24 04:50:29 PM PDT 24 27179739 ps
T72 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1783640470 Jul 24 04:50:28 PM PDT 24 Jul 24 04:50:28 PM PDT 24 27080209 ps
T73 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1010359387 Jul 24 04:50:25 PM PDT 24 Jul 24 04:50:26 PM PDT 24 27692761 ps
T74 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2374383223 Jul 24 04:50:09 PM PDT 24 Jul 24 04:50:10 PM PDT 24 25097134 ps
T5 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1689498160 Jul 24 04:50:34 PM PDT 24 Jul 24 04:50:34 PM PDT 24 28977210 ps
T75 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3853918822 Jul 24 04:50:32 PM PDT 24 Jul 24 04:50:32 PM PDT 24 26384857 ps
T76 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1149132616 Jul 24 04:50:12 PM PDT 24 Jul 24 04:50:12 PM PDT 24 27034448 ps
T77 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1093351278 Jul 24 04:50:09 PM PDT 24 Jul 24 04:50:10 PM PDT 24 27264379 ps
T78 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2001701585 Jul 24 04:50:11 PM PDT 24 Jul 24 04:50:12 PM PDT 24 26912629 ps
T79 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1064211448 Jul 24 04:50:22 PM PDT 24 Jul 24 04:50:22 PM PDT 24 30062517 ps
T80 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.571279511 Jul 24 04:50:21 PM PDT 24 Jul 24 04:50:21 PM PDT 24 26027240 ps

Test location /workspace/coverage/default/11.prim_async_alert.500054527
Short name T6
Test name
Test status
Simulation time 11553961 ps
CPU time 0.41 seconds
Started Jul 24 04:43:24 PM PDT 24
Finished Jul 24 04:43:25 PM PDT 24
Peak memory 145584 kb
Host smart-9fc2c9ea-8fac-415b-b2bb-aa14540a3810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500054527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.500054527
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3311032382
Short name T24
Test name
Test status
Simulation time 8955723 ps
CPU time 0.39 seconds
Started Jul 24 04:50:11 PM PDT 24
Finished Jul 24 04:50:12 PM PDT 24
Peak memory 145496 kb
Host smart-24b7f3b1-4275-4e62-a4e4-6a57aa122fb9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3311032382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3311032382
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2017633828
Short name T22
Test name
Test status
Simulation time 30404541 ps
CPU time 0.41 seconds
Started Jul 24 04:48:16 PM PDT 24
Finished Jul 24 04:48:17 PM PDT 24
Peak memory 145148 kb
Host smart-da2dba46-966f-4733-b290-679c0b82cb05
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2017633828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2017633828
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2579132102
Short name T17
Test name
Test status
Simulation time 11978564 ps
CPU time 0.45 seconds
Started Jul 24 04:43:22 PM PDT 24
Finished Jul 24 04:43:23 PM PDT 24
Peak memory 145564 kb
Host smart-180c1115-e791-4875-a8b6-14abb9adbc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579132102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2579132102
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3002774044
Short name T4
Test name
Test status
Simulation time 30574980 ps
CPU time 0.39 seconds
Started Jul 24 04:50:11 PM PDT 24
Finished Jul 24 04:50:12 PM PDT 24
Peak memory 145468 kb
Host smart-974afa0e-5a9d-4174-acf7-374eafd6c3c3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3002774044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3002774044
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.953502233
Short name T19
Test name
Test status
Simulation time 11610810 ps
CPU time 0.43 seconds
Started Jul 24 04:43:33 PM PDT 24
Finished Jul 24 04:43:34 PM PDT 24
Peak memory 145708 kb
Host smart-6f2366a9-8e00-4c92-8f8e-50b68753e9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953502233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.953502233
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1202171343
Short name T13
Test name
Test status
Simulation time 11182689 ps
CPU time 0.4 seconds
Started Jul 24 04:43:25 PM PDT 24
Finished Jul 24 04:43:26 PM PDT 24
Peak memory 145772 kb
Host smart-43b56369-7ac9-48e4-b82f-c52c43cde6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202171343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1202171343
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3955689482
Short name T9
Test name
Test status
Simulation time 11962064 ps
CPU time 0.42 seconds
Started Jul 24 04:43:20 PM PDT 24
Finished Jul 24 04:43:21 PM PDT 24
Peak memory 145632 kb
Host smart-5fe7552b-ae30-4a06-807f-de62aa0f281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955689482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3955689482
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2036568596
Short name T3
Test name
Test status
Simulation time 11396886 ps
CPU time 0.43 seconds
Started Jul 24 04:43:24 PM PDT 24
Finished Jul 24 04:43:25 PM PDT 24
Peak memory 145652 kb
Host smart-39cb2285-599f-48db-b168-3e921270bc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036568596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2036568596
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1547816828
Short name T20
Test name
Test status
Simulation time 11466012 ps
CPU time 0.4 seconds
Started Jul 24 04:43:24 PM PDT 24
Finished Jul 24 04:43:25 PM PDT 24
Peak memory 145628 kb
Host smart-acf90284-4ac0-405b-b8e7-6019f05456b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547816828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1547816828
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.19073301
Short name T11
Test name
Test status
Simulation time 12726522 ps
CPU time 0.41 seconds
Started Jul 24 04:43:22 PM PDT 24
Finished Jul 24 04:43:23 PM PDT 24
Peak memory 145684 kb
Host smart-f9b95af3-7e1c-4b95-abd4-17e1d24497e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19073301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.19073301
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.4165501179
Short name T16
Test name
Test status
Simulation time 12294501 ps
CPU time 0.4 seconds
Started Jul 24 04:43:24 PM PDT 24
Finished Jul 24 04:43:24 PM PDT 24
Peak memory 145632 kb
Host smart-2f7fa1a2-5345-47ab-9e3e-c6f8af880344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165501179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.4165501179
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2513403214
Short name T18
Test name
Test status
Simulation time 10997009 ps
CPU time 0.41 seconds
Started Jul 24 04:43:22 PM PDT 24
Finished Jul 24 04:43:23 PM PDT 24
Peak memory 145656 kb
Host smart-c913e60b-455c-4b82-ad60-7f212159ec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513403214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2513403214
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1715173704
Short name T8
Test name
Test status
Simulation time 11672999 ps
CPU time 0.41 seconds
Started Jul 24 04:43:22 PM PDT 24
Finished Jul 24 04:43:23 PM PDT 24
Peak memory 145704 kb
Host smart-bad1d46b-2f34-4faa-ae95-d34f46423e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715173704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1715173704
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2445775817
Short name T48
Test name
Test status
Simulation time 11935898 ps
CPU time 0.39 seconds
Started Jul 24 04:43:25 PM PDT 24
Finished Jul 24 04:43:25 PM PDT 24
Peak memory 145628 kb
Host smart-a01f06d2-69d9-4a4a-905a-87ba94cf76fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445775817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2445775817
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2794039570
Short name T47
Test name
Test status
Simulation time 10118667 ps
CPU time 0.38 seconds
Started Jul 24 04:43:25 PM PDT 24
Finished Jul 24 04:43:26 PM PDT 24
Peak memory 145612 kb
Host smart-5af9bf41-5696-4cf6-8387-2d6f9273e8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794039570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2794039570
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2809835133
Short name T1
Test name
Test status
Simulation time 11371583 ps
CPU time 0.4 seconds
Started Jul 24 04:43:22 PM PDT 24
Finished Jul 24 04:43:23 PM PDT 24
Peak memory 145636 kb
Host smart-b397cc4c-bac1-44a2-a74d-f0c354ff8a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809835133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2809835133
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3383342926
Short name T14
Test name
Test status
Simulation time 11265299 ps
CPU time 0.39 seconds
Started Jul 24 04:43:22 PM PDT 24
Finished Jul 24 04:43:23 PM PDT 24
Peak memory 145656 kb
Host smart-59bd0d20-6285-4916-8ba9-a9c640eacc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383342926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3383342926
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3513810999
Short name T10
Test name
Test status
Simulation time 11569911 ps
CPU time 0.38 seconds
Started Jul 24 04:43:25 PM PDT 24
Finished Jul 24 04:43:25 PM PDT 24
Peak memory 145640 kb
Host smart-956f4e6c-2a82-451f-b4b0-52e3d42f4971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513810999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3513810999
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1424867566
Short name T2
Test name
Test status
Simulation time 11294666 ps
CPU time 0.4 seconds
Started Jul 24 04:43:23 PM PDT 24
Finished Jul 24 04:43:23 PM PDT 24
Peak memory 145592 kb
Host smart-8e6265f3-1b47-4d70-b55b-45d19dc3362f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424867566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1424867566
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3078236708
Short name T7
Test name
Test status
Simulation time 10984694 ps
CPU time 0.4 seconds
Started Jul 24 04:43:22 PM PDT 24
Finished Jul 24 04:43:22 PM PDT 24
Peak memory 145648 kb
Host smart-a17516fd-ad4e-4870-a4fa-533e0a2c0404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078236708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3078236708
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1878661698
Short name T21
Test name
Test status
Simulation time 10407027 ps
CPU time 0.4 seconds
Started Jul 24 04:43:24 PM PDT 24
Finished Jul 24 04:43:25 PM PDT 24
Peak memory 145624 kb
Host smart-bc3d31d2-4cd4-46c2-8c97-589ff3b60555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878661698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1878661698
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2090166445
Short name T15
Test name
Test status
Simulation time 12258391 ps
CPU time 0.39 seconds
Started Jul 24 04:43:21 PM PDT 24
Finished Jul 24 04:43:22 PM PDT 24
Peak memory 145560 kb
Host smart-401126ea-595d-4f5c-98ce-3f766a36bfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090166445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2090166445
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1280979385
Short name T51
Test name
Test status
Simulation time 30278736 ps
CPU time 0.4 seconds
Started Jul 24 04:48:16 PM PDT 24
Finished Jul 24 04:48:17 PM PDT 24
Peak memory 145148 kb
Host smart-cb1df954-7dde-4095-9b48-f61d15e0e7fb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1280979385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1280979385
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.277459651
Short name T44
Test name
Test status
Simulation time 29685366 ps
CPU time 0.42 seconds
Started Jul 24 04:48:38 PM PDT 24
Finished Jul 24 04:48:39 PM PDT 24
Peak memory 145228 kb
Host smart-c332b15c-e062-4b98-89f5-31f446c345d2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=277459651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.277459651
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3156487856
Short name T42
Test name
Test status
Simulation time 30589226 ps
CPU time 0.4 seconds
Started Jul 24 04:48:27 PM PDT 24
Finished Jul 24 04:48:27 PM PDT 24
Peak memory 145180 kb
Host smart-60e00beb-c099-4f90-abb5-d3c3068f9482
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3156487856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3156487856
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.994981407
Short name T40
Test name
Test status
Simulation time 29216384 ps
CPU time 0.4 seconds
Started Jul 24 04:48:29 PM PDT 24
Finished Jul 24 04:48:30 PM PDT 24
Peak memory 145196 kb
Host smart-d7fd4e5e-7563-4a6e-8d60-c4405f0e7bf6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=994981407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.994981407
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2530983304
Short name T38
Test name
Test status
Simulation time 30197298 ps
CPU time 0.42 seconds
Started Jul 24 04:48:43 PM PDT 24
Finished Jul 24 04:48:44 PM PDT 24
Peak memory 145180 kb
Host smart-f97a0b9a-2f81-4739-9d53-1c141ebab3c0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2530983304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2530983304
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.756616744
Short name T54
Test name
Test status
Simulation time 31012942 ps
CPU time 0.4 seconds
Started Jul 24 04:48:53 PM PDT 24
Finished Jul 24 04:48:53 PM PDT 24
Peak memory 144532 kb
Host smart-4294bccf-cc11-4a97-960d-020ab9804682
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=756616744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.756616744
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.501613730
Short name T45
Test name
Test status
Simulation time 30191415 ps
CPU time 0.4 seconds
Started Jul 24 04:48:26 PM PDT 24
Finished Jul 24 04:48:27 PM PDT 24
Peak memory 145144 kb
Host smart-b24de038-e19b-4723-b933-e2a347d32cde
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=501613730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.501613730
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.961110237
Short name T12
Test name
Test status
Simulation time 31658829 ps
CPU time 0.4 seconds
Started Jul 24 04:48:25 PM PDT 24
Finished Jul 24 04:48:26 PM PDT 24
Peak memory 145200 kb
Host smart-32cd8276-8f37-4ae1-a5eb-dea85994c9a9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=961110237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.961110237
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1296811151
Short name T41
Test name
Test status
Simulation time 32468154 ps
CPU time 0.4 seconds
Started Jul 24 04:48:43 PM PDT 24
Finished Jul 24 04:48:44 PM PDT 24
Peak memory 145148 kb
Host smart-0fdecbc4-908f-4b1e-8307-1a89b82413c7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1296811151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1296811151
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1164353725
Short name T52
Test name
Test status
Simulation time 30039575 ps
CPU time 0.43 seconds
Started Jul 24 04:48:29 PM PDT 24
Finished Jul 24 04:48:30 PM PDT 24
Peak memory 145180 kb
Host smart-4b9e0a82-feb1-4d81-8419-0ae1b09a0fc7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1164353725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1164353725
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1499810051
Short name T50
Test name
Test status
Simulation time 30240024 ps
CPU time 0.39 seconds
Started Jul 24 04:48:56 PM PDT 24
Finished Jul 24 04:48:56 PM PDT 24
Peak memory 145168 kb
Host smart-c0bc3f85-34ab-41e2-a04c-6395204a9510
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1499810051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1499810051
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2683147479
Short name T55
Test name
Test status
Simulation time 27691183 ps
CPU time 0.38 seconds
Started Jul 24 04:48:53 PM PDT 24
Finished Jul 24 04:48:53 PM PDT 24
Peak memory 145172 kb
Host smart-0aa849e2-ae26-4aab-b490-0dc781b5d0c0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2683147479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2683147479
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2370244682
Short name T53
Test name
Test status
Simulation time 30140156 ps
CPU time 0.4 seconds
Started Jul 24 04:48:26 PM PDT 24
Finished Jul 24 04:48:26 PM PDT 24
Peak memory 145124 kb
Host smart-6d549781-f321-47c3-b424-1f115c301732
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2370244682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2370244682
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2140323278
Short name T39
Test name
Test status
Simulation time 30700957 ps
CPU time 0.39 seconds
Started Jul 24 04:48:31 PM PDT 24
Finished Jul 24 04:48:32 PM PDT 24
Peak memory 145172 kb
Host smart-5a0e04d0-41dd-4740-929d-06cc61d44218
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2140323278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2140323278
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1815187922
Short name T37
Test name
Test status
Simulation time 31464542 ps
CPU time 0.42 seconds
Started Jul 24 04:48:45 PM PDT 24
Finished Jul 24 04:48:46 PM PDT 24
Peak memory 145180 kb
Host smart-6387d4ce-6ee6-481e-a847-40f9292bcf76
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1815187922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1815187922
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3018874217
Short name T56
Test name
Test status
Simulation time 31787590 ps
CPU time 0.4 seconds
Started Jul 24 04:48:19 PM PDT 24
Finished Jul 24 04:48:20 PM PDT 24
Peak memory 145168 kb
Host smart-1ac3572c-cf4a-48e9-85f2-7306217a9d36
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3018874217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3018874217
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2714310479
Short name T49
Test name
Test status
Simulation time 30569628 ps
CPU time 0.45 seconds
Started Jul 24 04:48:20 PM PDT 24
Finished Jul 24 04:48:21 PM PDT 24
Peak memory 145260 kb
Host smart-d666efe3-d24d-4d91-8667-68211439f6b4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2714310479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2714310479
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3492939817
Short name T43
Test name
Test status
Simulation time 29769107 ps
CPU time 0.4 seconds
Started Jul 24 04:48:23 PM PDT 24
Finished Jul 24 04:48:24 PM PDT 24
Peak memory 145208 kb
Host smart-e9bcceb3-8e46-434d-9f65-0fd48ef0fa5d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3492939817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3492939817
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4108944030
Short name T46
Test name
Test status
Simulation time 30209049 ps
CPU time 0.41 seconds
Started Jul 24 04:48:49 PM PDT 24
Finished Jul 24 04:48:50 PM PDT 24
Peak memory 145172 kb
Host smart-58e5a38f-8c42-4c4e-840e-2927e063d2ec
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4108944030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.4108944030
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1421291277
Short name T32
Test name
Test status
Simulation time 9594506 ps
CPU time 0.39 seconds
Started Jul 24 04:50:06 PM PDT 24
Finished Jul 24 04:50:06 PM PDT 24
Peak memory 145536 kb
Host smart-10c53423-9062-4057-b85c-03adc07a2a16
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1421291277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1421291277
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2858856755
Short name T29
Test name
Test status
Simulation time 9083569 ps
CPU time 0.43 seconds
Started Jul 24 04:50:05 PM PDT 24
Finished Jul 24 04:50:06 PM PDT 24
Peak memory 145020 kb
Host smart-7a942b6a-bc1d-479c-b2c3-327b1d712943
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2858856755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2858856755
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1721831163
Short name T23
Test name
Test status
Simulation time 8867826 ps
CPU time 0.37 seconds
Started Jul 24 04:50:27 PM PDT 24
Finished Jul 24 04:50:28 PM PDT 24
Peak memory 145432 kb
Host smart-ecb07fde-c027-4b4b-ac01-05fc52adcff3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1721831163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1721831163
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1992099600
Short name T59
Test name
Test status
Simulation time 9214313 ps
CPU time 0.39 seconds
Started Jul 24 04:50:25 PM PDT 24
Finished Jul 24 04:50:26 PM PDT 24
Peak memory 145416 kb
Host smart-41b0e2a1-7e96-4ec3-8414-b8552fb1b8f5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1992099600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1992099600
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.365945462
Short name T28
Test name
Test status
Simulation time 10139831 ps
CPU time 0.42 seconds
Started Jul 24 04:50:28 PM PDT 24
Finished Jul 24 04:50:28 PM PDT 24
Peak memory 145428 kb
Host smart-290041f4-6ebb-4639-9cdc-33d10bbb073a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=365945462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.365945462
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3308049398
Short name T34
Test name
Test status
Simulation time 9632905 ps
CPU time 0.4 seconds
Started Jul 24 04:50:18 PM PDT 24
Finished Jul 24 04:50:19 PM PDT 24
Peak memory 145400 kb
Host smart-e6efe89a-7c4e-4d6c-a22a-f1d63ba54aa8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3308049398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3308049398
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2956228043
Short name T63
Test name
Test status
Simulation time 9082070 ps
CPU time 0.38 seconds
Started Jul 24 04:50:13 PM PDT 24
Finished Jul 24 04:50:14 PM PDT 24
Peak memory 145480 kb
Host smart-b64389cd-e449-4c22-a94e-679e28cb4999
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2956228043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2956228043
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.685054949
Short name T26
Test name
Test status
Simulation time 9772719 ps
CPU time 0.4 seconds
Started Jul 24 04:50:06 PM PDT 24
Finished Jul 24 04:50:06 PM PDT 24
Peak memory 145400 kb
Host smart-eb3f7521-8e54-437f-a7c8-a0d3c1ee7545
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=685054949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.685054949
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.399497423
Short name T30
Test name
Test status
Simulation time 9613494 ps
CPU time 0.4 seconds
Started Jul 24 04:50:13 PM PDT 24
Finished Jul 24 04:50:14 PM PDT 24
Peak memory 145472 kb
Host smart-bcb3738a-1bf8-4792-a024-f0c0d0d4cde2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=399497423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.399497423
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2187047464
Short name T60
Test name
Test status
Simulation time 8700540 ps
CPU time 0.37 seconds
Started Jul 24 04:50:12 PM PDT 24
Finished Jul 24 04:50:13 PM PDT 24
Peak memory 145464 kb
Host smart-8d064f99-86d1-49f3-aa28-8be260f3770b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2187047464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2187047464
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.116095622
Short name T36
Test name
Test status
Simulation time 9407851 ps
CPU time 0.38 seconds
Started Jul 24 04:50:15 PM PDT 24
Finished Jul 24 04:50:16 PM PDT 24
Peak memory 145440 kb
Host smart-135515e9-018f-4a9e-a150-55ce2683d7e3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=116095622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.116095622
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2641308188
Short name T58
Test name
Test status
Simulation time 10509580 ps
CPU time 0.37 seconds
Started Jul 24 04:50:04 PM PDT 24
Finished Jul 24 04:50:04 PM PDT 24
Peak memory 145444 kb
Host smart-eb2ebbbb-17b6-4b78-9989-a9889e841600
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2641308188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2641308188
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3192140474
Short name T61
Test name
Test status
Simulation time 9222419 ps
CPU time 0.39 seconds
Started Jul 24 04:50:07 PM PDT 24
Finished Jul 24 04:50:07 PM PDT 24
Peak memory 145444 kb
Host smart-f1848f51-4eb6-4530-902b-93e40ceb8189
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3192140474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3192140474
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.730394536
Short name T27
Test name
Test status
Simulation time 9469001 ps
CPU time 0.4 seconds
Started Jul 24 04:50:06 PM PDT 24
Finished Jul 24 04:50:06 PM PDT 24
Peak memory 145260 kb
Host smart-91e9632d-4876-44f7-94e2-1669b96247ae
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=730394536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.730394536
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2981347445
Short name T57
Test name
Test status
Simulation time 7790430 ps
CPU time 0.38 seconds
Started Jul 24 04:50:13 PM PDT 24
Finished Jul 24 04:50:13 PM PDT 24
Peak memory 145444 kb
Host smart-62d94a4f-7fc2-4a77-ae18-96e9f27320f1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2981347445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2981347445
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3589057234
Short name T62
Test name
Test status
Simulation time 9041764 ps
CPU time 0.37 seconds
Started Jul 24 04:50:08 PM PDT 24
Finished Jul 24 04:50:08 PM PDT 24
Peak memory 145184 kb
Host smart-f4043028-2719-4d2d-be64-82693b6aabcd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3589057234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3589057234
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.955395781
Short name T25
Test name
Test status
Simulation time 8739180 ps
CPU time 0.38 seconds
Started Jul 24 04:50:07 PM PDT 24
Finished Jul 24 04:50:08 PM PDT 24
Peak memory 145388 kb
Host smart-cbb7ae71-a528-4d5b-8d87-260316c17eac
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=955395781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.955395781
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.495073327
Short name T33
Test name
Test status
Simulation time 9235314 ps
CPU time 0.46 seconds
Started Jul 24 04:50:25 PM PDT 24
Finished Jul 24 04:50:26 PM PDT 24
Peak memory 145432 kb
Host smart-368ed191-9d31-463c-8e21-893511c18bd5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=495073327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.495073327
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2394381033
Short name T35
Test name
Test status
Simulation time 8886996 ps
CPU time 0.38 seconds
Started Jul 24 04:50:09 PM PDT 24
Finished Jul 24 04:50:10 PM PDT 24
Peak memory 145448 kb
Host smart-5ff9616b-9f84-40c1-a372-3349b3eaac48
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2394381033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2394381033
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4137187470
Short name T65
Test name
Test status
Simulation time 27189561 ps
CPU time 0.41 seconds
Started Jul 24 04:50:28 PM PDT 24
Finished Jul 24 04:50:29 PM PDT 24
Peak memory 145432 kb
Host smart-53b7d47f-cc5f-423f-a55f-b0d1a067931f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4137187470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4137187470
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3052320293
Short name T67
Test name
Test status
Simulation time 27120426 ps
CPU time 0.41 seconds
Started Jul 24 04:50:16 PM PDT 24
Finished Jul 24 04:50:16 PM PDT 24
Peak memory 145432 kb
Host smart-6a305e28-597a-4b9e-9917-b1e5c9dd66e0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3052320293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3052320293
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3853918822
Short name T75
Test name
Test status
Simulation time 26384857 ps
CPU time 0.42 seconds
Started Jul 24 04:50:32 PM PDT 24
Finished Jul 24 04:50:32 PM PDT 24
Peak memory 145476 kb
Host smart-e082bf90-971a-4409-a3cd-046487bc9533
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3853918822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3853918822
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1783640470
Short name T72
Test name
Test status
Simulation time 27080209 ps
CPU time 0.4 seconds
Started Jul 24 04:50:28 PM PDT 24
Finished Jul 24 04:50:28 PM PDT 24
Peak memory 145444 kb
Host smart-8087c0d7-750b-4b05-a4d7-ab44b6e1743c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1783640470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1783640470
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.571279511
Short name T80
Test name
Test status
Simulation time 26027240 ps
CPU time 0.39 seconds
Started Jul 24 04:50:21 PM PDT 24
Finished Jul 24 04:50:21 PM PDT 24
Peak memory 145400 kb
Host smart-3535cf74-1e3e-44f4-be98-00eb5359c774
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=571279511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.571279511
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1064211448
Short name T79
Test name
Test status
Simulation time 30062517 ps
CPU time 0.4 seconds
Started Jul 24 04:50:22 PM PDT 24
Finished Jul 24 04:50:22 PM PDT 24
Peak memory 145544 kb
Host smart-2c534c71-2d0c-427f-8b5f-b2be18e57fe8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1064211448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1064211448
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2848712386
Short name T31
Test name
Test status
Simulation time 28366489 ps
CPU time 0.38 seconds
Started Jul 24 04:50:07 PM PDT 24
Finished Jul 24 04:50:08 PM PDT 24
Peak memory 145448 kb
Host smart-f97cce88-17ab-48bf-b957-5867d315d4a2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2848712386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2848712386
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1010359387
Short name T73
Test name
Test status
Simulation time 27692761 ps
CPU time 0.4 seconds
Started Jul 24 04:50:25 PM PDT 24
Finished Jul 24 04:50:26 PM PDT 24
Peak memory 145424 kb
Host smart-88f5ccff-abc0-44b7-a2e9-ea57a0209b69
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1010359387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1010359387
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1099899318
Short name T70
Test name
Test status
Simulation time 27410428 ps
CPU time 0.42 seconds
Started Jul 24 04:50:12 PM PDT 24
Finished Jul 24 04:50:12 PM PDT 24
Peak memory 145464 kb
Host smart-817c1979-17ba-4b28-9e0e-e70956e8a5cd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1099899318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1099899318
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2374383223
Short name T74
Test name
Test status
Simulation time 25097134 ps
CPU time 0.39 seconds
Started Jul 24 04:50:09 PM PDT 24
Finished Jul 24 04:50:10 PM PDT 24
Peak memory 145472 kb
Host smart-2aaa1813-024e-4910-91f8-2cad0ed87b63
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2374383223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2374383223
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1330865999
Short name T69
Test name
Test status
Simulation time 26335219 ps
CPU time 0.4 seconds
Started Jul 24 04:50:18 PM PDT 24
Finished Jul 24 04:50:19 PM PDT 24
Peak memory 145468 kb
Host smart-01c12403-f8d3-43e3-a588-d0983dae81cd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1330865999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1330865999
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2001701585
Short name T78
Test name
Test status
Simulation time 26912629 ps
CPU time 0.48 seconds
Started Jul 24 04:50:11 PM PDT 24
Finished Jul 24 04:50:12 PM PDT 24
Peak memory 145516 kb
Host smart-731671c0-f3de-4240-ae75-6b954b704026
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2001701585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2001701585
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1149132616
Short name T76
Test name
Test status
Simulation time 27034448 ps
CPU time 0.39 seconds
Started Jul 24 04:50:12 PM PDT 24
Finished Jul 24 04:50:12 PM PDT 24
Peak memory 145472 kb
Host smart-83c62663-3f74-477c-a4dd-80f19cb7680a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1149132616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1149132616
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3090674310
Short name T66
Test name
Test status
Simulation time 26969106 ps
CPU time 0.42 seconds
Started Jul 24 04:50:08 PM PDT 24
Finished Jul 24 04:50:08 PM PDT 24
Peak memory 145468 kb
Host smart-cba8ac90-9ed1-4d42-8c60-bba5b922fbd0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3090674310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3090674310
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3479595166
Short name T64
Test name
Test status
Simulation time 27567057 ps
CPU time 0.39 seconds
Started Jul 24 04:50:18 PM PDT 24
Finished Jul 24 04:50:18 PM PDT 24
Peak memory 145484 kb
Host smart-e4c1e46a-b147-4658-8166-6c6d74e5b0c1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3479595166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3479595166
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3533197641
Short name T71
Test name
Test status
Simulation time 27179739 ps
CPU time 0.4 seconds
Started Jul 24 04:50:29 PM PDT 24
Finished Jul 24 04:50:29 PM PDT 24
Peak memory 145448 kb
Host smart-4e6c5b39-cef1-4459-b24a-ea970f8bc1a5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3533197641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3533197641
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1689498160
Short name T5
Test name
Test status
Simulation time 28977210 ps
CPU time 0.38 seconds
Started Jul 24 04:50:34 PM PDT 24
Finished Jul 24 04:50:34 PM PDT 24
Peak memory 145432 kb
Host smart-2670878f-73c4-48ec-a391-a28423dc79f3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1689498160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1689498160
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3502479793
Short name T68
Test name
Test status
Simulation time 26719664 ps
CPU time 0.4 seconds
Started Jul 24 04:50:21 PM PDT 24
Finished Jul 24 04:50:22 PM PDT 24
Peak memory 145484 kb
Host smart-5c8535b5-2bc8-458b-b4a9-4acf6d2a48c9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3502479793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3502479793
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1093351278
Short name T77
Test name
Test status
Simulation time 27264379 ps
CPU time 0.4 seconds
Started Jul 24 04:50:09 PM PDT 24
Finished Jul 24 04:50:10 PM PDT 24
Peak memory 145456 kb
Host smart-7f6adbad-4263-4414-bbe3-843b02a38d10
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1093351278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1093351278
Directory /workspace/9.prim_sync_fatal_alert/latest
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