Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 100.00 100.00 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/2.prim_async_alert.236822446
92.39 3.72 100.00 0.00 93.75 0.00 100.00 0.00 85.71 10.71 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/14.prim_sync_alert.2550559228
94.15 1.76 100.00 0.00 93.75 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2699622939
94.50 0.35 100.00 0.00 95.83 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/0.prim_async_alert.2036388709
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/12.prim_sync_alert.410794938

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.902266584
/workspace/coverage/default/10.prim_async_alert.3243864322
/workspace/coverage/default/11.prim_async_alert.4244632211
/workspace/coverage/default/12.prim_async_alert.2757062592
/workspace/coverage/default/13.prim_async_alert.1043087638
/workspace/coverage/default/14.prim_async_alert.1234293446
/workspace/coverage/default/15.prim_async_alert.4293254416
/workspace/coverage/default/16.prim_async_alert.4177973460
/workspace/coverage/default/17.prim_async_alert.4150608379
/workspace/coverage/default/19.prim_async_alert.3239750075
/workspace/coverage/default/3.prim_async_alert.1607097781
/workspace/coverage/default/4.prim_async_alert.859729926
/workspace/coverage/default/5.prim_async_alert.3544495219
/workspace/coverage/default/6.prim_async_alert.1401988864
/workspace/coverage/default/7.prim_async_alert.4105158985
/workspace/coverage/default/8.prim_async_alert.2483946924
/workspace/coverage/default/9.prim_async_alert.926830480
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3127843110
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.342924979
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3621506527
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.944635831
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1425755643
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.171126525
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1181462794
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2416711638
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.451392936
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2187107699
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2679489442
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3966068620
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.132675051
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2806156612
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1066292913
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2011392345
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2504513667
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1528052143
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3678870891
/workspace/coverage/sync_alert/0.prim_sync_alert.2408471046
/workspace/coverage/sync_alert/1.prim_sync_alert.168085954
/workspace/coverage/sync_alert/10.prim_sync_alert.2184578946
/workspace/coverage/sync_alert/11.prim_sync_alert.1928158868
/workspace/coverage/sync_alert/13.prim_sync_alert.3323899787
/workspace/coverage/sync_alert/15.prim_sync_alert.2829585807
/workspace/coverage/sync_alert/16.prim_sync_alert.3360246341
/workspace/coverage/sync_alert/17.prim_sync_alert.3302265733
/workspace/coverage/sync_alert/18.prim_sync_alert.4068763391
/workspace/coverage/sync_alert/19.prim_sync_alert.4290012817
/workspace/coverage/sync_alert/2.prim_sync_alert.3473785304
/workspace/coverage/sync_alert/3.prim_sync_alert.3557091302
/workspace/coverage/sync_alert/4.prim_sync_alert.215148291
/workspace/coverage/sync_alert/5.prim_sync_alert.4206607762
/workspace/coverage/sync_alert/6.prim_sync_alert.1317105377
/workspace/coverage/sync_alert/7.prim_sync_alert.155929531
/workspace/coverage/sync_alert/8.prim_sync_alert.2413682914
/workspace/coverage/sync_alert/9.prim_sync_alert.2019206084
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2239503799
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1148555703
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2329725669
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.144147435
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4275424689
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.56212024
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.444280379
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2862630866
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1692533790
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3650380588
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3863240285
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3651245641
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1696792365
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1911787919
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1463922532
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2641714960
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3870227827
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.379305106
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1244846534
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3803400762



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/14.prim_async_alert.1234293446 Jul 25 04:50:41 PM PDT 24 Jul 25 04:50:42 PM PDT 24 10621115 ps
T2 /workspace/coverage/default/19.prim_async_alert.3239750075 Jul 25 04:50:32 PM PDT 24 Jul 25 04:50:32 PM PDT 24 11011479 ps
T3 /workspace/coverage/default/6.prim_async_alert.1401988864 Jul 25 04:50:44 PM PDT 24 Jul 25 04:50:44 PM PDT 24 11206668 ps
T14 /workspace/coverage/default/4.prim_async_alert.859729926 Jul 25 04:50:30 PM PDT 24 Jul 25 04:50:31 PM PDT 24 10633110 ps
T17 /workspace/coverage/default/9.prim_async_alert.926830480 Jul 25 04:50:20 PM PDT 24 Jul 25 04:50:20 PM PDT 24 11083141 ps
T4 /workspace/coverage/default/3.prim_async_alert.1607097781 Jul 25 04:50:30 PM PDT 24 Jul 25 04:50:30 PM PDT 24 10979649 ps
T7 /workspace/coverage/default/15.prim_async_alert.4293254416 Jul 25 04:50:27 PM PDT 24 Jul 25 04:50:28 PM PDT 24 10112045 ps
T11 /workspace/coverage/default/2.prim_async_alert.236822446 Jul 25 04:50:29 PM PDT 24 Jul 25 04:50:30 PM PDT 24 12003828 ps
T20 /workspace/coverage/default/13.prim_async_alert.1043087638 Jul 25 04:50:33 PM PDT 24 Jul 25 04:50:34 PM PDT 24 11187981 ps
T5 /workspace/coverage/default/17.prim_async_alert.4150608379 Jul 25 04:50:32 PM PDT 24 Jul 25 04:50:32 PM PDT 24 10208308 ps
T21 /workspace/coverage/default/10.prim_async_alert.3243864322 Jul 25 04:50:21 PM PDT 24 Jul 25 04:50:22 PM PDT 24 11414622 ps
T22 /workspace/coverage/default/11.prim_async_alert.4244632211 Jul 25 04:50:27 PM PDT 24 Jul 25 04:50:28 PM PDT 24 10772333 ps
T6 /workspace/coverage/default/8.prim_async_alert.2483946924 Jul 25 04:50:45 PM PDT 24 Jul 25 04:50:45 PM PDT 24 10744392 ps
T18 /workspace/coverage/default/7.prim_async_alert.4105158985 Jul 25 04:50:27 PM PDT 24 Jul 25 04:50:27 PM PDT 24 11097530 ps
T23 /workspace/coverage/default/12.prim_async_alert.2757062592 Jul 25 04:50:14 PM PDT 24 Jul 25 04:50:14 PM PDT 24 9695848 ps
T12 /workspace/coverage/default/1.prim_async_alert.902266584 Jul 25 04:50:21 PM PDT 24 Jul 25 04:50:22 PM PDT 24 11925729 ps
T24 /workspace/coverage/default/0.prim_async_alert.2036388709 Jul 25 04:50:41 PM PDT 24 Jul 25 04:50:41 PM PDT 24 10919209 ps
T13 /workspace/coverage/default/5.prim_async_alert.3544495219 Jul 25 04:50:27 PM PDT 24 Jul 25 04:50:28 PM PDT 24 11634724 ps
T46 /workspace/coverage/default/16.prim_async_alert.4177973460 Jul 25 04:50:20 PM PDT 24 Jul 25 04:50:20 PM PDT 24 12778418 ps
T25 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.944635831 Jul 25 04:51:05 PM PDT 24 Jul 25 04:51:06 PM PDT 24 29881825 ps
T19 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1425755643 Jul 25 04:51:00 PM PDT 24 Jul 25 04:51:01 PM PDT 24 31368379 ps
T15 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2699622939 Jul 25 04:51:02 PM PDT 24 Jul 25 04:51:03 PM PDT 24 31749084 ps
T39 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1528052143 Jul 25 04:51:40 PM PDT 24 Jul 25 04:51:41 PM PDT 24 30806884 ps
T40 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2679489442 Jul 25 04:51:17 PM PDT 24 Jul 25 04:51:18 PM PDT 24 30572030 ps
T41 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.171126525 Jul 25 04:51:04 PM PDT 24 Jul 25 04:51:05 PM PDT 24 29980019 ps
T42 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.451392936 Jul 25 04:50:58 PM PDT 24 Jul 25 04:50:59 PM PDT 24 30459486 ps
T43 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2806156612 Jul 25 04:51:04 PM PDT 24 Jul 25 04:51:04 PM PDT 24 29471696 ps
T44 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2187107699 Jul 25 04:51:04 PM PDT 24 Jul 25 04:51:05 PM PDT 24 30117730 ps
T45 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3127843110 Jul 25 04:50:47 PM PDT 24 Jul 25 04:50:47 PM PDT 24 29609262 ps
T47 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2011392345 Jul 25 04:51:04 PM PDT 24 Jul 25 04:51:04 PM PDT 24 29754741 ps
T48 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3621506527 Jul 25 04:51:07 PM PDT 24 Jul 25 04:51:07 PM PDT 24 30587849 ps
T49 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3966068620 Jul 25 04:50:57 PM PDT 24 Jul 25 04:50:58 PM PDT 24 30386141 ps
T50 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1066292913 Jul 25 04:50:55 PM PDT 24 Jul 25 04:50:55 PM PDT 24 32110882 ps
T51 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3678870891 Jul 25 04:51:02 PM PDT 24 Jul 25 04:51:02 PM PDT 24 28694302 ps
T52 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1181462794 Jul 25 04:50:54 PM PDT 24 Jul 25 04:50:54 PM PDT 24 31734551 ps
T53 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.132675051 Jul 25 04:51:02 PM PDT 24 Jul 25 04:51:03 PM PDT 24 30400372 ps
T54 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.342924979 Jul 25 04:50:57 PM PDT 24 Jul 25 04:50:58 PM PDT 24 30371956 ps
T55 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2504513667 Jul 25 04:51:11 PM PDT 24 Jul 25 04:51:11 PM PDT 24 31203821 ps
T56 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2416711638 Jul 25 04:51:19 PM PDT 24 Jul 25 04:51:20 PM PDT 24 32352670 ps
T26 /workspace/coverage/sync_alert/9.prim_sync_alert.2019206084 Jul 25 04:51:05 PM PDT 24 Jul 25 04:51:06 PM PDT 24 9719702 ps
T36 /workspace/coverage/sync_alert/14.prim_sync_alert.2550559228 Jul 25 04:51:06 PM PDT 24 Jul 25 04:51:07 PM PDT 24 10231416 ps
T27 /workspace/coverage/sync_alert/2.prim_sync_alert.3473785304 Jul 25 04:51:04 PM PDT 24 Jul 25 04:51:04 PM PDT 24 10796207 ps
T37 /workspace/coverage/sync_alert/1.prim_sync_alert.168085954 Jul 25 04:51:07 PM PDT 24 Jul 25 04:51:07 PM PDT 24 8944526 ps
T38 /workspace/coverage/sync_alert/18.prim_sync_alert.4068763391 Jul 25 04:51:04 PM PDT 24 Jul 25 04:51:05 PM PDT 24 9538925 ps
T28 /workspace/coverage/sync_alert/11.prim_sync_alert.1928158868 Jul 25 04:51:03 PM PDT 24 Jul 25 04:51:04 PM PDT 24 9986902 ps
T29 /workspace/coverage/sync_alert/7.prim_sync_alert.155929531 Jul 25 04:50:59 PM PDT 24 Jul 25 04:50:59 PM PDT 24 9564541 ps
T30 /workspace/coverage/sync_alert/13.prim_sync_alert.3323899787 Jul 25 04:51:29 PM PDT 24 Jul 25 04:51:29 PM PDT 24 9365969 ps
T31 /workspace/coverage/sync_alert/3.prim_sync_alert.3557091302 Jul 25 04:51:02 PM PDT 24 Jul 25 04:51:02 PM PDT 24 9748485 ps
T32 /workspace/coverage/sync_alert/4.prim_sync_alert.215148291 Jul 25 04:50:52 PM PDT 24 Jul 25 04:50:52 PM PDT 24 9104960 ps
T57 /workspace/coverage/sync_alert/16.prim_sync_alert.3360246341 Jul 25 04:51:05 PM PDT 24 Jul 25 04:51:06 PM PDT 24 9441336 ps
T58 /workspace/coverage/sync_alert/15.prim_sync_alert.2829585807 Jul 25 04:51:05 PM PDT 24 Jul 25 04:51:05 PM PDT 24 9444809 ps
T33 /workspace/coverage/sync_alert/6.prim_sync_alert.1317105377 Jul 25 04:51:05 PM PDT 24 Jul 25 04:51:06 PM PDT 24 8021455 ps
T59 /workspace/coverage/sync_alert/17.prim_sync_alert.3302265733 Jul 25 04:51:34 PM PDT 24 Jul 25 04:51:34 PM PDT 24 8178804 ps
T34 /workspace/coverage/sync_alert/8.prim_sync_alert.2413682914 Jul 25 04:50:56 PM PDT 24 Jul 25 04:50:57 PM PDT 24 10003217 ps
T35 /workspace/coverage/sync_alert/0.prim_sync_alert.2408471046 Jul 25 04:51:07 PM PDT 24 Jul 25 04:51:07 PM PDT 24 8865954 ps
T60 /workspace/coverage/sync_alert/5.prim_sync_alert.4206607762 Jul 25 04:51:01 PM PDT 24 Jul 25 04:51:01 PM PDT 24 9847894 ps
T8 /workspace/coverage/sync_alert/12.prim_sync_alert.410794938 Jul 25 04:50:58 PM PDT 24 Jul 25 04:50:58 PM PDT 24 8794412 ps
T61 /workspace/coverage/sync_alert/10.prim_sync_alert.2184578946 Jul 25 04:50:59 PM PDT 24 Jul 25 04:51:00 PM PDT 24 10660041 ps
T62 /workspace/coverage/sync_alert/19.prim_sync_alert.4290012817 Jul 25 04:51:06 PM PDT 24 Jul 25 04:51:07 PM PDT 24 9035239 ps
T63 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.379305106 Jul 25 04:27:21 PM PDT 24 Jul 25 04:27:21 PM PDT 24 27493679 ps
T64 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3803400762 Jul 25 04:27:31 PM PDT 24 Jul 25 04:27:31 PM PDT 24 29417405 ps
T65 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1148555703 Jul 25 04:27:42 PM PDT 24 Jul 25 04:27:43 PM PDT 24 29927155 ps
T66 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3650380588 Jul 25 04:27:47 PM PDT 24 Jul 25 04:27:47 PM PDT 24 28878244 ps
T67 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.444280379 Jul 25 04:27:33 PM PDT 24 Jul 25 04:27:34 PM PDT 24 26185417 ps
T9 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1692533790 Jul 25 04:27:29 PM PDT 24 Jul 25 04:27:29 PM PDT 24 28571859 ps
T10 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4275424689 Jul 25 04:27:29 PM PDT 24 Jul 25 04:27:29 PM PDT 24 26685661 ps
T68 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1696792365 Jul 25 04:27:32 PM PDT 24 Jul 25 04:27:32 PM PDT 24 27135350 ps
T16 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3863240285 Jul 25 04:27:42 PM PDT 24 Jul 25 04:27:43 PM PDT 24 26640762 ps
T69 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1463922532 Jul 25 04:27:19 PM PDT 24 Jul 25 04:27:20 PM PDT 24 27423771 ps
T70 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1244846534 Jul 25 04:27:27 PM PDT 24 Jul 25 04:27:27 PM PDT 24 27463162 ps
T71 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3870227827 Jul 25 04:27:59 PM PDT 24 Jul 25 04:27:59 PM PDT 24 27384667 ps
T72 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2641714960 Jul 25 04:27:24 PM PDT 24 Jul 25 04:27:25 PM PDT 24 28856802 ps
T73 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3651245641 Jul 25 04:27:40 PM PDT 24 Jul 25 04:27:40 PM PDT 24 28461996 ps
T74 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2862630866 Jul 25 04:27:35 PM PDT 24 Jul 25 04:27:36 PM PDT 24 27668819 ps
T75 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2329725669 Jul 25 04:27:27 PM PDT 24 Jul 25 04:27:27 PM PDT 24 27334253 ps
T76 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1911787919 Jul 25 04:27:33 PM PDT 24 Jul 25 04:27:34 PM PDT 24 25992147 ps
T77 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.56212024 Jul 25 04:27:31 PM PDT 24 Jul 25 04:27:32 PM PDT 24 25645465 ps
T78 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.144147435 Jul 25 04:27:48 PM PDT 24 Jul 25 04:27:49 PM PDT 24 27595262 ps
T79 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2239503799 Jul 25 04:27:32 PM PDT 24 Jul 25 04:27:32 PM PDT 24 27782942 ps

Test location /workspace/coverage/default/2.prim_async_alert.236822446
Short name T11
Test name
Test status
Simulation time 12003828 ps
CPU time 0.38 seconds
Started Jul 25 04:50:29 PM PDT 24
Finished Jul 25 04:50:30 PM PDT 24
Peak memory 145772 kb
Host smart-0311c085-0f95-4077-a632-d87aae6f3e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236822446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.236822446
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2550559228
Short name T36
Test name
Test status
Simulation time 10231416 ps
CPU time 0.37 seconds
Started Jul 25 04:51:06 PM PDT 24
Finished Jul 25 04:51:07 PM PDT 24
Peak memory 145504 kb
Host smart-e4b5b1f3-74b7-4bcb-9275-a7edd756939a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2550559228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2550559228
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2699622939
Short name T15
Test name
Test status
Simulation time 31749084 ps
CPU time 0.41 seconds
Started Jul 25 04:51:02 PM PDT 24
Finished Jul 25 04:51:03 PM PDT 24
Peak memory 145164 kb
Host smart-9699f2a0-bdd3-46e8-880d-7da8e32809bf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2699622939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2699622939
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2036388709
Short name T24
Test name
Test status
Simulation time 10919209 ps
CPU time 0.38 seconds
Started Jul 25 04:50:41 PM PDT 24
Finished Jul 25 04:50:41 PM PDT 24
Peak memory 145784 kb
Host smart-01cbba75-e35a-4071-8f82-c087af32e83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036388709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2036388709
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.410794938
Short name T8
Test name
Test status
Simulation time 8794412 ps
CPU time 0.37 seconds
Started Jul 25 04:50:58 PM PDT 24
Finished Jul 25 04:50:58 PM PDT 24
Peak memory 145472 kb
Host smart-0d143804-324d-4fa5-85af-b5a2031a97b5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=410794938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.410794938
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.902266584
Short name T12
Test name
Test status
Simulation time 11925729 ps
CPU time 0.39 seconds
Started Jul 25 04:50:21 PM PDT 24
Finished Jul 25 04:50:22 PM PDT 24
Peak memory 145696 kb
Host smart-f5b5e05d-cd92-43b6-be09-4c70ad59e9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902266584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.902266584
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3243864322
Short name T21
Test name
Test status
Simulation time 11414622 ps
CPU time 0.38 seconds
Started Jul 25 04:50:21 PM PDT 24
Finished Jul 25 04:50:22 PM PDT 24
Peak memory 145704 kb
Host smart-d8b114fb-47d5-427d-9e8e-2335fab2c590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243864322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3243864322
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.4244632211
Short name T22
Test name
Test status
Simulation time 10772333 ps
CPU time 0.38 seconds
Started Jul 25 04:50:27 PM PDT 24
Finished Jul 25 04:50:28 PM PDT 24
Peak memory 145680 kb
Host smart-543931b2-6e07-4891-8409-82af40d69881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244632211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4244632211
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2757062592
Short name T23
Test name
Test status
Simulation time 9695848 ps
CPU time 0.37 seconds
Started Jul 25 04:50:14 PM PDT 24
Finished Jul 25 04:50:14 PM PDT 24
Peak memory 145748 kb
Host smart-6d43325f-26df-46bc-8eeb-cc7eaf62cd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757062592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2757062592
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1043087638
Short name T20
Test name
Test status
Simulation time 11187981 ps
CPU time 0.39 seconds
Started Jul 25 04:50:33 PM PDT 24
Finished Jul 25 04:50:34 PM PDT 24
Peak memory 145776 kb
Host smart-5cb1c6f9-28b7-48cd-be7d-2667abf4488d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043087638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1043087638
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1234293446
Short name T1
Test name
Test status
Simulation time 10621115 ps
CPU time 0.39 seconds
Started Jul 25 04:50:41 PM PDT 24
Finished Jul 25 04:50:42 PM PDT 24
Peak memory 145664 kb
Host smart-d10000aa-af23-46ab-ae56-b411475ae361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234293446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1234293446
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.4293254416
Short name T7
Test name
Test status
Simulation time 10112045 ps
CPU time 0.37 seconds
Started Jul 25 04:50:27 PM PDT 24
Finished Jul 25 04:50:28 PM PDT 24
Peak memory 145780 kb
Host smart-bb925d85-8599-44cf-9ad5-7f00832ba3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293254416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.4293254416
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.4177973460
Short name T46
Test name
Test status
Simulation time 12778418 ps
CPU time 0.38 seconds
Started Jul 25 04:50:20 PM PDT 24
Finished Jul 25 04:50:20 PM PDT 24
Peak memory 145680 kb
Host smart-a3c40ec7-d32b-4101-9928-a019905c51a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177973460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.4177973460
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.4150608379
Short name T5
Test name
Test status
Simulation time 10208308 ps
CPU time 0.38 seconds
Started Jul 25 04:50:32 PM PDT 24
Finished Jul 25 04:50:32 PM PDT 24
Peak memory 145680 kb
Host smart-4a5291f4-43d4-4df0-bb01-43ddd2777665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150608379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.4150608379
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3239750075
Short name T2
Test name
Test status
Simulation time 11011479 ps
CPU time 0.37 seconds
Started Jul 25 04:50:32 PM PDT 24
Finished Jul 25 04:50:32 PM PDT 24
Peak memory 145680 kb
Host smart-384c31c8-5233-4a4b-8741-d52ea5fccb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239750075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3239750075
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1607097781
Short name T4
Test name
Test status
Simulation time 10979649 ps
CPU time 0.39 seconds
Started Jul 25 04:50:30 PM PDT 24
Finished Jul 25 04:50:30 PM PDT 24
Peak memory 145672 kb
Host smart-b1593e39-ba9d-420e-8899-4fd358083b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607097781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1607097781
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.859729926
Short name T14
Test name
Test status
Simulation time 10633110 ps
CPU time 0.4 seconds
Started Jul 25 04:50:30 PM PDT 24
Finished Jul 25 04:50:31 PM PDT 24
Peak memory 145696 kb
Host smart-ef08849b-76e4-4b2d-9c3d-de8f092955c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859729926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.859729926
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3544495219
Short name T13
Test name
Test status
Simulation time 11634724 ps
CPU time 0.36 seconds
Started Jul 25 04:50:27 PM PDT 24
Finished Jul 25 04:50:28 PM PDT 24
Peak memory 145772 kb
Host smart-11ae5ace-a30c-4ffd-a6ee-6a51a442711b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544495219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3544495219
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1401988864
Short name T3
Test name
Test status
Simulation time 11206668 ps
CPU time 0.37 seconds
Started Jul 25 04:50:44 PM PDT 24
Finished Jul 25 04:50:44 PM PDT 24
Peak memory 145672 kb
Host smart-a7015eb4-1db0-4174-a913-12d018a46632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401988864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1401988864
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.4105158985
Short name T18
Test name
Test status
Simulation time 11097530 ps
CPU time 0.37 seconds
Started Jul 25 04:50:27 PM PDT 24
Finished Jul 25 04:50:27 PM PDT 24
Peak memory 145672 kb
Host smart-22f2898c-8f96-4d92-9c0f-17ec2d05d0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105158985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.4105158985
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2483946924
Short name T6
Test name
Test status
Simulation time 10744392 ps
CPU time 0.39 seconds
Started Jul 25 04:50:45 PM PDT 24
Finished Jul 25 04:50:45 PM PDT 24
Peak memory 145784 kb
Host smart-6e106986-b404-4aef-92d0-949460dd8e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483946924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2483946924
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.926830480
Short name T17
Test name
Test status
Simulation time 11083141 ps
CPU time 0.38 seconds
Started Jul 25 04:50:20 PM PDT 24
Finished Jul 25 04:50:20 PM PDT 24
Peak memory 145672 kb
Host smart-bd99a474-3502-45e3-a43b-3347933d8c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926830480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.926830480
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3127843110
Short name T45
Test name
Test status
Simulation time 29609262 ps
CPU time 0.4 seconds
Started Jul 25 04:50:47 PM PDT 24
Finished Jul 25 04:50:47 PM PDT 24
Peak memory 145220 kb
Host smart-ad00f86c-4db8-4d85-9a00-26ef6c8a6c6e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3127843110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3127843110
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.342924979
Short name T54
Test name
Test status
Simulation time 30371956 ps
CPU time 0.39 seconds
Started Jul 25 04:50:57 PM PDT 24
Finished Jul 25 04:50:58 PM PDT 24
Peak memory 145304 kb
Host smart-f9dad60b-3dbc-428f-a36a-81d688f79362
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=342924979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.342924979
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3621506527
Short name T48
Test name
Test status
Simulation time 30587849 ps
CPU time 0.4 seconds
Started Jul 25 04:51:07 PM PDT 24
Finished Jul 25 04:51:07 PM PDT 24
Peak memory 145296 kb
Host smart-7a9b671a-521a-4e63-8587-0d491c836402
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3621506527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3621506527
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.944635831
Short name T25
Test name
Test status
Simulation time 29881825 ps
CPU time 0.39 seconds
Started Jul 25 04:51:05 PM PDT 24
Finished Jul 25 04:51:06 PM PDT 24
Peak memory 145184 kb
Host smart-37f88c9b-f503-4b73-8e82-b10dd204fdb1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=944635831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.944635831
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1425755643
Short name T19
Test name
Test status
Simulation time 31368379 ps
CPU time 0.4 seconds
Started Jul 25 04:51:00 PM PDT 24
Finished Jul 25 04:51:01 PM PDT 24
Peak memory 145240 kb
Host smart-d5e4364c-5bd1-4662-a114-069a29470a19
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1425755643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1425755643
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.171126525
Short name T41
Test name
Test status
Simulation time 29980019 ps
CPU time 0.4 seconds
Started Jul 25 04:51:04 PM PDT 24
Finished Jul 25 04:51:05 PM PDT 24
Peak memory 145296 kb
Host smart-9b21a46e-bef2-4410-bf32-332a772877a6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=171126525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.171126525
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1181462794
Short name T52
Test name
Test status
Simulation time 31734551 ps
CPU time 0.4 seconds
Started Jul 25 04:50:54 PM PDT 24
Finished Jul 25 04:50:54 PM PDT 24
Peak memory 145296 kb
Host smart-19ab6230-c1b8-4706-a5ea-3320867dcadc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1181462794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1181462794
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2416711638
Short name T56
Test name
Test status
Simulation time 32352670 ps
CPU time 0.42 seconds
Started Jul 25 04:51:19 PM PDT 24
Finished Jul 25 04:51:20 PM PDT 24
Peak memory 145296 kb
Host smart-9950db45-8549-43ab-9014-f8f7cce76c64
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2416711638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2416711638
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.451392936
Short name T42
Test name
Test status
Simulation time 30459486 ps
CPU time 0.42 seconds
Started Jul 25 04:50:58 PM PDT 24
Finished Jul 25 04:50:59 PM PDT 24
Peak memory 145304 kb
Host smart-6c28a778-a724-4abc-a1eb-8b5acf088af4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=451392936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.451392936
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2187107699
Short name T44
Test name
Test status
Simulation time 30117730 ps
CPU time 0.39 seconds
Started Jul 25 04:51:04 PM PDT 24
Finished Jul 25 04:51:05 PM PDT 24
Peak memory 145316 kb
Host smart-c55e5776-dc8f-4561-9187-2f7e085ad42c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2187107699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2187107699
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2679489442
Short name T40
Test name
Test status
Simulation time 30572030 ps
CPU time 0.38 seconds
Started Jul 25 04:51:17 PM PDT 24
Finished Jul 25 04:51:18 PM PDT 24
Peak memory 145248 kb
Host smart-13de44e8-4100-4740-b1da-d6f0bc851825
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2679489442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2679489442
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3966068620
Short name T49
Test name
Test status
Simulation time 30386141 ps
CPU time 0.39 seconds
Started Jul 25 04:50:57 PM PDT 24
Finished Jul 25 04:50:58 PM PDT 24
Peak memory 145312 kb
Host smart-1d3584a8-c5ca-48d9-ab92-d81f3214117d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3966068620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3966068620
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.132675051
Short name T53
Test name
Test status
Simulation time 30400372 ps
CPU time 0.38 seconds
Started Jul 25 04:51:02 PM PDT 24
Finished Jul 25 04:51:03 PM PDT 24
Peak memory 145288 kb
Host smart-9297b383-e0db-449b-b7d1-beee5e1861f7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=132675051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.132675051
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2806156612
Short name T43
Test name
Test status
Simulation time 29471696 ps
CPU time 0.38 seconds
Started Jul 25 04:51:04 PM PDT 24
Finished Jul 25 04:51:04 PM PDT 24
Peak memory 145288 kb
Host smart-5d86445d-f93d-43d1-95b2-255c3456b4a6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2806156612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2806156612
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1066292913
Short name T50
Test name
Test status
Simulation time 32110882 ps
CPU time 0.41 seconds
Started Jul 25 04:50:55 PM PDT 24
Finished Jul 25 04:50:55 PM PDT 24
Peak memory 145164 kb
Host smart-78cdfaf2-d72d-4af7-ad25-ad7bbe04d487
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1066292913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1066292913
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2011392345
Short name T47
Test name
Test status
Simulation time 29754741 ps
CPU time 0.39 seconds
Started Jul 25 04:51:04 PM PDT 24
Finished Jul 25 04:51:04 PM PDT 24
Peak memory 145312 kb
Host smart-3606f7d6-cf5b-415b-a6f5-1969acbcb0fa
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2011392345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2011392345
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2504513667
Short name T55
Test name
Test status
Simulation time 31203821 ps
CPU time 0.38 seconds
Started Jul 25 04:51:11 PM PDT 24
Finished Jul 25 04:51:11 PM PDT 24
Peak memory 145312 kb
Host smart-fe2460a6-0512-4fda-b0ca-7c6d447d1f6c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2504513667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2504513667
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1528052143
Short name T39
Test name
Test status
Simulation time 30806884 ps
CPU time 0.42 seconds
Started Jul 25 04:51:40 PM PDT 24
Finished Jul 25 04:51:41 PM PDT 24
Peak memory 145248 kb
Host smart-a05e528d-c655-4c0c-88f2-fcff035f7505
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1528052143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1528052143
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3678870891
Short name T51
Test name
Test status
Simulation time 28694302 ps
CPU time 0.38 seconds
Started Jul 25 04:51:02 PM PDT 24
Finished Jul 25 04:51:02 PM PDT 24
Peak memory 145228 kb
Host smart-74988c02-8035-49c8-b9ec-91fa53b9a995
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3678870891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3678870891
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2408471046
Short name T35
Test name
Test status
Simulation time 8865954 ps
CPU time 0.38 seconds
Started Jul 25 04:51:07 PM PDT 24
Finished Jul 25 04:51:07 PM PDT 24
Peak memory 145420 kb
Host smart-27cf70aa-2a24-4fd6-8a24-ad76c5a4aba2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2408471046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2408471046
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.168085954
Short name T37
Test name
Test status
Simulation time 8944526 ps
CPU time 0.38 seconds
Started Jul 25 04:51:07 PM PDT 24
Finished Jul 25 04:51:07 PM PDT 24
Peak memory 145556 kb
Host smart-e2b7a807-3e83-4085-929a-a54a236ea08a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=168085954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.168085954
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2184578946
Short name T61
Test name
Test status
Simulation time 10660041 ps
CPU time 0.38 seconds
Started Jul 25 04:50:59 PM PDT 24
Finished Jul 25 04:51:00 PM PDT 24
Peak memory 145560 kb
Host smart-e9cffe33-4200-471b-90c6-a640602d7702
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2184578946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2184578946
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1928158868
Short name T28
Test name
Test status
Simulation time 9986902 ps
CPU time 0.38 seconds
Started Jul 25 04:51:03 PM PDT 24
Finished Jul 25 04:51:04 PM PDT 24
Peak memory 145596 kb
Host smart-30347ccd-92db-4fe9-b5e2-f42a2fc4b7b3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1928158868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1928158868
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3323899787
Short name T30
Test name
Test status
Simulation time 9365969 ps
CPU time 0.36 seconds
Started Jul 25 04:51:29 PM PDT 24
Finished Jul 25 04:51:29 PM PDT 24
Peak memory 145588 kb
Host smart-36c77c4d-f0af-47cd-aedc-d0aeb0235412
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3323899787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3323899787
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2829585807
Short name T58
Test name
Test status
Simulation time 9444809 ps
CPU time 0.38 seconds
Started Jul 25 04:51:05 PM PDT 24
Finished Jul 25 04:51:05 PM PDT 24
Peak memory 145596 kb
Host smart-2d3a2558-2d3b-4f42-9b5c-093d535dfae4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2829585807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2829585807
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3360246341
Short name T57
Test name
Test status
Simulation time 9441336 ps
CPU time 0.37 seconds
Started Jul 25 04:51:05 PM PDT 24
Finished Jul 25 04:51:06 PM PDT 24
Peak memory 145456 kb
Host smart-f12724d6-63e9-4d3f-b563-fe57c521f196
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3360246341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3360246341
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3302265733
Short name T59
Test name
Test status
Simulation time 8178804 ps
CPU time 0.37 seconds
Started Jul 25 04:51:34 PM PDT 24
Finished Jul 25 04:51:34 PM PDT 24
Peak memory 145580 kb
Host smart-379b3179-ddcf-4d24-89c0-308b5243c69c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3302265733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3302265733
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.4068763391
Short name T38
Test name
Test status
Simulation time 9538925 ps
CPU time 0.37 seconds
Started Jul 25 04:51:04 PM PDT 24
Finished Jul 25 04:51:05 PM PDT 24
Peak memory 145568 kb
Host smart-ae9b7bb7-1f52-4cef-877f-e0c2dffc3cfc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4068763391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.4068763391
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.4290012817
Short name T62
Test name
Test status
Simulation time 9035239 ps
CPU time 0.38 seconds
Started Jul 25 04:51:06 PM PDT 24
Finished Jul 25 04:51:07 PM PDT 24
Peak memory 145608 kb
Host smart-4a2b133d-3e82-4272-a02f-ffc32900ed14
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4290012817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.4290012817
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3473785304
Short name T27
Test name
Test status
Simulation time 10796207 ps
CPU time 0.42 seconds
Started Jul 25 04:51:04 PM PDT 24
Finished Jul 25 04:51:04 PM PDT 24
Peak memory 145568 kb
Host smart-74e9a5ee-277b-4faa-bcda-b07e49d2471d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3473785304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3473785304
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3557091302
Short name T31
Test name
Test status
Simulation time 9748485 ps
CPU time 0.4 seconds
Started Jul 25 04:51:02 PM PDT 24
Finished Jul 25 04:51:02 PM PDT 24
Peak memory 145668 kb
Host smart-7c53ddac-12a6-4374-aa2e-68cba6625d3b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3557091302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3557091302
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.215148291
Short name T32
Test name
Test status
Simulation time 9104960 ps
CPU time 0.38 seconds
Started Jul 25 04:50:52 PM PDT 24
Finished Jul 25 04:50:52 PM PDT 24
Peak memory 145540 kb
Host smart-7e45431d-4ba1-4487-95c7-d80ffc383d7a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=215148291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.215148291
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.4206607762
Short name T60
Test name
Test status
Simulation time 9847894 ps
CPU time 0.38 seconds
Started Jul 25 04:51:01 PM PDT 24
Finished Jul 25 04:51:01 PM PDT 24
Peak memory 145568 kb
Host smart-2e8de9aa-1f92-437d-9995-7cd3c3feb049
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4206607762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.4206607762
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1317105377
Short name T33
Test name
Test status
Simulation time 8021455 ps
CPU time 0.36 seconds
Started Jul 25 04:51:05 PM PDT 24
Finished Jul 25 04:51:06 PM PDT 24
Peak memory 145484 kb
Host smart-21420588-c65e-4f22-a460-1e3898cabde9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1317105377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1317105377
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.155929531
Short name T29
Test name
Test status
Simulation time 9564541 ps
CPU time 0.4 seconds
Started Jul 25 04:50:59 PM PDT 24
Finished Jul 25 04:50:59 PM PDT 24
Peak memory 145480 kb
Host smart-fe577c65-4b89-4121-8498-34b230647bb7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=155929531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.155929531
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2413682914
Short name T34
Test name
Test status
Simulation time 10003217 ps
CPU time 0.38 seconds
Started Jul 25 04:50:56 PM PDT 24
Finished Jul 25 04:50:57 PM PDT 24
Peak memory 145568 kb
Host smart-8181441d-2774-4326-a512-03a6ed54a572
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2413682914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2413682914
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2019206084
Short name T26
Test name
Test status
Simulation time 9719702 ps
CPU time 0.38 seconds
Started Jul 25 04:51:05 PM PDT 24
Finished Jul 25 04:51:06 PM PDT 24
Peak memory 145484 kb
Host smart-ad23c7d2-7633-4b40-9f10-842a3b8a2d80
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2019206084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2019206084
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2239503799
Short name T79
Test name
Test status
Simulation time 27782942 ps
CPU time 0.41 seconds
Started Jul 25 04:27:32 PM PDT 24
Finished Jul 25 04:27:32 PM PDT 24
Peak memory 145428 kb
Host smart-2997ba6a-cb09-4cb1-b0b0-30840b2fbc19
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2239503799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2239503799
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1148555703
Short name T65
Test name
Test status
Simulation time 29927155 ps
CPU time 0.4 seconds
Started Jul 25 04:27:42 PM PDT 24
Finished Jul 25 04:27:43 PM PDT 24
Peak memory 145420 kb
Host smart-fdf1a637-28b9-4eae-aa0e-0b647397c069
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1148555703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1148555703
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2329725669
Short name T75
Test name
Test status
Simulation time 27334253 ps
CPU time 0.42 seconds
Started Jul 25 04:27:27 PM PDT 24
Finished Jul 25 04:27:27 PM PDT 24
Peak memory 145456 kb
Host smart-07e853d0-ea56-415f-9911-b995a785a492
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2329725669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2329725669
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.144147435
Short name T78
Test name
Test status
Simulation time 27595262 ps
CPU time 0.39 seconds
Started Jul 25 04:27:48 PM PDT 24
Finished Jul 25 04:27:49 PM PDT 24
Peak memory 145436 kb
Host smart-ff8fbb22-3dc0-4548-ba1a-e177e986c32c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=144147435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.144147435
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4275424689
Short name T10
Test name
Test status
Simulation time 26685661 ps
CPU time 0.39 seconds
Started Jul 25 04:27:29 PM PDT 24
Finished Jul 25 04:27:29 PM PDT 24
Peak memory 145424 kb
Host smart-d39f1016-ceaf-4faa-a8ac-a0771dbd3ebe
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4275424689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.4275424689
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.56212024
Short name T77
Test name
Test status
Simulation time 25645465 ps
CPU time 0.38 seconds
Started Jul 25 04:27:31 PM PDT 24
Finished Jul 25 04:27:32 PM PDT 24
Peak memory 145360 kb
Host smart-de720bb8-1199-485c-85bb-636d24021356
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=56212024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.56212024
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.444280379
Short name T67
Test name
Test status
Simulation time 26185417 ps
CPU time 0.39 seconds
Started Jul 25 04:27:33 PM PDT 24
Finished Jul 25 04:27:34 PM PDT 24
Peak memory 145440 kb
Host smart-c205a9de-01d6-4062-9daf-986c73b4b552
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=444280379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.444280379
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2862630866
Short name T74
Test name
Test status
Simulation time 27668819 ps
CPU time 0.39 seconds
Started Jul 25 04:27:35 PM PDT 24
Finished Jul 25 04:27:36 PM PDT 24
Peak memory 145436 kb
Host smart-4df17050-3275-4f5e-aec2-884ed94e7e71
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2862630866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2862630866
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1692533790
Short name T9
Test name
Test status
Simulation time 28571859 ps
CPU time 0.4 seconds
Started Jul 25 04:27:29 PM PDT 24
Finished Jul 25 04:27:29 PM PDT 24
Peak memory 145464 kb
Host smart-418a673f-1791-48db-8a45-e8c547f29601
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1692533790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1692533790
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3650380588
Short name T66
Test name
Test status
Simulation time 28878244 ps
CPU time 0.39 seconds
Started Jul 25 04:27:47 PM PDT 24
Finished Jul 25 04:27:47 PM PDT 24
Peak memory 145448 kb
Host smart-8dc9c543-51f6-4abb-8496-2a050270457b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3650380588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3650380588
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3863240285
Short name T16
Test name
Test status
Simulation time 26640762 ps
CPU time 0.4 seconds
Started Jul 25 04:27:42 PM PDT 24
Finished Jul 25 04:27:43 PM PDT 24
Peak memory 145396 kb
Host smart-25ed3414-2a2b-4602-be53-80bc8a04c2fa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3863240285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3863240285
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3651245641
Short name T73
Test name
Test status
Simulation time 28461996 ps
CPU time 0.39 seconds
Started Jul 25 04:27:40 PM PDT 24
Finished Jul 25 04:27:40 PM PDT 24
Peak memory 145424 kb
Host smart-bb8304d0-bce9-4201-945d-c78848e7c454
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3651245641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3651245641
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1696792365
Short name T68
Test name
Test status
Simulation time 27135350 ps
CPU time 0.39 seconds
Started Jul 25 04:27:32 PM PDT 24
Finished Jul 25 04:27:32 PM PDT 24
Peak memory 145420 kb
Host smart-a48924a2-d54b-422f-bfde-7b876b877ffb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1696792365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1696792365
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1911787919
Short name T76
Test name
Test status
Simulation time 25992147 ps
CPU time 0.39 seconds
Started Jul 25 04:27:33 PM PDT 24
Finished Jul 25 04:27:34 PM PDT 24
Peak memory 145472 kb
Host smart-3cb5ad09-32a6-4421-8da8-43875226cfb9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1911787919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1911787919
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1463922532
Short name T69
Test name
Test status
Simulation time 27423771 ps
CPU time 0.39 seconds
Started Jul 25 04:27:19 PM PDT 24
Finished Jul 25 04:27:20 PM PDT 24
Peak memory 145436 kb
Host smart-7cd6ae7b-aa2f-4ed5-9976-defc5b57fc9a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1463922532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1463922532
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2641714960
Short name T72
Test name
Test status
Simulation time 28856802 ps
CPU time 0.39 seconds
Started Jul 25 04:27:24 PM PDT 24
Finished Jul 25 04:27:25 PM PDT 24
Peak memory 145468 kb
Host smart-c2977faa-e924-426a-bb7c-eb1bdd2151bb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2641714960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2641714960
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3870227827
Short name T71
Test name
Test status
Simulation time 27384667 ps
CPU time 0.42 seconds
Started Jul 25 04:27:59 PM PDT 24
Finished Jul 25 04:27:59 PM PDT 24
Peak memory 145420 kb
Host smart-8380f711-0cba-4b85-9af3-5903920e59c3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3870227827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3870227827
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.379305106
Short name T63
Test name
Test status
Simulation time 27493679 ps
CPU time 0.39 seconds
Started Jul 25 04:27:21 PM PDT 24
Finished Jul 25 04:27:21 PM PDT 24
Peak memory 145428 kb
Host smart-ee8ef4ed-ce07-48a9-9fc2-b2ec370d2e14
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=379305106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.379305106
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1244846534
Short name T70
Test name
Test status
Simulation time 27463162 ps
CPU time 0.4 seconds
Started Jul 25 04:27:27 PM PDT 24
Finished Jul 25 04:27:27 PM PDT 24
Peak memory 145420 kb
Host smart-476eee63-e44a-4132-b086-5b218ef0d98b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1244846534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1244846534
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3803400762
Short name T64
Test name
Test status
Simulation time 29417405 ps
CPU time 0.39 seconds
Started Jul 25 04:27:31 PM PDT 24
Finished Jul 25 04:27:31 PM PDT 24
Peak memory 145436 kb
Host smart-710897d4-4ca0-4bfc-aaf7-19e18298c037
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3803400762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3803400762
Directory /workspace/9.prim_sync_fatal_alert/latest
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