Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 96.43 96.43 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/1.prim_async_alert.1467788719
91.80 3.13 100.00 0.00 93.75 0.00 96.43 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/1.prim_sync_alert.525167007
93.90 2.11 100.00 0.00 95.83 2.08 100.00 3.57 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2080750960
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/3.prim_async_alert.3620144553
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1850638497
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/17.prim_sync_alert.2869479527

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2129300256
/workspace/coverage/default/10.prim_async_alert.940731531
/workspace/coverage/default/11.prim_async_alert.1377844353
/workspace/coverage/default/12.prim_async_alert.2067609646
/workspace/coverage/default/13.prim_async_alert.2586878504
/workspace/coverage/default/14.prim_async_alert.2135784986
/workspace/coverage/default/15.prim_async_alert.994353691
/workspace/coverage/default/16.prim_async_alert.2285000615
/workspace/coverage/default/17.prim_async_alert.2797420500
/workspace/coverage/default/18.prim_async_alert.4215015543
/workspace/coverage/default/19.prim_async_alert.543281792
/workspace/coverage/default/2.prim_async_alert.3909016998
/workspace/coverage/default/4.prim_async_alert.2931853094
/workspace/coverage/default/5.prim_async_alert.3515408266
/workspace/coverage/default/6.prim_async_alert.204083294
/workspace/coverage/default/7.prim_async_alert.2563394466
/workspace/coverage/default/8.prim_async_alert.199166769
/workspace/coverage/default/9.prim_async_alert.3159344668
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1335990861
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2987138060
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.847428403
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2817230864
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1689140845
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.879980005
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4156959733
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.616112711
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1417430670
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3654109092
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1507939406
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1053118777
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3654635081
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3328410026
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2952360748
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3100091635
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3615010124
/workspace/coverage/sync_alert/0.prim_sync_alert.2680466945
/workspace/coverage/sync_alert/10.prim_sync_alert.1985626456
/workspace/coverage/sync_alert/11.prim_sync_alert.1034740991
/workspace/coverage/sync_alert/12.prim_sync_alert.3391227109
/workspace/coverage/sync_alert/13.prim_sync_alert.1746037857
/workspace/coverage/sync_alert/14.prim_sync_alert.1163695528
/workspace/coverage/sync_alert/15.prim_sync_alert.4203687829
/workspace/coverage/sync_alert/16.prim_sync_alert.4263671771
/workspace/coverage/sync_alert/18.prim_sync_alert.3502212223
/workspace/coverage/sync_alert/19.prim_sync_alert.2326049323
/workspace/coverage/sync_alert/2.prim_sync_alert.1376524454
/workspace/coverage/sync_alert/3.prim_sync_alert.1871557612
/workspace/coverage/sync_alert/4.prim_sync_alert.20981079
/workspace/coverage/sync_alert/5.prim_sync_alert.3279279966
/workspace/coverage/sync_alert/6.prim_sync_alert.136572258
/workspace/coverage/sync_alert/7.prim_sync_alert.1372188442
/workspace/coverage/sync_alert/8.prim_sync_alert.553851984
/workspace/coverage/sync_alert/9.prim_sync_alert.3540515066
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1807988477
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1528270971
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2861191622
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1097747186
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.978191483
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3943916941
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3751812747
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2462388297
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2677404063
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3998834074
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2370450955
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1899433478
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2541709705
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1965077144
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1500445628
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.598333638
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3025085700
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3603655301
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3683446132
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3102943111



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/9.prim_async_alert.3159344668 Jul 26 04:28:15 PM PDT 24 Jul 26 04:28:16 PM PDT 24 10922509 ps
T2 /workspace/coverage/default/14.prim_async_alert.2135784986 Jul 26 04:28:38 PM PDT 24 Jul 26 04:28:39 PM PDT 24 10897654 ps
T3 /workspace/coverage/default/18.prim_async_alert.4215015543 Jul 26 04:28:38 PM PDT 24 Jul 26 04:28:39 PM PDT 24 10398197 ps
T8 /workspace/coverage/default/1.prim_async_alert.1467788719 Jul 26 04:28:17 PM PDT 24 Jul 26 04:28:17 PM PDT 24 11986683 ps
T5 /workspace/coverage/default/7.prim_async_alert.2563394466 Jul 26 04:28:15 PM PDT 24 Jul 26 04:28:16 PM PDT 24 10500420 ps
T9 /workspace/coverage/default/5.prim_async_alert.3515408266 Jul 26 04:28:24 PM PDT 24 Jul 26 04:28:24 PM PDT 24 12100421 ps
T17 /workspace/coverage/default/0.prim_async_alert.2129300256 Jul 26 04:28:15 PM PDT 24 Jul 26 04:28:16 PM PDT 24 10084854 ps
T6 /workspace/coverage/default/4.prim_async_alert.2931853094 Jul 26 04:28:16 PM PDT 24 Jul 26 04:28:17 PM PDT 24 11843070 ps
T18 /workspace/coverage/default/12.prim_async_alert.2067609646 Jul 26 04:28:27 PM PDT 24 Jul 26 04:28:27 PM PDT 24 11059041 ps
T19 /workspace/coverage/default/8.prim_async_alert.199166769 Jul 26 04:28:26 PM PDT 24 Jul 26 04:28:27 PM PDT 24 11364722 ps
T16 /workspace/coverage/default/6.prim_async_alert.204083294 Jul 26 04:28:24 PM PDT 24 Jul 26 04:28:24 PM PDT 24 10232286 ps
T7 /workspace/coverage/default/15.prim_async_alert.994353691 Jul 26 04:28:39 PM PDT 24 Jul 26 04:28:40 PM PDT 24 10138015 ps
T12 /workspace/coverage/default/13.prim_async_alert.2586878504 Jul 26 04:28:37 PM PDT 24 Jul 26 04:28:37 PM PDT 24 12176048 ps
T45 /workspace/coverage/default/16.prim_async_alert.2285000615 Jul 26 04:28:44 PM PDT 24 Jul 26 04:28:44 PM PDT 24 11262862 ps
T46 /workspace/coverage/default/2.prim_async_alert.3909016998 Jul 26 04:28:13 PM PDT 24 Jul 26 04:28:14 PM PDT 24 11707075 ps
T47 /workspace/coverage/default/17.prim_async_alert.2797420500 Jul 26 04:28:38 PM PDT 24 Jul 26 04:28:39 PM PDT 24 11477914 ps
T13 /workspace/coverage/default/3.prim_async_alert.3620144553 Jul 26 04:28:15 PM PDT 24 Jul 26 04:28:15 PM PDT 24 12874244 ps
T48 /workspace/coverage/default/11.prim_async_alert.1377844353 Jul 26 04:28:30 PM PDT 24 Jul 26 04:28:31 PM PDT 24 11111732 ps
T49 /workspace/coverage/default/10.prim_async_alert.940731531 Jul 26 04:28:38 PM PDT 24 Jul 26 04:28:38 PM PDT 24 12176205 ps
T50 /workspace/coverage/default/19.prim_async_alert.543281792 Jul 26 04:28:24 PM PDT 24 Jul 26 04:28:25 PM PDT 24 10875146 ps
T20 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1417430670 Jul 26 04:28:27 PM PDT 24 Jul 26 04:28:27 PM PDT 24 32584780 ps
T38 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4156959733 Jul 26 04:28:31 PM PDT 24 Jul 26 04:28:32 PM PDT 24 29353769 ps
T37 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.616112711 Jul 26 04:28:30 PM PDT 24 Jul 26 04:28:30 PM PDT 24 28451194 ps
T39 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2080750960 Jul 26 04:28:45 PM PDT 24 Jul 26 04:28:45 PM PDT 24 28987730 ps
T40 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1689140845 Jul 26 04:28:43 PM PDT 24 Jul 26 04:28:44 PM PDT 24 28976416 ps
T4 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1850638497 Jul 26 04:28:39 PM PDT 24 Jul 26 04:28:40 PM PDT 24 29399775 ps
T41 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.847428403 Jul 26 04:28:23 PM PDT 24 Jul 26 04:28:24 PM PDT 24 30849699 ps
T42 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3654109092 Jul 26 04:28:41 PM PDT 24 Jul 26 04:28:41 PM PDT 24 32797941 ps
T43 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2817230864 Jul 26 04:28:40 PM PDT 24 Jul 26 04:28:41 PM PDT 24 27965236 ps
T44 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3328410026 Jul 26 04:28:25 PM PDT 24 Jul 26 04:28:26 PM PDT 24 29600232 ps
T51 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1053118777 Jul 26 04:28:36 PM PDT 24 Jul 26 04:28:36 PM PDT 24 29287402 ps
T52 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2952360748 Jul 26 04:28:29 PM PDT 24 Jul 26 04:28:29 PM PDT 24 29550311 ps
T14 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3654635081 Jul 26 04:28:27 PM PDT 24 Jul 26 04:28:28 PM PDT 24 32279946 ps
T15 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.879980005 Jul 26 04:28:32 PM PDT 24 Jul 26 04:28:33 PM PDT 24 30170110 ps
T53 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1507939406 Jul 26 04:28:32 PM PDT 24 Jul 26 04:28:33 PM PDT 24 30346924 ps
T54 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3100091635 Jul 26 04:28:37 PM PDT 24 Jul 26 04:28:38 PM PDT 24 31090112 ps
T55 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2987138060 Jul 26 04:28:27 PM PDT 24 Jul 26 04:28:28 PM PDT 24 29835060 ps
T56 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3615010124 Jul 26 04:28:38 PM PDT 24 Jul 26 04:28:39 PM PDT 24 30028355 ps
T57 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1335990861 Jul 26 04:28:34 PM PDT 24 Jul 26 04:28:35 PM PDT 24 30165710 ps
T30 /workspace/coverage/sync_alert/18.prim_sync_alert.3502212223 Jul 26 05:32:32 PM PDT 24 Jul 26 05:32:33 PM PDT 24 9322143 ps
T21 /workspace/coverage/sync_alert/16.prim_sync_alert.4263671771 Jul 26 05:32:35 PM PDT 24 Jul 26 05:32:35 PM PDT 24 8956879 ps
T31 /workspace/coverage/sync_alert/10.prim_sync_alert.1985626456 Jul 26 05:32:36 PM PDT 24 Jul 26 05:32:37 PM PDT 24 8844530 ps
T22 /workspace/coverage/sync_alert/1.prim_sync_alert.525167007 Jul 26 05:32:40 PM PDT 24 Jul 26 05:32:40 PM PDT 24 9780289 ps
T23 /workspace/coverage/sync_alert/0.prim_sync_alert.2680466945 Jul 26 05:32:25 PM PDT 24 Jul 26 05:32:25 PM PDT 24 10009981 ps
T32 /workspace/coverage/sync_alert/14.prim_sync_alert.1163695528 Jul 26 05:32:30 PM PDT 24 Jul 26 05:32:30 PM PDT 24 9130863 ps
T33 /workspace/coverage/sync_alert/6.prim_sync_alert.136572258 Jul 26 05:32:36 PM PDT 24 Jul 26 05:32:37 PM PDT 24 8365027 ps
T34 /workspace/coverage/sync_alert/9.prim_sync_alert.3540515066 Jul 26 05:32:27 PM PDT 24 Jul 26 05:32:28 PM PDT 24 9591436 ps
T35 /workspace/coverage/sync_alert/12.prim_sync_alert.3391227109 Jul 26 05:32:30 PM PDT 24 Jul 26 05:32:30 PM PDT 24 9576432 ps
T36 /workspace/coverage/sync_alert/11.prim_sync_alert.1034740991 Jul 26 05:32:34 PM PDT 24 Jul 26 05:32:35 PM PDT 24 9377996 ps
T58 /workspace/coverage/sync_alert/8.prim_sync_alert.553851984 Jul 26 05:32:28 PM PDT 24 Jul 26 05:32:28 PM PDT 24 9121350 ps
T59 /workspace/coverage/sync_alert/2.prim_sync_alert.1376524454 Jul 26 05:32:31 PM PDT 24 Jul 26 05:32:31 PM PDT 24 10627666 ps
T60 /workspace/coverage/sync_alert/13.prim_sync_alert.1746037857 Jul 26 05:32:32 PM PDT 24 Jul 26 05:32:33 PM PDT 24 9950633 ps
T24 /workspace/coverage/sync_alert/19.prim_sync_alert.2326049323 Jul 26 05:32:29 PM PDT 24 Jul 26 05:32:29 PM PDT 24 9342969 ps
T25 /workspace/coverage/sync_alert/15.prim_sync_alert.4203687829 Jul 26 05:32:40 PM PDT 24 Jul 26 05:32:40 PM PDT 24 8965660 ps
T61 /workspace/coverage/sync_alert/3.prim_sync_alert.1871557612 Jul 26 05:32:31 PM PDT 24 Jul 26 05:32:32 PM PDT 24 8495819 ps
T62 /workspace/coverage/sync_alert/7.prim_sync_alert.1372188442 Jul 26 05:32:36 PM PDT 24 Jul 26 05:32:37 PM PDT 24 8855228 ps
T26 /workspace/coverage/sync_alert/5.prim_sync_alert.3279279966 Jul 26 05:32:29 PM PDT 24 Jul 26 05:32:30 PM PDT 24 8878704 ps
T10 /workspace/coverage/sync_alert/17.prim_sync_alert.2869479527 Jul 26 05:32:31 PM PDT 24 Jul 26 05:32:31 PM PDT 24 9669677 ps
T63 /workspace/coverage/sync_alert/4.prim_sync_alert.20981079 Jul 26 05:32:30 PM PDT 24 Jul 26 05:32:30 PM PDT 24 8966073 ps
T64 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2462388297 Jul 26 04:31:56 PM PDT 24 Jul 26 04:31:56 PM PDT 24 27349258 ps
T27 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3943916941 Jul 26 04:31:45 PM PDT 24 Jul 26 04:31:51 PM PDT 24 27289951 ps
T28 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2677404063 Jul 26 04:31:53 PM PDT 24 Jul 26 04:31:54 PM PDT 24 27669904 ps
T29 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1965077144 Jul 26 04:32:15 PM PDT 24 Jul 26 04:32:16 PM PDT 24 26481776 ps
T65 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3683446132 Jul 26 04:32:05 PM PDT 24 Jul 26 04:32:05 PM PDT 24 27404426 ps
T66 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1899433478 Jul 26 04:31:54 PM PDT 24 Jul 26 04:31:54 PM PDT 24 26744539 ps
T11 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3751812747 Jul 26 04:31:51 PM PDT 24 Jul 26 04:31:51 PM PDT 24 28594343 ps
T67 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1500445628 Jul 26 04:31:49 PM PDT 24 Jul 26 04:31:50 PM PDT 24 30373393 ps
T68 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3102943111 Jul 26 04:31:50 PM PDT 24 Jul 26 04:31:51 PM PDT 24 24476619 ps
T69 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2861191622 Jul 26 04:31:56 PM PDT 24 Jul 26 04:31:56 PM PDT 24 24977929 ps
T70 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1097747186 Jul 26 04:32:08 PM PDT 24 Jul 26 04:32:08 PM PDT 24 27693611 ps
T71 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2541709705 Jul 26 04:31:42 PM PDT 24 Jul 26 04:31:43 PM PDT 24 27234507 ps
T72 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.978191483 Jul 26 04:31:47 PM PDT 24 Jul 26 04:31:48 PM PDT 24 27645189 ps
T73 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2370450955 Jul 26 04:32:09 PM PDT 24 Jul 26 04:32:09 PM PDT 24 27708098 ps
T74 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3998834074 Jul 26 04:32:11 PM PDT 24 Jul 26 04:32:12 PM PDT 24 29733077 ps
T75 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3025085700 Jul 26 04:31:38 PM PDT 24 Jul 26 04:31:39 PM PDT 24 25961877 ps
T76 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3603655301 Jul 26 04:31:40 PM PDT 24 Jul 26 04:31:40 PM PDT 24 27504633 ps
T77 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.598333638 Jul 26 04:31:48 PM PDT 24 Jul 26 04:31:48 PM PDT 24 27569906 ps
T78 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1807988477 Jul 26 04:32:18 PM PDT 24 Jul 26 04:32:19 PM PDT 24 28571219 ps
T79 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1528270971 Jul 26 04:31:52 PM PDT 24 Jul 26 04:31:52 PM PDT 24 28055011 ps

Test location /workspace/coverage/default/1.prim_async_alert.1467788719
Short name T8
Test name
Test status
Simulation time 11986683 ps
CPU time 0.37 seconds
Started Jul 26 04:28:17 PM PDT 24
Finished Jul 26 04:28:17 PM PDT 24
Peak memory 145600 kb
Host smart-0cde7042-82d3-4496-a841-28b47895c825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467788719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1467788719
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.525167007
Short name T22
Test name
Test status
Simulation time 9780289 ps
CPU time 0.37 seconds
Started Jul 26 05:32:40 PM PDT 24
Finished Jul 26 05:32:40 PM PDT 24
Peak memory 145572 kb
Host smart-42990398-f625-41fe-af8a-bbe9bf2dfc7b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=525167007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.525167007
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2080750960
Short name T39
Test name
Test status
Simulation time 28987730 ps
CPU time 0.4 seconds
Started Jul 26 04:28:45 PM PDT 24
Finished Jul 26 04:28:45 PM PDT 24
Peak memory 145132 kb
Host smart-763c0f5f-7e9f-46b3-877c-e26301a92520
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2080750960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2080750960
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3620144553
Short name T13
Test name
Test status
Simulation time 12874244 ps
CPU time 0.39 seconds
Started Jul 26 04:28:15 PM PDT 24
Finished Jul 26 04:28:15 PM PDT 24
Peak memory 145636 kb
Host smart-d0914f9d-1828-4758-a19f-43fa78e24b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620144553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3620144553
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1850638497
Short name T4
Test name
Test status
Simulation time 29399775 ps
CPU time 0.47 seconds
Started Jul 26 04:28:39 PM PDT 24
Finished Jul 26 04:28:40 PM PDT 24
Peak memory 145048 kb
Host smart-a79e4159-bc3e-415f-881e-bb3b7f94d4cf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1850638497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1850638497
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2869479527
Short name T10
Test name
Test status
Simulation time 9669677 ps
CPU time 0.38 seconds
Started Jul 26 05:32:31 PM PDT 24
Finished Jul 26 05:32:31 PM PDT 24
Peak memory 145552 kb
Host smart-3fdb715c-11a1-4a76-89cf-a087c90f2837
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2869479527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2869479527
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2129300256
Short name T17
Test name
Test status
Simulation time 10084854 ps
CPU time 0.38 seconds
Started Jul 26 04:28:15 PM PDT 24
Finished Jul 26 04:28:16 PM PDT 24
Peak memory 145604 kb
Host smart-bdef7ab1-a7f6-4a32-85fc-0423d7eeb155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129300256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2129300256
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.940731531
Short name T49
Test name
Test status
Simulation time 12176205 ps
CPU time 0.39 seconds
Started Jul 26 04:28:38 PM PDT 24
Finished Jul 26 04:28:38 PM PDT 24
Peak memory 145772 kb
Host smart-d01011aa-8394-4a38-828a-9ecc1ed60a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940731531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.940731531
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1377844353
Short name T48
Test name
Test status
Simulation time 11111732 ps
CPU time 0.42 seconds
Started Jul 26 04:28:30 PM PDT 24
Finished Jul 26 04:28:31 PM PDT 24
Peak memory 145628 kb
Host smart-772a3def-86e5-4ab3-bffc-d667990e156d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377844353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1377844353
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2067609646
Short name T18
Test name
Test status
Simulation time 11059041 ps
CPU time 0.38 seconds
Started Jul 26 04:28:27 PM PDT 24
Finished Jul 26 04:28:27 PM PDT 24
Peak memory 145612 kb
Host smart-1791438f-6a3b-49f8-97c2-44447eb1c759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067609646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2067609646
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2586878504
Short name T12
Test name
Test status
Simulation time 12176048 ps
CPU time 0.39 seconds
Started Jul 26 04:28:37 PM PDT 24
Finished Jul 26 04:28:37 PM PDT 24
Peak memory 145668 kb
Host smart-7316e1b7-4897-4c6c-a6a9-ae291e7c5360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586878504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2586878504
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2135784986
Short name T2
Test name
Test status
Simulation time 10897654 ps
CPU time 0.37 seconds
Started Jul 26 04:28:38 PM PDT 24
Finished Jul 26 04:28:39 PM PDT 24
Peak memory 145608 kb
Host smart-eb8dc180-2ed1-49be-9e80-5ec8771e5b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135784986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2135784986
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.994353691
Short name T7
Test name
Test status
Simulation time 10138015 ps
CPU time 0.38 seconds
Started Jul 26 04:28:39 PM PDT 24
Finished Jul 26 04:28:40 PM PDT 24
Peak memory 145600 kb
Host smart-4a8cbb3c-6464-48bf-bf6c-18bcd942417e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994353691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.994353691
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2285000615
Short name T45
Test name
Test status
Simulation time 11262862 ps
CPU time 0.39 seconds
Started Jul 26 04:28:44 PM PDT 24
Finished Jul 26 04:28:44 PM PDT 24
Peak memory 145612 kb
Host smart-7811a3d1-9582-4882-9552-6977215b0e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285000615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2285000615
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2797420500
Short name T47
Test name
Test status
Simulation time 11477914 ps
CPU time 0.38 seconds
Started Jul 26 04:28:38 PM PDT 24
Finished Jul 26 04:28:39 PM PDT 24
Peak memory 145628 kb
Host smart-433e6324-cb4c-4cfe-a579-eed86f32bac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797420500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2797420500
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.4215015543
Short name T3
Test name
Test status
Simulation time 10398197 ps
CPU time 0.38 seconds
Started Jul 26 04:28:38 PM PDT 24
Finished Jul 26 04:28:39 PM PDT 24
Peak memory 145568 kb
Host smart-9bd84396-0bc0-48f9-b4fd-323ec5473cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215015543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.4215015543
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.543281792
Short name T50
Test name
Test status
Simulation time 10875146 ps
CPU time 0.39 seconds
Started Jul 26 04:28:24 PM PDT 24
Finished Jul 26 04:28:25 PM PDT 24
Peak memory 145632 kb
Host smart-d67f8da9-e47e-4384-8634-b2a67d341097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543281792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.543281792
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3909016998
Short name T46
Test name
Test status
Simulation time 11707075 ps
CPU time 0.39 seconds
Started Jul 26 04:28:13 PM PDT 24
Finished Jul 26 04:28:14 PM PDT 24
Peak memory 145600 kb
Host smart-8248e32f-4c7f-40db-9ec2-d37882be402e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909016998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3909016998
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2931853094
Short name T6
Test name
Test status
Simulation time 11843070 ps
CPU time 0.37 seconds
Started Jul 26 04:28:16 PM PDT 24
Finished Jul 26 04:28:17 PM PDT 24
Peak memory 145632 kb
Host smart-644db7eb-12c1-4eef-8142-fced7e1d299a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931853094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2931853094
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3515408266
Short name T9
Test name
Test status
Simulation time 12100421 ps
CPU time 0.38 seconds
Started Jul 26 04:28:24 PM PDT 24
Finished Jul 26 04:28:24 PM PDT 24
Peak memory 145652 kb
Host smart-ca5cc8ee-506f-4175-bbd1-0556fd3ca8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515408266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3515408266
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.204083294
Short name T16
Test name
Test status
Simulation time 10232286 ps
CPU time 0.39 seconds
Started Jul 26 04:28:24 PM PDT 24
Finished Jul 26 04:28:24 PM PDT 24
Peak memory 145576 kb
Host smart-5e45fa5c-46cf-4b7d-a096-46c360822a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204083294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.204083294
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2563394466
Short name T5
Test name
Test status
Simulation time 10500420 ps
CPU time 0.4 seconds
Started Jul 26 04:28:15 PM PDT 24
Finished Jul 26 04:28:16 PM PDT 24
Peak memory 145608 kb
Host smart-01331731-c05f-4443-b5b9-b7c9e6271c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563394466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2563394466
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.199166769
Short name T19
Test name
Test status
Simulation time 11364722 ps
CPU time 0.38 seconds
Started Jul 26 04:28:26 PM PDT 24
Finished Jul 26 04:28:27 PM PDT 24
Peak memory 145620 kb
Host smart-419f0ab8-2526-469e-b053-62c702668aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199166769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.199166769
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3159344668
Short name T1
Test name
Test status
Simulation time 10922509 ps
CPU time 0.37 seconds
Started Jul 26 04:28:15 PM PDT 24
Finished Jul 26 04:28:16 PM PDT 24
Peak memory 145604 kb
Host smart-59633f6c-0465-426d-bc4d-d03c724ec8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159344668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3159344668
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1335990861
Short name T57
Test name
Test status
Simulation time 30165710 ps
CPU time 0.4 seconds
Started Jul 26 04:28:34 PM PDT 24
Finished Jul 26 04:28:35 PM PDT 24
Peak memory 145172 kb
Host smart-f3277abd-b44d-4b11-bac2-2051257f54a0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1335990861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1335990861
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2987138060
Short name T55
Test name
Test status
Simulation time 29835060 ps
CPU time 0.4 seconds
Started Jul 26 04:28:27 PM PDT 24
Finished Jul 26 04:28:28 PM PDT 24
Peak memory 145192 kb
Host smart-db0205e6-0bed-423d-8f61-cd3a403daf4f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2987138060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2987138060
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.847428403
Short name T41
Test name
Test status
Simulation time 30849699 ps
CPU time 0.41 seconds
Started Jul 26 04:28:23 PM PDT 24
Finished Jul 26 04:28:24 PM PDT 24
Peak memory 145140 kb
Host smart-a114bd4a-a701-4e93-848f-306652ad3078
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=847428403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.847428403
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2817230864
Short name T43
Test name
Test status
Simulation time 27965236 ps
CPU time 0.41 seconds
Started Jul 26 04:28:40 PM PDT 24
Finished Jul 26 04:28:41 PM PDT 24
Peak memory 145308 kb
Host smart-69bb9415-68fb-4cab-abe9-3e302ca380be
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2817230864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2817230864
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1689140845
Short name T40
Test name
Test status
Simulation time 28976416 ps
CPU time 0.42 seconds
Started Jul 26 04:28:43 PM PDT 24
Finished Jul 26 04:28:44 PM PDT 24
Peak memory 145164 kb
Host smart-f8075429-3445-4304-ba94-c05d58aff85a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1689140845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1689140845
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.879980005
Short name T15
Test name
Test status
Simulation time 30170110 ps
CPU time 0.4 seconds
Started Jul 26 04:28:32 PM PDT 24
Finished Jul 26 04:28:33 PM PDT 24
Peak memory 145180 kb
Host smart-abbf901d-0741-4c95-9390-82a5b2d349a6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=879980005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.879980005
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4156959733
Short name T38
Test name
Test status
Simulation time 29353769 ps
CPU time 0.39 seconds
Started Jul 26 04:28:31 PM PDT 24
Finished Jul 26 04:28:32 PM PDT 24
Peak memory 145068 kb
Host smart-dae585e3-98b9-470d-9a51-1cebb5fea949
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4156959733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.4156959733
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.616112711
Short name T37
Test name
Test status
Simulation time 28451194 ps
CPU time 0.39 seconds
Started Jul 26 04:28:30 PM PDT 24
Finished Jul 26 04:28:30 PM PDT 24
Peak memory 145160 kb
Host smart-fcd14e13-6ec3-4585-b3b9-17313348cfcf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=616112711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.616112711
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1417430670
Short name T20
Test name
Test status
Simulation time 32584780 ps
CPU time 0.4 seconds
Started Jul 26 04:28:27 PM PDT 24
Finished Jul 26 04:28:27 PM PDT 24
Peak memory 145156 kb
Host smart-87823d83-58ea-4127-8cbf-ca96cc504e05
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1417430670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1417430670
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3654109092
Short name T42
Test name
Test status
Simulation time 32797941 ps
CPU time 0.41 seconds
Started Jul 26 04:28:41 PM PDT 24
Finished Jul 26 04:28:41 PM PDT 24
Peak memory 145180 kb
Host smart-34814003-3195-4c0a-ab3f-3c7e13cf5390
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3654109092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3654109092
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1507939406
Short name T53
Test name
Test status
Simulation time 30346924 ps
CPU time 0.39 seconds
Started Jul 26 04:28:32 PM PDT 24
Finished Jul 26 04:28:33 PM PDT 24
Peak memory 145148 kb
Host smart-32f287f6-f6b8-4202-9032-c387e46a06d5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1507939406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1507939406
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1053118777
Short name T51
Test name
Test status
Simulation time 29287402 ps
CPU time 0.41 seconds
Started Jul 26 04:28:36 PM PDT 24
Finished Jul 26 04:28:36 PM PDT 24
Peak memory 145136 kb
Host smart-75b4588a-caba-4986-8a72-8562dd35988a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1053118777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1053118777
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3654635081
Short name T14
Test name
Test status
Simulation time 32279946 ps
CPU time 0.4 seconds
Started Jul 26 04:28:27 PM PDT 24
Finished Jul 26 04:28:28 PM PDT 24
Peak memory 145172 kb
Host smart-3a80851f-f9ba-439d-938d-701750803b05
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3654635081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3654635081
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3328410026
Short name T44
Test name
Test status
Simulation time 29600232 ps
CPU time 0.4 seconds
Started Jul 26 04:28:25 PM PDT 24
Finished Jul 26 04:28:26 PM PDT 24
Peak memory 145196 kb
Host smart-3ef64f46-ead9-4694-891d-9c52bef0b346
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3328410026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3328410026
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2952360748
Short name T52
Test name
Test status
Simulation time 29550311 ps
CPU time 0.38 seconds
Started Jul 26 04:28:29 PM PDT 24
Finished Jul 26 04:28:29 PM PDT 24
Peak memory 145192 kb
Host smart-9dd374ec-090c-4bc1-8707-d9874ef66fc7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2952360748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2952360748
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3100091635
Short name T54
Test name
Test status
Simulation time 31090112 ps
CPU time 0.46 seconds
Started Jul 26 04:28:37 PM PDT 24
Finished Jul 26 04:28:38 PM PDT 24
Peak memory 145156 kb
Host smart-91abf8a3-b69b-4985-b78b-20a0110047fb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3100091635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3100091635
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3615010124
Short name T56
Test name
Test status
Simulation time 30028355 ps
CPU time 0.4 seconds
Started Jul 26 04:28:38 PM PDT 24
Finished Jul 26 04:28:39 PM PDT 24
Peak memory 145160 kb
Host smart-b90840ba-5097-4f63-97f5-bdbb67f95e2d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3615010124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3615010124
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2680466945
Short name T23
Test name
Test status
Simulation time 10009981 ps
CPU time 0.37 seconds
Started Jul 26 05:32:25 PM PDT 24
Finished Jul 26 05:32:25 PM PDT 24
Peak memory 145448 kb
Host smart-53f94f6c-aa0a-4970-87f2-9ae23bb4c33d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2680466945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2680466945
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1985626456
Short name T31
Test name
Test status
Simulation time 8844530 ps
CPU time 0.38 seconds
Started Jul 26 05:32:36 PM PDT 24
Finished Jul 26 05:32:37 PM PDT 24
Peak memory 145536 kb
Host smart-ad96fd5e-18b1-4357-ab48-cabef56f2a57
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1985626456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1985626456
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1034740991
Short name T36
Test name
Test status
Simulation time 9377996 ps
CPU time 0.38 seconds
Started Jul 26 05:32:34 PM PDT 24
Finished Jul 26 05:32:35 PM PDT 24
Peak memory 145556 kb
Host smart-f621185e-1236-4b70-8d21-40696e6c805b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1034740991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1034740991
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3391227109
Short name T35
Test name
Test status
Simulation time 9576432 ps
CPU time 0.36 seconds
Started Jul 26 05:32:30 PM PDT 24
Finished Jul 26 05:32:30 PM PDT 24
Peak memory 145608 kb
Host smart-abc4ced2-cc47-48a6-88c5-e9afacf4600f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3391227109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3391227109
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1746037857
Short name T60
Test name
Test status
Simulation time 9950633 ps
CPU time 0.38 seconds
Started Jul 26 05:32:32 PM PDT 24
Finished Jul 26 05:32:33 PM PDT 24
Peak memory 145572 kb
Host smart-e3c30cc0-913a-49aa-9054-e30a2fea11dd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1746037857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1746037857
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.1163695528
Short name T32
Test name
Test status
Simulation time 9130863 ps
CPU time 0.38 seconds
Started Jul 26 05:32:30 PM PDT 24
Finished Jul 26 05:32:30 PM PDT 24
Peak memory 145608 kb
Host smart-6b9a1224-94f1-473e-9f30-387d2431e43d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1163695528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1163695528
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.4203687829
Short name T25
Test name
Test status
Simulation time 8965660 ps
CPU time 0.4 seconds
Started Jul 26 05:32:40 PM PDT 24
Finished Jul 26 05:32:40 PM PDT 24
Peak memory 145556 kb
Host smart-8a5cb61a-2f23-4c53-bd38-9c1271f5107b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4203687829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.4203687829
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.4263671771
Short name T21
Test name
Test status
Simulation time 8956879 ps
CPU time 0.38 seconds
Started Jul 26 05:32:35 PM PDT 24
Finished Jul 26 05:32:35 PM PDT 24
Peak memory 145556 kb
Host smart-9f05ec02-3dcb-45aa-b621-5ec57205adb9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4263671771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.4263671771
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3502212223
Short name T30
Test name
Test status
Simulation time 9322143 ps
CPU time 0.39 seconds
Started Jul 26 05:32:32 PM PDT 24
Finished Jul 26 05:32:33 PM PDT 24
Peak memory 145552 kb
Host smart-da353855-edda-4621-92b3-d805cf11521e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3502212223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3502212223
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2326049323
Short name T24
Test name
Test status
Simulation time 9342969 ps
CPU time 0.38 seconds
Started Jul 26 05:32:29 PM PDT 24
Finished Jul 26 05:32:29 PM PDT 24
Peak memory 145592 kb
Host smart-4f696ffb-215c-4c2a-bad8-4be24a58d67e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2326049323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2326049323
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1376524454
Short name T59
Test name
Test status
Simulation time 10627666 ps
CPU time 0.37 seconds
Started Jul 26 05:32:31 PM PDT 24
Finished Jul 26 05:32:31 PM PDT 24
Peak memory 145560 kb
Host smart-67f9f43e-06fc-4cd1-8365-b2b49e31b3cc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1376524454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1376524454
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1871557612
Short name T61
Test name
Test status
Simulation time 8495819 ps
CPU time 0.39 seconds
Started Jul 26 05:32:31 PM PDT 24
Finished Jul 26 05:32:32 PM PDT 24
Peak memory 145560 kb
Host smart-34f72c06-8da1-4f5a-b4b8-4064263786a7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1871557612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1871557612
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.20981079
Short name T63
Test name
Test status
Simulation time 8966073 ps
CPU time 0.38 seconds
Started Jul 26 05:32:30 PM PDT 24
Finished Jul 26 05:32:30 PM PDT 24
Peak memory 145560 kb
Host smart-2e42acf9-e3de-43c0-aaa2-6f2306997b0f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=20981079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.20981079
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3279279966
Short name T26
Test name
Test status
Simulation time 8878704 ps
CPU time 0.37 seconds
Started Jul 26 05:32:29 PM PDT 24
Finished Jul 26 05:32:30 PM PDT 24
Peak memory 145568 kb
Host smart-dad5bd1d-0431-46f9-b417-2e492e806f35
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3279279966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3279279966
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.136572258
Short name T33
Test name
Test status
Simulation time 8365027 ps
CPU time 0.38 seconds
Started Jul 26 05:32:36 PM PDT 24
Finished Jul 26 05:32:37 PM PDT 24
Peak memory 145516 kb
Host smart-8b54563e-2556-4830-a5b8-43571c1678bd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=136572258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.136572258
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1372188442
Short name T62
Test name
Test status
Simulation time 8855228 ps
CPU time 0.39 seconds
Started Jul 26 05:32:36 PM PDT 24
Finished Jul 26 05:32:37 PM PDT 24
Peak memory 145516 kb
Host smart-fb8ef173-8e48-4140-af1a-0e9aae971f7a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1372188442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1372188442
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.553851984
Short name T58
Test name
Test status
Simulation time 9121350 ps
CPU time 0.39 seconds
Started Jul 26 05:32:28 PM PDT 24
Finished Jul 26 05:32:28 PM PDT 24
Peak memory 145560 kb
Host smart-a6be8a16-c486-4992-8846-d1d5816bca95
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=553851984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.553851984
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3540515066
Short name T34
Test name
Test status
Simulation time 9591436 ps
CPU time 0.41 seconds
Started Jul 26 05:32:27 PM PDT 24
Finished Jul 26 05:32:28 PM PDT 24
Peak memory 145572 kb
Host smart-bec7e0f8-a92f-4b54-a63b-add92b0082d3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3540515066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3540515066
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1807988477
Short name T78
Test name
Test status
Simulation time 28571219 ps
CPU time 0.4 seconds
Started Jul 26 04:32:18 PM PDT 24
Finished Jul 26 04:32:19 PM PDT 24
Peak memory 145216 kb
Host smart-34af931e-440f-4a96-9a07-efc2e6c5c2e7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1807988477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1807988477
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1528270971
Short name T79
Test name
Test status
Simulation time 28055011 ps
CPU time 0.37 seconds
Started Jul 26 04:31:52 PM PDT 24
Finished Jul 26 04:31:52 PM PDT 24
Peak memory 145216 kb
Host smart-0f952d9e-570e-47ad-bb6f-88e17f14f1bc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1528270971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1528270971
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2861191622
Short name T69
Test name
Test status
Simulation time 24977929 ps
CPU time 0.39 seconds
Started Jul 26 04:31:56 PM PDT 24
Finished Jul 26 04:31:56 PM PDT 24
Peak memory 145420 kb
Host smart-3172227a-9556-4b98-8067-a54f14554037
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2861191622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2861191622
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1097747186
Short name T70
Test name
Test status
Simulation time 27693611 ps
CPU time 0.42 seconds
Started Jul 26 04:32:08 PM PDT 24
Finished Jul 26 04:32:08 PM PDT 24
Peak memory 145432 kb
Host smart-d1f5f28c-67ef-4344-9fa7-51bcd7a79e24
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1097747186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1097747186
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.978191483
Short name T72
Test name
Test status
Simulation time 27645189 ps
CPU time 0.39 seconds
Started Jul 26 04:31:47 PM PDT 24
Finished Jul 26 04:31:48 PM PDT 24
Peak memory 145436 kb
Host smart-3339ab3d-f757-4c7d-bd2b-74f22863b41b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=978191483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.978191483
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3943916941
Short name T27
Test name
Test status
Simulation time 27289951 ps
CPU time 0.39 seconds
Started Jul 26 04:31:45 PM PDT 24
Finished Jul 26 04:31:51 PM PDT 24
Peak memory 145440 kb
Host smart-613ceec2-15a0-4f26-a9ee-94ef4a30c49d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3943916941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3943916941
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3751812747
Short name T11
Test name
Test status
Simulation time 28594343 ps
CPU time 0.42 seconds
Started Jul 26 04:31:51 PM PDT 24
Finished Jul 26 04:31:51 PM PDT 24
Peak memory 145452 kb
Host smart-a1b9f8c3-30ed-43db-9024-c9de07064f95
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3751812747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3751812747
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2462388297
Short name T64
Test name
Test status
Simulation time 27349258 ps
CPU time 0.39 seconds
Started Jul 26 04:31:56 PM PDT 24
Finished Jul 26 04:31:56 PM PDT 24
Peak memory 145456 kb
Host smart-3bc29fe0-6113-42a1-8d2a-623d383e2651
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2462388297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2462388297
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2677404063
Short name T28
Test name
Test status
Simulation time 27669904 ps
CPU time 0.4 seconds
Started Jul 26 04:31:53 PM PDT 24
Finished Jul 26 04:31:54 PM PDT 24
Peak memory 145436 kb
Host smart-4bfefcdd-8f9a-4602-b6f1-89f822726df4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2677404063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2677404063
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3998834074
Short name T74
Test name
Test status
Simulation time 29733077 ps
CPU time 0.39 seconds
Started Jul 26 04:32:11 PM PDT 24
Finished Jul 26 04:32:12 PM PDT 24
Peak memory 145376 kb
Host smart-b1ba8557-11c8-4317-803c-4a355e76b365
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3998834074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3998834074
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2370450955
Short name T73
Test name
Test status
Simulation time 27708098 ps
CPU time 0.42 seconds
Started Jul 26 04:32:09 PM PDT 24
Finished Jul 26 04:32:09 PM PDT 24
Peak memory 145432 kb
Host smart-0d8dfc99-7552-48cb-bd51-16df22ea051a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2370450955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2370450955
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1899433478
Short name T66
Test name
Test status
Simulation time 26744539 ps
CPU time 0.41 seconds
Started Jul 26 04:31:54 PM PDT 24
Finished Jul 26 04:31:54 PM PDT 24
Peak memory 145664 kb
Host smart-079b9335-f7b9-4c51-b5a4-8b82196638fe
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1899433478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1899433478
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2541709705
Short name T71
Test name
Test status
Simulation time 27234507 ps
CPU time 0.41 seconds
Started Jul 26 04:31:42 PM PDT 24
Finished Jul 26 04:31:43 PM PDT 24
Peak memory 145856 kb
Host smart-849ebc6b-1e59-4506-b2b5-441106dd00cc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2541709705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2541709705
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1965077144
Short name T29
Test name
Test status
Simulation time 26481776 ps
CPU time 0.39 seconds
Started Jul 26 04:32:15 PM PDT 24
Finished Jul 26 04:32:16 PM PDT 24
Peak memory 145208 kb
Host smart-db66fba7-185b-4771-809a-b86b44aee43a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1965077144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1965077144
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1500445628
Short name T67
Test name
Test status
Simulation time 30373393 ps
CPU time 0.38 seconds
Started Jul 26 04:31:49 PM PDT 24
Finished Jul 26 04:31:50 PM PDT 24
Peak memory 145408 kb
Host smart-c5d158a4-e5a5-439d-bb8c-4b5b3d92961c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1500445628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1500445628
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.598333638
Short name T77
Test name
Test status
Simulation time 27569906 ps
CPU time 0.38 seconds
Started Jul 26 04:31:48 PM PDT 24
Finished Jul 26 04:31:48 PM PDT 24
Peak memory 145424 kb
Host smart-4ca09a83-8cd8-4c32-b380-1ff2c5adfa82
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=598333638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.598333638
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3025085700
Short name T75
Test name
Test status
Simulation time 25961877 ps
CPU time 0.38 seconds
Started Jul 26 04:31:38 PM PDT 24
Finished Jul 26 04:31:39 PM PDT 24
Peak memory 145500 kb
Host smart-93bc2882-0ea3-4070-b022-55b17c7334db
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3025085700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3025085700
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3603655301
Short name T76
Test name
Test status
Simulation time 27504633 ps
CPU time 0.39 seconds
Started Jul 26 04:31:40 PM PDT 24
Finished Jul 26 04:31:40 PM PDT 24
Peak memory 145436 kb
Host smart-827acf5c-d1a1-4f73-9431-7badc501d77d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3603655301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3603655301
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3683446132
Short name T65
Test name
Test status
Simulation time 27404426 ps
CPU time 0.39 seconds
Started Jul 26 04:32:05 PM PDT 24
Finished Jul 26 04:32:05 PM PDT 24
Peak memory 145420 kb
Host smart-8bae2378-1a94-440e-a907-5b9035e36ce0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3683446132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3683446132
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3102943111
Short name T68
Test name
Test status
Simulation time 24476619 ps
CPU time 0.39 seconds
Started Jul 26 04:31:50 PM PDT 24
Finished Jul 26 04:31:51 PM PDT 24
Peak memory 145424 kb
Host smart-cec47932-5a5a-4916-821a-ef68444c4234
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3102943111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3102943111
Directory /workspace/9.prim_sync_fatal_alert/latest
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