| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.92 | 88.92 | 100.00 | 100.00 | 91.67 | 91.67 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/13.prim_async_alert.396654533 |
| 92.39 | 3.48 | 100.00 | 0.00 | 93.75 | 2.08 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/9.prim_sync_alert.3606375572 |
| 94.25 | 1.86 | 100.00 | 0.00 | 97.92 | 4.17 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3579599272 |
| 94.85 | 0.60 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/2.prim_async_alert.2057159678 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.100577237 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.1022895010 |
| /workspace/coverage/default/1.prim_async_alert.1731552043 |
| /workspace/coverage/default/10.prim_async_alert.872127105 |
| /workspace/coverage/default/11.prim_async_alert.3497051190 |
| /workspace/coverage/default/12.prim_async_alert.2621703756 |
| /workspace/coverage/default/14.prim_async_alert.2046845395 |
| /workspace/coverage/default/15.prim_async_alert.311682722 |
| /workspace/coverage/default/16.prim_async_alert.2268597897 |
| /workspace/coverage/default/17.prim_async_alert.1522162782 |
| /workspace/coverage/default/18.prim_async_alert.3284545913 |
| /workspace/coverage/default/19.prim_async_alert.2514643823 |
| /workspace/coverage/default/3.prim_async_alert.1880023158 |
| /workspace/coverage/default/4.prim_async_alert.981828971 |
| /workspace/coverage/default/5.prim_async_alert.1842515039 |
| /workspace/coverage/default/6.prim_async_alert.831668947 |
| /workspace/coverage/default/7.prim_async_alert.96605932 |
| /workspace/coverage/default/8.prim_async_alert.1956556290 |
| /workspace/coverage/default/9.prim_async_alert.2231087992 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2198370757 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2137502133 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2645284294 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4073991434 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3245931164 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.602172659 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3625377665 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1567828234 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3117722592 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3077853971 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1310515653 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1032100374 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2968083674 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3383483014 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.494015152 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.586915909 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4159992875 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3453161901 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.2920403045 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.3062655920 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3812478962 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.3493449956 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.254364311 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1346047379 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1123639527 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.556961840 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.362977047 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.586545551 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.3469235217 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.2308160357 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2629019179 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.1970245914 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.104863051 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.616960513 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.739324834 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.1386471640 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.935752023 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2406663631 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2668459069 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3653184948 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.559885887 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2283321996 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1634648983 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.431256595 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1308817543 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1881539045 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.983000116 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2112896260 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2142042271 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3436245476 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1917539370 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3136318130 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3214872979 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.805409809 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.76001830 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3346823801 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/2.prim_async_alert.2057159678 | Jul 27 05:42:40 PM PDT 24 | Jul 27 05:42:40 PM PDT 24 | 11295936 ps | ||
| T2 | /workspace/coverage/default/18.prim_async_alert.3284545913 | Jul 27 05:42:54 PM PDT 24 | Jul 27 05:42:55 PM PDT 24 | 11788308 ps | ||
| T3 | /workspace/coverage/default/13.prim_async_alert.396654533 | Jul 27 05:42:33 PM PDT 24 | Jul 27 05:42:34 PM PDT 24 | 12987762 ps | ||
| T13 | /workspace/coverage/default/0.prim_async_alert.1022895010 | Jul 27 05:42:46 PM PDT 24 | Jul 27 05:42:47 PM PDT 24 | 11852353 ps | ||
| T10 | /workspace/coverage/default/11.prim_async_alert.3497051190 | Jul 27 05:42:56 PM PDT 24 | Jul 27 05:42:57 PM PDT 24 | 11439055 ps | ||
| T17 | /workspace/coverage/default/1.prim_async_alert.1731552043 | Jul 27 05:42:40 PM PDT 24 | Jul 27 05:42:40 PM PDT 24 | 11341831 ps | ||
| T7 | /workspace/coverage/default/12.prim_async_alert.2621703756 | Jul 27 05:42:47 PM PDT 24 | Jul 27 05:42:48 PM PDT 24 | 10761061 ps | ||
| T16 | /workspace/coverage/default/3.prim_async_alert.1880023158 | Jul 27 05:42:35 PM PDT 24 | Jul 27 05:42:35 PM PDT 24 | 10086973 ps | ||
| T18 | /workspace/coverage/default/6.prim_async_alert.831668947 | Jul 27 05:42:34 PM PDT 24 | Jul 27 05:42:35 PM PDT 24 | 11448544 ps | ||
| T14 | /workspace/coverage/default/15.prim_async_alert.311682722 | Jul 27 05:42:32 PM PDT 24 | Jul 27 05:42:32 PM PDT 24 | 11361976 ps | ||
| T8 | /workspace/coverage/default/14.prim_async_alert.2046845395 | Jul 27 05:42:42 PM PDT 24 | Jul 27 05:42:42 PM PDT 24 | 11048237 ps | ||
| T19 | /workspace/coverage/default/7.prim_async_alert.96605932 | Jul 27 05:42:52 PM PDT 24 | Jul 27 05:42:53 PM PDT 24 | 11255317 ps | ||
| T9 | /workspace/coverage/default/9.prim_async_alert.2231087992 | Jul 27 05:42:32 PM PDT 24 | Jul 27 05:42:33 PM PDT 24 | 10801982 ps | ||
| T20 | /workspace/coverage/default/4.prim_async_alert.981828971 | Jul 27 05:42:31 PM PDT 24 | Jul 27 05:42:31 PM PDT 24 | 11510782 ps | ||
| T21 | /workspace/coverage/default/16.prim_async_alert.2268597897 | Jul 27 05:42:32 PM PDT 24 | Jul 27 05:42:33 PM PDT 24 | 11612956 ps | ||
| T41 | /workspace/coverage/default/17.prim_async_alert.1522162782 | Jul 27 05:42:48 PM PDT 24 | Jul 27 05:42:48 PM PDT 24 | 10662139 ps | ||
| T42 | /workspace/coverage/default/19.prim_async_alert.2514643823 | Jul 27 05:42:33 PM PDT 24 | Jul 27 05:42:34 PM PDT 24 | 10615297 ps | ||
| T43 | /workspace/coverage/default/10.prim_async_alert.872127105 | Jul 27 05:42:39 PM PDT 24 | Jul 27 05:42:40 PM PDT 24 | 11019447 ps | ||
| T44 | /workspace/coverage/default/8.prim_async_alert.1956556290 | Jul 27 05:42:48 PM PDT 24 | Jul 27 05:42:48 PM PDT 24 | 11025597 ps | ||
| T45 | /workspace/coverage/default/5.prim_async_alert.1842515039 | Jul 27 05:42:47 PM PDT 24 | Jul 27 05:42:48 PM PDT 24 | 11390020 ps | ||
| T4 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3579599272 | Jul 27 05:45:13 PM PDT 24 | Jul 27 05:45:14 PM PDT 24 | 29607049 ps | ||
| T15 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.602172659 | Jul 27 05:45:15 PM PDT 24 | Jul 27 05:45:15 PM PDT 24 | 30054289 ps | ||
| T35 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1032100374 | Jul 27 05:45:14 PM PDT 24 | Jul 27 05:45:14 PM PDT 24 | 27737666 ps | ||
| T36 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1310515653 | Jul 27 05:45:16 PM PDT 24 | Jul 27 05:45:17 PM PDT 24 | 32643737 ps | ||
| T37 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3453161901 | Jul 27 05:45:17 PM PDT 24 | Jul 27 05:45:17 PM PDT 24 | 28465021 ps | ||
| T38 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1567828234 | Jul 27 05:45:14 PM PDT 24 | Jul 27 05:45:14 PM PDT 24 | 30083362 ps | ||
| T39 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3117722592 | Jul 27 05:45:17 PM PDT 24 | Jul 27 05:45:18 PM PDT 24 | 30771170 ps | ||
| T12 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3245931164 | Jul 27 05:45:18 PM PDT 24 | Jul 27 05:45:18 PM PDT 24 | 33394951 ps | ||
| T5 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4159992875 | Jul 27 05:45:13 PM PDT 24 | Jul 27 05:45:13 PM PDT 24 | 29429266 ps | ||
| T40 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2968083674 | Jul 27 05:45:14 PM PDT 24 | Jul 27 05:45:14 PM PDT 24 | 29601616 ps | ||
| T46 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3383483014 | Jul 27 05:45:13 PM PDT 24 | Jul 27 05:45:14 PM PDT 24 | 31370467 ps | ||
| T47 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.586915909 | Jul 27 05:45:14 PM PDT 24 | Jul 27 05:45:15 PM PDT 24 | 29992106 ps | ||
| T48 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3077853971 | Jul 27 05:45:14 PM PDT 24 | Jul 27 05:45:14 PM PDT 24 | 29979754 ps | ||
| T49 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4073991434 | Jul 27 05:45:18 PM PDT 24 | Jul 27 05:45:18 PM PDT 24 | 31644905 ps | ||
| T50 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2198370757 | Jul 27 05:45:14 PM PDT 24 | Jul 27 05:45:15 PM PDT 24 | 30834895 ps | ||
| T51 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2137502133 | Jul 27 05:45:16 PM PDT 24 | Jul 27 05:45:16 PM PDT 24 | 29085640 ps | ||
| T52 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2645284294 | Jul 27 05:45:14 PM PDT 24 | Jul 27 05:45:15 PM PDT 24 | 31268421 ps | ||
| T53 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3625377665 | Jul 27 05:45:13 PM PDT 24 | Jul 27 05:45:14 PM PDT 24 | 29547886 ps | ||
| T54 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.494015152 | Jul 27 05:45:13 PM PDT 24 | Jul 27 05:45:14 PM PDT 24 | 29201031 ps | ||
| T22 | /workspace/coverage/sync_alert/1.prim_sync_alert.3062655920 | Jul 27 05:45:16 PM PDT 24 | Jul 27 05:45:16 PM PDT 24 | 9286568 ps | ||
| T23 | /workspace/coverage/sync_alert/3.prim_sync_alert.1970245914 | Jul 27 05:45:15 PM PDT 24 | Jul 27 05:45:15 PM PDT 24 | 8875363 ps | ||
| T24 | /workspace/coverage/sync_alert/11.prim_sync_alert.3493449956 | Jul 27 05:45:21 PM PDT 24 | Jul 27 05:45:21 PM PDT 24 | 7914064 ps | ||
| T25 | /workspace/coverage/sync_alert/0.prim_sync_alert.2920403045 | Jul 27 05:45:13 PM PDT 24 | Jul 27 05:45:14 PM PDT 24 | 10055294 ps | ||
| T32 | /workspace/coverage/sync_alert/9.prim_sync_alert.3606375572 | Jul 27 05:45:22 PM PDT 24 | Jul 27 05:45:22 PM PDT 24 | 9474454 ps | ||
| T26 | /workspace/coverage/sync_alert/12.prim_sync_alert.254364311 | Jul 27 05:45:25 PM PDT 24 | Jul 27 05:45:26 PM PDT 24 | 9172845 ps | ||
| T33 | /workspace/coverage/sync_alert/17.prim_sync_alert.586545551 | Jul 27 05:45:25 PM PDT 24 | Jul 27 05:45:25 PM PDT 24 | 9671969 ps | ||
| T27 | /workspace/coverage/sync_alert/15.prim_sync_alert.556961840 | Jul 27 05:45:22 PM PDT 24 | Jul 27 05:45:23 PM PDT 24 | 10028435 ps | ||
| T34 | /workspace/coverage/sync_alert/6.prim_sync_alert.739324834 | Jul 27 05:45:16 PM PDT 24 | Jul 27 05:45:17 PM PDT 24 | 9455286 ps | ||
| T28 | /workspace/coverage/sync_alert/19.prim_sync_alert.2308160357 | Jul 27 05:45:21 PM PDT 24 | Jul 27 05:45:21 PM PDT 24 | 8865563 ps | ||
| T29 | /workspace/coverage/sync_alert/18.prim_sync_alert.3469235217 | Jul 27 05:45:22 PM PDT 24 | Jul 27 05:45:23 PM PDT 24 | 9465978 ps | ||
| T55 | /workspace/coverage/sync_alert/10.prim_sync_alert.3812478962 | Jul 27 05:45:23 PM PDT 24 | Jul 27 05:45:23 PM PDT 24 | 9015452 ps | ||
| T56 | /workspace/coverage/sync_alert/13.prim_sync_alert.1346047379 | Jul 27 05:45:22 PM PDT 24 | Jul 27 05:45:23 PM PDT 24 | 8571004 ps | ||
| T30 | /workspace/coverage/sync_alert/16.prim_sync_alert.362977047 | Jul 27 05:45:23 PM PDT 24 | Jul 27 05:45:23 PM PDT 24 | 8970906 ps | ||
| T31 | /workspace/coverage/sync_alert/2.prim_sync_alert.2629019179 | Jul 27 05:45:13 PM PDT 24 | Jul 27 05:45:13 PM PDT 24 | 9640131 ps | ||
| T57 | /workspace/coverage/sync_alert/7.prim_sync_alert.1386471640 | Jul 27 05:45:17 PM PDT 24 | Jul 27 05:45:18 PM PDT 24 | 9263442 ps | ||
| T58 | /workspace/coverage/sync_alert/5.prim_sync_alert.616960513 | Jul 27 05:45:15 PM PDT 24 | Jul 27 05:45:16 PM PDT 24 | 8455187 ps | ||
| T59 | /workspace/coverage/sync_alert/4.prim_sync_alert.104863051 | Jul 27 05:45:16 PM PDT 24 | Jul 27 05:45:16 PM PDT 24 | 9241991 ps | ||
| T60 | /workspace/coverage/sync_alert/8.prim_sync_alert.935752023 | Jul 27 05:45:22 PM PDT 24 | Jul 27 05:45:22 PM PDT 24 | 8775173 ps | ||
| T61 | /workspace/coverage/sync_alert/14.prim_sync_alert.1123639527 | Jul 27 05:45:20 PM PDT 24 | Jul 27 05:45:21 PM PDT 24 | 10137420 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3653184948 | Jul 27 05:45:29 PM PDT 24 | Jul 27 05:45:29 PM PDT 24 | 26957028 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3214872979 | Jul 27 05:45:21 PM PDT 24 | Jul 27 05:45:22 PM PDT 24 | 27280946 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1634648983 | Jul 27 05:45:28 PM PDT 24 | Jul 27 05:45:28 PM PDT 24 | 28235757 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.983000116 | Jul 27 05:45:26 PM PDT 24 | Jul 27 05:45:26 PM PDT 24 | 26866362 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3136318130 | Jul 27 05:45:18 PM PDT 24 | Jul 27 05:45:19 PM PDT 24 | 26164313 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2283321996 | Jul 27 05:45:29 PM PDT 24 | Jul 27 05:45:29 PM PDT 24 | 29410096 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2668459069 | Jul 27 05:45:30 PM PDT 24 | Jul 27 05:45:31 PM PDT 24 | 24646058 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1881539045 | Jul 27 05:45:30 PM PDT 24 | Jul 27 05:45:31 PM PDT 24 | 27411584 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.431256595 | Jul 27 05:45:29 PM PDT 24 | Jul 27 05:45:29 PM PDT 24 | 28520342 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3346823801 | Jul 27 05:45:30 PM PDT 24 | Jul 27 05:45:30 PM PDT 24 | 25848561 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1308817543 | Jul 27 05:45:28 PM PDT 24 | Jul 27 05:45:28 PM PDT 24 | 27188828 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3436245476 | Jul 27 05:45:24 PM PDT 24 | Jul 27 05:45:24 PM PDT 24 | 27430120 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.76001830 | Jul 27 05:45:24 PM PDT 24 | Jul 27 05:45:25 PM PDT 24 | 26222137 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.559885887 | Jul 27 05:45:28 PM PDT 24 | Jul 27 05:45:28 PM PDT 24 | 27582845 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2142042271 | Jul 27 05:45:19 PM PDT 24 | Jul 27 05:45:20 PM PDT 24 | 26290272 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1917539370 | Jul 27 05:45:25 PM PDT 24 | Jul 27 05:45:25 PM PDT 24 | 28465766 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2112896260 | Jul 27 05:45:28 PM PDT 24 | Jul 27 05:45:29 PM PDT 24 | 28905099 ps | ||
| T11 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.100577237 | Jul 27 05:45:24 PM PDT 24 | Jul 27 05:45:24 PM PDT 24 | 28551608 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2406663631 | Jul 27 05:45:20 PM PDT 24 | Jul 27 05:45:21 PM PDT 24 | 26473850 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.805409809 | Jul 27 05:45:22 PM PDT 24 | Jul 27 05:45:23 PM PDT 24 | 28430421 ps |
| Test location | /workspace/coverage/default/13.prim_async_alert.396654533 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12987762 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:42:33 PM PDT 24 |
| Finished | Jul 27 05:42:34 PM PDT 24 |
| Peak memory | 145752 kb |
| Host | smart-d46ff2cd-3a12-4c3b-9c46-bb34ab4bbe73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=396654533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.396654533 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.3606375572 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9474454 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:22 PM PDT 24 |
| Finished | Jul 27 05:45:22 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-878b7a5a-e635-43df-8a4a-b3929ae242bd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3606375572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3606375572 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3579599272 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 29607049 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 05:45:13 PM PDT 24 |
| Finished | Jul 27 05:45:14 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-09afeba6-e88f-43bf-a592-52985d5bd754 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3579599272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3579599272 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.2057159678 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11295936 ps |
| CPU time | 0.37 seconds |
| Started | Jul 27 05:42:40 PM PDT 24 |
| Finished | Jul 27 05:42:40 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-e5ea968e-695c-48e9-8514-c7e6801ec489 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2057159678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2057159678 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.100577237 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 28551608 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:24 PM PDT 24 |
| Finished | Jul 27 05:45:24 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-84d92be8-4d84-4461-a7ff-f9ce7091c617 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=100577237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.100577237 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.1022895010 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11852353 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 05:42:46 PM PDT 24 |
| Finished | Jul 27 05:42:47 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-46b39609-e74f-4d5d-8541-b7d4ce127281 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022895010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1022895010 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1731552043 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11341831 ps |
| CPU time | 0.37 seconds |
| Started | Jul 27 05:42:40 PM PDT 24 |
| Finished | Jul 27 05:42:40 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-e5b51cae-1331-475e-abd0-5451870d8169 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1731552043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1731552043 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.872127105 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11019447 ps |
| CPU time | 0.37 seconds |
| Started | Jul 27 05:42:39 PM PDT 24 |
| Finished | Jul 27 05:42:40 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-fcf52597-04fe-44df-889e-fc4e8516cec8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872127105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.872127105 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.3497051190 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11439055 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:42:56 PM PDT 24 |
| Finished | Jul 27 05:42:57 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-7506d1ff-aff7-4a85-be1c-54d076fb8949 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3497051190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3497051190 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.2621703756 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10761061 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 05:42:47 PM PDT 24 |
| Finished | Jul 27 05:42:48 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-ec515808-16b2-4fb9-942b-027a93ddbd3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2621703756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2621703756 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.2046845395 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11048237 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:42:42 PM PDT 24 |
| Finished | Jul 27 05:42:42 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-69b8012e-c7e8-41cd-ab1d-eee26d8be4a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046845395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2046845395 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.311682722 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11361976 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:42:32 PM PDT 24 |
| Finished | Jul 27 05:42:32 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-8d769f13-8dc6-4bb6-8e0b-6560c5c8cdcc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=311682722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.311682722 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.2268597897 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11612956 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:42:32 PM PDT 24 |
| Finished | Jul 27 05:42:33 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-f169f3f7-e26e-4f03-9733-ed81363539e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2268597897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2268597897 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.1522162782 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10662139 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:42:48 PM PDT 24 |
| Finished | Jul 27 05:42:48 PM PDT 24 |
| Peak memory | 145748 kb |
| Host | smart-c1d52d0e-ee6f-4c82-bd91-e09b0264fe55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1522162782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1522162782 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.3284545913 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11788308 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:42:54 PM PDT 24 |
| Finished | Jul 27 05:42:55 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-e3d479e4-1318-4b4d-b469-13281f9e2ade |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3284545913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3284545913 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.2514643823 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10615297 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:42:33 PM PDT 24 |
| Finished | Jul 27 05:42:34 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-8f7d428c-b4d4-49b5-ae9d-d18e199f83e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2514643823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2514643823 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.1880023158 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10086973 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:42:35 PM PDT 24 |
| Finished | Jul 27 05:42:35 PM PDT 24 |
| Peak memory | 145832 kb |
| Host | smart-d626ad56-2f6b-4dd8-b610-95692f7fd56d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880023158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1880023158 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.981828971 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11510782 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 05:42:31 PM PDT 24 |
| Finished | Jul 27 05:42:31 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-e1c3aa86-646f-42ed-bc7f-2ac50b0bbb70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=981828971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.981828971 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.1842515039 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11390020 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:42:47 PM PDT 24 |
| Finished | Jul 27 05:42:48 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-51fe5ffc-3e97-4ba9-9a56-76cc55a35ad0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842515039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1842515039 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.831668947 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11448544 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:42:34 PM PDT 24 |
| Finished | Jul 27 05:42:35 PM PDT 24 |
| Peak memory | 145748 kb |
| Host | smart-9373512c-0a61-4bac-a65e-bedabcd355a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=831668947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.831668947 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.96605932 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11255317 ps |
| CPU time | 0.37 seconds |
| Started | Jul 27 05:42:52 PM PDT 24 |
| Finished | Jul 27 05:42:53 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-a6a0b1e8-2b4e-442a-8398-3e7571ca7253 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96605932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.96605932 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.1956556290 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11025597 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:42:48 PM PDT 24 |
| Finished | Jul 27 05:42:48 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-f5b2cb32-5993-4a1c-8b3c-79cb3d478b60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1956556290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1956556290 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.2231087992 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10801982 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:42:32 PM PDT 24 |
| Finished | Jul 27 05:42:33 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-b234df7d-75cb-4759-8a14-581401514a01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2231087992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2231087992 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2198370757 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30834895 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 05:45:14 PM PDT 24 |
| Finished | Jul 27 05:45:15 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-56f1b367-ef98-4ca6-87ea-a3247ac80d85 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2198370757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2198370757 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2137502133 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29085640 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 05:45:16 PM PDT 24 |
| Finished | Jul 27 05:45:16 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-f68c9d6b-d3f7-40d9-94b5-6750b619104c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2137502133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2137502133 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2645284294 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 31268421 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:45:14 PM PDT 24 |
| Finished | Jul 27 05:45:15 PM PDT 24 |
| Peak memory | 145260 kb |
| Host | smart-0b1c767d-5dd4-4ce4-a45a-f4d7f9340ca8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2645284294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2645284294 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4073991434 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 31644905 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 05:45:18 PM PDT 24 |
| Finished | Jul 27 05:45:18 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-ba6efb8b-56ba-4d14-b09c-8fb96b93a512 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4073991434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.4073991434 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3245931164 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 33394951 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 05:45:18 PM PDT 24 |
| Finished | Jul 27 05:45:18 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-9f20e756-d1ab-4f38-9d12-d431ba551a99 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3245931164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3245931164 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.602172659 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 30054289 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:15 PM PDT 24 |
| Finished | Jul 27 05:45:15 PM PDT 24 |
| Peak memory | 145308 kb |
| Host | smart-f5d510ec-33e8-4a72-a27d-d8fd5d9a8a76 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=602172659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.602172659 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3625377665 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 29547886 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:13 PM PDT 24 |
| Finished | Jul 27 05:45:14 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-f394ceff-85bf-46ee-8e1a-492fcd0ffd8e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3625377665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3625377665 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1567828234 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 30083362 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:14 PM PDT 24 |
| Finished | Jul 27 05:45:14 PM PDT 24 |
| Peak memory | 145260 kb |
| Host | smart-de7c6d09-624e-464c-969e-2327b4c4a574 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1567828234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1567828234 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3117722592 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 30771170 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:17 PM PDT 24 |
| Finished | Jul 27 05:45:18 PM PDT 24 |
| Peak memory | 145344 kb |
| Host | smart-16d5cf58-d40a-448b-b8e6-11fb2426fa62 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3117722592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3117722592 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3077853971 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 29979754 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 05:45:14 PM PDT 24 |
| Finished | Jul 27 05:45:14 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-4980f1d7-6427-4fa4-a17f-16c7c967c6b3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3077853971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3077853971 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1310515653 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 32643737 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 05:45:16 PM PDT 24 |
| Finished | Jul 27 05:45:17 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-b19669b6-7107-42e7-b7bb-e1f4f5dee47c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1310515653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1310515653 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1032100374 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 27737666 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 05:45:14 PM PDT 24 |
| Finished | Jul 27 05:45:14 PM PDT 24 |
| Peak memory | 145292 kb |
| Host | smart-e916c028-a63e-4bca-99fb-ab889bd74594 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1032100374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1032100374 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2968083674 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29601616 ps |
| CPU time | 0.42 seconds |
| Started | Jul 27 05:45:14 PM PDT 24 |
| Finished | Jul 27 05:45:14 PM PDT 24 |
| Peak memory | 145308 kb |
| Host | smart-0ce874d5-2f48-4840-acc0-825901b66c49 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2968083674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2968083674 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3383483014 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 31370467 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 05:45:13 PM PDT 24 |
| Finished | Jul 27 05:45:14 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-a8d25ae0-af59-4209-ae27-69d5ce6513c5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3383483014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3383483014 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.494015152 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 29201031 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:13 PM PDT 24 |
| Finished | Jul 27 05:45:14 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-9d23bc94-78a0-4842-b4fb-cc6be5f0e226 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=494015152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.494015152 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.586915909 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 29992106 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:45:14 PM PDT 24 |
| Finished | Jul 27 05:45:15 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-802c5e28-9adf-4152-8890-7fb53d848c9e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=586915909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.586915909 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4159992875 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 29429266 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:13 PM PDT 24 |
| Finished | Jul 27 05:45:13 PM PDT 24 |
| Peak memory | 145240 kb |
| Host | smart-de7ecfe3-3ad1-41e6-827c-37fb0091c827 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4159992875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.4159992875 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3453161901 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 28465021 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 05:45:17 PM PDT 24 |
| Finished | Jul 27 05:45:17 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-7408957f-0c62-4f85-8c4d-3d384e95445f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3453161901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3453161901 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.2920403045 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10055294 ps |
| CPU time | 0.44 seconds |
| Started | Jul 27 05:45:13 PM PDT 24 |
| Finished | Jul 27 05:45:14 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-acb4b2a9-f499-4238-9587-42c8258b081c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2920403045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2920403045 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.3062655920 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9286568 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 05:45:16 PM PDT 24 |
| Finished | Jul 27 05:45:16 PM PDT 24 |
| Peak memory | 145480 kb |
| Host | smart-09a573b8-63be-4306-ad85-aa8e1a4dfcbc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3062655920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3062655920 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3812478962 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 9015452 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 05:45:23 PM PDT 24 |
| Finished | Jul 27 05:45:23 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-2c903579-2f4a-496a-813e-ace693b56c10 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3812478962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3812478962 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.3493449956 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7914064 ps |
| CPU time | 0.37 seconds |
| Started | Jul 27 05:45:21 PM PDT 24 |
| Finished | Jul 27 05:45:21 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-a73d6904-8a7c-470a-8c2f-b38c4fcbdce9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3493449956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3493449956 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.254364311 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9172845 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 05:45:25 PM PDT 24 |
| Finished | Jul 27 05:45:26 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-33249e8f-8179-4b35-ad5c-5368e1af933f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=254364311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.254364311 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1346047379 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8571004 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:45:22 PM PDT 24 |
| Finished | Jul 27 05:45:23 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-11017cfe-622a-496d-8116-7fb7ff475449 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1346047379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1346047379 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1123639527 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 10137420 ps |
| CPU time | 0.37 seconds |
| Started | Jul 27 05:45:20 PM PDT 24 |
| Finished | Jul 27 05:45:21 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-052b2f28-bc43-4997-bc28-17d10eb745b5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1123639527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1123639527 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.556961840 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10028435 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:45:22 PM PDT 24 |
| Finished | Jul 27 05:45:23 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-8f6e6665-5387-4d53-aa54-0a8ea4670b6e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=556961840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.556961840 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.362977047 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8970906 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:23 PM PDT 24 |
| Finished | Jul 27 05:45:23 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-172fdeaa-63df-4c5d-9850-7443a3190fce |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=362977047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.362977047 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.586545551 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9671969 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:45:25 PM PDT 24 |
| Finished | Jul 27 05:45:25 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-f7992882-76c7-453b-ac2a-b2aef94c5ecf |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=586545551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.586545551 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.3469235217 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9465978 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:45:22 PM PDT 24 |
| Finished | Jul 27 05:45:23 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-2c5715cd-4e89-4dd8-b3b4-5588ef28aa6a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3469235217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3469235217 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.2308160357 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8865563 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 05:45:21 PM PDT 24 |
| Finished | Jul 27 05:45:21 PM PDT 24 |
| Peak memory | 145500 kb |
| Host | smart-14f0cb88-f15b-434e-bb3e-b71b3c94c554 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2308160357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2308160357 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2629019179 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9640131 ps |
| CPU time | 0.37 seconds |
| Started | Jul 27 05:45:13 PM PDT 24 |
| Finished | Jul 27 05:45:13 PM PDT 24 |
| Peak memory | 145536 kb |
| Host | smart-d70d5320-8150-4b97-ae91-fb0ca9272136 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2629019179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2629019179 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.1970245914 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8875363 ps |
| CPU time | 0.36 seconds |
| Started | Jul 27 05:45:15 PM PDT 24 |
| Finished | Jul 27 05:45:15 PM PDT 24 |
| Peak memory | 145500 kb |
| Host | smart-6baeda1a-6f59-41fe-a30c-c014b2f3ae6e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1970245914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1970245914 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.104863051 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9241991 ps |
| CPU time | 0.43 seconds |
| Started | Jul 27 05:45:16 PM PDT 24 |
| Finished | Jul 27 05:45:16 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-b7d8b50b-c75c-4981-9484-39cd03eaa5e2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=104863051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.104863051 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.616960513 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8455187 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:15 PM PDT 24 |
| Finished | Jul 27 05:45:16 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-4e88e6fa-0c17-470f-b6b7-feb036ba6ac2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=616960513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.616960513 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.739324834 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9455286 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 05:45:16 PM PDT 24 |
| Finished | Jul 27 05:45:17 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-9dedd725-a78f-4491-b7b2-5f43ec2d6456 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=739324834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.739324834 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.1386471640 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9263442 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 05:45:17 PM PDT 24 |
| Finished | Jul 27 05:45:18 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-5226f950-277b-444e-abae-6736e11eae5b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1386471640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1386471640 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.935752023 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8775173 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 05:45:22 PM PDT 24 |
| Finished | Jul 27 05:45:22 PM PDT 24 |
| Peak memory | 145536 kb |
| Host | smart-69eaa5d4-2d2a-40a3-9a1e-1d9e8c3e4463 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=935752023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.935752023 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2406663631 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26473850 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 05:45:20 PM PDT 24 |
| Finished | Jul 27 05:45:21 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-16554f2e-d68d-419f-a750-75833b527f2d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2406663631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2406663631 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2668459069 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 24646058 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:45:30 PM PDT 24 |
| Finished | Jul 27 05:45:31 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-b89dceb0-bd9c-4638-8645-f9ada2c686bb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2668459069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2668459069 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3653184948 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 26957028 ps |
| CPU time | 0.45 seconds |
| Started | Jul 27 05:45:29 PM PDT 24 |
| Finished | Jul 27 05:45:29 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-8e2e3478-5b87-4697-b17c-0bbbe12950a1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3653184948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3653184948 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.559885887 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27582845 ps |
| CPU time | 0.45 seconds |
| Started | Jul 27 05:45:28 PM PDT 24 |
| Finished | Jul 27 05:45:28 PM PDT 24 |
| Peak memory | 145536 kb |
| Host | smart-381091c7-decd-48e8-a921-d66c5b85b8b3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=559885887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.559885887 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2283321996 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 29410096 ps |
| CPU time | 0.44 seconds |
| Started | Jul 27 05:45:29 PM PDT 24 |
| Finished | Jul 27 05:45:29 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-4c8233d2-e4e5-4c88-b825-931807339836 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2283321996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2283321996 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1634648983 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 28235757 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 05:45:28 PM PDT 24 |
| Finished | Jul 27 05:45:28 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-dbbec91e-2b7a-43d2-ab14-6e09cad95867 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1634648983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1634648983 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.431256595 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28520342 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:29 PM PDT 24 |
| Finished | Jul 27 05:45:29 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-c2a65835-89ab-4173-a7fc-045bd1769a47 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=431256595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.431256595 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1308817543 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27188828 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:28 PM PDT 24 |
| Finished | Jul 27 05:45:28 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-88cbf992-dfb2-4e58-88d6-43d16a911787 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1308817543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1308817543 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1881539045 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27411584 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:30 PM PDT 24 |
| Finished | Jul 27 05:45:31 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-0ed78e86-8168-4f48-84d0-e51f281a2ef2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1881539045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1881539045 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.983000116 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26866362 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:26 PM PDT 24 |
| Finished | Jul 27 05:45:26 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-37fc8874-6bff-47f0-8e25-365a064b4719 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=983000116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.983000116 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2112896260 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 28905099 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:45:28 PM PDT 24 |
| Finished | Jul 27 05:45:29 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-524cfda0-d1cf-4297-9e1a-52b861696661 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2112896260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2112896260 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2142042271 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26290272 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 05:45:19 PM PDT 24 |
| Finished | Jul 27 05:45:20 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-79054262-1836-422c-bd8d-8df66668531f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2142042271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2142042271 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3436245476 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27430120 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:45:24 PM PDT 24 |
| Finished | Jul 27 05:45:24 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-06bf0849-eb02-400d-8300-3900cda8681d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3436245476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3436245476 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1917539370 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 28465766 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 05:45:25 PM PDT 24 |
| Finished | Jul 27 05:45:25 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-b40fd88b-29f5-4203-9783-be55a0c21647 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1917539370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1917539370 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3136318130 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 26164313 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:45:18 PM PDT 24 |
| Finished | Jul 27 05:45:19 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-dd727ad7-9dc1-4a1c-a042-b00b69689c34 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3136318130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3136318130 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3214872979 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27280946 ps |
| CPU time | 0.45 seconds |
| Started | Jul 27 05:45:21 PM PDT 24 |
| Finished | Jul 27 05:45:22 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-f239543e-b307-4b48-96ae-3f21d9d1b20a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3214872979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3214872979 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.805409809 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 28430421 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:45:22 PM PDT 24 |
| Finished | Jul 27 05:45:23 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-9f46ae4b-085c-4f77-a9b9-491c7eafa6d5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=805409809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.805409809 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.76001830 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26222137 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:45:24 PM PDT 24 |
| Finished | Jul 27 05:45:25 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-c0db0198-0b18-4403-9d4a-5f552b01ebf1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=76001830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.76001830 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3346823801 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 25848561 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 05:45:30 PM PDT 24 |
| Finished | Jul 27 05:45:30 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-18763cc2-88e2-4306-9342-6d0e646d2a08 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3346823801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3346823801 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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