| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.85 | 100.00 | 97.92 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.04 | 88.04 | 100.00 | 100.00 | 95.83 | 95.83 | 96.43 | 96.43 | 75.00 | 75.00 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/15.prim_async_alert.62790352 |
| 91.76 | 3.72 | 100.00 | 0.00 | 95.83 | 0.00 | 96.43 | 0.00 | 85.71 | 10.71 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/13.prim_sync_alert.1992412822 |
| 93.52 | 1.76 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 3.57 | 85.71 | 0.00 | 95.83 | 0.00 | 83.72 | 6.98 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2625844757 |
| 94.11 | 0.60 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 83.72 | 0.00 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4051061255 |
| 94.50 | 0.39 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 2.33 | /workspace/coverage/default/1.prim_async_alert.1535215745 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2515305766 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.1058030045 |
| /workspace/coverage/default/10.prim_async_alert.3577872409 |
| /workspace/coverage/default/11.prim_async_alert.3302833811 |
| /workspace/coverage/default/12.prim_async_alert.2172946654 |
| /workspace/coverage/default/13.prim_async_alert.4031333073 |
| /workspace/coverage/default/14.prim_async_alert.4113345329 |
| /workspace/coverage/default/16.prim_async_alert.3498655376 |
| /workspace/coverage/default/17.prim_async_alert.1611892644 |
| /workspace/coverage/default/18.prim_async_alert.4240119694 |
| /workspace/coverage/default/19.prim_async_alert.655970179 |
| /workspace/coverage/default/2.prim_async_alert.2598930830 |
| /workspace/coverage/default/3.prim_async_alert.2447671827 |
| /workspace/coverage/default/4.prim_async_alert.2753851569 |
| /workspace/coverage/default/5.prim_async_alert.2908492443 |
| /workspace/coverage/default/6.prim_async_alert.2872452358 |
| /workspace/coverage/default/7.prim_async_alert.4275938886 |
| /workspace/coverage/default/8.prim_async_alert.2279502253 |
| /workspace/coverage/default/9.prim_async_alert.796202516 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3481272428 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1477889781 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.143241059 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3501432996 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1531783476 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3608248870 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2148906478 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2268594202 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3641048457 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3149545996 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2798895833 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1604373366 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.48932192 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.854315775 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3651992269 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2737016456 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2824109910 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.764108041 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.2993660111 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.2983646546 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.982584597 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.927538112 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.188931260 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.3958458281 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.1495137798 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.232198874 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.2557992502 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.3322999044 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2777886501 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3775702856 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.3847431889 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.372149505 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.3352125453 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.1377204473 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.3184304708 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.397288110 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.720177359 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3430907099 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1569112143 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.203233360 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1535543955 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1025889892 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4223107903 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3681452054 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1438853367 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1073334096 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1135220220 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3615129542 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2473258248 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1812632707 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1878754339 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3523257501 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3341466316 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.465464229 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.672498362 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.493016627 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_async_alert.2172946654 | Jul 28 04:50:05 PM PDT 24 | Jul 28 04:50:06 PM PDT 24 | 11237136 ps | ||
| T2 | /workspace/coverage/default/15.prim_async_alert.62790352 | Jul 28 04:50:28 PM PDT 24 | Jul 28 04:50:28 PM PDT 24 | 11255559 ps | ||
| T3 | /workspace/coverage/default/11.prim_async_alert.3302833811 | Jul 28 04:50:02 PM PDT 24 | Jul 28 04:50:02 PM PDT 24 | 10965708 ps | ||
| T12 | /workspace/coverage/default/3.prim_async_alert.2447671827 | Jul 28 04:50:13 PM PDT 24 | Jul 28 04:50:13 PM PDT 24 | 10350244 ps | ||
| T14 | /workspace/coverage/default/17.prim_async_alert.1611892644 | Jul 28 04:50:06 PM PDT 24 | Jul 28 04:50:07 PM PDT 24 | 10937219 ps | ||
| T7 | /workspace/coverage/default/9.prim_async_alert.796202516 | Jul 28 04:49:58 PM PDT 24 | Jul 28 04:49:59 PM PDT 24 | 11308807 ps | ||
| T8 | /workspace/coverage/default/14.prim_async_alert.4113345329 | Jul 28 04:50:04 PM PDT 24 | Jul 28 04:50:05 PM PDT 24 | 11144281 ps | ||
| T19 | /workspace/coverage/default/2.prim_async_alert.2598930830 | Jul 28 04:49:56 PM PDT 24 | Jul 28 04:49:57 PM PDT 24 | 10431501 ps | ||
| T20 | /workspace/coverage/default/4.prim_async_alert.2753851569 | Jul 28 04:50:07 PM PDT 24 | Jul 28 04:50:07 PM PDT 24 | 10787864 ps | ||
| T21 | /workspace/coverage/default/18.prim_async_alert.4240119694 | Jul 28 04:50:46 PM PDT 24 | Jul 28 04:50:46 PM PDT 24 | 10628060 ps | ||
| T15 | /workspace/coverage/default/10.prim_async_alert.3577872409 | Jul 28 04:50:02 PM PDT 24 | Jul 28 04:50:03 PM PDT 24 | 11321201 ps | ||
| T45 | /workspace/coverage/default/6.prim_async_alert.2872452358 | Jul 28 04:50:33 PM PDT 24 | Jul 28 04:50:33 PM PDT 24 | 11603995 ps | ||
| T46 | /workspace/coverage/default/7.prim_async_alert.4275938886 | Jul 28 04:50:02 PM PDT 24 | Jul 28 04:50:03 PM PDT 24 | 11525478 ps | ||
| T47 | /workspace/coverage/default/8.prim_async_alert.2279502253 | Jul 28 04:50:08 PM PDT 24 | Jul 28 04:50:09 PM PDT 24 | 11644493 ps | ||
| T22 | /workspace/coverage/default/13.prim_async_alert.4031333073 | Jul 28 04:50:01 PM PDT 24 | Jul 28 04:50:02 PM PDT 24 | 10812166 ps | ||
| T23 | /workspace/coverage/default/19.prim_async_alert.655970179 | Jul 28 04:50:00 PM PDT 24 | Jul 28 04:50:00 PM PDT 24 | 11037582 ps | ||
| T24 | /workspace/coverage/default/1.prim_async_alert.1535215745 | Jul 28 04:50:00 PM PDT 24 | Jul 28 04:50:01 PM PDT 24 | 11326906 ps | ||
| T48 | /workspace/coverage/default/16.prim_async_alert.3498655376 | Jul 28 04:50:08 PM PDT 24 | Jul 28 04:50:08 PM PDT 24 | 11388169 ps | ||
| T49 | /workspace/coverage/default/5.prim_async_alert.2908492443 | Jul 28 04:49:59 PM PDT 24 | Jul 28 04:49:59 PM PDT 24 | 10754720 ps | ||
| T50 | /workspace/coverage/default/0.prim_async_alert.1058030045 | Jul 28 04:49:58 PM PDT 24 | Jul 28 04:49:59 PM PDT 24 | 11532641 ps | ||
| T9 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1477889781 | Jul 28 04:50:04 PM PDT 24 | Jul 28 04:50:05 PM PDT 24 | 30342942 ps | ||
| T10 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3651992269 | Jul 28 04:50:35 PM PDT 24 | Jul 28 04:50:35 PM PDT 24 | 28105072 ps | ||
| T11 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1531783476 | Jul 28 04:49:59 PM PDT 24 | Jul 28 04:49:59 PM PDT 24 | 30818435 ps | ||
| T38 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2798895833 | Jul 28 04:50:00 PM PDT 24 | Jul 28 04:50:00 PM PDT 24 | 32243305 ps | ||
| T39 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.143241059 | Jul 28 04:49:57 PM PDT 24 | Jul 28 04:49:58 PM PDT 24 | 30049310 ps | ||
| T40 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3481272428 | Jul 28 04:50:03 PM PDT 24 | Jul 28 04:50:03 PM PDT 24 | 29154944 ps | ||
| T41 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2268594202 | Jul 28 04:50:10 PM PDT 24 | Jul 28 04:50:10 PM PDT 24 | 29174163 ps | ||
| T42 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1604373366 | Jul 28 04:50:08 PM PDT 24 | Jul 28 04:50:09 PM PDT 24 | 30561169 ps | ||
| T43 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.48932192 | Jul 28 04:50:09 PM PDT 24 | Jul 28 04:50:10 PM PDT 24 | 29012230 ps | ||
| T44 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2625844757 | Jul 28 04:50:02 PM PDT 24 | Jul 28 04:50:02 PM PDT 24 | 29623479 ps | ||
| T51 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3641048457 | Jul 28 04:50:12 PM PDT 24 | Jul 28 04:50:17 PM PDT 24 | 29551141 ps | ||
| T52 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3501432996 | Jul 28 04:50:14 PM PDT 24 | Jul 28 04:50:14 PM PDT 24 | 30844727 ps | ||
| T53 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.854315775 | Jul 28 04:50:02 PM PDT 24 | Jul 28 04:50:02 PM PDT 24 | 28974461 ps | ||
| T13 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4051061255 | Jul 28 04:50:10 PM PDT 24 | Jul 28 04:50:11 PM PDT 24 | 32906777 ps | ||
| T54 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2737016456 | Jul 28 04:50:01 PM PDT 24 | Jul 28 04:50:02 PM PDT 24 | 30552546 ps | ||
| T4 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2515305766 | Jul 28 04:50:04 PM PDT 24 | Jul 28 04:50:04 PM PDT 24 | 31868115 ps | ||
| T55 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3608248870 | Jul 28 04:50:05 PM PDT 24 | Jul 28 04:50:16 PM PDT 24 | 29396705 ps | ||
| T5 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2824109910 | Jul 28 04:50:01 PM PDT 24 | Jul 28 04:50:01 PM PDT 24 | 30872308 ps | ||
| T56 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3149545996 | Jul 28 04:50:48 PM PDT 24 | Jul 28 04:50:49 PM PDT 24 | 30166709 ps | ||
| T57 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2148906478 | Jul 28 04:49:56 PM PDT 24 | Jul 28 04:49:56 PM PDT 24 | 29982726 ps | ||
| T16 | /workspace/coverage/sync_alert/2.prim_sync_alert.2777886501 | Jul 28 04:55:00 PM PDT 24 | Jul 28 04:55:00 PM PDT 24 | 9339103 ps | ||
| T25 | /workspace/coverage/sync_alert/9.prim_sync_alert.397288110 | Jul 28 04:54:41 PM PDT 24 | Jul 28 04:54:42 PM PDT 24 | 9910476 ps | ||
| T26 | /workspace/coverage/sync_alert/12.prim_sync_alert.927538112 | Jul 28 04:54:56 PM PDT 24 | Jul 28 04:54:57 PM PDT 24 | 8467513 ps | ||
| T17 | /workspace/coverage/sync_alert/13.prim_sync_alert.1992412822 | Jul 28 04:54:46 PM PDT 24 | Jul 28 04:54:47 PM PDT 24 | 9233601 ps | ||
| T33 | /workspace/coverage/sync_alert/15.prim_sync_alert.3958458281 | Jul 28 04:54:41 PM PDT 24 | Jul 28 04:54:41 PM PDT 24 | 8653909 ps | ||
| T27 | /workspace/coverage/sync_alert/17.prim_sync_alert.232198874 | Jul 28 04:54:42 PM PDT 24 | Jul 28 04:54:43 PM PDT 24 | 9507006 ps | ||
| T34 | /workspace/coverage/sync_alert/5.prim_sync_alert.372149505 | Jul 28 04:55:01 PM PDT 24 | Jul 28 04:55:01 PM PDT 24 | 9851770 ps | ||
| T35 | /workspace/coverage/sync_alert/3.prim_sync_alert.3775702856 | Jul 28 04:54:45 PM PDT 24 | Jul 28 04:54:46 PM PDT 24 | 8567216 ps | ||
| T36 | /workspace/coverage/sync_alert/1.prim_sync_alert.2993660111 | Jul 28 04:54:54 PM PDT 24 | Jul 28 04:54:55 PM PDT 24 | 10162011 ps | ||
| T37 | /workspace/coverage/sync_alert/6.prim_sync_alert.3352125453 | Jul 28 04:54:39 PM PDT 24 | Jul 28 04:54:40 PM PDT 24 | 7883749 ps | ||
| T28 | /workspace/coverage/sync_alert/18.prim_sync_alert.2557992502 | Jul 28 04:54:48 PM PDT 24 | Jul 28 04:54:48 PM PDT 24 | 9933907 ps | ||
| T18 | /workspace/coverage/sync_alert/7.prim_sync_alert.1377204473 | Jul 28 04:54:57 PM PDT 24 | Jul 28 04:54:58 PM PDT 24 | 9483182 ps | ||
| T29 | /workspace/coverage/sync_alert/11.prim_sync_alert.982584597 | Jul 28 04:55:00 PM PDT 24 | Jul 28 04:55:00 PM PDT 24 | 8641654 ps | ||
| T58 | /workspace/coverage/sync_alert/10.prim_sync_alert.2983646546 | Jul 28 04:55:04 PM PDT 24 | Jul 28 04:55:05 PM PDT 24 | 8574827 ps | ||
| T30 | /workspace/coverage/sync_alert/19.prim_sync_alert.3322999044 | Jul 28 04:54:50 PM PDT 24 | Jul 28 04:54:50 PM PDT 24 | 8942301 ps | ||
| T31 | /workspace/coverage/sync_alert/14.prim_sync_alert.188931260 | Jul 28 04:54:51 PM PDT 24 | Jul 28 04:54:51 PM PDT 24 | 8999334 ps | ||
| T32 | /workspace/coverage/sync_alert/8.prim_sync_alert.3184304708 | Jul 28 04:54:58 PM PDT 24 | Jul 28 04:54:59 PM PDT 24 | 8517685 ps | ||
| T59 | /workspace/coverage/sync_alert/0.prim_sync_alert.764108041 | Jul 28 04:54:38 PM PDT 24 | Jul 28 04:54:39 PM PDT 24 | 9971958 ps | ||
| T60 | /workspace/coverage/sync_alert/4.prim_sync_alert.3847431889 | Jul 28 04:54:59 PM PDT 24 | Jul 28 04:55:00 PM PDT 24 | 9082547 ps | ||
| T61 | /workspace/coverage/sync_alert/16.prim_sync_alert.1495137798 | Jul 28 04:54:58 PM PDT 24 | Jul 28 04:54:58 PM PDT 24 | 9137989 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1535543955 | Jul 28 04:54:54 PM PDT 24 | Jul 28 04:55:00 PM PDT 24 | 26674825 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3341466316 | Jul 28 04:54:46 PM PDT 24 | Jul 28 04:54:46 PM PDT 24 | 27213815 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1878754339 | Jul 28 04:54:56 PM PDT 24 | Jul 28 04:55:01 PM PDT 24 | 26710208 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3523257501 | Jul 28 04:54:57 PM PDT 24 | Jul 28 04:54:57 PM PDT 24 | 28470670 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1073334096 | Jul 28 04:54:58 PM PDT 24 | Jul 28 04:54:59 PM PDT 24 | 26633068 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.720177359 | Jul 28 04:54:58 PM PDT 24 | Jul 28 04:54:58 PM PDT 24 | 26946005 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1025889892 | Jul 28 04:55:05 PM PDT 24 | Jul 28 04:55:15 PM PDT 24 | 28412121 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.493016627 | Jul 28 04:54:50 PM PDT 24 | Jul 28 04:54:51 PM PDT 24 | 28644304 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.203233360 | Jul 28 04:54:52 PM PDT 24 | Jul 28 04:54:52 PM PDT 24 | 27370519 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3430907099 | Jul 28 04:55:07 PM PDT 24 | Jul 28 04:55:08 PM PDT 24 | 27206527 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1135220220 | Jul 28 04:55:11 PM PDT 24 | Jul 28 04:55:11 PM PDT 24 | 28697172 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3615129542 | Jul 28 04:55:03 PM PDT 24 | Jul 28 04:55:03 PM PDT 24 | 25387857 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1569112143 | Jul 28 04:55:05 PM PDT 24 | Jul 28 04:55:06 PM PDT 24 | 29193992 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.465464229 | Jul 28 04:55:06 PM PDT 24 | Jul 28 04:55:06 PM PDT 24 | 26211599 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1812632707 | Jul 28 04:54:48 PM PDT 24 | Jul 28 04:54:48 PM PDT 24 | 27609850 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4223107903 | Jul 28 04:54:57 PM PDT 24 | Jul 28 04:54:58 PM PDT 24 | 27178149 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3681452054 | Jul 28 04:54:59 PM PDT 24 | Jul 28 04:54:59 PM PDT 24 | 28588928 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2473258248 | Jul 28 04:55:10 PM PDT 24 | Jul 28 04:55:11 PM PDT 24 | 27974741 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1438853367 | Jul 28 04:55:12 PM PDT 24 | Jul 28 04:55:12 PM PDT 24 | 27532141 ps | ||
| T80 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.672498362 | Jul 28 04:55:00 PM PDT 24 | Jul 28 04:55:01 PM PDT 24 | 28070731 ps |
| Test location | /workspace/coverage/default/15.prim_async_alert.62790352 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11255559 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:50:28 PM PDT 24 |
| Finished | Jul 28 04:50:28 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-adbc9f06-cf36-436d-80cf-54f675250c38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62790352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.62790352 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1992412822 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9233601 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:54:46 PM PDT 24 |
| Finished | Jul 28 04:54:47 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-8d439618-d8ac-4bb4-91bc-d0294a65aea2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1992412822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1992412822 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2625844757 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 29623479 ps |
| CPU time | 0.42 seconds |
| Started | Jul 28 04:50:02 PM PDT 24 |
| Finished | Jul 28 04:50:02 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-f8578fe8-bb9f-492d-a73a-7c15f7d3ca18 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2625844757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2625844757 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4051061255 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 32906777 ps |
| CPU time | 0.42 seconds |
| Started | Jul 28 04:50:10 PM PDT 24 |
| Finished | Jul 28 04:50:11 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-31d8806e-0ab0-4f82-9cd5-9908f9814635 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4051061255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.4051061255 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1535215745 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11326906 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:50:00 PM PDT 24 |
| Finished | Jul 28 04:50:01 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-d93a6345-7c7f-4849-b511-2a187567edee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1535215745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1535215745 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2515305766 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 31868115 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:50:04 PM PDT 24 |
| Finished | Jul 28 04:50:04 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-d3121e5a-c4fe-4024-970a-2e3b6aea9395 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2515305766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2515305766 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.1058030045 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11532641 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:49:58 PM PDT 24 |
| Finished | Jul 28 04:49:59 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-c0ee04af-f98d-476a-8777-fe29e75e3bda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1058030045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1058030045 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.3577872409 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11321201 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:50:02 PM PDT 24 |
| Finished | Jul 28 04:50:03 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-1301efbf-5626-4e19-8c25-b7a5cb76d826 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577872409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3577872409 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.3302833811 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10965708 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:50:02 PM PDT 24 |
| Finished | Jul 28 04:50:02 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-e5aa186e-18a4-4b0f-9491-bca8dcc39e82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3302833811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3302833811 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.2172946654 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11237136 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:50:05 PM PDT 24 |
| Finished | Jul 28 04:50:06 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-accecf67-cb6e-4471-8049-4d2d61cdff79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172946654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2172946654 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.4031333073 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10812166 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:50:01 PM PDT 24 |
| Finished | Jul 28 04:50:02 PM PDT 24 |
| Peak memory | 145836 kb |
| Host | smart-4e1af595-fc32-461d-873e-9f5ab8efa5d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031333073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.4031333073 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.4113345329 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11144281 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:50:04 PM PDT 24 |
| Finished | Jul 28 04:50:05 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-a96e0de9-035c-44c7-b05e-a5846e8a2d3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4113345329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.4113345329 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.3498655376 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11388169 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:50:08 PM PDT 24 |
| Finished | Jul 28 04:50:08 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-f0e7a8a2-aaca-4ca5-9c8c-273c104502fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498655376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3498655376 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.1611892644 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10937219 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:50:06 PM PDT 24 |
| Finished | Jul 28 04:50:07 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-c78f2ac6-31aa-4a04-867f-7b0b1884f0cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611892644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1611892644 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.4240119694 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10628060 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:50:46 PM PDT 24 |
| Finished | Jul 28 04:50:46 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-dc4bf3e1-b8f8-45d5-b3fe-3ef96f81cbc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240119694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.4240119694 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.655970179 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11037582 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:50:00 PM PDT 24 |
| Finished | Jul 28 04:50:00 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-03a2b897-0587-4982-a21f-9cbd34f70039 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=655970179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.655970179 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.2598930830 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10431501 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:49:56 PM PDT 24 |
| Finished | Jul 28 04:49:57 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-51e9733d-fdc8-4ab1-8f17-1d18d15ceb31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2598930830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2598930830 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.2447671827 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10350244 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:50:13 PM PDT 24 |
| Finished | Jul 28 04:50:13 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-eafa7793-efbd-4ae6-b3e4-c81fff23d6da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447671827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2447671827 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.2753851569 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10787864 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:50:07 PM PDT 24 |
| Finished | Jul 28 04:50:07 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-3eb10808-04a0-4750-a6a7-efc72bc815b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2753851569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2753851569 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.2908492443 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10754720 ps |
| CPU time | 0.42 seconds |
| Started | Jul 28 04:49:59 PM PDT 24 |
| Finished | Jul 28 04:49:59 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-5c224f97-b990-4936-8f3a-d2f0aa874a54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908492443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2908492443 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2872452358 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11603995 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:50:33 PM PDT 24 |
| Finished | Jul 28 04:50:33 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-21f07a34-9219-46fd-abfb-5bd2bd3be33c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872452358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2872452358 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.4275938886 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11525478 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:50:02 PM PDT 24 |
| Finished | Jul 28 04:50:03 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-47291615-c86a-4a6c-8d27-0de2c0c47e0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275938886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.4275938886 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.2279502253 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11644493 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:50:08 PM PDT 24 |
| Finished | Jul 28 04:50:09 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-193e7914-1dae-4b0f-82ad-6662ea79dcc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279502253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2279502253 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.796202516 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11308807 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:49:58 PM PDT 24 |
| Finished | Jul 28 04:49:59 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-bdca69cd-ff53-42fe-8cc9-bb14c1fad24a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796202516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.796202516 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3481272428 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29154944 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:50:03 PM PDT 24 |
| Finished | Jul 28 04:50:03 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-613d2c1d-fe57-4cfa-b599-45ba92fdaa64 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3481272428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3481272428 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1477889781 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 30342942 ps |
| CPU time | 0.45 seconds |
| Started | Jul 28 04:50:04 PM PDT 24 |
| Finished | Jul 28 04:50:05 PM PDT 24 |
| Peak memory | 144784 kb |
| Host | smart-70d21899-1c98-4d65-b603-90e83db0189f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1477889781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1477889781 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.143241059 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 30049310 ps |
| CPU time | 0.42 seconds |
| Started | Jul 28 04:49:57 PM PDT 24 |
| Finished | Jul 28 04:49:58 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-cba91fba-ca44-4786-9730-183e3a471067 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=143241059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.143241059 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3501432996 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30844727 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:50:14 PM PDT 24 |
| Finished | Jul 28 04:50:14 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-779dec52-769e-4a33-9962-a1827bc8c06a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3501432996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3501432996 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1531783476 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 30818435 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:49:59 PM PDT 24 |
| Finished | Jul 28 04:49:59 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-54f7a257-cc8d-48b4-a84b-c30ab724f6d7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1531783476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1531783476 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3608248870 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29396705 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:50:05 PM PDT 24 |
| Finished | Jul 28 04:50:16 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-4d2a2077-14cf-4568-8c8b-53f2266f0c09 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3608248870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3608248870 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2148906478 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 29982726 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:49:56 PM PDT 24 |
| Finished | Jul 28 04:49:56 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-c43af217-5f21-4e46-a10c-b57ec7aa4616 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2148906478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2148906478 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2268594202 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29174163 ps |
| CPU time | 0.42 seconds |
| Started | Jul 28 04:50:10 PM PDT 24 |
| Finished | Jul 28 04:50:10 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-ef9e0be6-44b2-4f89-915c-ebbbd3d130aa |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2268594202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2268594202 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3641048457 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29551141 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:50:12 PM PDT 24 |
| Finished | Jul 28 04:50:17 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-7db5d1bd-6bd5-4f3d-ab72-17dd5260c3b6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3641048457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3641048457 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3149545996 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 30166709 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:50:48 PM PDT 24 |
| Finished | Jul 28 04:50:49 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-15c82caa-1caa-4763-8f8b-a64a7eb4728f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3149545996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3149545996 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2798895833 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 32243305 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:50:00 PM PDT 24 |
| Finished | Jul 28 04:50:00 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-db445935-8a19-4d4c-8187-b4fef61fe5a2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2798895833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2798895833 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1604373366 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30561169 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:50:08 PM PDT 24 |
| Finished | Jul 28 04:50:09 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-2471428c-a58c-47fa-b8e2-99c3d73eabeb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1604373366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1604373366 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.48932192 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 29012230 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:50:09 PM PDT 24 |
| Finished | Jul 28 04:50:10 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-f1cbf970-1f49-4f88-a079-ad0fb452b670 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=48932192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.48932192 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.854315775 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 28974461 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:50:02 PM PDT 24 |
| Finished | Jul 28 04:50:02 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-2ce16b73-1e36-4120-bb33-cfdcd3c0a0dd |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=854315775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.854315775 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3651992269 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 28105072 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:50:35 PM PDT 24 |
| Finished | Jul 28 04:50:35 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-8546d016-59f1-485a-b394-37600ef03e53 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3651992269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3651992269 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2737016456 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30552546 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:50:01 PM PDT 24 |
| Finished | Jul 28 04:50:02 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-e773f80c-af66-4f90-87a2-51501054bc35 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2737016456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2737016456 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2824109910 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30872308 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:50:01 PM PDT 24 |
| Finished | Jul 28 04:50:01 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-90fcdf1b-3e20-472c-91e9-5a0e1b569490 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2824109910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2824109910 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.764108041 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9971958 ps |
| CPU time | 0.42 seconds |
| Started | Jul 28 04:54:38 PM PDT 24 |
| Finished | Jul 28 04:54:39 PM PDT 24 |
| Peak memory | 145840 kb |
| Host | smart-bd77c9cc-0841-4fdf-8c9d-4040aa78efd3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=764108041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.764108041 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.2993660111 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10162011 ps |
| CPU time | 0.46 seconds |
| Started | Jul 28 04:54:54 PM PDT 24 |
| Finished | Jul 28 04:54:55 PM PDT 24 |
| Peak memory | 145840 kb |
| Host | smart-f6a5489f-58d9-4a48-b084-7db0df20ea2d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2993660111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2993660111 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.2983646546 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8574827 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:55:04 PM PDT 24 |
| Finished | Jul 28 04:55:05 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-4a479a67-33da-44c8-83ee-1b7e22158bcb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2983646546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2983646546 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.982584597 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8641654 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:55:00 PM PDT 24 |
| Finished | Jul 28 04:55:00 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-0e767317-542d-483a-ae2f-def1e1a71bb9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=982584597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.982584597 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.927538112 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8467513 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:54:56 PM PDT 24 |
| Finished | Jul 28 04:54:57 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-54cf82e9-0fbe-4aa2-8aa0-7a3674673b5a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=927538112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.927538112 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.188931260 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8999334 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:54:51 PM PDT 24 |
| Finished | Jul 28 04:54:51 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-776233ce-781a-453f-a010-8170c46be865 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=188931260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.188931260 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.3958458281 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8653909 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:54:41 PM PDT 24 |
| Finished | Jul 28 04:54:41 PM PDT 24 |
| Peak memory | 145392 kb |
| Host | smart-df332aa2-3be4-4985-b118-beb339d9ae93 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3958458281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3958458281 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.1495137798 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9137989 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:54:58 PM PDT 24 |
| Finished | Jul 28 04:54:58 PM PDT 24 |
| Peak memory | 145852 kb |
| Host | smart-cb642955-4bc3-43a9-ae87-cca2df5d3bb9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1495137798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1495137798 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.232198874 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9507006 ps |
| CPU time | 0.37 seconds |
| Started | Jul 28 04:54:42 PM PDT 24 |
| Finished | Jul 28 04:54:43 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-fca72df4-d3f7-40d5-bbd0-1880f3dd60fe |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=232198874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.232198874 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.2557992502 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9933907 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:54:48 PM PDT 24 |
| Finished | Jul 28 04:54:48 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-7d9462fe-2864-4e5c-bf16-c4fb38494c45 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2557992502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2557992502 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.3322999044 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8942301 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:54:50 PM PDT 24 |
| Finished | Jul 28 04:54:50 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-e49b3e04-b56d-4246-af6a-6ada1789ef63 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3322999044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3322999044 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2777886501 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9339103 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:55:00 PM PDT 24 |
| Finished | Jul 28 04:55:00 PM PDT 24 |
| Peak memory | 145500 kb |
| Host | smart-46a45120-1111-4ebb-8b63-88db396bd908 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2777886501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2777886501 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3775702856 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8567216 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:54:45 PM PDT 24 |
| Finished | Jul 28 04:54:46 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-149eb0b3-8088-4b8f-b30f-c0c4995257b7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3775702856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3775702856 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.3847431889 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9082547 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:54:59 PM PDT 24 |
| Finished | Jul 28 04:55:00 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-2cbca307-2773-4b28-befd-b4cc8f995b3f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3847431889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3847431889 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.372149505 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9851770 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:55:01 PM PDT 24 |
| Finished | Jul 28 04:55:01 PM PDT 24 |
| Peak memory | 145412 kb |
| Host | smart-680f635b-fecf-4cc3-a53b-8721e00258bb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=372149505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.372149505 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.3352125453 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 7883749 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:54:39 PM PDT 24 |
| Finished | Jul 28 04:54:40 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-dd81ca52-1ba9-4b27-a9db-992d2e4ad5d7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3352125453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3352125453 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.1377204473 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9483182 ps |
| CPU time | 0.37 seconds |
| Started | Jul 28 04:54:57 PM PDT 24 |
| Finished | Jul 28 04:54:58 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-5af5fb29-14b9-4257-8483-136e8d82cf94 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1377204473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1377204473 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.3184304708 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8517685 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:54:58 PM PDT 24 |
| Finished | Jul 28 04:54:59 PM PDT 24 |
| Peak memory | 145500 kb |
| Host | smart-21ece419-bf68-455f-ae06-0cfc0fe27ea2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3184304708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3184304708 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.397288110 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9910476 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:54:41 PM PDT 24 |
| Finished | Jul 28 04:54:42 PM PDT 24 |
| Peak memory | 145400 kb |
| Host | smart-f490989a-4234-4ce8-9aa3-264e593bf1ad |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=397288110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.397288110 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.720177359 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26946005 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:54:58 PM PDT 24 |
| Finished | Jul 28 04:54:58 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-028fee85-dcb6-4485-a344-15cfb774cbdd |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=720177359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.720177359 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3430907099 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27206527 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:55:07 PM PDT 24 |
| Finished | Jul 28 04:55:08 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-ebca93e8-c342-4e0e-bade-78424d149a83 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3430907099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3430907099 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1569112143 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 29193992 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:55:05 PM PDT 24 |
| Finished | Jul 28 04:55:06 PM PDT 24 |
| Peak memory | 145448 kb |
| Host | smart-02131c59-8943-441e-a68a-ab74cc3754ca |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1569112143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1569112143 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.203233360 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27370519 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:54:52 PM PDT 24 |
| Finished | Jul 28 04:54:52 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-bbff32e6-c2c8-48c6-b545-ce7771c90e02 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=203233360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.203233360 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1535543955 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 26674825 ps |
| CPU time | 0.37 seconds |
| Started | Jul 28 04:54:54 PM PDT 24 |
| Finished | Jul 28 04:55:00 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-59fab147-6b5e-4393-a849-6056b1284a1a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1535543955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1535543955 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1025889892 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28412121 ps |
| CPU time | 0.42 seconds |
| Started | Jul 28 04:55:05 PM PDT 24 |
| Finished | Jul 28 04:55:15 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-9d34ac2f-5343-45dc-8d9f-cb5e1f440ee2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1025889892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1025889892 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4223107903 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27178149 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:54:57 PM PDT 24 |
| Finished | Jul 28 04:54:58 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-2cab6917-f9b1-4637-a5ec-8236297eb9ea |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4223107903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.4223107903 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3681452054 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 28588928 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:54:59 PM PDT 24 |
| Finished | Jul 28 04:54:59 PM PDT 24 |
| Peak memory | 145524 kb |
| Host | smart-4409062c-a8be-43b4-8783-1a633ac36c1c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3681452054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3681452054 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1438853367 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 27532141 ps |
| CPU time | 0.45 seconds |
| Started | Jul 28 04:55:12 PM PDT 24 |
| Finished | Jul 28 04:55:12 PM PDT 24 |
| Peak memory | 145412 kb |
| Host | smart-f18d855a-7eae-4e85-b4f2-c00a7ee6b0aa |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1438853367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1438853367 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1073334096 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 26633068 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:54:58 PM PDT 24 |
| Finished | Jul 28 04:54:59 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-c4d3fb8c-625f-481f-8cc9-bd32315c3650 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1073334096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1073334096 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1135220220 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 28697172 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:55:11 PM PDT 24 |
| Finished | Jul 28 04:55:11 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-ab327e06-4d18-4ff2-83c1-d3a9529995da |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1135220220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1135220220 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3615129542 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 25387857 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:55:03 PM PDT 24 |
| Finished | Jul 28 04:55:03 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-8e39e73f-6772-432d-9810-1218661419f8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3615129542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3615129542 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2473258248 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 27974741 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:55:10 PM PDT 24 |
| Finished | Jul 28 04:55:11 PM PDT 24 |
| Peak memory | 145448 kb |
| Host | smart-17f9cdbc-973b-48e9-a65a-b93742f64e54 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2473258248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2473258248 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1812632707 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27609850 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:54:48 PM PDT 24 |
| Finished | Jul 28 04:54:48 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-9d0e1eaf-5078-47ba-9cb0-fc4a3e26e67c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1812632707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1812632707 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1878754339 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 26710208 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:54:56 PM PDT 24 |
| Finished | Jul 28 04:55:01 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-dcf4c5df-a197-40de-bc15-749ff36b52ef |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1878754339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1878754339 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3523257501 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 28470670 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:54:57 PM PDT 24 |
| Finished | Jul 28 04:54:57 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-6af125e9-567a-4d7e-adf2-629758d82c49 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3523257501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3523257501 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3341466316 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27213815 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:54:46 PM PDT 24 |
| Finished | Jul 28 04:54:46 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-adbd3fa7-2b45-4f78-8168-c5f053791784 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3341466316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3341466316 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.465464229 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26211599 ps |
| CPU time | 0.42 seconds |
| Started | Jul 28 04:55:06 PM PDT 24 |
| Finished | Jul 28 04:55:06 PM PDT 24 |
| Peak memory | 145412 kb |
| Host | smart-ac4973d9-0a6f-41c4-a95e-eca6d9ee8049 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=465464229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.465464229 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.672498362 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 28070731 ps |
| CPU time | 0.41 seconds |
| Started | Jul 28 04:55:00 PM PDT 24 |
| Finished | Jul 28 04:55:01 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-79e0cb4b-34db-48e9-81eb-e36db928848d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=672498362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.672498362 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.493016627 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28644304 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:54:50 PM PDT 24 |
| Finished | Jul 28 04:54:51 PM PDT 24 |
| Peak memory | 145412 kb |
| Host | smart-98b579a7-8a34-42f7-a664-c199a72970ba |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=493016627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.493016627 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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