| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.85 | 100.00 | 97.92 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.28 | 88.28 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 75.00 | 75.00 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/19.prim_async_alert.2126450741 |
| 90.82 | 2.53 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 78.57 | 3.57 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/15.prim_sync_alert.2364767708 |
| 92.39 | 1.58 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 2.33 | /workspace/coverage/default/11.prim_async_alert.1109811086 |
| 93.90 | 1.51 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1197696377 |
| 94.50 | 0.60 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/17.prim_async_alert.1743681649 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1824795063 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.1689939540 |
| /workspace/coverage/default/1.prim_async_alert.2591196719 |
| /workspace/coverage/default/10.prim_async_alert.521745684 |
| /workspace/coverage/default/12.prim_async_alert.2694604199 |
| /workspace/coverage/default/13.prim_async_alert.674363235 |
| /workspace/coverage/default/14.prim_async_alert.2619910557 |
| /workspace/coverage/default/15.prim_async_alert.1194782538 |
| /workspace/coverage/default/16.prim_async_alert.1746606396 |
| /workspace/coverage/default/18.prim_async_alert.1050810074 |
| /workspace/coverage/default/2.prim_async_alert.3430601683 |
| /workspace/coverage/default/3.prim_async_alert.1671334153 |
| /workspace/coverage/default/4.prim_async_alert.555058857 |
| /workspace/coverage/default/5.prim_async_alert.1514511010 |
| /workspace/coverage/default/6.prim_async_alert.2258388455 |
| /workspace/coverage/default/7.prim_async_alert.664906013 |
| /workspace/coverage/default/8.prim_async_alert.798560553 |
| /workspace/coverage/default/9.prim_async_alert.3596350115 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1472276396 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2713723691 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2740568195 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.6732239 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.510055653 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1578550374 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3810688599 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4032088452 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.406993010 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2932036217 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.947235516 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2313090055 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1610546290 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2928235514 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4156397233 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3902864852 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1701032544 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.3392645091 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.644030996 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3798615190 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1324482377 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3055022507 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.39584944 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1669812725 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.3936775932 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.1307532952 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.2469430890 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.3456524574 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.1978958518 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.4108719616 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.1900053224 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.1879076719 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.331939411 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.2745667012 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.2861650387 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.2900166538 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1022100132 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3796535244 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2330969115 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1000596779 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.247536558 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1836104701 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.379526645 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.975501221 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3073903679 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3068162658 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3215761112 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3575038168 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.478170570 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1491839950 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.807200773 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.973712488 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.793221496 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3604802735 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.870065133 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3036266957 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/11.prim_async_alert.1109811086 | Jul 29 06:38:09 PM PDT 24 | Jul 29 06:38:10 PM PDT 24 | 11656765 ps | ||
| T2 | /workspace/coverage/default/14.prim_async_alert.2619910557 | Jul 29 06:38:09 PM PDT 24 | Jul 29 06:38:10 PM PDT 24 | 11033723 ps | ||
| T3 | /workspace/coverage/default/12.prim_async_alert.2694604199 | Jul 29 06:38:09 PM PDT 24 | Jul 29 06:38:10 PM PDT 24 | 11415197 ps | ||
| T8 | /workspace/coverage/default/13.prim_async_alert.674363235 | Jul 29 06:38:09 PM PDT 24 | Jul 29 06:38:10 PM PDT 24 | 11165019 ps | ||
| T7 | /workspace/coverage/default/7.prim_async_alert.664906013 | Jul 29 06:38:07 PM PDT 24 | Jul 29 06:38:08 PM PDT 24 | 10692290 ps | ||
| T11 | /workspace/coverage/default/19.prim_async_alert.2126450741 | Jul 29 06:38:07 PM PDT 24 | Jul 29 06:38:08 PM PDT 24 | 12309781 ps | ||
| T18 | /workspace/coverage/default/0.prim_async_alert.1689939540 | Jul 29 06:38:07 PM PDT 24 | Jul 29 06:38:07 PM PDT 24 | 11100758 ps | ||
| T19 | /workspace/coverage/default/16.prim_async_alert.1746606396 | Jul 29 06:38:11 PM PDT 24 | Jul 29 06:38:12 PM PDT 24 | 10899113 ps | ||
| T20 | /workspace/coverage/default/5.prim_async_alert.1514511010 | Jul 29 06:38:09 PM PDT 24 | Jul 29 06:38:10 PM PDT 24 | 10634011 ps | ||
| T21 | /workspace/coverage/default/18.prim_async_alert.1050810074 | Jul 29 06:38:11 PM PDT 24 | Jul 29 06:38:11 PM PDT 24 | 10942278 ps | ||
| T9 | /workspace/coverage/default/15.prim_async_alert.1194782538 | Jul 29 06:38:07 PM PDT 24 | Jul 29 06:38:08 PM PDT 24 | 10923342 ps | ||
| T16 | /workspace/coverage/default/10.prim_async_alert.521745684 | Jul 29 06:38:11 PM PDT 24 | Jul 29 06:38:11 PM PDT 24 | 12107339 ps | ||
| T10 | /workspace/coverage/default/8.prim_async_alert.798560553 | Jul 29 06:38:09 PM PDT 24 | Jul 29 06:38:10 PM PDT 24 | 10196129 ps | ||
| T17 | /workspace/coverage/default/2.prim_async_alert.3430601683 | Jul 29 06:38:07 PM PDT 24 | Jul 29 06:38:08 PM PDT 24 | 11557150 ps | ||
| T48 | /workspace/coverage/default/6.prim_async_alert.2258388455 | Jul 29 06:38:10 PM PDT 24 | Jul 29 06:38:11 PM PDT 24 | 11454479 ps | ||
| T15 | /workspace/coverage/default/4.prim_async_alert.555058857 | Jul 29 06:37:56 PM PDT 24 | Jul 29 06:37:57 PM PDT 24 | 10584522 ps | ||
| T12 | /workspace/coverage/default/3.prim_async_alert.1671334153 | Jul 29 06:38:09 PM PDT 24 | Jul 29 06:38:09 PM PDT 24 | 12475047 ps | ||
| T13 | /workspace/coverage/default/17.prim_async_alert.1743681649 | Jul 29 06:38:11 PM PDT 24 | Jul 29 06:38:11 PM PDT 24 | 12301111 ps | ||
| T22 | /workspace/coverage/default/1.prim_async_alert.2591196719 | Jul 29 06:38:07 PM PDT 24 | Jul 29 06:38:08 PM PDT 24 | 11102710 ps | ||
| T49 | /workspace/coverage/default/9.prim_async_alert.3596350115 | Jul 29 06:38:11 PM PDT 24 | Jul 29 06:38:11 PM PDT 24 | 11273034 ps | ||
| T23 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.6732239 | Jul 29 06:38:12 PM PDT 24 | Jul 29 06:38:13 PM PDT 24 | 28550054 ps | ||
| T24 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4156397233 | Jul 29 06:38:12 PM PDT 24 | Jul 29 06:38:12 PM PDT 24 | 29392154 ps | ||
| T41 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3902864852 | Jul 29 06:38:16 PM PDT 24 | Jul 29 06:38:16 PM PDT 24 | 30957857 ps | ||
| T42 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2740568195 | Jul 29 06:38:12 PM PDT 24 | Jul 29 06:38:13 PM PDT 24 | 29992648 ps | ||
| T43 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2932036217 | Jul 29 06:38:17 PM PDT 24 | Jul 29 06:38:17 PM PDT 24 | 30865542 ps | ||
| T4 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1824795063 | Jul 29 06:38:14 PM PDT 24 | Jul 29 06:38:14 PM PDT 24 | 28735098 ps | ||
| T44 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4032088452 | Jul 29 06:38:21 PM PDT 24 | Jul 29 06:38:21 PM PDT 24 | 31236667 ps | ||
| T45 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1197696377 | Jul 29 06:38:15 PM PDT 24 | Jul 29 06:38:16 PM PDT 24 | 29809074 ps | ||
| T46 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1472276396 | Jul 29 06:38:11 PM PDT 24 | Jul 29 06:38:11 PM PDT 24 | 29023055 ps | ||
| T47 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.947235516 | Jul 29 06:38:11 PM PDT 24 | Jul 29 06:38:12 PM PDT 24 | 28744222 ps | ||
| T50 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.510055653 | Jul 29 06:38:12 PM PDT 24 | Jul 29 06:38:13 PM PDT 24 | 26903160 ps | ||
| T51 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1578550374 | Jul 29 06:38:16 PM PDT 24 | Jul 29 06:38:17 PM PDT 24 | 32247731 ps | ||
| T52 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2713723691 | Jul 29 06:38:14 PM PDT 24 | Jul 29 06:38:14 PM PDT 24 | 30209621 ps | ||
| T53 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.406993010 | Jul 29 06:38:21 PM PDT 24 | Jul 29 06:38:22 PM PDT 24 | 30624952 ps | ||
| T54 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2928235514 | Jul 29 06:38:11 PM PDT 24 | Jul 29 06:38:11 PM PDT 24 | 30415474 ps | ||
| T55 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1701032544 | Jul 29 06:38:13 PM PDT 24 | Jul 29 06:38:14 PM PDT 24 | 31796726 ps | ||
| T56 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2313090055 | Jul 29 06:38:10 PM PDT 24 | Jul 29 06:38:10 PM PDT 24 | 30348455 ps | ||
| T57 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1610546290 | Jul 29 06:38:10 PM PDT 24 | Jul 29 06:38:10 PM PDT 24 | 30019457 ps | ||
| T58 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3810688599 | Jul 29 06:38:13 PM PDT 24 | Jul 29 06:38:14 PM PDT 24 | 29486992 ps | ||
| T33 | /workspace/coverage/sync_alert/15.prim_sync_alert.2364767708 | Jul 29 04:44:25 PM PDT 24 | Jul 29 04:44:25 PM PDT 24 | 9851479 ps | ||
| T34 | /workspace/coverage/sync_alert/12.prim_sync_alert.3055022507 | Jul 29 04:44:28 PM PDT 24 | Jul 29 04:44:29 PM PDT 24 | 9710321 ps | ||
| T35 | /workspace/coverage/sync_alert/0.prim_sync_alert.3392645091 | Jul 29 04:44:21 PM PDT 24 | Jul 29 04:44:22 PM PDT 24 | 9411154 ps | ||
| T36 | /workspace/coverage/sync_alert/3.prim_sync_alert.4108719616 | Jul 29 04:44:22 PM PDT 24 | Jul 29 04:44:23 PM PDT 24 | 9434715 ps | ||
| T37 | /workspace/coverage/sync_alert/8.prim_sync_alert.2861650387 | Jul 29 04:44:24 PM PDT 24 | Jul 29 04:44:24 PM PDT 24 | 9504350 ps | ||
| T25 | /workspace/coverage/sync_alert/11.prim_sync_alert.1324482377 | Jul 29 04:44:22 PM PDT 24 | Jul 29 04:44:22 PM PDT 24 | 9084345 ps | ||
| T38 | /workspace/coverage/sync_alert/7.prim_sync_alert.2745667012 | Jul 29 04:44:21 PM PDT 24 | Jul 29 04:44:21 PM PDT 24 | 9840220 ps | ||
| T39 | /workspace/coverage/sync_alert/18.prim_sync_alert.2469430890 | Jul 29 04:44:23 PM PDT 24 | Jul 29 04:44:24 PM PDT 24 | 9833542 ps | ||
| T14 | /workspace/coverage/sync_alert/4.prim_sync_alert.1900053224 | Jul 29 04:44:24 PM PDT 24 | Jul 29 04:44:25 PM PDT 24 | 9584615 ps | ||
| T40 | /workspace/coverage/sync_alert/6.prim_sync_alert.331939411 | Jul 29 04:44:23 PM PDT 24 | Jul 29 04:44:28 PM PDT 24 | 9459993 ps | ||
| T59 | /workspace/coverage/sync_alert/13.prim_sync_alert.39584944 | Jul 29 04:44:23 PM PDT 24 | Jul 29 04:44:24 PM PDT 24 | 9322882 ps | ||
| T26 | /workspace/coverage/sync_alert/1.prim_sync_alert.644030996 | Jul 29 04:44:19 PM PDT 24 | Jul 29 04:44:19 PM PDT 24 | 8670824 ps | ||
| T27 | /workspace/coverage/sync_alert/17.prim_sync_alert.1307532952 | Jul 29 04:44:25 PM PDT 24 | Jul 29 04:44:26 PM PDT 24 | 7977611 ps | ||
| T60 | /workspace/coverage/sync_alert/10.prim_sync_alert.3798615190 | Jul 29 04:44:25 PM PDT 24 | Jul 29 04:44:25 PM PDT 24 | 10103027 ps | ||
| T61 | /workspace/coverage/sync_alert/14.prim_sync_alert.1669812725 | Jul 29 04:44:25 PM PDT 24 | Jul 29 04:44:26 PM PDT 24 | 10319960 ps | ||
| T62 | /workspace/coverage/sync_alert/9.prim_sync_alert.2900166538 | Jul 29 04:44:24 PM PDT 24 | Jul 29 04:44:24 PM PDT 24 | 8258757 ps | ||
| T63 | /workspace/coverage/sync_alert/19.prim_sync_alert.3456524574 | Jul 29 04:44:25 PM PDT 24 | Jul 29 04:44:25 PM PDT 24 | 10042833 ps | ||
| T64 | /workspace/coverage/sync_alert/2.prim_sync_alert.1978958518 | Jul 29 04:44:22 PM PDT 24 | Jul 29 04:44:23 PM PDT 24 | 8291279 ps | ||
| T65 | /workspace/coverage/sync_alert/5.prim_sync_alert.1879076719 | Jul 29 04:44:20 PM PDT 24 | Jul 29 04:44:21 PM PDT 24 | 9010403 ps | ||
| T66 | /workspace/coverage/sync_alert/16.prim_sync_alert.3936775932 | Jul 29 04:44:25 PM PDT 24 | Jul 29 04:44:26 PM PDT 24 | 10079076 ps | ||
| T28 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.807200773 | Jul 29 04:49:20 PM PDT 24 | Jul 29 04:49:21 PM PDT 24 | 27603532 ps | ||
| T29 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1491839950 | Jul 29 04:49:26 PM PDT 24 | Jul 29 04:49:26 PM PDT 24 | 29166659 ps | ||
| T30 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.247536558 | Jul 29 04:49:17 PM PDT 24 | Jul 29 04:49:18 PM PDT 24 | 27597375 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2330969115 | Jul 29 04:49:15 PM PDT 24 | Jul 29 04:49:15 PM PDT 24 | 26592567 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.379526645 | Jul 29 04:49:23 PM PDT 24 | Jul 29 04:49:23 PM PDT 24 | 26970900 ps | ||
| T31 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1022100132 | Jul 29 04:49:20 PM PDT 24 | Jul 29 04:49:20 PM PDT 24 | 26879234 ps | ||
| T32 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.870065133 | Jul 29 04:49:17 PM PDT 24 | Jul 29 04:49:17 PM PDT 24 | 25773870 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.478170570 | Jul 29 04:49:23 PM PDT 24 | Jul 29 04:49:23 PM PDT 24 | 27583665 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1000596779 | Jul 29 04:49:14 PM PDT 24 | Jul 29 04:49:14 PM PDT 24 | 28448510 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.975501221 | Jul 29 04:49:12 PM PDT 24 | Jul 29 04:49:12 PM PDT 24 | 27357365 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3604802735 | Jul 29 04:49:21 PM PDT 24 | Jul 29 04:49:22 PM PDT 24 | 26437259 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3575038168 | Jul 29 04:49:25 PM PDT 24 | Jul 29 04:49:25 PM PDT 24 | 27518176 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1836104701 | Jul 29 04:49:09 PM PDT 24 | Jul 29 04:49:10 PM PDT 24 | 27372785 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3068162658 | Jul 29 04:49:22 PM PDT 24 | Jul 29 04:49:22 PM PDT 24 | 25841971 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.793221496 | Jul 29 04:49:27 PM PDT 24 | Jul 29 04:49:27 PM PDT 24 | 27737599 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3796535244 | Jul 29 04:49:18 PM PDT 24 | Jul 29 04:49:18 PM PDT 24 | 26270087 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3215761112 | Jul 29 04:49:02 PM PDT 24 | Jul 29 04:49:02 PM PDT 24 | 26830724 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3073903679 | Jul 29 04:49:08 PM PDT 24 | Jul 29 04:49:08 PM PDT 24 | 29872851 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3036266957 | Jul 29 04:49:08 PM PDT 24 | Jul 29 04:49:09 PM PDT 24 | 27744334 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.973712488 | Jul 29 04:49:15 PM PDT 24 | Jul 29 04:49:15 PM PDT 24 | 26493120 ps |
| Test location | /workspace/coverage/default/19.prim_async_alert.2126450741 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12309781 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 06:38:07 PM PDT 24 |
| Finished | Jul 29 06:38:08 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-82c44255-83ca-4527-b2b0-4dc45bda873d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126450741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2126450741 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.2364767708 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9851479 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 04:44:25 PM PDT 24 |
| Finished | Jul 29 04:44:25 PM PDT 24 |
| Peak memory | 145456 kb |
| Host | smart-5117b3b7-d7c5-40f0-9bcd-60e3924e1102 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2364767708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2364767708 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.1109811086 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11656765 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 06:38:09 PM PDT 24 |
| Finished | Jul 29 06:38:10 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-2419a4f3-6252-40b9-a82e-a1b91ddada78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1109811086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1109811086 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1197696377 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29809074 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 06:38:15 PM PDT 24 |
| Finished | Jul 29 06:38:16 PM PDT 24 |
| Peak memory | 145336 kb |
| Host | smart-eae43841-381b-416c-af2d-3d4a347cab2d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1197696377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1197696377 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.1743681649 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12301111 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 06:38:11 PM PDT 24 |
| Finished | Jul 29 06:38:11 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-9e20bdf2-e7dd-4141-828d-ac0d36773f86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1743681649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1743681649 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1824795063 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28735098 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 06:38:14 PM PDT 24 |
| Finished | Jul 29 06:38:14 PM PDT 24 |
| Peak memory | 145344 kb |
| Host | smart-b0a10959-9ad5-434e-af3b-6fcdd911255e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1824795063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1824795063 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.1689939540 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11100758 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 06:38:07 PM PDT 24 |
| Finished | Jul 29 06:38:07 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-849d7c8f-2494-4ec8-80f1-1c0a096241d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1689939540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1689939540 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.2591196719 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11102710 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 06:38:07 PM PDT 24 |
| Finished | Jul 29 06:38:08 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-d4fc662c-506e-42c9-aa26-d6ee709c0799 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591196719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2591196719 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.521745684 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12107339 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 06:38:11 PM PDT 24 |
| Finished | Jul 29 06:38:11 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-423b49e8-a703-469d-99fe-16234cc15f10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=521745684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.521745684 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.2694604199 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11415197 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 06:38:09 PM PDT 24 |
| Finished | Jul 29 06:38:10 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-3a7dd76f-e092-44cc-85f3-72ede69a8ed5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2694604199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2694604199 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.674363235 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11165019 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 06:38:09 PM PDT 24 |
| Finished | Jul 29 06:38:10 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-0f4646b5-b09e-490a-b8a5-4f47c8ff1693 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=674363235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.674363235 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.2619910557 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11033723 ps |
| CPU time | 0.37 seconds |
| Started | Jul 29 06:38:09 PM PDT 24 |
| Finished | Jul 29 06:38:10 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-7f89a096-6c2f-45c1-9350-3c86b6cb9c87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2619910557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2619910557 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1194782538 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10923342 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 06:38:07 PM PDT 24 |
| Finished | Jul 29 06:38:08 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-6c4d4be9-552b-43b3-91b5-633f75304e5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1194782538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1194782538 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.1746606396 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10899113 ps |
| CPU time | 0.41 seconds |
| Started | Jul 29 06:38:11 PM PDT 24 |
| Finished | Jul 29 06:38:12 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-a699308a-5b6d-4d76-93ce-c6b7836338ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746606396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1746606396 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.1050810074 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10942278 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 06:38:11 PM PDT 24 |
| Finished | Jul 29 06:38:11 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-e9b0b701-788e-425d-ae2f-e3ef494ee0c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050810074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1050810074 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3430601683 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11557150 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 06:38:07 PM PDT 24 |
| Finished | Jul 29 06:38:08 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-3e21754d-c4fb-47bb-a91e-2690687ef04f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3430601683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3430601683 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.1671334153 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12475047 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 06:38:09 PM PDT 24 |
| Finished | Jul 29 06:38:09 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-fc56ba6a-fd2b-46aa-bc01-159a111e75a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671334153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1671334153 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.555058857 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10584522 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 06:37:56 PM PDT 24 |
| Finished | Jul 29 06:37:57 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-82f208d1-0024-4cff-a77d-ccedcc62be35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555058857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.555058857 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.1514511010 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10634011 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 06:38:09 PM PDT 24 |
| Finished | Jul 29 06:38:10 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-358bcf5c-eab9-499f-b48c-4c63d180a4c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514511010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1514511010 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2258388455 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11454479 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 06:38:10 PM PDT 24 |
| Finished | Jul 29 06:38:11 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-a3a5ba09-8b5f-449d-83bd-d6bf17e89640 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258388455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2258388455 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.664906013 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10692290 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 06:38:07 PM PDT 24 |
| Finished | Jul 29 06:38:08 PM PDT 24 |
| Peak memory | 145844 kb |
| Host | smart-ecfcf1ca-cb04-4cf1-9f8a-8255235836e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=664906013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.664906013 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.798560553 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10196129 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 06:38:09 PM PDT 24 |
| Finished | Jul 29 06:38:10 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-d46a198a-7011-4a21-a4ce-3a74d7f556ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=798560553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.798560553 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.3596350115 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11273034 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 06:38:11 PM PDT 24 |
| Finished | Jul 29 06:38:11 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-578a3d7e-46bb-4b1a-be47-b8d5bd33bbed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596350115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3596350115 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1472276396 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29023055 ps |
| CPU time | 0.41 seconds |
| Started | Jul 29 06:38:11 PM PDT 24 |
| Finished | Jul 29 06:38:11 PM PDT 24 |
| Peak memory | 145340 kb |
| Host | smart-fb865f3f-cc09-4e20-88b5-a74bd479b3ca |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1472276396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1472276396 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2713723691 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30209621 ps |
| CPU time | 0.41 seconds |
| Started | Jul 29 06:38:14 PM PDT 24 |
| Finished | Jul 29 06:38:14 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-e1fb5ad0-a5cb-43e0-9fa2-7e7a128fcebe |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2713723691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2713723691 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2740568195 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29992648 ps |
| CPU time | 0.41 seconds |
| Started | Jul 29 06:38:12 PM PDT 24 |
| Finished | Jul 29 06:38:13 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-a912e2dd-1ad8-4d2d-8613-3ebe89400a1d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2740568195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2740568195 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.6732239 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 28550054 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 06:38:12 PM PDT 24 |
| Finished | Jul 29 06:38:13 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-c3289a23-dfb2-4839-9520-2b8fcb218f2b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=6732239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.6732239 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.510055653 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 26903160 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 06:38:12 PM PDT 24 |
| Finished | Jul 29 06:38:13 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-b9a550af-d502-4751-8e48-72cdada46a6f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=510055653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.510055653 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1578550374 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 32247731 ps |
| CPU time | 0.41 seconds |
| Started | Jul 29 06:38:16 PM PDT 24 |
| Finished | Jul 29 06:38:17 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-cfed7213-1b1a-466e-a97d-8ac2ef26e744 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1578550374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1578550374 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3810688599 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 29486992 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 06:38:13 PM PDT 24 |
| Finished | Jul 29 06:38:14 PM PDT 24 |
| Peak memory | 145336 kb |
| Host | smart-a155bb83-9c42-4e6e-bc78-a1e24465188d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3810688599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3810688599 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4032088452 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 31236667 ps |
| CPU time | 0.41 seconds |
| Started | Jul 29 06:38:21 PM PDT 24 |
| Finished | Jul 29 06:38:21 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-c50c2403-8acd-4597-b061-aad79df3ea8f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4032088452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.4032088452 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.406993010 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30624952 ps |
| CPU time | 0.42 seconds |
| Started | Jul 29 06:38:21 PM PDT 24 |
| Finished | Jul 29 06:38:22 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-d1c845b1-2051-4a34-8f02-7d61bdff5ff9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=406993010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.406993010 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2932036217 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30865542 ps |
| CPU time | 0.42 seconds |
| Started | Jul 29 06:38:17 PM PDT 24 |
| Finished | Jul 29 06:38:17 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-5f3fbef5-c0b4-4a82-b018-00ec48cf1bfa |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2932036217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2932036217 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.947235516 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 28744222 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 06:38:11 PM PDT 24 |
| Finished | Jul 29 06:38:12 PM PDT 24 |
| Peak memory | 145344 kb |
| Host | smart-1bf905fe-8543-4550-beb7-cb69a16335cd |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=947235516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.947235516 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2313090055 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 30348455 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 06:38:10 PM PDT 24 |
| Finished | Jul 29 06:38:10 PM PDT 24 |
| Peak memory | 146408 kb |
| Host | smart-07876da5-c3b3-451e-a9cf-21ac1785f55f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2313090055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2313090055 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1610546290 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 30019457 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 06:38:10 PM PDT 24 |
| Finished | Jul 29 06:38:10 PM PDT 24 |
| Peak memory | 146624 kb |
| Host | smart-d39177b4-bea8-431f-b3f5-308436102cbc |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1610546290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1610546290 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2928235514 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30415474 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 06:38:11 PM PDT 24 |
| Finished | Jul 29 06:38:11 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-0859e9f6-baea-4c41-8937-e0e5abb81a8b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2928235514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2928235514 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4156397233 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 29392154 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 06:38:12 PM PDT 24 |
| Finished | Jul 29 06:38:12 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-fa286a75-42ad-4e3a-a387-9fad6cf999f2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4156397233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.4156397233 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3902864852 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30957857 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 06:38:16 PM PDT 24 |
| Finished | Jul 29 06:38:16 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-266ca351-7242-459f-8eb0-d644c20df300 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3902864852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3902864852 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1701032544 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 31796726 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 06:38:13 PM PDT 24 |
| Finished | Jul 29 06:38:14 PM PDT 24 |
| Peak memory | 145336 kb |
| Host | smart-29543eeb-c3f2-4bba-85c5-95061061e872 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1701032544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1701032544 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.3392645091 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9411154 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 04:44:21 PM PDT 24 |
| Finished | Jul 29 04:44:22 PM PDT 24 |
| Peak memory | 145376 kb |
| Host | smart-fbb62c55-5d1c-4d98-a54f-26dca20b2120 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3392645091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3392645091 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.644030996 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8670824 ps |
| CPU time | 0.37 seconds |
| Started | Jul 29 04:44:19 PM PDT 24 |
| Finished | Jul 29 04:44:19 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-ba326177-a856-441c-aad6-f9a110cc67d5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=644030996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.644030996 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3798615190 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 10103027 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 04:44:25 PM PDT 24 |
| Finished | Jul 29 04:44:25 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-a3c74be3-a7f5-4db7-bc08-d16d093dc32c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3798615190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3798615190 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1324482377 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9084345 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 04:44:22 PM PDT 24 |
| Finished | Jul 29 04:44:22 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-255d6976-87f8-4f04-a877-ca90ae933edf |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1324482377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1324482377 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3055022507 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9710321 ps |
| CPU time | 0.37 seconds |
| Started | Jul 29 04:44:28 PM PDT 24 |
| Finished | Jul 29 04:44:29 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-e306ba5f-01c8-461b-ae24-f2945aa9d42e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3055022507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3055022507 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.39584944 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9322882 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 04:44:23 PM PDT 24 |
| Finished | Jul 29 04:44:24 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-f72365d6-eb37-4dc3-a912-a98b107c3192 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=39584944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.39584944 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1669812725 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 10319960 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 04:44:25 PM PDT 24 |
| Finished | Jul 29 04:44:26 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-6af5c35b-efce-4dee-abcc-e596b258b7f9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1669812725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1669812725 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.3936775932 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 10079076 ps |
| CPU time | 0.42 seconds |
| Started | Jul 29 04:44:25 PM PDT 24 |
| Finished | Jul 29 04:44:26 PM PDT 24 |
| Peak memory | 145396 kb |
| Host | smart-85fb9c02-3d79-4c2a-b7b5-15a8d139c982 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3936775932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3936775932 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.1307532952 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7977611 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 04:44:25 PM PDT 24 |
| Finished | Jul 29 04:44:26 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-d9b32a3f-5308-4944-a3b0-41c7379d3085 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1307532952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1307532952 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.2469430890 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9833542 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 04:44:23 PM PDT 24 |
| Finished | Jul 29 04:44:24 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-837a96e0-0b75-42bc-91a7-88e85274c0c8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2469430890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2469430890 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.3456524574 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 10042833 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 04:44:25 PM PDT 24 |
| Finished | Jul 29 04:44:25 PM PDT 24 |
| Peak memory | 145456 kb |
| Host | smart-4dc61397-5ac8-4f07-ab42-bcaace0b404c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3456524574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3456524574 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.1978958518 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 8291279 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 04:44:22 PM PDT 24 |
| Finished | Jul 29 04:44:23 PM PDT 24 |
| Peak memory | 145384 kb |
| Host | smart-b61be0cc-7c1e-457a-8624-c0b150653fea |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1978958518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1978958518 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.4108719616 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9434715 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 04:44:22 PM PDT 24 |
| Finished | Jul 29 04:44:23 PM PDT 24 |
| Peak memory | 145384 kb |
| Host | smart-3f16953f-bd27-43e0-be2b-e180cac2b183 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4108719616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.4108719616 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.1900053224 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 9584615 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 04:44:24 PM PDT 24 |
| Finished | Jul 29 04:44:25 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-dfb2fe2a-2d3c-4135-89f8-5b90610c372f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1900053224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1900053224 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1879076719 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 9010403 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 04:44:20 PM PDT 24 |
| Finished | Jul 29 04:44:21 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-f695be25-bb86-4c41-a1c5-9cca4e17d76b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1879076719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1879076719 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.331939411 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9459993 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 04:44:23 PM PDT 24 |
| Finished | Jul 29 04:44:28 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-63a31078-fa13-4aba-b843-74b52c9abca3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=331939411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.331939411 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.2745667012 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9840220 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 04:44:21 PM PDT 24 |
| Finished | Jul 29 04:44:21 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-f44b4057-3f7d-4b63-9c9c-738b8d9620be |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2745667012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2745667012 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.2861650387 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9504350 ps |
| CPU time | 0.38 seconds |
| Started | Jul 29 04:44:24 PM PDT 24 |
| Finished | Jul 29 04:44:24 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-52280edb-4ab1-48cb-a4d4-d95d1ec9e00b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2861650387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2861650387 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.2900166538 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 8258757 ps |
| CPU time | 0.36 seconds |
| Started | Jul 29 04:44:24 PM PDT 24 |
| Finished | Jul 29 04:44:24 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-eb8f066b-1541-417f-8513-1306eadde96f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2900166538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2900166538 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1022100132 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 26879234 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 04:49:20 PM PDT 24 |
| Finished | Jul 29 04:49:20 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-fa4f4d13-7540-4666-8306-ccd80f9065f4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1022100132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1022100132 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3796535244 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26270087 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 04:49:18 PM PDT 24 |
| Finished | Jul 29 04:49:18 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-385d15e5-a5b6-49ec-a558-51a0e10f4399 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3796535244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3796535244 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2330969115 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 26592567 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 04:49:15 PM PDT 24 |
| Finished | Jul 29 04:49:15 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-65c9feaf-422d-402d-8b35-ac945c7a35e4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2330969115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2330969115 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1000596779 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28448510 ps |
| CPU time | 0.41 seconds |
| Started | Jul 29 04:49:14 PM PDT 24 |
| Finished | Jul 29 04:49:14 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-06250589-005a-4303-ad37-abad1063a2a7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1000596779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1000596779 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.247536558 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 27597375 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 04:49:17 PM PDT 24 |
| Finished | Jul 29 04:49:18 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-f3005b12-64a9-4389-ae0b-817564f81924 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=247536558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.247536558 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1836104701 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27372785 ps |
| CPU time | 0.41 seconds |
| Started | Jul 29 04:49:09 PM PDT 24 |
| Finished | Jul 29 04:49:10 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-bf0b07de-7611-44f0-b6c4-13d8eb8f7393 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1836104701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1836104701 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.379526645 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26970900 ps |
| CPU time | 0.41 seconds |
| Started | Jul 29 04:49:23 PM PDT 24 |
| Finished | Jul 29 04:49:23 PM PDT 24 |
| Peak memory | 145404 kb |
| Host | smart-9a197f72-0c21-49d1-8a55-808f09f79864 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=379526645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.379526645 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.975501221 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27357365 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 04:49:12 PM PDT 24 |
| Finished | Jul 29 04:49:12 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-63216637-6972-4e06-aefe-377f06a8f17a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=975501221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.975501221 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3073903679 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 29872851 ps |
| CPU time | 0.41 seconds |
| Started | Jul 29 04:49:08 PM PDT 24 |
| Finished | Jul 29 04:49:08 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-e7aa746d-b0d8-4e14-bfad-03b8200c663d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3073903679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3073903679 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3068162658 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 25841971 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 04:49:22 PM PDT 24 |
| Finished | Jul 29 04:49:22 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-239a6cf0-75c0-491c-8455-fb35c0535202 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3068162658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3068162658 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3215761112 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 26830724 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 04:49:02 PM PDT 24 |
| Finished | Jul 29 04:49:02 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-aa019679-5391-470d-8a3b-ed45582f9c5e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3215761112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3215761112 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3575038168 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27518176 ps |
| CPU time | 0.43 seconds |
| Started | Jul 29 04:49:25 PM PDT 24 |
| Finished | Jul 29 04:49:25 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-c4f38ae9-9440-47d0-a701-0a502ee297bd |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3575038168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3575038168 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.478170570 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27583665 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 04:49:23 PM PDT 24 |
| Finished | Jul 29 04:49:23 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-7332b7b8-6d20-4444-b11b-6d9129874e51 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=478170570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.478170570 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1491839950 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 29166659 ps |
| CPU time | 0.44 seconds |
| Started | Jul 29 04:49:26 PM PDT 24 |
| Finished | Jul 29 04:49:26 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-f17818ec-d71b-4eb3-b302-2f494c42f781 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1491839950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1491839950 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.807200773 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 27603532 ps |
| CPU time | 0.43 seconds |
| Started | Jul 29 04:49:20 PM PDT 24 |
| Finished | Jul 29 04:49:21 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-8318159b-9db4-45f4-b1ee-138365e880da |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=807200773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.807200773 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.973712488 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 26493120 ps |
| CPU time | 0.41 seconds |
| Started | Jul 29 04:49:15 PM PDT 24 |
| Finished | Jul 29 04:49:15 PM PDT 24 |
| Peak memory | 145396 kb |
| Host | smart-609d4cf4-c69a-454f-8452-745b7df3c581 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=973712488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.973712488 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.793221496 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27737599 ps |
| CPU time | 0.41 seconds |
| Started | Jul 29 04:49:27 PM PDT 24 |
| Finished | Jul 29 04:49:27 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-2adbe0eb-893a-4750-b332-32e644b7ea92 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=793221496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.793221496 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3604802735 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26437259 ps |
| CPU time | 0.39 seconds |
| Started | Jul 29 04:49:21 PM PDT 24 |
| Finished | Jul 29 04:49:22 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-178881e5-d7cc-4fc8-a6d9-b7d7941bb989 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3604802735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3604802735 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.870065133 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 25773870 ps |
| CPU time | 0.4 seconds |
| Started | Jul 29 04:49:17 PM PDT 24 |
| Finished | Jul 29 04:49:17 PM PDT 24 |
| Peak memory | 145480 kb |
| Host | smart-6b7acf82-ad83-4bf4-ba0a-0861b1dd18c9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=870065133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.870065133 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3036266957 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 27744334 ps |
| CPU time | 0.42 seconds |
| Started | Jul 29 04:49:08 PM PDT 24 |
| Finished | Jul 29 04:49:09 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-22061311-2db8-4c22-8d74-6f3093c872f1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3036266957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3036266957 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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