Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 78
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.92 88.92 100.00 100.00 91.67 91.67 100.00 100.00 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/18.prim_async_alert.3939760617
92.05 3.13 100.00 0.00 91.67 0.00 100.00 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/12.prim_sync_alert.777737278
94.15 2.11 100.00 0.00 93.75 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3366749882
94.50 0.35 100.00 0.00 95.83 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/14.prim_async_alert.1875130533
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1043324541
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/17.prim_sync_alert.3158426674

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2508590196
/workspace/coverage/default/1.prim_async_alert.2044892145
/workspace/coverage/default/10.prim_async_alert.3679759836
/workspace/coverage/default/11.prim_async_alert.3750742832
/workspace/coverage/default/12.prim_async_alert.1114464456
/workspace/coverage/default/13.prim_async_alert.2928601471
/workspace/coverage/default/15.prim_async_alert.77688368
/workspace/coverage/default/16.prim_async_alert.531014184
/workspace/coverage/default/17.prim_async_alert.1860707348
/workspace/coverage/default/19.prim_async_alert.2078473378
/workspace/coverage/default/2.prim_async_alert.2516033235
/workspace/coverage/default/3.prim_async_alert.1384746814
/workspace/coverage/default/4.prim_async_alert.2452622833
/workspace/coverage/default/5.prim_async_alert.1081835192
/workspace/coverage/default/6.prim_async_alert.596497284
/workspace/coverage/default/7.prim_async_alert.3782857794
/workspace/coverage/default/8.prim_async_alert.1105824563
/workspace/coverage/default/9.prim_async_alert.4207840204
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.374804246
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3136968119
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.329529909
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3878345533
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3081771812
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2470419828
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1230630249
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.206826401
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1719584427
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.206709815
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.246720074
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.61187516
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1646771362
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2303889721
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4255459614
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2052724371
/workspace/coverage/sync_alert/0.prim_sync_alert.2758041520
/workspace/coverage/sync_alert/1.prim_sync_alert.4193769043
/workspace/coverage/sync_alert/10.prim_sync_alert.3538642603
/workspace/coverage/sync_alert/11.prim_sync_alert.2832112959
/workspace/coverage/sync_alert/13.prim_sync_alert.1654299047
/workspace/coverage/sync_alert/14.prim_sync_alert.767801081
/workspace/coverage/sync_alert/15.prim_sync_alert.4105458873
/workspace/coverage/sync_alert/16.prim_sync_alert.4027035238
/workspace/coverage/sync_alert/18.prim_sync_alert.2698018946
/workspace/coverage/sync_alert/19.prim_sync_alert.2876890
/workspace/coverage/sync_alert/2.prim_sync_alert.4266700368
/workspace/coverage/sync_alert/3.prim_sync_alert.209921020
/workspace/coverage/sync_alert/4.prim_sync_alert.1196924265
/workspace/coverage/sync_alert/5.prim_sync_alert.3691404134
/workspace/coverage/sync_alert/6.prim_sync_alert.1478686210
/workspace/coverage/sync_alert/7.prim_sync_alert.1359559159
/workspace/coverage/sync_alert/8.prim_sync_alert.3896947982
/workspace/coverage/sync_alert/9.prim_sync_alert.3647123667
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2101847167
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3635119583
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2015842285
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.342376099
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3942553174
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2764556690
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2521573346
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4010866360
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1025597587
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.446184832
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1597704350
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.497337320
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.479968602
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1470280709
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2997280534
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.256079564
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1187063817
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2080873222
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.561790673
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1462646111



Total test records in report: 78
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/5.prim_async_alert.1081835192 Jul 30 05:56:40 PM PDT 24 Jul 30 05:56:41 PM PDT 24 11236234 ps
T2 /workspace/coverage/default/7.prim_async_alert.3782857794 Jul 30 05:56:37 PM PDT 24 Jul 30 05:56:37 PM PDT 24 11786222 ps
T3 /workspace/coverage/default/0.prim_async_alert.2508590196 Jul 30 05:56:38 PM PDT 24 Jul 30 05:56:38 PM PDT 24 11208204 ps
T13 /workspace/coverage/default/18.prim_async_alert.3939760617 Jul 30 05:56:42 PM PDT 24 Jul 30 05:56:42 PM PDT 24 12163041 ps
T20 /workspace/coverage/default/4.prim_async_alert.2452622833 Jul 30 05:56:40 PM PDT 24 Jul 30 05:56:40 PM PDT 24 10536025 ps
T21 /workspace/coverage/default/10.prim_async_alert.3679759836 Jul 30 05:56:40 PM PDT 24 Jul 30 05:56:40 PM PDT 24 11186315 ps
T7 /workspace/coverage/default/9.prim_async_alert.4207840204 Jul 30 05:56:39 PM PDT 24 Jul 30 05:56:40 PM PDT 24 12294643 ps
T22 /workspace/coverage/default/13.prim_async_alert.2928601471 Jul 30 05:56:41 PM PDT 24 Jul 30 05:56:41 PM PDT 24 11227291 ps
T8 /workspace/coverage/default/14.prim_async_alert.1875130533 Jul 30 05:56:41 PM PDT 24 Jul 30 05:56:42 PM PDT 24 11246009 ps
T23 /workspace/coverage/default/17.prim_async_alert.1860707348 Jul 30 05:56:39 PM PDT 24 Jul 30 05:56:39 PM PDT 24 10284045 ps
T24 /workspace/coverage/default/11.prim_async_alert.3750742832 Jul 30 05:56:37 PM PDT 24 Jul 30 05:56:37 PM PDT 24 11421873 ps
T9 /workspace/coverage/default/3.prim_async_alert.1384746814 Jul 30 05:56:40 PM PDT 24 Jul 30 05:56:40 PM PDT 24 11012418 ps
T47 /workspace/coverage/default/6.prim_async_alert.596497284 Jul 30 05:56:38 PM PDT 24 Jul 30 05:56:39 PM PDT 24 11661199 ps
T17 /workspace/coverage/default/1.prim_async_alert.2044892145 Jul 30 05:56:38 PM PDT 24 Jul 30 05:56:38 PM PDT 24 11878064 ps
T16 /workspace/coverage/default/2.prim_async_alert.2516033235 Jul 30 05:56:37 PM PDT 24 Jul 30 05:56:37 PM PDT 24 11267510 ps
T10 /workspace/coverage/default/15.prim_async_alert.77688368 Jul 30 05:56:39 PM PDT 24 Jul 30 05:56:40 PM PDT 24 11010789 ps
T18 /workspace/coverage/default/19.prim_async_alert.2078473378 Jul 30 05:56:42 PM PDT 24 Jul 30 05:56:42 PM PDT 24 10677897 ps
T19 /workspace/coverage/default/16.prim_async_alert.531014184 Jul 30 05:56:44 PM PDT 24 Jul 30 05:56:44 PM PDT 24 10850556 ps
T25 /workspace/coverage/default/8.prim_async_alert.1105824563 Jul 30 05:56:39 PM PDT 24 Jul 30 05:56:40 PM PDT 24 11194295 ps
T11 /workspace/coverage/default/12.prim_async_alert.1114464456 Jul 30 05:56:36 PM PDT 24 Jul 30 05:56:37 PM PDT 24 12054241 ps
T4 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1043324541 Jul 30 06:38:56 PM PDT 24 Jul 30 06:38:57 PM PDT 24 28346170 ps
T26 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.329529909 Jul 30 06:38:52 PM PDT 24 Jul 30 06:38:52 PM PDT 24 29765285 ps
T41 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1719584427 Jul 30 06:38:56 PM PDT 24 Jul 30 06:38:57 PM PDT 24 30327777 ps
T42 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2303889721 Jul 30 06:39:02 PM PDT 24 Jul 30 06:39:02 PM PDT 24 31262593 ps
T43 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4255459614 Jul 30 06:38:56 PM PDT 24 Jul 30 06:38:56 PM PDT 24 29572123 ps
T14 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3366749882 Jul 30 06:39:07 PM PDT 24 Jul 30 06:39:07 PM PDT 24 29631555 ps
T44 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.374804246 Jul 30 06:39:09 PM PDT 24 Jul 30 06:39:10 PM PDT 24 30321039 ps
T5 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3878345533 Jul 30 06:38:54 PM PDT 24 Jul 30 06:38:55 PM PDT 24 29233349 ps
T45 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1646771362 Jul 30 06:38:58 PM PDT 24 Jul 30 06:38:59 PM PDT 24 30924432 ps
T46 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3081771812 Jul 30 06:38:56 PM PDT 24 Jul 30 06:38:57 PM PDT 24 30323700 ps
T48 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1230630249 Jul 30 06:38:59 PM PDT 24 Jul 30 06:38:59 PM PDT 24 31687919 ps
T49 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.246720074 Jul 30 06:39:00 PM PDT 24 Jul 30 06:39:00 PM PDT 24 30764662 ps
T50 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2470419828 Jul 30 06:39:00 PM PDT 24 Jul 30 06:39:00 PM PDT 24 30001869 ps
T51 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3136968119 Jul 30 06:38:52 PM PDT 24 Jul 30 06:38:52 PM PDT 24 29849344 ps
T15 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2052724371 Jul 30 06:39:04 PM PDT 24 Jul 30 06:39:05 PM PDT 24 31780248 ps
T52 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.61187516 Jul 30 06:38:53 PM PDT 24 Jul 30 06:38:53 PM PDT 24 30015857 ps
T53 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.206709815 Jul 30 06:38:53 PM PDT 24 Jul 30 06:38:53 PM PDT 24 32069171 ps
T54 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.206826401 Jul 30 06:39:05 PM PDT 24 Jul 30 06:39:06 PM PDT 24 30946244 ps
T27 /workspace/coverage/sync_alert/2.prim_sync_alert.4266700368 Jul 30 06:40:03 PM PDT 24 Jul 30 06:40:03 PM PDT 24 9623642 ps
T37 /workspace/coverage/sync_alert/12.prim_sync_alert.777737278 Jul 30 06:40:16 PM PDT 24 Jul 30 06:40:16 PM PDT 24 8645671 ps
T28 /workspace/coverage/sync_alert/7.prim_sync_alert.1359559159 Jul 30 06:40:07 PM PDT 24 Jul 30 06:40:07 PM PDT 24 8500242 ps
T29 /workspace/coverage/sync_alert/1.prim_sync_alert.4193769043 Jul 30 06:40:03 PM PDT 24 Jul 30 06:40:03 PM PDT 24 10518149 ps
T38 /workspace/coverage/sync_alert/11.prim_sync_alert.2832112959 Jul 30 06:40:16 PM PDT 24 Jul 30 06:40:16 PM PDT 24 8934664 ps
T30 /workspace/coverage/sync_alert/3.prim_sync_alert.209921020 Jul 30 06:40:02 PM PDT 24 Jul 30 06:40:02 PM PDT 24 8396146 ps
T39 /workspace/coverage/sync_alert/10.prim_sync_alert.3538642603 Jul 30 06:40:07 PM PDT 24 Jul 30 06:40:07 PM PDT 24 8899551 ps
T31 /workspace/coverage/sync_alert/8.prim_sync_alert.3896947982 Jul 30 06:40:09 PM PDT 24 Jul 30 06:40:09 PM PDT 24 9385797 ps
T32 /workspace/coverage/sync_alert/16.prim_sync_alert.4027035238 Jul 30 06:40:18 PM PDT 24 Jul 30 06:40:18 PM PDT 24 9222419 ps
T40 /workspace/coverage/sync_alert/14.prim_sync_alert.767801081 Jul 30 06:40:10 PM PDT 24 Jul 30 06:40:10 PM PDT 24 8993013 ps
T55 /workspace/coverage/sync_alert/9.prim_sync_alert.3647123667 Jul 30 06:40:09 PM PDT 24 Jul 30 06:40:09 PM PDT 24 10192346 ps
T56 /workspace/coverage/sync_alert/13.prim_sync_alert.1654299047 Jul 30 06:40:16 PM PDT 24 Jul 30 06:40:16 PM PDT 24 10707616 ps
T57 /workspace/coverage/sync_alert/19.prim_sync_alert.2876890 Jul 30 06:40:20 PM PDT 24 Jul 30 06:40:21 PM PDT 24 9354739 ps
T58 /workspace/coverage/sync_alert/15.prim_sync_alert.4105458873 Jul 30 06:40:16 PM PDT 24 Jul 30 06:40:16 PM PDT 24 9579573 ps
T33 /workspace/coverage/sync_alert/0.prim_sync_alert.2758041520 Jul 30 06:40:02 PM PDT 24 Jul 30 06:40:02 PM PDT 24 9143746 ps
T59 /workspace/coverage/sync_alert/4.prim_sync_alert.1196924265 Jul 30 06:40:04 PM PDT 24 Jul 30 06:40:04 PM PDT 24 10070371 ps
T60 /workspace/coverage/sync_alert/18.prim_sync_alert.2698018946 Jul 30 06:40:20 PM PDT 24 Jul 30 06:40:21 PM PDT 24 9120358 ps
T34 /workspace/coverage/sync_alert/5.prim_sync_alert.3691404134 Jul 30 06:40:03 PM PDT 24 Jul 30 06:40:04 PM PDT 24 9761254 ps
T35 /workspace/coverage/sync_alert/6.prim_sync_alert.1478686210 Jul 30 06:40:16 PM PDT 24 Jul 30 06:40:16 PM PDT 24 8151134 ps
T12 /workspace/coverage/sync_alert/17.prim_sync_alert.3158426674 Jul 30 06:40:12 PM PDT 24 Jul 30 06:40:13 PM PDT 24 10024472 ps
T61 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2015842285 Jul 30 05:56:45 PM PDT 24 Jul 30 05:56:45 PM PDT 24 28537233 ps
T6 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4010866360 Jul 30 05:56:49 PM PDT 24 Jul 30 05:56:50 PM PDT 24 30200915 ps
T36 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2764556690 Jul 30 05:56:48 PM PDT 24 Jul 30 05:56:49 PM PDT 24 29227858 ps
T62 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1597704350 Jul 30 05:56:46 PM PDT 24 Jul 30 05:56:46 PM PDT 24 28742311 ps
T63 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3942553174 Jul 30 05:56:49 PM PDT 24 Jul 30 05:56:49 PM PDT 24 27012642 ps
T64 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.446184832 Jul 30 05:56:47 PM PDT 24 Jul 30 05:56:48 PM PDT 24 28503893 ps
T65 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.479968602 Jul 30 05:56:44 PM PDT 24 Jul 30 05:56:44 PM PDT 24 25842362 ps
T66 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2101847167 Jul 30 05:56:41 PM PDT 24 Jul 30 05:56:41 PM PDT 24 27127542 ps
T67 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3635119583 Jul 30 05:56:42 PM PDT 24 Jul 30 05:56:42 PM PDT 24 27310361 ps
T68 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1187063817 Jul 30 05:56:42 PM PDT 24 Jul 30 05:56:43 PM PDT 24 26652716 ps
T69 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1025597587 Jul 30 05:56:46 PM PDT 24 Jul 30 05:56:46 PM PDT 24 27759230 ps
T70 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1470280709 Jul 30 05:56:39 PM PDT 24 Jul 30 05:56:40 PM PDT 24 27821684 ps
T71 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.256079564 Jul 30 05:56:40 PM PDT 24 Jul 30 05:56:40 PM PDT 24 26781008 ps
T72 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.497337320 Jul 30 05:56:47 PM PDT 24 Jul 30 05:56:47 PM PDT 24 29449519 ps
T73 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1462646111 Jul 30 05:56:47 PM PDT 24 Jul 30 05:56:48 PM PDT 24 28569051 ps
T74 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2997280534 Jul 30 05:56:42 PM PDT 24 Jul 30 05:56:42 PM PDT 24 27102075 ps
T75 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.342376099 Jul 30 05:56:44 PM PDT 24 Jul 30 05:56:45 PM PDT 24 26664044 ps
T76 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2080873222 Jul 30 05:56:41 PM PDT 24 Jul 30 05:56:41 PM PDT 24 27644305 ps
T77 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.561790673 Jul 30 05:56:40 PM PDT 24 Jul 30 05:56:41 PM PDT 24 26795064 ps
T78 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2521573346 Jul 30 05:56:46 PM PDT 24 Jul 30 05:56:47 PM PDT 24 28204974 ps

Test location /workspace/coverage/default/18.prim_async_alert.3939760617
Short name T13
Test name
Test status
Simulation time 12163041 ps
CPU time 0.44 seconds
Started Jul 30 05:56:42 PM PDT 24
Finished Jul 30 05:56:42 PM PDT 24
Peak memory 145760 kb
Host smart-925fdd5a-eb50-40f2-8f7b-bd9c0e86d755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939760617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3939760617
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.777737278
Short name T37
Test name
Test status
Simulation time 8645671 ps
CPU time 0.37 seconds
Started Jul 30 06:40:16 PM PDT 24
Finished Jul 30 06:40:16 PM PDT 24
Peak memory 145560 kb
Host smart-6f7e2174-f7a3-49d8-9261-bb439080356a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=777737278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.777737278
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3366749882
Short name T14
Test name
Test status
Simulation time 29631555 ps
CPU time 0.4 seconds
Started Jul 30 06:39:07 PM PDT 24
Finished Jul 30 06:39:07 PM PDT 24
Peak memory 145176 kb
Host smart-0bffe777-4470-4bb6-ba82-dee73f3cefb6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3366749882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3366749882
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1875130533
Short name T8
Test name
Test status
Simulation time 11246009 ps
CPU time 0.39 seconds
Started Jul 30 05:56:41 PM PDT 24
Finished Jul 30 05:56:42 PM PDT 24
Peak memory 145804 kb
Host smart-c3ec5548-3e7e-4c47-9fa7-414663b214d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875130533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1875130533
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1043324541
Short name T4
Test name
Test status
Simulation time 28346170 ps
CPU time 0.4 seconds
Started Jul 30 06:38:56 PM PDT 24
Finished Jul 30 06:38:57 PM PDT 24
Peak memory 145364 kb
Host smart-3582d4b2-9989-4a79-8fd9-b295da3da588
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1043324541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1043324541
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3158426674
Short name T12
Test name
Test status
Simulation time 10024472 ps
CPU time 0.39 seconds
Started Jul 30 06:40:12 PM PDT 24
Finished Jul 30 06:40:13 PM PDT 24
Peak memory 145600 kb
Host smart-d9872a49-7bab-471a-8c7d-08b88eb77b9c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3158426674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3158426674
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2508590196
Short name T3
Test name
Test status
Simulation time 11208204 ps
CPU time 0.38 seconds
Started Jul 30 05:56:38 PM PDT 24
Finished Jul 30 05:56:38 PM PDT 24
Peak memory 145816 kb
Host smart-aa47d0a8-d140-4bab-813a-a06c40e511ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508590196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2508590196
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2044892145
Short name T17
Test name
Test status
Simulation time 11878064 ps
CPU time 0.38 seconds
Started Jul 30 05:56:38 PM PDT 24
Finished Jul 30 05:56:38 PM PDT 24
Peak memory 145844 kb
Host smart-ecc9c09c-e842-4741-90e2-807a2ef7a3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044892145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2044892145
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3679759836
Short name T21
Test name
Test status
Simulation time 11186315 ps
CPU time 0.38 seconds
Started Jul 30 05:56:40 PM PDT 24
Finished Jul 30 05:56:40 PM PDT 24
Peak memory 145860 kb
Host smart-a6ec5d06-82cd-4738-98b5-e1f1f71bb722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679759836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3679759836
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3750742832
Short name T24
Test name
Test status
Simulation time 11421873 ps
CPU time 0.4 seconds
Started Jul 30 05:56:37 PM PDT 24
Finished Jul 30 05:56:37 PM PDT 24
Peak memory 145836 kb
Host smart-688952c2-189a-43f3-988a-2a84b10eaf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750742832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3750742832
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1114464456
Short name T11
Test name
Test status
Simulation time 12054241 ps
CPU time 0.38 seconds
Started Jul 30 05:56:36 PM PDT 24
Finished Jul 30 05:56:37 PM PDT 24
Peak memory 145800 kb
Host smart-ca2391df-5cca-48b9-998e-3c556ade94a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114464456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1114464456
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2928601471
Short name T22
Test name
Test status
Simulation time 11227291 ps
CPU time 0.4 seconds
Started Jul 30 05:56:41 PM PDT 24
Finished Jul 30 05:56:41 PM PDT 24
Peak memory 145848 kb
Host smart-71a3c2ba-85c2-4354-aa0d-9ea7fe13680e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928601471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2928601471
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.77688368
Short name T10
Test name
Test status
Simulation time 11010789 ps
CPU time 0.39 seconds
Started Jul 30 05:56:39 PM PDT 24
Finished Jul 30 05:56:40 PM PDT 24
Peak memory 145652 kb
Host smart-2df0e04c-95d7-4e19-8dde-e395d82fd39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77688368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.77688368
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.531014184
Short name T19
Test name
Test status
Simulation time 10850556 ps
CPU time 0.39 seconds
Started Jul 30 05:56:44 PM PDT 24
Finished Jul 30 05:56:44 PM PDT 24
Peak memory 145792 kb
Host smart-35c55bbf-a292-487c-a666-616bc16bc415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531014184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.531014184
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1860707348
Short name T23
Test name
Test status
Simulation time 10284045 ps
CPU time 0.38 seconds
Started Jul 30 05:56:39 PM PDT 24
Finished Jul 30 05:56:39 PM PDT 24
Peak memory 145840 kb
Host smart-51900d97-4a49-468d-89af-8d90512ad116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860707348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1860707348
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2078473378
Short name T18
Test name
Test status
Simulation time 10677897 ps
CPU time 0.4 seconds
Started Jul 30 05:56:42 PM PDT 24
Finished Jul 30 05:56:42 PM PDT 24
Peak memory 145784 kb
Host smart-87d97702-6c04-40fc-8e64-cf8a80946a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078473378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2078473378
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2516033235
Short name T16
Test name
Test status
Simulation time 11267510 ps
CPU time 0.42 seconds
Started Jul 30 05:56:37 PM PDT 24
Finished Jul 30 05:56:37 PM PDT 24
Peak memory 145832 kb
Host smart-2eacfbc2-f927-42a9-ab20-8120a6f26f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516033235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2516033235
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1384746814
Short name T9
Test name
Test status
Simulation time 11012418 ps
CPU time 0.4 seconds
Started Jul 30 05:56:40 PM PDT 24
Finished Jul 30 05:56:40 PM PDT 24
Peak memory 145800 kb
Host smart-b6732941-036a-4cb3-8ad6-1313e2628ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384746814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1384746814
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2452622833
Short name T20
Test name
Test status
Simulation time 10536025 ps
CPU time 0.4 seconds
Started Jul 30 05:56:40 PM PDT 24
Finished Jul 30 05:56:40 PM PDT 24
Peak memory 145848 kb
Host smart-d2488fe9-e407-412a-9f87-76c6cb46cee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452622833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2452622833
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1081835192
Short name T1
Test name
Test status
Simulation time 11236234 ps
CPU time 0.41 seconds
Started Jul 30 05:56:40 PM PDT 24
Finished Jul 30 05:56:41 PM PDT 24
Peak memory 145804 kb
Host smart-614f9593-d247-4481-bc30-406ec9e12c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081835192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1081835192
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.596497284
Short name T47
Test name
Test status
Simulation time 11661199 ps
CPU time 0.4 seconds
Started Jul 30 05:56:38 PM PDT 24
Finished Jul 30 05:56:39 PM PDT 24
Peak memory 145820 kb
Host smart-cd2d4736-9db3-451d-9c9e-d4c3be4555f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596497284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.596497284
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3782857794
Short name T2
Test name
Test status
Simulation time 11786222 ps
CPU time 0.42 seconds
Started Jul 30 05:56:37 PM PDT 24
Finished Jul 30 05:56:37 PM PDT 24
Peak memory 145792 kb
Host smart-e27d9522-87ee-4981-8c2e-5c21134c45d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782857794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3782857794
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1105824563
Short name T25
Test name
Test status
Simulation time 11194295 ps
CPU time 0.43 seconds
Started Jul 30 05:56:39 PM PDT 24
Finished Jul 30 05:56:40 PM PDT 24
Peak memory 145788 kb
Host smart-a47a24c0-87aa-47e8-ba29-cb35d999a32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105824563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1105824563
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.4207840204
Short name T7
Test name
Test status
Simulation time 12294643 ps
CPU time 0.4 seconds
Started Jul 30 05:56:39 PM PDT 24
Finished Jul 30 05:56:40 PM PDT 24
Peak memory 145796 kb
Host smart-4559dc9a-8912-448e-82d5-b0b9d988013d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207840204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.4207840204
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.374804246
Short name T44
Test name
Test status
Simulation time 30321039 ps
CPU time 0.41 seconds
Started Jul 30 06:39:09 PM PDT 24
Finished Jul 30 06:39:10 PM PDT 24
Peak memory 145376 kb
Host smart-2720c27b-bd9b-4bde-b9b7-1d26c37d21d6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=374804246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.374804246
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3136968119
Short name T51
Test name
Test status
Simulation time 29849344 ps
CPU time 0.39 seconds
Started Jul 30 06:38:52 PM PDT 24
Finished Jul 30 06:38:52 PM PDT 24
Peak memory 145320 kb
Host smart-ecb109da-d934-48b5-a81e-9e9159b74526
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3136968119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3136968119
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.329529909
Short name T26
Test name
Test status
Simulation time 29765285 ps
CPU time 0.4 seconds
Started Jul 30 06:38:52 PM PDT 24
Finished Jul 30 06:38:52 PM PDT 24
Peak memory 145352 kb
Host smart-7151c615-7261-4218-92e8-bb904ed4c35c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=329529909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.329529909
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3878345533
Short name T5
Test name
Test status
Simulation time 29233349 ps
CPU time 0.39 seconds
Started Jul 30 06:38:54 PM PDT 24
Finished Jul 30 06:38:55 PM PDT 24
Peak memory 145312 kb
Host smart-be2a4772-e486-4586-8183-0a3e80785578
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3878345533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3878345533
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3081771812
Short name T46
Test name
Test status
Simulation time 30323700 ps
CPU time 0.43 seconds
Started Jul 30 06:38:56 PM PDT 24
Finished Jul 30 06:38:57 PM PDT 24
Peak memory 145312 kb
Host smart-c61ef7de-2618-4f62-98ea-08660ebe39db
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3081771812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3081771812
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2470419828
Short name T50
Test name
Test status
Simulation time 30001869 ps
CPU time 0.41 seconds
Started Jul 30 06:39:00 PM PDT 24
Finished Jul 30 06:39:00 PM PDT 24
Peak memory 145372 kb
Host smart-a1703cb7-bf41-4f7b-929b-dbc92a097741
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2470419828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2470419828
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1230630249
Short name T48
Test name
Test status
Simulation time 31687919 ps
CPU time 0.42 seconds
Started Jul 30 06:38:59 PM PDT 24
Finished Jul 30 06:38:59 PM PDT 24
Peak memory 145340 kb
Host smart-7a8333c5-55c3-408a-8c97-8dd135bdd485
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1230630249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1230630249
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.206826401
Short name T54
Test name
Test status
Simulation time 30946244 ps
CPU time 0.4 seconds
Started Jul 30 06:39:05 PM PDT 24
Finished Jul 30 06:39:06 PM PDT 24
Peak memory 145336 kb
Host smart-9d8dbf82-7fb3-42d0-a77d-27899c97705f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=206826401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.206826401
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1719584427
Short name T41
Test name
Test status
Simulation time 30327777 ps
CPU time 0.39 seconds
Started Jul 30 06:38:56 PM PDT 24
Finished Jul 30 06:38:57 PM PDT 24
Peak memory 145352 kb
Host smart-7db5bf73-615e-40a1-ad66-749b05ccb842
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1719584427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1719584427
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.206709815
Short name T53
Test name
Test status
Simulation time 32069171 ps
CPU time 0.41 seconds
Started Jul 30 06:38:53 PM PDT 24
Finished Jul 30 06:38:53 PM PDT 24
Peak memory 145360 kb
Host smart-a097b3a6-aedd-4cf1-beb6-2ca469396a6b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=206709815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.206709815
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.246720074
Short name T49
Test name
Test status
Simulation time 30764662 ps
CPU time 0.41 seconds
Started Jul 30 06:39:00 PM PDT 24
Finished Jul 30 06:39:00 PM PDT 24
Peak memory 145332 kb
Host smart-c858a409-a8fb-4b35-8cb4-4eaee67613db
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=246720074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.246720074
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.61187516
Short name T52
Test name
Test status
Simulation time 30015857 ps
CPU time 0.42 seconds
Started Jul 30 06:38:53 PM PDT 24
Finished Jul 30 06:38:53 PM PDT 24
Peak memory 145384 kb
Host smart-443bfc0a-3c5c-44c1-a18b-c5abb95a92a5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=61187516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.61187516
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1646771362
Short name T45
Test name
Test status
Simulation time 30924432 ps
CPU time 0.39 seconds
Started Jul 30 06:38:58 PM PDT 24
Finished Jul 30 06:38:59 PM PDT 24
Peak memory 145316 kb
Host smart-f456c5dc-f750-45f2-b1d9-9ef18a8f26c4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1646771362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1646771362
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2303889721
Short name T42
Test name
Test status
Simulation time 31262593 ps
CPU time 0.39 seconds
Started Jul 30 06:39:02 PM PDT 24
Finished Jul 30 06:39:02 PM PDT 24
Peak memory 145316 kb
Host smart-5558c7cb-3bb7-4839-a46e-5fc7788b80b5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2303889721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2303889721
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4255459614
Short name T43
Test name
Test status
Simulation time 29572123 ps
CPU time 0.4 seconds
Started Jul 30 06:38:56 PM PDT 24
Finished Jul 30 06:38:56 PM PDT 24
Peak memory 145340 kb
Host smart-30ab6079-9d59-41cd-9f4d-a2c4e8fdfb86
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4255459614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.4255459614
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2052724371
Short name T15
Test name
Test status
Simulation time 31780248 ps
CPU time 0.41 seconds
Started Jul 30 06:39:04 PM PDT 24
Finished Jul 30 06:39:05 PM PDT 24
Peak memory 145388 kb
Host smart-d996c0fd-16e9-4d47-8564-9b4c5bd388a0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2052724371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2052724371
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2758041520
Short name T33
Test name
Test status
Simulation time 9143746 ps
CPU time 0.38 seconds
Started Jul 30 06:40:02 PM PDT 24
Finished Jul 30 06:40:02 PM PDT 24
Peak memory 145584 kb
Host smart-b4658a0a-ba07-46e4-a873-8f9f729a8d86
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2758041520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2758041520
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.4193769043
Short name T29
Test name
Test status
Simulation time 10518149 ps
CPU time 0.4 seconds
Started Jul 30 06:40:03 PM PDT 24
Finished Jul 30 06:40:03 PM PDT 24
Peak memory 145584 kb
Host smart-6957a576-eb03-47dc-b187-fbe75913d5ea
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4193769043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.4193769043
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3538642603
Short name T39
Test name
Test status
Simulation time 8899551 ps
CPU time 0.41 seconds
Started Jul 30 06:40:07 PM PDT 24
Finished Jul 30 06:40:07 PM PDT 24
Peak memory 145600 kb
Host smart-a67e30dd-4668-426e-9ef2-ac20defd0eed
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3538642603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3538642603
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2832112959
Short name T38
Test name
Test status
Simulation time 8934664 ps
CPU time 0.38 seconds
Started Jul 30 06:40:16 PM PDT 24
Finished Jul 30 06:40:16 PM PDT 24
Peak memory 145564 kb
Host smart-d53e3035-23b5-4996-b500-72b2242f3085
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2832112959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2832112959
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1654299047
Short name T56
Test name
Test status
Simulation time 10707616 ps
CPU time 0.37 seconds
Started Jul 30 06:40:16 PM PDT 24
Finished Jul 30 06:40:16 PM PDT 24
Peak memory 145564 kb
Host smart-88f36361-f765-43a5-a7ba-669917e44680
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1654299047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1654299047
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.767801081
Short name T40
Test name
Test status
Simulation time 8993013 ps
CPU time 0.39 seconds
Started Jul 30 06:40:10 PM PDT 24
Finished Jul 30 06:40:10 PM PDT 24
Peak memory 145588 kb
Host smart-1f55de6b-8e03-4127-aaca-ac923ea03845
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=767801081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.767801081
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.4105458873
Short name T58
Test name
Test status
Simulation time 9579573 ps
CPU time 0.38 seconds
Started Jul 30 06:40:16 PM PDT 24
Finished Jul 30 06:40:16 PM PDT 24
Peak memory 145564 kb
Host smart-210a2fea-e1a9-4765-a4ab-7ecb21755e56
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4105458873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.4105458873
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.4027035238
Short name T32
Test name
Test status
Simulation time 9222419 ps
CPU time 0.38 seconds
Started Jul 30 06:40:18 PM PDT 24
Finished Jul 30 06:40:18 PM PDT 24
Peak memory 145620 kb
Host smart-80a085af-b325-430f-ba0b-498016edb2ca
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4027035238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.4027035238
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2698018946
Short name T60
Test name
Test status
Simulation time 9120358 ps
CPU time 0.39 seconds
Started Jul 30 06:40:20 PM PDT 24
Finished Jul 30 06:40:21 PM PDT 24
Peak memory 145596 kb
Host smart-71a9d62b-d4fa-4296-ad6e-d1889a7fffe1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2698018946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2698018946
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2876890
Short name T57
Test name
Test status
Simulation time 9354739 ps
CPU time 0.39 seconds
Started Jul 30 06:40:20 PM PDT 24
Finished Jul 30 06:40:21 PM PDT 24
Peak memory 145608 kb
Host smart-e12bb661-71c8-4968-b1f7-44190a76155b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2876890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2876890
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.4266700368
Short name T27
Test name
Test status
Simulation time 9623642 ps
CPU time 0.41 seconds
Started Jul 30 06:40:03 PM PDT 24
Finished Jul 30 06:40:03 PM PDT 24
Peak memory 145608 kb
Host smart-e19c4dd4-016d-4a65-8361-66961990ef3b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4266700368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.4266700368
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.209921020
Short name T30
Test name
Test status
Simulation time 8396146 ps
CPU time 0.39 seconds
Started Jul 30 06:40:02 PM PDT 24
Finished Jul 30 06:40:02 PM PDT 24
Peak memory 145632 kb
Host smart-0350690e-d561-4d9d-ab6c-820fe045d6d2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=209921020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.209921020
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1196924265
Short name T59
Test name
Test status
Simulation time 10070371 ps
CPU time 0.38 seconds
Started Jul 30 06:40:04 PM PDT 24
Finished Jul 30 06:40:04 PM PDT 24
Peak memory 145624 kb
Host smart-9a9d6f4d-dd65-4e8e-afe8-e79055e45ffc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1196924265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1196924265
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3691404134
Short name T34
Test name
Test status
Simulation time 9761254 ps
CPU time 0.41 seconds
Started Jul 30 06:40:03 PM PDT 24
Finished Jul 30 06:40:04 PM PDT 24
Peak memory 145660 kb
Host smart-976078bb-e04c-445b-af56-9bbd0c795f0c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3691404134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3691404134
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1478686210
Short name T35
Test name
Test status
Simulation time 8151134 ps
CPU time 0.38 seconds
Started Jul 30 06:40:16 PM PDT 24
Finished Jul 30 06:40:16 PM PDT 24
Peak memory 145568 kb
Host smart-3d981504-94f9-4c59-afb8-2348ff54a74c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1478686210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1478686210
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1359559159
Short name T28
Test name
Test status
Simulation time 8500242 ps
CPU time 0.38 seconds
Started Jul 30 06:40:07 PM PDT 24
Finished Jul 30 06:40:07 PM PDT 24
Peak memory 145584 kb
Host smart-a8b67ba1-ac9c-4377-915c-323c90db9527
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1359559159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1359559159
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.3896947982
Short name T31
Test name
Test status
Simulation time 9385797 ps
CPU time 0.38 seconds
Started Jul 30 06:40:09 PM PDT 24
Finished Jul 30 06:40:09 PM PDT 24
Peak memory 145632 kb
Host smart-27688b86-35a3-4ce3-8442-38e2724b2f59
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3896947982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3896947982
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3647123667
Short name T55
Test name
Test status
Simulation time 10192346 ps
CPU time 0.39 seconds
Started Jul 30 06:40:09 PM PDT 24
Finished Jul 30 06:40:09 PM PDT 24
Peak memory 145640 kb
Host smart-09e8700d-c949-4f41-9918-ab80b041d300
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3647123667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3647123667
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2101847167
Short name T66
Test name
Test status
Simulation time 27127542 ps
CPU time 0.44 seconds
Started Jul 30 05:56:41 PM PDT 24
Finished Jul 30 05:56:41 PM PDT 24
Peak memory 145516 kb
Host smart-e9fcab0e-b94c-4e8c-a86c-68f6466fb245
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2101847167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2101847167
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3635119583
Short name T67
Test name
Test status
Simulation time 27310361 ps
CPU time 0.41 seconds
Started Jul 30 05:56:42 PM PDT 24
Finished Jul 30 05:56:42 PM PDT 24
Peak memory 145660 kb
Host smart-ac3baa80-9a41-45d4-a3be-d6efe64cb8d2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3635119583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3635119583
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2015842285
Short name T61
Test name
Test status
Simulation time 28537233 ps
CPU time 0.43 seconds
Started Jul 30 05:56:45 PM PDT 24
Finished Jul 30 05:56:45 PM PDT 24
Peak memory 145612 kb
Host smart-13e39a4b-4558-41ef-913b-36cebaf9171e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2015842285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2015842285
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.342376099
Short name T75
Test name
Test status
Simulation time 26664044 ps
CPU time 0.43 seconds
Started Jul 30 05:56:44 PM PDT 24
Finished Jul 30 05:56:45 PM PDT 24
Peak memory 145604 kb
Host smart-0d29bd03-8fa1-4a2d-83c0-1ba8b5edf312
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=342376099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.342376099
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3942553174
Short name T63
Test name
Test status
Simulation time 27012642 ps
CPU time 0.42 seconds
Started Jul 30 05:56:49 PM PDT 24
Finished Jul 30 05:56:49 PM PDT 24
Peak memory 145608 kb
Host smart-c92c7686-fa14-4298-9490-62d60d4c79fa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3942553174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3942553174
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2764556690
Short name T36
Test name
Test status
Simulation time 29227858 ps
CPU time 0.4 seconds
Started Jul 30 05:56:48 PM PDT 24
Finished Jul 30 05:56:49 PM PDT 24
Peak memory 145572 kb
Host smart-64fc1de2-00a5-4e98-ac1b-b70eee95b9f6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2764556690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2764556690
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2521573346
Short name T78
Test name
Test status
Simulation time 28204974 ps
CPU time 0.41 seconds
Started Jul 30 05:56:46 PM PDT 24
Finished Jul 30 05:56:47 PM PDT 24
Peak memory 145584 kb
Host smart-405fc567-6a6e-4661-98a1-a93cb31643fd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2521573346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2521573346
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4010866360
Short name T6
Test name
Test status
Simulation time 30200915 ps
CPU time 0.41 seconds
Started Jul 30 05:56:49 PM PDT 24
Finished Jul 30 05:56:50 PM PDT 24
Peak memory 145572 kb
Host smart-781ffbd2-1888-4a3b-a9d0-5a6dbea0bc96
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4010866360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.4010866360
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1025597587
Short name T69
Test name
Test status
Simulation time 27759230 ps
CPU time 0.39 seconds
Started Jul 30 05:56:46 PM PDT 24
Finished Jul 30 05:56:46 PM PDT 24
Peak memory 145576 kb
Host smart-4a0e8a05-d3fa-4374-b281-625954d51153
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1025597587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1025597587
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.446184832
Short name T64
Test name
Test status
Simulation time 28503893 ps
CPU time 0.41 seconds
Started Jul 30 05:56:47 PM PDT 24
Finished Jul 30 05:56:48 PM PDT 24
Peak memory 145612 kb
Host smart-dab030a9-d2e3-42d6-8b07-da4c854799cc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=446184832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.446184832
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1597704350
Short name T62
Test name
Test status
Simulation time 28742311 ps
CPU time 0.41 seconds
Started Jul 30 05:56:46 PM PDT 24
Finished Jul 30 05:56:46 PM PDT 24
Peak memory 145640 kb
Host smart-6b987773-eb48-4242-93ae-bc911b8bfccc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1597704350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1597704350
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.497337320
Short name T72
Test name
Test status
Simulation time 29449519 ps
CPU time 0.4 seconds
Started Jul 30 05:56:47 PM PDT 24
Finished Jul 30 05:56:47 PM PDT 24
Peak memory 145600 kb
Host smart-56735baf-76dd-46d1-a394-24771859d589
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=497337320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.497337320
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.479968602
Short name T65
Test name
Test status
Simulation time 25842362 ps
CPU time 0.4 seconds
Started Jul 30 05:56:44 PM PDT 24
Finished Jul 30 05:56:44 PM PDT 24
Peak memory 145604 kb
Host smart-224a1074-742a-4b62-802a-8ba00fe0230d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=479968602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.479968602
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1470280709
Short name T70
Test name
Test status
Simulation time 27821684 ps
CPU time 0.41 seconds
Started Jul 30 05:56:39 PM PDT 24
Finished Jul 30 05:56:40 PM PDT 24
Peak memory 145640 kb
Host smart-b72f7bb6-4aea-49cd-bf6a-56737137bcdc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1470280709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1470280709
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2997280534
Short name T74
Test name
Test status
Simulation time 27102075 ps
CPU time 0.39 seconds
Started Jul 30 05:56:42 PM PDT 24
Finished Jul 30 05:56:42 PM PDT 24
Peak memory 145612 kb
Host smart-3e5c028f-de16-489b-8ba4-2f69ffb1554b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2997280534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2997280534
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.256079564
Short name T71
Test name
Test status
Simulation time 26781008 ps
CPU time 0.4 seconds
Started Jul 30 05:56:40 PM PDT 24
Finished Jul 30 05:56:40 PM PDT 24
Peak memory 145620 kb
Host smart-ee39816e-7385-46aa-84e4-76e5ab620b8c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=256079564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.256079564
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1187063817
Short name T68
Test name
Test status
Simulation time 26652716 ps
CPU time 0.4 seconds
Started Jul 30 05:56:42 PM PDT 24
Finished Jul 30 05:56:43 PM PDT 24
Peak memory 145644 kb
Host smart-332db9fa-66de-4715-9aaa-fb94bbca1b80
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1187063817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1187063817
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2080873222
Short name T76
Test name
Test status
Simulation time 27644305 ps
CPU time 0.4 seconds
Started Jul 30 05:56:41 PM PDT 24
Finished Jul 30 05:56:41 PM PDT 24
Peak memory 145596 kb
Host smart-6d43c846-394e-4cff-adb2-98971c02e655
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2080873222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2080873222
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.561790673
Short name T77
Test name
Test status
Simulation time 26795064 ps
CPU time 0.4 seconds
Started Jul 30 05:56:40 PM PDT 24
Finished Jul 30 05:56:41 PM PDT 24
Peak memory 145504 kb
Host smart-2b5c94b2-83ba-4f31-9a20-1d1d9d0fb606
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=561790673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.561790673
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1462646111
Short name T73
Test name
Test status
Simulation time 28569051 ps
CPU time 0.4 seconds
Started Jul 30 05:56:47 PM PDT 24
Finished Jul 30 05:56:48 PM PDT 24
Peak memory 145612 kb
Host smart-80e736cd-21fb-4cb9-a85a-654d96fd19c2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1462646111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1462646111
Directory /workspace/9.prim_sync_fatal_alert/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%