Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.86 89.86 100.00 100.00 93.75 93.75 100.00 100.00 82.14 82.14 95.83 95.83 67.44 67.44 /workspace/coverage/default/0.prim_async_alert.2106121642
92.39 2.53 100.00 0.00 93.75 0.00 100.00 0.00 85.71 3.57 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/0.prim_sync_alert.4071737895
94.50 2.11 100.00 0.00 95.83 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3220716286
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2809413955

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.3066561624
/workspace/coverage/default/10.prim_async_alert.3517206672
/workspace/coverage/default/11.prim_async_alert.518680733
/workspace/coverage/default/12.prim_async_alert.760768546
/workspace/coverage/default/13.prim_async_alert.1938068909
/workspace/coverage/default/14.prim_async_alert.4214132248
/workspace/coverage/default/15.prim_async_alert.115107282
/workspace/coverage/default/16.prim_async_alert.2220766429
/workspace/coverage/default/17.prim_async_alert.2700685963
/workspace/coverage/default/18.prim_async_alert.3100208779
/workspace/coverage/default/19.prim_async_alert.502150684
/workspace/coverage/default/2.prim_async_alert.871664472
/workspace/coverage/default/3.prim_async_alert.2044418224
/workspace/coverage/default/4.prim_async_alert.451024986
/workspace/coverage/default/5.prim_async_alert.1090671042
/workspace/coverage/default/6.prim_async_alert.141731985
/workspace/coverage/default/7.prim_async_alert.3228725487
/workspace/coverage/default/8.prim_async_alert.1112506534
/workspace/coverage/default/9.prim_async_alert.1640737101
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1054987227
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1070750877
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4156828867
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3364915169
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2650246185
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4132575396
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2190928752
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3136230284
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2362897215
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1404187727
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1654526360
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3957240621
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2998019713
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1225091470
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.870792159
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4171279328
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.838585600
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1473229971
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1239625726
/workspace/coverage/sync_alert/1.prim_sync_alert.2188777032
/workspace/coverage/sync_alert/10.prim_sync_alert.3921612667
/workspace/coverage/sync_alert/11.prim_sync_alert.166048789
/workspace/coverage/sync_alert/12.prim_sync_alert.596264291
/workspace/coverage/sync_alert/13.prim_sync_alert.2577868385
/workspace/coverage/sync_alert/14.prim_sync_alert.1994466551
/workspace/coverage/sync_alert/15.prim_sync_alert.87334312
/workspace/coverage/sync_alert/16.prim_sync_alert.3338238546
/workspace/coverage/sync_alert/17.prim_sync_alert.980421714
/workspace/coverage/sync_alert/18.prim_sync_alert.1239012067
/workspace/coverage/sync_alert/19.prim_sync_alert.3327952812
/workspace/coverage/sync_alert/2.prim_sync_alert.3473013878
/workspace/coverage/sync_alert/3.prim_sync_alert.1598887247
/workspace/coverage/sync_alert/4.prim_sync_alert.2152690940
/workspace/coverage/sync_alert/5.prim_sync_alert.2928853419
/workspace/coverage/sync_alert/6.prim_sync_alert.3341869978
/workspace/coverage/sync_alert/7.prim_sync_alert.1323005921
/workspace/coverage/sync_alert/8.prim_sync_alert.2945095852
/workspace/coverage/sync_alert/9.prim_sync_alert.481924287
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.244573230
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1322504348
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3702249067
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.453801927
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4035358807
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1319931280
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.893470936
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2823606666
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.367575902
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2766656832
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1955618275
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.575084528
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2215664456
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.998384148
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3680839946
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3779577599
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.879090719
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.347680112
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2241714924



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/10.prim_async_alert.3517206672 Jul 31 04:40:48 PM PDT 24 Jul 31 04:40:48 PM PDT 24 11576751 ps
T2 /workspace/coverage/default/18.prim_async_alert.3100208779 Jul 31 04:40:50 PM PDT 24 Jul 31 04:40:51 PM PDT 24 10476176 ps
T3 /workspace/coverage/default/5.prim_async_alert.1090671042 Jul 31 04:40:52 PM PDT 24 Jul 31 04:40:52 PM PDT 24 10859422 ps
T7 /workspace/coverage/default/12.prim_async_alert.760768546 Jul 31 04:40:54 PM PDT 24 Jul 31 04:40:55 PM PDT 24 10622342 ps
T11 /workspace/coverage/default/7.prim_async_alert.3228725487 Jul 31 04:40:51 PM PDT 24 Jul 31 04:40:51 PM PDT 24 11312036 ps
T17 /workspace/coverage/default/17.prim_async_alert.2700685963 Jul 31 04:40:51 PM PDT 24 Jul 31 04:40:52 PM PDT 24 10674517 ps
T15 /workspace/coverage/default/11.prim_async_alert.518680733 Jul 31 04:40:46 PM PDT 24 Jul 31 04:40:46 PM PDT 24 11403912 ps
T14 /workspace/coverage/default/3.prim_async_alert.2044418224 Jul 31 04:41:07 PM PDT 24 Jul 31 04:41:08 PM PDT 24 10871955 ps
T8 /workspace/coverage/default/6.prim_async_alert.141731985 Jul 31 04:40:43 PM PDT 24 Jul 31 04:40:44 PM PDT 24 12425369 ps
T9 /workspace/coverage/default/0.prim_async_alert.2106121642 Jul 31 04:40:45 PM PDT 24 Jul 31 04:40:46 PM PDT 24 12453666 ps
T18 /workspace/coverage/default/8.prim_async_alert.1112506534 Jul 31 04:40:52 PM PDT 24 Jul 31 04:40:52 PM PDT 24 10936897 ps
T19 /workspace/coverage/default/19.prim_async_alert.502150684 Jul 31 04:40:51 PM PDT 24 Jul 31 04:40:52 PM PDT 24 11001218 ps
T16 /workspace/coverage/default/2.prim_async_alert.871664472 Jul 31 04:40:49 PM PDT 24 Jul 31 04:40:49 PM PDT 24 11085265 ps
T44 /workspace/coverage/default/15.prim_async_alert.115107282 Jul 31 04:40:46 PM PDT 24 Jul 31 04:40:47 PM PDT 24 10168040 ps
T20 /workspace/coverage/default/16.prim_async_alert.2220766429 Jul 31 04:40:52 PM PDT 24 Jul 31 04:40:52 PM PDT 24 10943505 ps
T21 /workspace/coverage/default/4.prim_async_alert.451024986 Jul 31 04:40:48 PM PDT 24 Jul 31 04:40:48 PM PDT 24 11267332 ps
T22 /workspace/coverage/default/9.prim_async_alert.1640737101 Jul 31 04:40:55 PM PDT 24 Jul 31 04:40:55 PM PDT 24 10954924 ps
T45 /workspace/coverage/default/14.prim_async_alert.4214132248 Jul 31 04:40:46 PM PDT 24 Jul 31 04:40:52 PM PDT 24 11162007 ps
T46 /workspace/coverage/default/13.prim_async_alert.1938068909 Jul 31 04:40:57 PM PDT 24 Jul 31 04:40:58 PM PDT 24 10390437 ps
T47 /workspace/coverage/default/1.prim_async_alert.3066561624 Jul 31 04:40:49 PM PDT 24 Jul 31 04:40:49 PM PDT 24 10905095 ps
T10 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1239625726 Jul 31 04:40:48 PM PDT 24 Jul 31 04:40:49 PM PDT 24 27858080 ps
T36 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2998019713 Jul 31 04:40:57 PM PDT 24 Jul 31 04:40:57 PM PDT 24 28473387 ps
T37 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4156828867 Jul 31 04:40:52 PM PDT 24 Jul 31 04:40:53 PM PDT 24 30979021 ps
T38 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1404187727 Jul 31 04:40:51 PM PDT 24 Jul 31 04:40:52 PM PDT 24 30467922 ps
T12 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2362897215 Jul 31 04:40:45 PM PDT 24 Jul 31 04:40:46 PM PDT 24 32209081 ps
T39 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3220716286 Jul 31 04:40:46 PM PDT 24 Jul 31 04:40:46 PM PDT 24 29714659 ps
T40 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3957240621 Jul 31 04:40:56 PM PDT 24 Jul 31 04:40:57 PM PDT 24 30425607 ps
T41 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1473229971 Jul 31 04:40:57 PM PDT 24 Jul 31 04:40:57 PM PDT 24 32436430 ps
T42 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2650246185 Jul 31 04:40:44 PM PDT 24 Jul 31 04:40:45 PM PDT 24 28960234 ps
T43 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.838585600 Jul 31 04:40:54 PM PDT 24 Jul 31 04:40:55 PM PDT 24 29623332 ps
T48 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3136230284 Jul 31 04:40:55 PM PDT 24 Jul 31 04:40:55 PM PDT 24 31796877 ps
T49 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2190928752 Jul 31 04:40:44 PM PDT 24 Jul 31 04:40:44 PM PDT 24 28861093 ps
T50 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4171279328 Jul 31 04:40:48 PM PDT 24 Jul 31 04:40:48 PM PDT 24 30327469 ps
T51 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4132575396 Jul 31 04:40:47 PM PDT 24 Jul 31 04:40:47 PM PDT 24 32005437 ps
T52 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.870792159 Jul 31 04:40:39 PM PDT 24 Jul 31 04:40:40 PM PDT 24 30026805 ps
T53 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1070750877 Jul 31 04:40:54 PM PDT 24 Jul 31 04:40:55 PM PDT 24 30968053 ps
T54 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1054987227 Jul 31 04:40:50 PM PDT 24 Jul 31 04:40:51 PM PDT 24 29732285 ps
T55 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1225091470 Jul 31 04:40:46 PM PDT 24 Jul 31 04:40:46 PM PDT 24 30033932 ps
T56 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1654526360 Jul 31 04:40:53 PM PDT 24 Jul 31 04:40:54 PM PDT 24 31163724 ps
T57 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3364915169 Jul 31 04:40:58 PM PDT 24 Jul 31 04:40:59 PM PDT 24 28488977 ps
T32 /workspace/coverage/sync_alert/0.prim_sync_alert.4071737895 Jul 31 04:40:47 PM PDT 24 Jul 31 04:40:47 PM PDT 24 8736831 ps
T23 /workspace/coverage/sync_alert/18.prim_sync_alert.1239012067 Jul 31 04:41:04 PM PDT 24 Jul 31 04:41:05 PM PDT 24 10396763 ps
T24 /workspace/coverage/sync_alert/16.prim_sync_alert.3338238546 Jul 31 04:40:49 PM PDT 24 Jul 31 04:40:49 PM PDT 24 9386139 ps
T25 /workspace/coverage/sync_alert/19.prim_sync_alert.3327952812 Jul 31 04:41:16 PM PDT 24 Jul 31 04:41:16 PM PDT 24 8324280 ps
T26 /workspace/coverage/sync_alert/4.prim_sync_alert.2152690940 Jul 31 04:41:03 PM PDT 24 Jul 31 04:41:03 PM PDT 24 7956188 ps
T33 /workspace/coverage/sync_alert/6.prim_sync_alert.3341869978 Jul 31 04:41:12 PM PDT 24 Jul 31 04:41:12 PM PDT 24 8353986 ps
T34 /workspace/coverage/sync_alert/8.prim_sync_alert.2945095852 Jul 31 04:40:55 PM PDT 24 Jul 31 04:40:55 PM PDT 24 10009186 ps
T27 /workspace/coverage/sync_alert/1.prim_sync_alert.2188777032 Jul 31 04:40:59 PM PDT 24 Jul 31 04:40:59 PM PDT 24 8586640 ps
T35 /workspace/coverage/sync_alert/13.prim_sync_alert.2577868385 Jul 31 04:40:55 PM PDT 24 Jul 31 04:40:56 PM PDT 24 9348138 ps
T13 /workspace/coverage/sync_alert/15.prim_sync_alert.87334312 Jul 31 04:41:01 PM PDT 24 Jul 31 04:41:01 PM PDT 24 9632216 ps
T28 /workspace/coverage/sync_alert/17.prim_sync_alert.980421714 Jul 31 04:40:51 PM PDT 24 Jul 31 04:40:51 PM PDT 24 8106899 ps
T29 /workspace/coverage/sync_alert/10.prim_sync_alert.3921612667 Jul 31 04:40:53 PM PDT 24 Jul 31 04:40:54 PM PDT 24 9900894 ps
T30 /workspace/coverage/sync_alert/12.prim_sync_alert.596264291 Jul 31 04:41:01 PM PDT 24 Jul 31 04:41:01 PM PDT 24 8521661 ps
T58 /workspace/coverage/sync_alert/14.prim_sync_alert.1994466551 Jul 31 04:40:54 PM PDT 24 Jul 31 04:40:54 PM PDT 24 8353388 ps
T31 /workspace/coverage/sync_alert/3.prim_sync_alert.1598887247 Jul 31 04:40:47 PM PDT 24 Jul 31 04:40:48 PM PDT 24 8227595 ps
T59 /workspace/coverage/sync_alert/11.prim_sync_alert.166048789 Jul 31 04:41:13 PM PDT 24 Jul 31 04:41:13 PM PDT 24 9744010 ps
T60 /workspace/coverage/sync_alert/2.prim_sync_alert.3473013878 Jul 31 04:40:58 PM PDT 24 Jul 31 04:40:59 PM PDT 24 8957282 ps
T61 /workspace/coverage/sync_alert/9.prim_sync_alert.481924287 Jul 31 04:40:51 PM PDT 24 Jul 31 04:40:51 PM PDT 24 8541638 ps
T62 /workspace/coverage/sync_alert/7.prim_sync_alert.1323005921 Jul 31 04:40:57 PM PDT 24 Jul 31 04:40:58 PM PDT 24 9938744 ps
T63 /workspace/coverage/sync_alert/5.prim_sync_alert.2928853419 Jul 31 04:40:40 PM PDT 24 Jul 31 04:40:40 PM PDT 24 9064333 ps
T64 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3779577599 Jul 31 04:41:10 PM PDT 24 Jul 31 04:41:10 PM PDT 24 27309958 ps
T65 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1319931280 Jul 31 04:40:47 PM PDT 24 Jul 31 04:40:47 PM PDT 24 26499689 ps
T4 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.453801927 Jul 31 04:41:07 PM PDT 24 Jul 31 04:41:07 PM PDT 24 25320638 ps
T66 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3680839946 Jul 31 04:40:46 PM PDT 24 Jul 31 04:40:47 PM PDT 24 29684184 ps
T67 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2241714924 Jul 31 04:40:50 PM PDT 24 Jul 31 04:40:51 PM PDT 24 26363680 ps
T68 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.575084528 Jul 31 04:40:48 PM PDT 24 Jul 31 04:40:48 PM PDT 24 26818429 ps
T69 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2766656832 Jul 31 04:41:01 PM PDT 24 Jul 31 04:41:02 PM PDT 24 27594441 ps
T70 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.998384148 Jul 31 04:41:09 PM PDT 24 Jul 31 04:41:10 PM PDT 24 29065376 ps
T71 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.347680112 Jul 31 04:41:10 PM PDT 24 Jul 31 04:41:11 PM PDT 24 26481614 ps
T72 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.367575902 Jul 31 04:40:54 PM PDT 24 Jul 31 04:40:55 PM PDT 24 27249217 ps
T73 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2823606666 Jul 31 04:40:59 PM PDT 24 Jul 31 04:40:59 PM PDT 24 26727822 ps
T74 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2215664456 Jul 31 04:41:03 PM PDT 24 Jul 31 04:41:04 PM PDT 24 27816268 ps
T75 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4035358807 Jul 31 04:41:03 PM PDT 24 Jul 31 04:41:04 PM PDT 24 27434562 ps
T76 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1322504348 Jul 31 04:41:05 PM PDT 24 Jul 31 04:41:05 PM PDT 24 28519932 ps
T5 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3702249067 Jul 31 04:40:51 PM PDT 24 Jul 31 04:40:51 PM PDT 24 25867133 ps
T77 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.244573230 Jul 31 04:40:54 PM PDT 24 Jul 31 04:40:55 PM PDT 24 26180989 ps
T78 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1955618275 Jul 31 04:41:09 PM PDT 24 Jul 31 04:41:09 PM PDT 24 27058358 ps
T79 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.879090719 Jul 31 04:41:17 PM PDT 24 Jul 31 04:41:18 PM PDT 24 28056360 ps
T80 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.893470936 Jul 31 04:41:12 PM PDT 24 Jul 31 04:41:12 PM PDT 24 28433440 ps
T6 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2809413955 Jul 31 04:40:58 PM PDT 24 Jul 31 04:40:58 PM PDT 24 27414556 ps

Test location /workspace/coverage/default/0.prim_async_alert.2106121642
Short name T9
Test name
Test status
Simulation time 12453666 ps
CPU time 0.4 seconds
Started Jul 31 04:40:45 PM PDT 24
Finished Jul 31 04:40:46 PM PDT 24
Peak memory 145792 kb
Host smart-1e503c96-0ab1-4216-b954-7aafe4abd8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106121642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2106121642
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.4071737895
Short name T32
Test name
Test status
Simulation time 8736831 ps
CPU time 0.36 seconds
Started Jul 31 04:40:47 PM PDT 24
Finished Jul 31 04:40:47 PM PDT 24
Peak memory 145428 kb
Host smart-e8d6cf69-132d-4a64-9897-025d4525abe2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4071737895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.4071737895
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3220716286
Short name T39
Test name
Test status
Simulation time 29714659 ps
CPU time 0.39 seconds
Started Jul 31 04:40:46 PM PDT 24
Finished Jul 31 04:40:46 PM PDT 24
Peak memory 145140 kb
Host smart-426217c2-cb9f-45c7-a390-37e2fd3442f1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3220716286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3220716286
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2809413955
Short name T6
Test name
Test status
Simulation time 27414556 ps
CPU time 0.39 seconds
Started Jul 31 04:40:58 PM PDT 24
Finished Jul 31 04:40:58 PM PDT 24
Peak memory 145480 kb
Host smart-29607969-a17d-4d34-97fb-ce48bcdc500c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2809413955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2809413955
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3066561624
Short name T47
Test name
Test status
Simulation time 10905095 ps
CPU time 0.39 seconds
Started Jul 31 04:40:49 PM PDT 24
Finished Jul 31 04:40:49 PM PDT 24
Peak memory 145636 kb
Host smart-ada77400-7cd8-4f79-a4e5-3932367a8ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066561624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3066561624
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3517206672
Short name T1
Test name
Test status
Simulation time 11576751 ps
CPU time 0.41 seconds
Started Jul 31 04:40:48 PM PDT 24
Finished Jul 31 04:40:48 PM PDT 24
Peak memory 145588 kb
Host smart-fdb9ce77-43bd-4e7b-84c3-563f6ce3016d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517206672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3517206672
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.518680733
Short name T15
Test name
Test status
Simulation time 11403912 ps
CPU time 0.38 seconds
Started Jul 31 04:40:46 PM PDT 24
Finished Jul 31 04:40:46 PM PDT 24
Peak memory 145728 kb
Host smart-12c3541a-0ac7-4ee8-a804-95ce403f05b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518680733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.518680733
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.760768546
Short name T7
Test name
Test status
Simulation time 10622342 ps
CPU time 0.38 seconds
Started Jul 31 04:40:54 PM PDT 24
Finished Jul 31 04:40:55 PM PDT 24
Peak memory 145644 kb
Host smart-3cb3da44-9bf8-4138-9728-63a52f39f515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760768546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.760768546
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1938068909
Short name T46
Test name
Test status
Simulation time 10390437 ps
CPU time 0.37 seconds
Started Jul 31 04:40:57 PM PDT 24
Finished Jul 31 04:40:58 PM PDT 24
Peak memory 145748 kb
Host smart-b7776d16-8635-4f37-bdb2-929b294d6be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938068909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1938068909
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.4214132248
Short name T45
Test name
Test status
Simulation time 11162007 ps
CPU time 0.4 seconds
Started Jul 31 04:40:46 PM PDT 24
Finished Jul 31 04:40:52 PM PDT 24
Peak memory 145652 kb
Host smart-0e6c0943-3597-432a-b40f-12fcaff85b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214132248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.4214132248
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.115107282
Short name T44
Test name
Test status
Simulation time 10168040 ps
CPU time 0.38 seconds
Started Jul 31 04:40:46 PM PDT 24
Finished Jul 31 04:40:47 PM PDT 24
Peak memory 145652 kb
Host smart-bc1abbca-405a-40c3-ae89-b79a03719162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115107282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.115107282
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2220766429
Short name T20
Test name
Test status
Simulation time 10943505 ps
CPU time 0.39 seconds
Started Jul 31 04:40:52 PM PDT 24
Finished Jul 31 04:40:52 PM PDT 24
Peak memory 145672 kb
Host smart-e7bdf69b-0a40-4eb3-877b-3045ae2bf524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220766429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2220766429
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2700685963
Short name T17
Test name
Test status
Simulation time 10674517 ps
CPU time 0.39 seconds
Started Jul 31 04:40:51 PM PDT 24
Finished Jul 31 04:40:52 PM PDT 24
Peak memory 145652 kb
Host smart-5f6f57a4-8a25-40c7-8ea6-ca447625b737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700685963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2700685963
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3100208779
Short name T2
Test name
Test status
Simulation time 10476176 ps
CPU time 0.39 seconds
Started Jul 31 04:40:50 PM PDT 24
Finished Jul 31 04:40:51 PM PDT 24
Peak memory 145596 kb
Host smart-fa6608cd-30ef-4b5d-9416-f704c3823357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100208779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3100208779
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.502150684
Short name T19
Test name
Test status
Simulation time 11001218 ps
CPU time 0.39 seconds
Started Jul 31 04:40:51 PM PDT 24
Finished Jul 31 04:40:52 PM PDT 24
Peak memory 145636 kb
Host smart-d0b0c6ca-c40d-44d8-b6b2-dbfbb3fd9164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502150684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.502150684
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.871664472
Short name T16
Test name
Test status
Simulation time 11085265 ps
CPU time 0.39 seconds
Started Jul 31 04:40:49 PM PDT 24
Finished Jul 31 04:40:49 PM PDT 24
Peak memory 145648 kb
Host smart-3ec60225-7091-454c-9e62-9986c8875ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871664472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.871664472
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2044418224
Short name T14
Test name
Test status
Simulation time 10871955 ps
CPU time 0.39 seconds
Started Jul 31 04:41:07 PM PDT 24
Finished Jul 31 04:41:08 PM PDT 24
Peak memory 145672 kb
Host smart-5b215ca8-be84-45f0-ac7e-0c036f662459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044418224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2044418224
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.451024986
Short name T21
Test name
Test status
Simulation time 11267332 ps
CPU time 0.38 seconds
Started Jul 31 04:40:48 PM PDT 24
Finished Jul 31 04:40:48 PM PDT 24
Peak memory 145768 kb
Host smart-41db3819-617f-451d-a0ba-c09f19a6ae53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451024986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.451024986
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1090671042
Short name T3
Test name
Test status
Simulation time 10859422 ps
CPU time 0.39 seconds
Started Jul 31 04:40:52 PM PDT 24
Finished Jul 31 04:40:52 PM PDT 24
Peak memory 145644 kb
Host smart-6b9186f6-2162-4faf-b9b2-57cd32635fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090671042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1090671042
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.141731985
Short name T8
Test name
Test status
Simulation time 12425369 ps
CPU time 0.42 seconds
Started Jul 31 04:40:43 PM PDT 24
Finished Jul 31 04:40:44 PM PDT 24
Peak memory 145744 kb
Host smart-fde4bb98-5fe2-49e2-9cca-b17b77390315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141731985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.141731985
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3228725487
Short name T11
Test name
Test status
Simulation time 11312036 ps
CPU time 0.39 seconds
Started Jul 31 04:40:51 PM PDT 24
Finished Jul 31 04:40:51 PM PDT 24
Peak memory 145604 kb
Host smart-15329238-6457-4e9e-a07b-e766858153aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228725487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3228725487
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1112506534
Short name T18
Test name
Test status
Simulation time 10936897 ps
CPU time 0.41 seconds
Started Jul 31 04:40:52 PM PDT 24
Finished Jul 31 04:40:52 PM PDT 24
Peak memory 145752 kb
Host smart-1bd38907-ba0c-4f28-b323-6270cf96e761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112506534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1112506534
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1640737101
Short name T22
Test name
Test status
Simulation time 10954924 ps
CPU time 0.4 seconds
Started Jul 31 04:40:55 PM PDT 24
Finished Jul 31 04:40:55 PM PDT 24
Peak memory 145560 kb
Host smart-e98bc01d-f0dc-495d-88a1-ba72197c163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640737101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1640737101
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1054987227
Short name T54
Test name
Test status
Simulation time 29732285 ps
CPU time 0.39 seconds
Started Jul 31 04:40:50 PM PDT 24
Finished Jul 31 04:40:51 PM PDT 24
Peak memory 145224 kb
Host smart-9bd4d9a1-04d6-4a63-a9bb-e5c5fc863edf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1054987227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1054987227
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1070750877
Short name T53
Test name
Test status
Simulation time 30968053 ps
CPU time 0.39 seconds
Started Jul 31 04:40:54 PM PDT 24
Finished Jul 31 04:40:55 PM PDT 24
Peak memory 145304 kb
Host smart-5878618b-a07b-424e-9bc4-b5868b58b6e6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1070750877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1070750877
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4156828867
Short name T37
Test name
Test status
Simulation time 30979021 ps
CPU time 0.46 seconds
Started Jul 31 04:40:52 PM PDT 24
Finished Jul 31 04:40:53 PM PDT 24
Peak memory 145228 kb
Host smart-d2750656-ee25-4637-8604-a5479390671a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4156828867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.4156828867
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3364915169
Short name T57
Test name
Test status
Simulation time 28488977 ps
CPU time 0.44 seconds
Started Jul 31 04:40:58 PM PDT 24
Finished Jul 31 04:40:59 PM PDT 24
Peak memory 145244 kb
Host smart-ecca4d35-8bd1-44a6-8db6-8fb414a5d0a2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3364915169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3364915169
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2650246185
Short name T42
Test name
Test status
Simulation time 28960234 ps
CPU time 0.4 seconds
Started Jul 31 04:40:44 PM PDT 24
Finished Jul 31 04:40:45 PM PDT 24
Peak memory 145188 kb
Host smart-31756b9a-c114-4e64-90dc-403d9070f81e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2650246185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2650246185
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4132575396
Short name T51
Test name
Test status
Simulation time 32005437 ps
CPU time 0.4 seconds
Started Jul 31 04:40:47 PM PDT 24
Finished Jul 31 04:40:47 PM PDT 24
Peak memory 145204 kb
Host smart-f765d121-f0ea-4f8b-9b89-4f9fa8226445
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4132575396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.4132575396
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2190928752
Short name T49
Test name
Test status
Simulation time 28861093 ps
CPU time 0.39 seconds
Started Jul 31 04:40:44 PM PDT 24
Finished Jul 31 04:40:44 PM PDT 24
Peak memory 145268 kb
Host smart-495004f5-9028-4dbd-a71e-3ecf6af20abf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2190928752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2190928752
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3136230284
Short name T48
Test name
Test status
Simulation time 31796877 ps
CPU time 0.41 seconds
Started Jul 31 04:40:55 PM PDT 24
Finished Jul 31 04:40:55 PM PDT 24
Peak memory 145176 kb
Host smart-a4751747-9564-4157-912e-dc75655eaa60
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3136230284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3136230284
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2362897215
Short name T12
Test name
Test status
Simulation time 32209081 ps
CPU time 0.4 seconds
Started Jul 31 04:40:45 PM PDT 24
Finished Jul 31 04:40:46 PM PDT 24
Peak memory 145096 kb
Host smart-79afbcd0-2710-44dc-b97d-3806f2f53374
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2362897215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2362897215
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1404187727
Short name T38
Test name
Test status
Simulation time 30467922 ps
CPU time 0.41 seconds
Started Jul 31 04:40:51 PM PDT 24
Finished Jul 31 04:40:52 PM PDT 24
Peak memory 145208 kb
Host smart-28687e11-ec8f-48a0-b7e2-bbcc458cc458
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1404187727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1404187727
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1654526360
Short name T56
Test name
Test status
Simulation time 31163724 ps
CPU time 0.41 seconds
Started Jul 31 04:40:53 PM PDT 24
Finished Jul 31 04:40:54 PM PDT 24
Peak memory 145280 kb
Host smart-b0f2c570-3bd3-4a18-92fb-ffe96f7ea91b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1654526360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1654526360
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3957240621
Short name T40
Test name
Test status
Simulation time 30425607 ps
CPU time 0.4 seconds
Started Jul 31 04:40:56 PM PDT 24
Finished Jul 31 04:40:57 PM PDT 24
Peak memory 145244 kb
Host smart-368193e2-554d-4616-a3ad-61171ef0f3a0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3957240621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3957240621
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2998019713
Short name T36
Test name
Test status
Simulation time 28473387 ps
CPU time 0.39 seconds
Started Jul 31 04:40:57 PM PDT 24
Finished Jul 31 04:40:57 PM PDT 24
Peak memory 145176 kb
Host smart-d519ab86-e287-4e55-bb61-ed4d7db1e61a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2998019713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2998019713
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1225091470
Short name T55
Test name
Test status
Simulation time 30033932 ps
CPU time 0.39 seconds
Started Jul 31 04:40:46 PM PDT 24
Finished Jul 31 04:40:46 PM PDT 24
Peak memory 145164 kb
Host smart-4dfe3bd0-2f7c-4d15-b641-bae5d24efb0d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1225091470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1225091470
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.870792159
Short name T52
Test name
Test status
Simulation time 30026805 ps
CPU time 0.38 seconds
Started Jul 31 04:40:39 PM PDT 24
Finished Jul 31 04:40:40 PM PDT 24
Peak memory 145204 kb
Host smart-52c8902e-0288-44ec-867e-4d8b9d842260
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=870792159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.870792159
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4171279328
Short name T50
Test name
Test status
Simulation time 30327469 ps
CPU time 0.39 seconds
Started Jul 31 04:40:48 PM PDT 24
Finished Jul 31 04:40:48 PM PDT 24
Peak memory 145204 kb
Host smart-c491789a-45af-4c22-b781-f4f14ee6b140
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4171279328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.4171279328
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.838585600
Short name T43
Test name
Test status
Simulation time 29623332 ps
CPU time 0.4 seconds
Started Jul 31 04:40:54 PM PDT 24
Finished Jul 31 04:40:55 PM PDT 24
Peak memory 145160 kb
Host smart-42e35a1a-e4c4-4995-baca-68c52806ad7c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=838585600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.838585600
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1473229971
Short name T41
Test name
Test status
Simulation time 32436430 ps
CPU time 0.41 seconds
Started Jul 31 04:40:57 PM PDT 24
Finished Jul 31 04:40:57 PM PDT 24
Peak memory 145168 kb
Host smart-bbbe296c-7eb2-4459-b3d5-573e69f729db
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1473229971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1473229971
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1239625726
Short name T10
Test name
Test status
Simulation time 27858080 ps
CPU time 0.39 seconds
Started Jul 31 04:40:48 PM PDT 24
Finished Jul 31 04:40:49 PM PDT 24
Peak memory 145208 kb
Host smart-369595a1-b3af-4e24-a5dd-273128e0214b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1239625726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1239625726
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2188777032
Short name T27
Test name
Test status
Simulation time 8586640 ps
CPU time 0.37 seconds
Started Jul 31 04:40:59 PM PDT 24
Finished Jul 31 04:40:59 PM PDT 24
Peak memory 145524 kb
Host smart-2892e7eb-ae47-457d-b967-00e68ba9fde9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2188777032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2188777032
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3921612667
Short name T29
Test name
Test status
Simulation time 9900894 ps
CPU time 0.38 seconds
Started Jul 31 04:40:53 PM PDT 24
Finished Jul 31 04:40:54 PM PDT 24
Peak memory 145484 kb
Host smart-c688d4e0-4d2a-4da0-aec8-f2d92284fe69
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3921612667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3921612667
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.166048789
Short name T59
Test name
Test status
Simulation time 9744010 ps
CPU time 0.38 seconds
Started Jul 31 04:41:13 PM PDT 24
Finished Jul 31 04:41:13 PM PDT 24
Peak memory 145400 kb
Host smart-b844edcc-9a48-44ce-b633-408c6ecab8f8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=166048789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.166048789
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.596264291
Short name T30
Test name
Test status
Simulation time 8521661 ps
CPU time 0.38 seconds
Started Jul 31 04:41:01 PM PDT 24
Finished Jul 31 04:41:01 PM PDT 24
Peak memory 145460 kb
Host smart-37f2d8b5-5712-4719-9c2f-4c85d09019cc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=596264291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.596264291
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2577868385
Short name T35
Test name
Test status
Simulation time 9348138 ps
CPU time 0.4 seconds
Started Jul 31 04:40:55 PM PDT 24
Finished Jul 31 04:40:56 PM PDT 24
Peak memory 145428 kb
Host smart-d8f263d4-74cd-4864-85b7-dab276802bac
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2577868385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2577868385
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.1994466551
Short name T58
Test name
Test status
Simulation time 8353388 ps
CPU time 0.36 seconds
Started Jul 31 04:40:54 PM PDT 24
Finished Jul 31 04:40:54 PM PDT 24
Peak memory 145520 kb
Host smart-c7b71cdc-761a-4dc5-af7b-4e07356fff8f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1994466551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1994466551
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.87334312
Short name T13
Test name
Test status
Simulation time 9632216 ps
CPU time 0.38 seconds
Started Jul 31 04:41:01 PM PDT 24
Finished Jul 31 04:41:01 PM PDT 24
Peak memory 145396 kb
Host smart-29426469-9a11-4477-9746-85ce00796b30
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=87334312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.87334312
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3338238546
Short name T24
Test name
Test status
Simulation time 9386139 ps
CPU time 0.39 seconds
Started Jul 31 04:40:49 PM PDT 24
Finished Jul 31 04:40:49 PM PDT 24
Peak memory 145148 kb
Host smart-1d9e6740-f51a-47db-9704-b7f7e3325c7e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3338238546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3338238546
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.980421714
Short name T28
Test name
Test status
Simulation time 8106899 ps
CPU time 0.39 seconds
Started Jul 31 04:40:51 PM PDT 24
Finished Jul 31 04:40:51 PM PDT 24
Peak memory 145476 kb
Host smart-e193e911-22c2-494d-ab0b-ad0d17bb5085
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=980421714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.980421714
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1239012067
Short name T23
Test name
Test status
Simulation time 10396763 ps
CPU time 0.41 seconds
Started Jul 31 04:41:04 PM PDT 24
Finished Jul 31 04:41:05 PM PDT 24
Peak memory 145440 kb
Host smart-3720c8b9-e26c-4747-a83d-90cb39ed7aeb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1239012067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1239012067
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3327952812
Short name T25
Test name
Test status
Simulation time 8324280 ps
CPU time 0.38 seconds
Started Jul 31 04:41:16 PM PDT 24
Finished Jul 31 04:41:16 PM PDT 24
Peak memory 145452 kb
Host smart-671bab81-ed3c-413e-8eb9-83595ce48b95
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3327952812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3327952812
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3473013878
Short name T60
Test name
Test status
Simulation time 8957282 ps
CPU time 0.38 seconds
Started Jul 31 04:40:58 PM PDT 24
Finished Jul 31 04:40:59 PM PDT 24
Peak memory 145544 kb
Host smart-be1125c0-4c53-4bdc-a8d8-22e74214b12a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3473013878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3473013878
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1598887247
Short name T31
Test name
Test status
Simulation time 8227595 ps
CPU time 0.38 seconds
Started Jul 31 04:40:47 PM PDT 24
Finished Jul 31 04:40:48 PM PDT 24
Peak memory 145528 kb
Host smart-a169eebf-b27e-4fac-aff3-8dfd967ebda2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1598887247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1598887247
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2152690940
Short name T26
Test name
Test status
Simulation time 7956188 ps
CPU time 0.45 seconds
Started Jul 31 04:41:03 PM PDT 24
Finished Jul 31 04:41:03 PM PDT 24
Peak memory 145440 kb
Host smart-d205287a-e615-4115-94ec-98266f26d464
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2152690940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2152690940
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2928853419
Short name T63
Test name
Test status
Simulation time 9064333 ps
CPU time 0.39 seconds
Started Jul 31 04:40:40 PM PDT 24
Finished Jul 31 04:40:40 PM PDT 24
Peak memory 145500 kb
Host smart-a391f755-ccfe-40c3-92c3-61c8f5ebbae6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2928853419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2928853419
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3341869978
Short name T33
Test name
Test status
Simulation time 8353986 ps
CPU time 0.38 seconds
Started Jul 31 04:41:12 PM PDT 24
Finished Jul 31 04:41:12 PM PDT 24
Peak memory 145500 kb
Host smart-f5d3964e-a11f-4e40-9a44-cbd0ea2498ed
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3341869978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3341869978
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1323005921
Short name T62
Test name
Test status
Simulation time 9938744 ps
CPU time 0.44 seconds
Started Jul 31 04:40:57 PM PDT 24
Finished Jul 31 04:40:58 PM PDT 24
Peak memory 145484 kb
Host smart-1a828835-b91f-45cd-94c6-12df859e504c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1323005921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1323005921
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2945095852
Short name T34
Test name
Test status
Simulation time 10009186 ps
CPU time 0.38 seconds
Started Jul 31 04:40:55 PM PDT 24
Finished Jul 31 04:40:55 PM PDT 24
Peak memory 145460 kb
Host smart-1d701a19-b0ac-482a-9ae0-081f8227895b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2945095852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2945095852
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.481924287
Short name T61
Test name
Test status
Simulation time 8541638 ps
CPU time 0.39 seconds
Started Jul 31 04:40:51 PM PDT 24
Finished Jul 31 04:40:51 PM PDT 24
Peak memory 145460 kb
Host smart-b4d4011d-1634-47a5-be5a-3f48af453572
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=481924287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.481924287
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.244573230
Short name T77
Test name
Test status
Simulation time 26180989 ps
CPU time 0.4 seconds
Started Jul 31 04:40:54 PM PDT 24
Finished Jul 31 04:40:55 PM PDT 24
Peak memory 145176 kb
Host smart-64d24ae8-e2ab-4fdb-8b68-c454c4037550
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=244573230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.244573230
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1322504348
Short name T76
Test name
Test status
Simulation time 28519932 ps
CPU time 0.41 seconds
Started Jul 31 04:41:05 PM PDT 24
Finished Jul 31 04:41:05 PM PDT 24
Peak memory 145396 kb
Host smart-c039eeab-6ce5-4f47-916c-daf8b636ab98
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1322504348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1322504348
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3702249067
Short name T5
Test name
Test status
Simulation time 25867133 ps
CPU time 0.39 seconds
Started Jul 31 04:40:51 PM PDT 24
Finished Jul 31 04:40:51 PM PDT 24
Peak memory 145468 kb
Host smart-0eef3119-cc1b-45d6-8bb2-b668f8b5a7e2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3702249067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3702249067
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.453801927
Short name T4
Test name
Test status
Simulation time 25320638 ps
CPU time 0.44 seconds
Started Jul 31 04:41:07 PM PDT 24
Finished Jul 31 04:41:07 PM PDT 24
Peak memory 145448 kb
Host smart-def0a3cd-a9e3-490a-a4aa-fa15530fc100
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=453801927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.453801927
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4035358807
Short name T75
Test name
Test status
Simulation time 27434562 ps
CPU time 0.43 seconds
Started Jul 31 04:41:03 PM PDT 24
Finished Jul 31 04:41:04 PM PDT 24
Peak memory 145516 kb
Host smart-97e36155-4f80-4ded-9422-567867b0b679
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4035358807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.4035358807
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1319931280
Short name T65
Test name
Test status
Simulation time 26499689 ps
CPU time 0.39 seconds
Started Jul 31 04:40:47 PM PDT 24
Finished Jul 31 04:40:47 PM PDT 24
Peak memory 145468 kb
Host smart-64f9163c-c507-4aa4-b585-a64d5031dd01
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1319931280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1319931280
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.893470936
Short name T80
Test name
Test status
Simulation time 28433440 ps
CPU time 0.39 seconds
Started Jul 31 04:41:12 PM PDT 24
Finished Jul 31 04:41:12 PM PDT 24
Peak memory 145576 kb
Host smart-1c491aa4-aafb-48fe-8804-a8a0e6615877
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=893470936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.893470936
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2823606666
Short name T73
Test name
Test status
Simulation time 26727822 ps
CPU time 0.42 seconds
Started Jul 31 04:40:59 PM PDT 24
Finished Jul 31 04:40:59 PM PDT 24
Peak memory 145512 kb
Host smart-a160944e-d947-47da-8ee7-ef4da3ca302f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2823606666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2823606666
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.367575902
Short name T72
Test name
Test status
Simulation time 27249217 ps
CPU time 0.39 seconds
Started Jul 31 04:40:54 PM PDT 24
Finished Jul 31 04:40:55 PM PDT 24
Peak memory 145544 kb
Host smart-125c7ecf-09da-4c9b-a578-3f8f28161e1f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=367575902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.367575902
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2766656832
Short name T69
Test name
Test status
Simulation time 27594441 ps
CPU time 0.42 seconds
Started Jul 31 04:41:01 PM PDT 24
Finished Jul 31 04:41:02 PM PDT 24
Peak memory 145460 kb
Host smart-33fcaeb3-3b53-4910-acfb-5b82d95b7e9e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2766656832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2766656832
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1955618275
Short name T78
Test name
Test status
Simulation time 27058358 ps
CPU time 0.38 seconds
Started Jul 31 04:41:09 PM PDT 24
Finished Jul 31 04:41:09 PM PDT 24
Peak memory 145604 kb
Host smart-0cffec4d-8810-4fac-b721-51d3126e9bd9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1955618275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1955618275
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.575084528
Short name T68
Test name
Test status
Simulation time 26818429 ps
CPU time 0.4 seconds
Started Jul 31 04:40:48 PM PDT 24
Finished Jul 31 04:40:48 PM PDT 24
Peak memory 145452 kb
Host smart-39aff2e1-ec14-425d-bd45-93a1feea878a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=575084528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.575084528
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2215664456
Short name T74
Test name
Test status
Simulation time 27816268 ps
CPU time 0.41 seconds
Started Jul 31 04:41:03 PM PDT 24
Finished Jul 31 04:41:04 PM PDT 24
Peak memory 145560 kb
Host smart-816a9d40-b83e-4c1d-8706-79ebba75dc48
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2215664456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2215664456
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.998384148
Short name T70
Test name
Test status
Simulation time 29065376 ps
CPU time 0.4 seconds
Started Jul 31 04:41:09 PM PDT 24
Finished Jul 31 04:41:10 PM PDT 24
Peak memory 145488 kb
Host smart-3f5b177b-01ad-4c42-a2d2-ab74db100f0d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=998384148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.998384148
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3680839946
Short name T66
Test name
Test status
Simulation time 29684184 ps
CPU time 0.4 seconds
Started Jul 31 04:40:46 PM PDT 24
Finished Jul 31 04:40:47 PM PDT 24
Peak memory 145484 kb
Host smart-3c0edd34-57df-43c5-814a-f4af532abc71
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3680839946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3680839946
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3779577599
Short name T64
Test name
Test status
Simulation time 27309958 ps
CPU time 0.4 seconds
Started Jul 31 04:41:10 PM PDT 24
Finished Jul 31 04:41:10 PM PDT 24
Peak memory 145452 kb
Host smart-9e3f758f-d04d-4709-b71a-4c3c4c619b25
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3779577599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3779577599
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.879090719
Short name T79
Test name
Test status
Simulation time 28056360 ps
CPU time 0.39 seconds
Started Jul 31 04:41:17 PM PDT 24
Finished Jul 31 04:41:18 PM PDT 24
Peak memory 145488 kb
Host smart-d4d05a6e-5106-40a1-baca-4382563714a8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=879090719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.879090719
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.347680112
Short name T71
Test name
Test status
Simulation time 26481614 ps
CPU time 0.4 seconds
Started Jul 31 04:41:10 PM PDT 24
Finished Jul 31 04:41:11 PM PDT 24
Peak memory 145540 kb
Host smart-01b82ba2-0697-4793-90b1-a4660f217c46
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=347680112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.347680112
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2241714924
Short name T67
Test name
Test status
Simulation time 26363680 ps
CPU time 0.39 seconds
Started Jul 31 04:40:50 PM PDT 24
Finished Jul 31 04:40:51 PM PDT 24
Peak memory 145616 kb
Host smart-dd71f827-8263-4770-ad93-39cc80f9f509
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2241714924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2241714924
Directory /workspace/9.prim_sync_fatal_alert/latest
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