| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.49 | 88.49 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 62.79 | 62.79 | /workspace/coverage/default/3.prim_async_alert.791530844 |
| 92.56 | 4.07 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 10.71 | 95.83 | 0.00 | 74.42 | 11.63 | /workspace/coverage/sync_alert/18.prim_sync_alert.3899714695 |
| 94.11 | 1.55 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 83.72 | 9.30 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1857250420 |
| 94.85 | 0.73 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 2.33 | /workspace/coverage/default/17.prim_async_alert.3181308189 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1827352112 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.1096234929 |
| /workspace/coverage/default/1.prim_async_alert.1770152804 |
| /workspace/coverage/default/10.prim_async_alert.641321052 |
| /workspace/coverage/default/11.prim_async_alert.4281901450 |
| /workspace/coverage/default/12.prim_async_alert.3538165912 |
| /workspace/coverage/default/13.prim_async_alert.4012196520 |
| /workspace/coverage/default/14.prim_async_alert.4085406702 |
| /workspace/coverage/default/15.prim_async_alert.1266549067 |
| /workspace/coverage/default/16.prim_async_alert.3008243678 |
| /workspace/coverage/default/18.prim_async_alert.2925592825 |
| /workspace/coverage/default/19.prim_async_alert.3752191189 |
| /workspace/coverage/default/2.prim_async_alert.3979011778 |
| /workspace/coverage/default/4.prim_async_alert.1032711856 |
| /workspace/coverage/default/5.prim_async_alert.4037046770 |
| /workspace/coverage/default/6.prim_async_alert.2824560654 |
| /workspace/coverage/default/7.prim_async_alert.711821331 |
| /workspace/coverage/default/8.prim_async_alert.3789472669 |
| /workspace/coverage/default/9.prim_async_alert.3482655222 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3172194803 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1295764185 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3879774280 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1231548599 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1967761774 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2187281957 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2417999539 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2158978236 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.961937569 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3159088826 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.14802885 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2985495242 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2022174958 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4160044521 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3972574389 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2636089457 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1663182021 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.578394810 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.990124445 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.2900607832 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3637521401 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.3387358240 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3921736997 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1443054200 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1860269536 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.1086833144 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.219816036 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.3520051808 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.2628105601 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.3575595843 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.2475226161 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.3853906394 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.449219939 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1396195254 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.2681560396 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.3938357332 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.337915539 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2814348902 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.888532187 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1946909507 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4174590719 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3089147579 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2918191496 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1031364357 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1559419528 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.465812000 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2294031304 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2540171166 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3931822862 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2148917554 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.128267326 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1487213897 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2272851561 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2313734549 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2223248517 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.231612658 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4165111259 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/5.prim_async_alert.4037046770 | Aug 01 05:28:53 PM PDT 24 | Aug 01 05:28:54 PM PDT 24 | 12172537 ps | ||
| T2 | /workspace/coverage/default/1.prim_async_alert.1770152804 | Aug 01 05:28:52 PM PDT 24 | Aug 01 05:28:52 PM PDT 24 | 11935944 ps | ||
| T3 | /workspace/coverage/default/3.prim_async_alert.791530844 | Aug 01 05:28:51 PM PDT 24 | Aug 01 05:28:52 PM PDT 24 | 11587394 ps | ||
| T7 | /workspace/coverage/default/11.prim_async_alert.4281901450 | Aug 01 05:29:01 PM PDT 24 | Aug 01 05:29:02 PM PDT 24 | 11771460 ps | ||
| T8 | /workspace/coverage/default/18.prim_async_alert.2925592825 | Aug 01 05:29:01 PM PDT 24 | Aug 01 05:29:01 PM PDT 24 | 10510597 ps | ||
| T19 | /workspace/coverage/default/16.prim_async_alert.3008243678 | Aug 01 05:29:03 PM PDT 24 | Aug 01 05:29:03 PM PDT 24 | 11106632 ps | ||
| T9 | /workspace/coverage/default/7.prim_async_alert.711821331 | Aug 01 05:28:48 PM PDT 24 | Aug 01 05:28:48 PM PDT 24 | 10621488 ps | ||
| T10 | /workspace/coverage/default/8.prim_async_alert.3789472669 | Aug 01 05:28:53 PM PDT 24 | Aug 01 05:28:53 PM PDT 24 | 10955941 ps | ||
| T13 | /workspace/coverage/default/13.prim_async_alert.4012196520 | Aug 01 05:29:02 PM PDT 24 | Aug 01 05:29:02 PM PDT 24 | 11147674 ps | ||
| T20 | /workspace/coverage/default/2.prim_async_alert.3979011778 | Aug 01 05:28:53 PM PDT 24 | Aug 01 05:28:53 PM PDT 24 | 10331037 ps | ||
| T21 | /workspace/coverage/default/10.prim_async_alert.641321052 | Aug 01 05:29:01 PM PDT 24 | Aug 01 05:29:01 PM PDT 24 | 10780169 ps | ||
| T22 | /workspace/coverage/default/17.prim_async_alert.3181308189 | Aug 01 05:29:01 PM PDT 24 | Aug 01 05:29:01 PM PDT 24 | 10534823 ps | ||
| T16 | /workspace/coverage/default/6.prim_async_alert.2824560654 | Aug 01 05:28:52 PM PDT 24 | Aug 01 05:28:53 PM PDT 24 | 11493258 ps | ||
| T28 | /workspace/coverage/default/9.prim_async_alert.3482655222 | Aug 01 05:29:01 PM PDT 24 | Aug 01 05:29:02 PM PDT 24 | 10572421 ps | ||
| T49 | /workspace/coverage/default/12.prim_async_alert.3538165912 | Aug 01 05:29:02 PM PDT 24 | Aug 01 05:29:03 PM PDT 24 | 11711010 ps | ||
| T23 | /workspace/coverage/default/0.prim_async_alert.1096234929 | Aug 01 05:28:53 PM PDT 24 | Aug 01 05:28:53 PM PDT 24 | 11149286 ps | ||
| T14 | /workspace/coverage/default/14.prim_async_alert.4085406702 | Aug 01 05:29:03 PM PDT 24 | Aug 01 05:29:04 PM PDT 24 | 12649659 ps | ||
| T50 | /workspace/coverage/default/4.prim_async_alert.1032711856 | Aug 01 05:28:52 PM PDT 24 | Aug 01 05:28:52 PM PDT 24 | 10916394 ps | ||
| T24 | /workspace/coverage/default/15.prim_async_alert.1266549067 | Aug 01 05:29:02 PM PDT 24 | Aug 01 05:29:03 PM PDT 24 | 11157004 ps | ||
| T51 | /workspace/coverage/default/19.prim_async_alert.3752191189 | Aug 01 05:29:02 PM PDT 24 | Aug 01 05:29:03 PM PDT 24 | 11294387 ps | ||
| T25 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1857250420 | Aug 01 04:26:07 PM PDT 24 | Aug 01 04:26:07 PM PDT 24 | 28078333 ps | ||
| T44 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1967761774 | Aug 01 04:26:19 PM PDT 24 | Aug 01 04:26:19 PM PDT 24 | 29820402 ps | ||
| T45 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3159088826 | Aug 01 04:26:28 PM PDT 24 | Aug 01 04:26:29 PM PDT 24 | 29978927 ps | ||
| T26 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2022174958 | Aug 01 04:26:08 PM PDT 24 | Aug 01 04:26:09 PM PDT 24 | 29870603 ps | ||
| T46 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.961937569 | Aug 01 04:26:28 PM PDT 24 | Aug 01 04:26:28 PM PDT 24 | 29372016 ps | ||
| T27 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2187281957 | Aug 01 04:26:17 PM PDT 24 | Aug 01 04:26:17 PM PDT 24 | 30012399 ps | ||
| T17 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2636089457 | Aug 01 04:26:07 PM PDT 24 | Aug 01 04:26:08 PM PDT 24 | 29758015 ps | ||
| T47 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2158978236 | Aug 01 04:26:17 PM PDT 24 | Aug 01 04:26:17 PM PDT 24 | 31169733 ps | ||
| T48 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.14802885 | Aug 01 04:26:17 PM PDT 24 | Aug 01 04:26:17 PM PDT 24 | 32000299 ps | ||
| T42 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3972574389 | Aug 01 04:26:20 PM PDT 24 | Aug 01 04:26:20 PM PDT 24 | 29823948 ps | ||
| T4 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1663182021 | Aug 01 04:26:20 PM PDT 24 | Aug 01 04:26:20 PM PDT 24 | 30218242 ps | ||
| T15 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3879774280 | Aug 01 04:26:17 PM PDT 24 | Aug 01 04:26:18 PM PDT 24 | 31388292 ps | ||
| T18 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1231548599 | Aug 01 04:26:22 PM PDT 24 | Aug 01 04:26:23 PM PDT 24 | 30252084 ps | ||
| T43 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3172194803 | Aug 01 04:26:08 PM PDT 24 | Aug 01 04:26:08 PM PDT 24 | 31083866 ps | ||
| T52 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4160044521 | Aug 01 04:26:17 PM PDT 24 | Aug 01 04:26:17 PM PDT 24 | 30448306 ps | ||
| T5 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1827352112 | Aug 01 04:26:17 PM PDT 24 | Aug 01 04:26:17 PM PDT 24 | 31298320 ps | ||
| T53 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2985495242 | Aug 01 04:26:05 PM PDT 24 | Aug 01 04:26:06 PM PDT 24 | 32235244 ps | ||
| T54 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2417999539 | Aug 01 04:26:18 PM PDT 24 | Aug 01 04:26:19 PM PDT 24 | 30137514 ps | ||
| T55 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.578394810 | Aug 01 04:26:14 PM PDT 24 | Aug 01 04:26:15 PM PDT 24 | 29145887 ps | ||
| T56 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1295764185 | Aug 01 04:26:08 PM PDT 24 | Aug 01 04:26:08 PM PDT 24 | 29164446 ps | ||
| T37 | /workspace/coverage/sync_alert/1.prim_sync_alert.2900607832 | Aug 01 05:29:07 PM PDT 24 | Aug 01 05:29:07 PM PDT 24 | 9463857 ps | ||
| T38 | /workspace/coverage/sync_alert/3.prim_sync_alert.2475226161 | Aug 01 05:29:05 PM PDT 24 | Aug 01 05:29:05 PM PDT 24 | 10208680 ps | ||
| T29 | /workspace/coverage/sync_alert/17.prim_sync_alert.3520051808 | Aug 01 05:29:10 PM PDT 24 | Aug 01 05:29:11 PM PDT 24 | 8588639 ps | ||
| T30 | /workspace/coverage/sync_alert/16.prim_sync_alert.219816036 | Aug 01 05:29:07 PM PDT 24 | Aug 01 05:29:07 PM PDT 24 | 10197146 ps | ||
| T39 | /workspace/coverage/sync_alert/9.prim_sync_alert.337915539 | Aug 01 05:29:05 PM PDT 24 | Aug 01 05:29:05 PM PDT 24 | 8836009 ps | ||
| T40 | /workspace/coverage/sync_alert/4.prim_sync_alert.3853906394 | Aug 01 05:29:04 PM PDT 24 | Aug 01 05:29:05 PM PDT 24 | 9724995 ps | ||
| T31 | /workspace/coverage/sync_alert/15.prim_sync_alert.1086833144 | Aug 01 05:29:05 PM PDT 24 | Aug 01 05:29:05 PM PDT 24 | 8739120 ps | ||
| T32 | /workspace/coverage/sync_alert/6.prim_sync_alert.1396195254 | Aug 01 05:29:03 PM PDT 24 | Aug 01 05:29:03 PM PDT 24 | 8780680 ps | ||
| T41 | /workspace/coverage/sync_alert/8.prim_sync_alert.3938357332 | Aug 01 05:29:15 PM PDT 24 | Aug 01 05:29:16 PM PDT 24 | 8727573 ps | ||
| T11 | /workspace/coverage/sync_alert/18.prim_sync_alert.3899714695 | Aug 01 05:29:02 PM PDT 24 | Aug 01 05:29:03 PM PDT 24 | 10170303 ps | ||
| T57 | /workspace/coverage/sync_alert/14.prim_sync_alert.1860269536 | Aug 01 05:29:07 PM PDT 24 | Aug 01 05:29:07 PM PDT 24 | 8836074 ps | ||
| T58 | /workspace/coverage/sync_alert/0.prim_sync_alert.990124445 | Aug 01 05:29:15 PM PDT 24 | Aug 01 05:29:16 PM PDT 24 | 8492568 ps | ||
| T33 | /workspace/coverage/sync_alert/2.prim_sync_alert.3575595843 | Aug 01 05:29:02 PM PDT 24 | Aug 01 05:29:03 PM PDT 24 | 9757730 ps | ||
| T59 | /workspace/coverage/sync_alert/5.prim_sync_alert.449219939 | Aug 01 05:29:05 PM PDT 24 | Aug 01 05:29:06 PM PDT 24 | 10780607 ps | ||
| T34 | /workspace/coverage/sync_alert/7.prim_sync_alert.2681560396 | Aug 01 05:29:02 PM PDT 24 | Aug 01 05:29:03 PM PDT 24 | 9554130 ps | ||
| T12 | /workspace/coverage/sync_alert/12.prim_sync_alert.3921736997 | Aug 01 05:29:03 PM PDT 24 | Aug 01 05:29:03 PM PDT 24 | 9793660 ps | ||
| T35 | /workspace/coverage/sync_alert/10.prim_sync_alert.3637521401 | Aug 01 05:29:02 PM PDT 24 | Aug 01 05:29:02 PM PDT 24 | 8224472 ps | ||
| T60 | /workspace/coverage/sync_alert/13.prim_sync_alert.1443054200 | Aug 01 05:29:03 PM PDT 24 | Aug 01 05:29:04 PM PDT 24 | 10425899 ps | ||
| T36 | /workspace/coverage/sync_alert/19.prim_sync_alert.2628105601 | Aug 01 05:29:02 PM PDT 24 | Aug 01 05:29:03 PM PDT 24 | 8659578 ps | ||
| T61 | /workspace/coverage/sync_alert/11.prim_sync_alert.3387358240 | Aug 01 05:29:05 PM PDT 24 | Aug 01 05:29:05 PM PDT 24 | 9080683 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.128267326 | Aug 01 04:26:28 PM PDT 24 | Aug 01 04:26:29 PM PDT 24 | 27227764 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2294031304 | Aug 01 04:26:16 PM PDT 24 | Aug 01 04:26:17 PM PDT 24 | 26020574 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3089147579 | Aug 01 04:26:18 PM PDT 24 | Aug 01 04:26:18 PM PDT 24 | 28102531 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2313734549 | Aug 01 04:26:23 PM PDT 24 | Aug 01 04:26:24 PM PDT 24 | 25520830 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1487213897 | Aug 01 04:26:14 PM PDT 24 | Aug 01 04:26:15 PM PDT 24 | 28446255 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1946909507 | Aug 01 04:26:16 PM PDT 24 | Aug 01 04:26:16 PM PDT 24 | 27133158 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1559419528 | Aug 01 04:26:18 PM PDT 24 | Aug 01 04:26:18 PM PDT 24 | 27661609 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2540171166 | Aug 01 04:26:16 PM PDT 24 | Aug 01 04:26:16 PM PDT 24 | 27682511 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2223248517 | Aug 01 04:26:16 PM PDT 24 | Aug 01 04:26:16 PM PDT 24 | 28915136 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1031364357 | Aug 01 04:26:22 PM PDT 24 | Aug 01 04:26:23 PM PDT 24 | 28823277 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3931822862 | Aug 01 04:26:22 PM PDT 24 | Aug 01 04:26:23 PM PDT 24 | 27452083 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4174590719 | Aug 01 04:26:18 PM PDT 24 | Aug 01 04:26:18 PM PDT 24 | 26825482 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2272851561 | Aug 01 04:26:16 PM PDT 24 | Aug 01 04:26:17 PM PDT 24 | 28092115 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2814348902 | Aug 01 04:26:15 PM PDT 24 | Aug 01 04:26:15 PM PDT 24 | 28665207 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4165111259 | Aug 01 04:26:14 PM PDT 24 | Aug 01 04:26:14 PM PDT 24 | 29692588 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.231612658 | Aug 01 04:26:18 PM PDT 24 | Aug 01 04:26:18 PM PDT 24 | 27681786 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.465812000 | Aug 01 04:26:18 PM PDT 24 | Aug 01 04:26:19 PM PDT 24 | 27240193 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2918191496 | Aug 01 04:26:16 PM PDT 24 | Aug 01 04:26:17 PM PDT 24 | 27702194 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2148917554 | Aug 01 04:26:16 PM PDT 24 | Aug 01 04:26:17 PM PDT 24 | 26933034 ps | ||
| T80 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.888532187 | Aug 01 04:26:30 PM PDT 24 | Aug 01 04:26:31 PM PDT 24 | 28816647 ps |
| Test location | /workspace/coverage/default/3.prim_async_alert.791530844 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11587394 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 05:28:51 PM PDT 24 |
| Finished | Aug 01 05:28:52 PM PDT 24 |
| Peak memory | 145748 kb |
| Host | smart-654bd176-a620-4a79-ba09-75cf643d1b41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=791530844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.791530844 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.3899714695 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10170303 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 05:29:02 PM PDT 24 |
| Finished | Aug 01 05:29:03 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-8df13081-a158-48ed-8f5b-1b51afaa7eb5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3899714695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3899714695 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1857250420 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 28078333 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 04:26:07 PM PDT 24 |
| Finished | Aug 01 04:26:07 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-d886da69-7bbc-48d6-9389-7a94411c896e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1857250420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1857250420 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.3181308189 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10534823 ps |
| CPU time | 0.46 seconds |
| Started | Aug 01 05:29:01 PM PDT 24 |
| Finished | Aug 01 05:29:01 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-a0b8c026-3e6a-4204-8de4-a943106c74b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3181308189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3181308189 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1827352112 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 31298320 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:17 PM PDT 24 |
| Finished | Aug 01 04:26:17 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-07dbb945-9bf7-403e-a164-5893b21f38c7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1827352112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1827352112 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.1096234929 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11149286 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:28:53 PM PDT 24 |
| Finished | Aug 01 05:28:53 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-580f5d96-ccba-4d61-ae9a-e927b3c63392 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1096234929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1096234929 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1770152804 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11935944 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 05:28:52 PM PDT 24 |
| Finished | Aug 01 05:28:52 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-465f0523-a700-4301-b5f2-9270f8a77219 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770152804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1770152804 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.641321052 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10780169 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 05:29:01 PM PDT 24 |
| Finished | Aug 01 05:29:01 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-906b38bd-02ce-46ba-a1de-06f6e220b925 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=641321052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.641321052 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.4281901450 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11771460 ps |
| CPU time | 0.43 seconds |
| Started | Aug 01 05:29:01 PM PDT 24 |
| Finished | Aug 01 05:29:02 PM PDT 24 |
| Peak memory | 145668 kb |
| Host | smart-dae6b7c5-9e6f-4058-a02c-8936b22330d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281901450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4281901450 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.3538165912 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11711010 ps |
| CPU time | 0.42 seconds |
| Started | Aug 01 05:29:02 PM PDT 24 |
| Finished | Aug 01 05:29:03 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-1787081c-acc2-443d-a2cf-b2fd13200320 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3538165912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3538165912 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.4012196520 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11147674 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 05:29:02 PM PDT 24 |
| Finished | Aug 01 05:29:02 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-a0d91e2b-107d-4e89-9f0e-0f51c004e892 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4012196520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.4012196520 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.4085406702 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12649659 ps |
| CPU time | 0.41 seconds |
| Started | Aug 01 05:29:03 PM PDT 24 |
| Finished | Aug 01 05:29:04 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-78788ddd-b66f-47f6-bc2d-412f58b89a6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4085406702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.4085406702 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1266549067 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11157004 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 05:29:02 PM PDT 24 |
| Finished | Aug 01 05:29:03 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-047b77d5-7ff8-4987-a0d4-cb6c0d9d627c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266549067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1266549067 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.3008243678 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11106632 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 05:29:03 PM PDT 24 |
| Finished | Aug 01 05:29:03 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-ab7a6d52-0b36-4f6d-b765-6ba3b93f9bd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008243678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3008243678 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.2925592825 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10510597 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:29:01 PM PDT 24 |
| Finished | Aug 01 05:29:01 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-410fbaf9-14a2-410d-9d62-eccfc635d3b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2925592825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2925592825 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.3752191189 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 11294387 ps |
| CPU time | 0.41 seconds |
| Started | Aug 01 05:29:02 PM PDT 24 |
| Finished | Aug 01 05:29:03 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-50b2e863-570f-4a63-b6ec-5238c93255a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3752191189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3752191189 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3979011778 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10331037 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:28:53 PM PDT 24 |
| Finished | Aug 01 05:28:53 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-cab91ae0-0440-4ecb-9526-0f61878774dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3979011778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3979011778 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.1032711856 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10916394 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:28:52 PM PDT 24 |
| Finished | Aug 01 05:28:52 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-34a6003c-5b00-4d6e-8745-2201a6e5888b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1032711856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1032711856 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.4037046770 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12172537 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:28:53 PM PDT 24 |
| Finished | Aug 01 05:28:54 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-26d47f91-2987-4014-82b8-6aa8a8457a32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037046770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.4037046770 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2824560654 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11493258 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 05:28:52 PM PDT 24 |
| Finished | Aug 01 05:28:53 PM PDT 24 |
| Peak memory | 145744 kb |
| Host | smart-558d80c4-65a3-4251-92f6-4a70fa6f0a8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2824560654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2824560654 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.711821331 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10621488 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:28:48 PM PDT 24 |
| Finished | Aug 01 05:28:48 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-e6317114-e46b-4165-aaa6-7d6ba53a2e32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=711821331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.711821331 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.3789472669 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10955941 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 05:28:53 PM PDT 24 |
| Finished | Aug 01 05:28:53 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-7c00b3b5-1a1a-4841-899a-a08f7da46704 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3789472669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3789472669 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.3482655222 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10572421 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:29:01 PM PDT 24 |
| Finished | Aug 01 05:29:02 PM PDT 24 |
| Peak memory | 145756 kb |
| Host | smart-307a9323-b03f-43d2-8c3b-fa727743714c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3482655222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3482655222 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3172194803 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 31083866 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:08 PM PDT 24 |
| Finished | Aug 01 04:26:08 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-9896629e-b50e-4b0c-adc4-9f702130372f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3172194803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3172194803 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1295764185 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 29164446 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 04:26:08 PM PDT 24 |
| Finished | Aug 01 04:26:08 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-87636324-35b5-4b95-a54e-cb3f6e3a8528 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1295764185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1295764185 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3879774280 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 31388292 ps |
| CPU time | 0.41 seconds |
| Started | Aug 01 04:26:17 PM PDT 24 |
| Finished | Aug 01 04:26:18 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-6e911860-525f-411c-a8da-51d2a2184064 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3879774280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3879774280 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1231548599 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 30252084 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:22 PM PDT 24 |
| Finished | Aug 01 04:26:23 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-aa886029-50a9-4eb3-b661-3a3b00f68f70 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1231548599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1231548599 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1967761774 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 29820402 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 04:26:19 PM PDT 24 |
| Finished | Aug 01 04:26:19 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-c29caacb-2466-4420-979a-9839e8a14aa5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1967761774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1967761774 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2187281957 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 30012399 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:17 PM PDT 24 |
| Finished | Aug 01 04:26:17 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-623fb9ff-e3de-4e08-8007-3b1b0e3263d3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2187281957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2187281957 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2417999539 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30137514 ps |
| CPU time | 0.41 seconds |
| Started | Aug 01 04:26:18 PM PDT 24 |
| Finished | Aug 01 04:26:19 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-9ac7be57-d673-4547-b2f9-688f50ce7c87 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2417999539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2417999539 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2158978236 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 31169733 ps |
| CPU time | 0.41 seconds |
| Started | Aug 01 04:26:17 PM PDT 24 |
| Finished | Aug 01 04:26:17 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-82c26120-7d49-4870-bcc1-5d3d78cbc43a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2158978236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2158978236 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.961937569 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29372016 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 04:26:28 PM PDT 24 |
| Finished | Aug 01 04:26:28 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-3a6a4b2c-e2ed-426e-8fc5-2d01aed8e83b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=961937569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.961937569 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3159088826 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29978927 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 04:26:28 PM PDT 24 |
| Finished | Aug 01 04:26:29 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-b37ac85d-3146-4e86-bba8-e45ae80349d0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3159088826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3159088826 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.14802885 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 32000299 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:17 PM PDT 24 |
| Finished | Aug 01 04:26:17 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-f913881f-f89e-4b9c-b7ef-26ba4a10ce6c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=14802885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.14802885 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2985495242 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 32235244 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 04:26:05 PM PDT 24 |
| Finished | Aug 01 04:26:06 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-e32dc63d-bdcf-4ad9-b628-e355ba82944a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2985495242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2985495242 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2022174958 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 29870603 ps |
| CPU time | 0.42 seconds |
| Started | Aug 01 04:26:08 PM PDT 24 |
| Finished | Aug 01 04:26:09 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-828f8020-4d40-435b-affa-70a3f1bb2a9a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2022174958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2022174958 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4160044521 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30448306 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 04:26:17 PM PDT 24 |
| Finished | Aug 01 04:26:17 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-4f3fdae2-738f-46fc-a823-615aa4bb2839 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4160044521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.4160044521 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3972574389 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29823948 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 04:26:20 PM PDT 24 |
| Finished | Aug 01 04:26:20 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-965d5a78-1dbb-4d18-9e6f-d233933b61a6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3972574389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3972574389 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2636089457 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 29758015 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 04:26:07 PM PDT 24 |
| Finished | Aug 01 04:26:08 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-ed7f00f2-e44a-4397-ae21-b8d29b9d606e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2636089457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2636089457 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1663182021 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30218242 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 04:26:20 PM PDT 24 |
| Finished | Aug 01 04:26:20 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-83c7a06c-2267-4ca4-80ef-e5521a4f8cf2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1663182021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1663182021 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.578394810 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29145887 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 04:26:14 PM PDT 24 |
| Finished | Aug 01 04:26:15 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-633e3aab-47f7-427c-841e-43aec3133779 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=578394810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.578394810 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.990124445 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8492568 ps |
| CPU time | 0.37 seconds |
| Started | Aug 01 05:29:15 PM PDT 24 |
| Finished | Aug 01 05:29:16 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-df203b6a-5b9b-4b47-88d2-fb5dc53065b8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=990124445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.990124445 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.2900607832 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9463857 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 05:29:07 PM PDT 24 |
| Finished | Aug 01 05:29:07 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-ac91d13e-cc4f-4838-82a0-3208745d0c35 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2900607832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2900607832 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3637521401 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8224472 ps |
| CPU time | 0.42 seconds |
| Started | Aug 01 05:29:02 PM PDT 24 |
| Finished | Aug 01 05:29:02 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-93008cd2-8a23-4f83-85aa-b5a3cab3634c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3637521401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3637521401 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.3387358240 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9080683 ps |
| CPU time | 0.37 seconds |
| Started | Aug 01 05:29:05 PM PDT 24 |
| Finished | Aug 01 05:29:05 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-b75b9710-e4dc-4382-b4a6-b00e84119b6c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3387358240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3387358240 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3921736997 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 9793660 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 05:29:03 PM PDT 24 |
| Finished | Aug 01 05:29:03 PM PDT 24 |
| Peak memory | 145500 kb |
| Host | smart-53ed7595-5f60-46ce-a8e5-5e800cf7b362 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3921736997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3921736997 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1443054200 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 10425899 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:29:03 PM PDT 24 |
| Finished | Aug 01 05:29:04 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-47809e5c-bece-4b61-b00d-2958be8e814b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1443054200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1443054200 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1860269536 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8836074 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:29:07 PM PDT 24 |
| Finished | Aug 01 05:29:07 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-1013b2cb-b28f-4898-abc5-60c1c3a8b86e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1860269536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1860269536 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.1086833144 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8739120 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:29:05 PM PDT 24 |
| Finished | Aug 01 05:29:05 PM PDT 24 |
| Peak memory | 145500 kb |
| Host | smart-38814bfa-32c6-4ef1-af4f-4a6750ba79ad |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1086833144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1086833144 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.219816036 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 10197146 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:29:07 PM PDT 24 |
| Finished | Aug 01 05:29:07 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-bb6cda54-328d-4843-9282-c95c5fd3406f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=219816036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.219816036 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.3520051808 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8588639 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:29:10 PM PDT 24 |
| Finished | Aug 01 05:29:11 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-96f860c0-c8bc-4d25-a015-e5d95a56e5da |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3520051808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3520051808 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.2628105601 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8659578 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 05:29:02 PM PDT 24 |
| Finished | Aug 01 05:29:03 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-dd1a9329-0506-4c6a-8705-baca9647c764 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2628105601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2628105601 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.3575595843 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9757730 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:29:02 PM PDT 24 |
| Finished | Aug 01 05:29:03 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-8258d293-eb99-48d8-a582-85378131cb9d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3575595843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3575595843 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.2475226161 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10208680 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 05:29:05 PM PDT 24 |
| Finished | Aug 01 05:29:05 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-0111c8b5-eab8-4729-9f05-db648e8aa380 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2475226161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2475226161 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.3853906394 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9724995 ps |
| CPU time | 0.37 seconds |
| Started | Aug 01 05:29:04 PM PDT 24 |
| Finished | Aug 01 05:29:05 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-4cd46948-59cc-4bc6-845c-4b581b286a50 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3853906394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3853906394 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.449219939 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 10780607 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 05:29:05 PM PDT 24 |
| Finished | Aug 01 05:29:06 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-cf5efbbf-9e25-4b8d-8731-ee2638f0cf6c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=449219939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.449219939 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1396195254 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8780680 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:29:03 PM PDT 24 |
| Finished | Aug 01 05:29:03 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-e603d3d4-f116-40a1-8ea6-626068d867e6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1396195254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1396195254 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.2681560396 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9554130 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 05:29:02 PM PDT 24 |
| Finished | Aug 01 05:29:03 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-d1998d73-e2f1-4dae-b83d-11a56dfa22e2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2681560396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2681560396 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.3938357332 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8727573 ps |
| CPU time | 0.37 seconds |
| Started | Aug 01 05:29:15 PM PDT 24 |
| Finished | Aug 01 05:29:16 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-30728109-73d3-4c04-9d87-6c26a77db0c6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3938357332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3938357332 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.337915539 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8836009 ps |
| CPU time | 0.37 seconds |
| Started | Aug 01 05:29:05 PM PDT 24 |
| Finished | Aug 01 05:29:05 PM PDT 24 |
| Peak memory | 145476 kb |
| Host | smart-7622cbae-ab16-4bd3-8866-a31fa5850136 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=337915539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.337915539 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2814348902 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28665207 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:15 PM PDT 24 |
| Finished | Aug 01 04:26:15 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-bab75a89-dc9a-4fbf-b1be-3eb64219af37 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2814348902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2814348902 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.888532187 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 28816647 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:30 PM PDT 24 |
| Finished | Aug 01 04:26:31 PM PDT 24 |
| Peak memory | 145372 kb |
| Host | smart-01c71b59-03a3-4df0-937d-0686b01e1943 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=888532187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.888532187 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1946909507 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27133158 ps |
| CPU time | 0.42 seconds |
| Started | Aug 01 04:26:16 PM PDT 24 |
| Finished | Aug 01 04:26:16 PM PDT 24 |
| Peak memory | 145536 kb |
| Host | smart-5d4fda8f-a432-46b6-ad1b-b1bdc7892e80 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1946909507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1946909507 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4174590719 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26825482 ps |
| CPU time | 0.42 seconds |
| Started | Aug 01 04:26:18 PM PDT 24 |
| Finished | Aug 01 04:26:18 PM PDT 24 |
| Peak memory | 145448 kb |
| Host | smart-50c8cb66-c866-4aca-8312-fd3820a318f5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4174590719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.4174590719 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3089147579 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 28102531 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 04:26:18 PM PDT 24 |
| Finished | Aug 01 04:26:18 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-3c1efe6f-d032-4f81-903d-325af6b235db |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3089147579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3089147579 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2918191496 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 27702194 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:16 PM PDT 24 |
| Finished | Aug 01 04:26:17 PM PDT 24 |
| Peak memory | 145396 kb |
| Host | smart-9e5e8a62-0fd6-4c77-b074-8d8e38fcb3cc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2918191496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2918191496 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1031364357 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28823277 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:22 PM PDT 24 |
| Finished | Aug 01 04:26:23 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-93e3f1bf-034d-4ebe-b85c-a36bbea6384f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1031364357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1031364357 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1559419528 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27661609 ps |
| CPU time | 0.41 seconds |
| Started | Aug 01 04:26:18 PM PDT 24 |
| Finished | Aug 01 04:26:18 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-9322723d-9955-44fe-b868-e92389456a64 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1559419528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1559419528 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.465812000 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27240193 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 04:26:18 PM PDT 24 |
| Finished | Aug 01 04:26:19 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-7a90650d-eea9-4174-9828-883a02482c13 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=465812000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.465812000 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2294031304 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 26020574 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 04:26:16 PM PDT 24 |
| Finished | Aug 01 04:26:17 PM PDT 24 |
| Peak memory | 145372 kb |
| Host | smart-c7934fb8-9657-408d-a626-0accde9766fd |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2294031304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2294031304 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2540171166 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27682511 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 04:26:16 PM PDT 24 |
| Finished | Aug 01 04:26:16 PM PDT 24 |
| Peak memory | 145400 kb |
| Host | smart-5bcc0a26-c05a-4466-afd4-061d6cf37d89 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2540171166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2540171166 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3931822862 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27452083 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:22 PM PDT 24 |
| Finished | Aug 01 04:26:23 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-3f3ab881-476b-4691-84f6-d3e0b3962eba |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3931822862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3931822862 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2148917554 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 26933034 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 04:26:16 PM PDT 24 |
| Finished | Aug 01 04:26:17 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-1b573303-a5f7-4d4d-b06a-05d9c2796c0e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2148917554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2148917554 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.128267326 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27227764 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:28 PM PDT 24 |
| Finished | Aug 01 04:26:29 PM PDT 24 |
| Peak memory | 145372 kb |
| Host | smart-e02f865b-dcb4-4024-9fb4-38e2041600d3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=128267326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.128267326 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1487213897 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 28446255 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:14 PM PDT 24 |
| Finished | Aug 01 04:26:15 PM PDT 24 |
| Peak memory | 145400 kb |
| Host | smart-1c410a9b-1c0c-4611-9908-ee2bafcd6d35 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1487213897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1487213897 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2272851561 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 28092115 ps |
| CPU time | 0.42 seconds |
| Started | Aug 01 04:26:16 PM PDT 24 |
| Finished | Aug 01 04:26:17 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-80ea98ec-cdc5-4d22-8a23-e406de963ebb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2272851561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2272851561 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2313734549 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 25520830 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:23 PM PDT 24 |
| Finished | Aug 01 04:26:24 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-cec328c2-ff8b-4739-a901-8632e1b01d1b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2313734549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2313734549 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2223248517 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28915136 ps |
| CPU time | 0.44 seconds |
| Started | Aug 01 04:26:16 PM PDT 24 |
| Finished | Aug 01 04:26:16 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-c0e02e65-d433-4c0d-90a7-d82543085934 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2223248517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2223248517 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.231612658 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27681786 ps |
| CPU time | 0.4 seconds |
| Started | Aug 01 04:26:18 PM PDT 24 |
| Finished | Aug 01 04:26:18 PM PDT 24 |
| Peak memory | 145524 kb |
| Host | smart-9a090c83-1382-4627-8ae4-7a100339ca9f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=231612658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.231612658 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4165111259 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 29692588 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:26:14 PM PDT 24 |
| Finished | Aug 01 04:26:14 PM PDT 24 |
| Peak memory | 145404 kb |
| Host | smart-c04207dc-7b06-4fef-bd23-991694b42a35 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4165111259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.4165111259 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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