| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.60 | 100.00 | 100.00 | 100.00 | 85.71 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.32 | 88.32 | 100.00 | 100.00 | 91.67 | 91.67 | 100.00 | 100.00 | 75.00 | 75.00 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/2.prim_async_alert.3427282566 |
| 91.80 | 3.48 | 100.00 | 0.00 | 93.75 | 2.08 | 100.00 | 0.00 | 82.14 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/0.prim_sync_alert.1431628428 |
| 93.56 | 1.76 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 85.71 | 3.57 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.137503781 |
| 94.25 | 0.69 | 100.00 | 0.00 | 97.92 | 4.17 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/13.prim_async_alert.924405699 |
| 94.60 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.468146330 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.3279722848 |
| /workspace/coverage/default/1.prim_async_alert.681347727 |
| /workspace/coverage/default/10.prim_async_alert.3158030599 |
| /workspace/coverage/default/11.prim_async_alert.2662159484 |
| /workspace/coverage/default/12.prim_async_alert.2280949244 |
| /workspace/coverage/default/14.prim_async_alert.3928693091 |
| /workspace/coverage/default/15.prim_async_alert.2215291506 |
| /workspace/coverage/default/16.prim_async_alert.2775872934 |
| /workspace/coverage/default/17.prim_async_alert.3826914506 |
| /workspace/coverage/default/18.prim_async_alert.2633578726 |
| /workspace/coverage/default/19.prim_async_alert.1480669967 |
| /workspace/coverage/default/3.prim_async_alert.419213974 |
| /workspace/coverage/default/4.prim_async_alert.3838113279 |
| /workspace/coverage/default/5.prim_async_alert.2618153819 |
| /workspace/coverage/default/6.prim_async_alert.6865456 |
| /workspace/coverage/default/7.prim_async_alert.1133358114 |
| /workspace/coverage/default/8.prim_async_alert.1658619027 |
| /workspace/coverage/default/9.prim_async_alert.1984114891 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4094582264 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1156478802 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2683812327 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1313101744 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.857978733 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3706430263 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.310925119 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.345519622 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3277034226 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.212342834 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4194358186 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3044248806 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.643006231 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1169884862 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1255628626 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4021745216 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.742611670 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2493385482 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.1498429900 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3509950169 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.707937979 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3499850941 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.467727621 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1953468376 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.3848321996 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.2772641248 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.619191668 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.473674605 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.3697861305 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.3952047479 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.2759912483 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.1520002520 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.1407111986 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1462434042 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.1350728667 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.520873083 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.257544845 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1195653868 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3967384312 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4098303361 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3525252456 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2559510105 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3379781700 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3948171717 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1250392135 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2610293605 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3940880817 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1415156841 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2544811764 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3405398546 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3911611298 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4080796199 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2482206109 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2971594316 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2427550170 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3745851039 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3835490690 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/15.prim_async_alert.2215291506 | Aug 02 05:05:29 PM PDT 24 | Aug 02 05:05:30 PM PDT 24 | 10810794 ps | ||
| T2 | /workspace/coverage/default/18.prim_async_alert.2633578726 | Aug 02 05:05:30 PM PDT 24 | Aug 02 05:05:31 PM PDT 24 | 11426136 ps | ||
| T3 | /workspace/coverage/default/2.prim_async_alert.3427282566 | Aug 02 05:05:18 PM PDT 24 | Aug 02 05:05:19 PM PDT 24 | 11039326 ps | ||
| T10 | /workspace/coverage/default/3.prim_async_alert.419213974 | Aug 02 05:05:24 PM PDT 24 | Aug 02 05:05:24 PM PDT 24 | 10718496 ps | ||
| T22 | /workspace/coverage/default/16.prim_async_alert.2775872934 | Aug 02 05:05:28 PM PDT 24 | Aug 02 05:05:29 PM PDT 24 | 11581939 ps | ||
| T11 | /workspace/coverage/default/5.prim_async_alert.2618153819 | Aug 02 05:05:21 PM PDT 24 | Aug 02 05:05:21 PM PDT 24 | 11237328 ps | ||
| T23 | /workspace/coverage/default/19.prim_async_alert.1480669967 | Aug 02 05:05:38 PM PDT 24 | Aug 02 05:05:38 PM PDT 24 | 11148334 ps | ||
| T24 | /workspace/coverage/default/0.prim_async_alert.3279722848 | Aug 02 05:05:21 PM PDT 24 | Aug 02 05:05:21 PM PDT 24 | 10976044 ps | ||
| T15 | /workspace/coverage/default/10.prim_async_alert.3158030599 | Aug 02 05:05:27 PM PDT 24 | Aug 02 05:05:28 PM PDT 24 | 11977709 ps | ||
| T16 | /workspace/coverage/default/7.prim_async_alert.1133358114 | Aug 02 05:05:27 PM PDT 24 | Aug 02 05:05:28 PM PDT 24 | 11910168 ps | ||
| T20 | /workspace/coverage/default/6.prim_async_alert.6865456 | Aug 02 05:05:28 PM PDT 24 | Aug 02 05:05:29 PM PDT 24 | 11742332 ps | ||
| T25 | /workspace/coverage/default/9.prim_async_alert.1984114891 | Aug 02 05:05:30 PM PDT 24 | Aug 02 05:05:30 PM PDT 24 | 10228036 ps | ||
| T17 | /workspace/coverage/default/1.prim_async_alert.681347727 | Aug 02 05:05:23 PM PDT 24 | Aug 02 05:05:23 PM PDT 24 | 12417302 ps | ||
| T26 | /workspace/coverage/default/4.prim_async_alert.3838113279 | Aug 02 05:05:21 PM PDT 24 | Aug 02 05:05:22 PM PDT 24 | 11595953 ps | ||
| T27 | /workspace/coverage/default/11.prim_async_alert.2662159484 | Aug 02 05:05:30 PM PDT 24 | Aug 02 05:05:31 PM PDT 24 | 11321319 ps | ||
| T46 | /workspace/coverage/default/14.prim_async_alert.3928693091 | Aug 02 05:05:30 PM PDT 24 | Aug 02 05:05:30 PM PDT 24 | 11835761 ps | ||
| T7 | /workspace/coverage/default/13.prim_async_alert.924405699 | Aug 02 05:05:28 PM PDT 24 | Aug 02 05:05:29 PM PDT 24 | 10360402 ps | ||
| T8 | /workspace/coverage/default/12.prim_async_alert.2280949244 | Aug 02 05:05:30 PM PDT 24 | Aug 02 05:05:31 PM PDT 24 | 11343129 ps | ||
| T9 | /workspace/coverage/default/8.prim_async_alert.1658619027 | Aug 02 05:05:28 PM PDT 24 | Aug 02 05:05:29 PM PDT 24 | 11867162 ps | ||
| T47 | /workspace/coverage/default/17.prim_async_alert.3826914506 | Aug 02 05:05:28 PM PDT 24 | Aug 02 05:05:28 PM PDT 24 | 10976918 ps | ||
| T21 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2493385482 | Aug 02 05:05:35 PM PDT 24 | Aug 02 05:05:36 PM PDT 24 | 29180479 ps | ||
| T18 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4094582264 | Aug 02 05:05:39 PM PDT 24 | Aug 02 05:05:39 PM PDT 24 | 30067081 ps | ||
| T40 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4021745216 | Aug 02 05:05:39 PM PDT 24 | Aug 02 05:05:40 PM PDT 24 | 29504303 ps | ||
| T41 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3706430263 | Aug 02 05:05:36 PM PDT 24 | Aug 02 05:05:37 PM PDT 24 | 32212399 ps | ||
| T19 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.137503781 | Aug 02 05:05:37 PM PDT 24 | Aug 02 05:05:38 PM PDT 24 | 31321405 ps | ||
| T42 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4194358186 | Aug 02 05:05:38 PM PDT 24 | Aug 02 05:05:39 PM PDT 24 | 28025188 ps | ||
| T43 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1313101744 | Aug 02 05:05:37 PM PDT 24 | Aug 02 05:05:38 PM PDT 24 | 30651355 ps | ||
| T44 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.212342834 | Aug 02 05:05:36 PM PDT 24 | Aug 02 05:05:36 PM PDT 24 | 31343220 ps | ||
| T45 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1156478802 | Aug 02 05:05:38 PM PDT 24 | Aug 02 05:05:38 PM PDT 24 | 30128340 ps | ||
| T4 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.468146330 | Aug 02 05:05:34 PM PDT 24 | Aug 02 05:05:35 PM PDT 24 | 30463732 ps | ||
| T48 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3277034226 | Aug 02 05:05:34 PM PDT 24 | Aug 02 05:05:34 PM PDT 24 | 31053535 ps | ||
| T49 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1255628626 | Aug 02 05:05:35 PM PDT 24 | Aug 02 05:05:36 PM PDT 24 | 30939630 ps | ||
| T50 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.345519622 | Aug 02 05:05:37 PM PDT 24 | Aug 02 05:05:37 PM PDT 24 | 30484849 ps | ||
| T51 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.310925119 | Aug 02 05:05:35 PM PDT 24 | Aug 02 05:05:35 PM PDT 24 | 31119996 ps | ||
| T39 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.643006231 | Aug 02 05:05:35 PM PDT 24 | Aug 02 05:05:36 PM PDT 24 | 31189991 ps | ||
| T52 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3044248806 | Aug 02 05:05:35 PM PDT 24 | Aug 02 05:05:35 PM PDT 24 | 27608369 ps | ||
| T53 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.857978733 | Aug 02 05:05:35 PM PDT 24 | Aug 02 05:05:36 PM PDT 24 | 28450878 ps | ||
| T54 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2683812327 | Aug 02 05:05:34 PM PDT 24 | Aug 02 05:05:35 PM PDT 24 | 30408455 ps | ||
| T55 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1169884862 | Aug 02 05:05:36 PM PDT 24 | Aug 02 05:05:37 PM PDT 24 | 29550513 ps | ||
| T56 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.742611670 | Aug 02 05:05:37 PM PDT 24 | Aug 02 05:05:38 PM PDT 24 | 30056906 ps | ||
| T36 | /workspace/coverage/sync_alert/18.prim_sync_alert.473674605 | Aug 02 05:07:35 PM PDT 24 | Aug 02 05:07:35 PM PDT 24 | 10247307 ps | ||
| T28 | /workspace/coverage/sync_alert/5.prim_sync_alert.1407111986 | Aug 02 05:07:30 PM PDT 24 | Aug 02 05:07:30 PM PDT 24 | 9174673 ps | ||
| T29 | /workspace/coverage/sync_alert/13.prim_sync_alert.467727621 | Aug 02 05:07:31 PM PDT 24 | Aug 02 05:07:31 PM PDT 24 | 9524880 ps | ||
| T30 | /workspace/coverage/sync_alert/2.prim_sync_alert.3952047479 | Aug 02 05:07:33 PM PDT 24 | Aug 02 05:07:33 PM PDT 24 | 9995822 ps | ||
| T37 | /workspace/coverage/sync_alert/6.prim_sync_alert.1462434042 | Aug 02 05:07:32 PM PDT 24 | Aug 02 05:07:33 PM PDT 24 | 8523815 ps | ||
| T31 | /workspace/coverage/sync_alert/11.prim_sync_alert.707937979 | Aug 02 05:07:30 PM PDT 24 | Aug 02 05:07:31 PM PDT 24 | 9304784 ps | ||
| T32 | /workspace/coverage/sync_alert/10.prim_sync_alert.3509950169 | Aug 02 05:07:34 PM PDT 24 | Aug 02 05:07:35 PM PDT 24 | 10088674 ps | ||
| T33 | /workspace/coverage/sync_alert/16.prim_sync_alert.2772641248 | Aug 02 05:07:31 PM PDT 24 | Aug 02 05:07:31 PM PDT 24 | 8437871 ps | ||
| T38 | /workspace/coverage/sync_alert/1.prim_sync_alert.1498429900 | Aug 02 05:07:32 PM PDT 24 | Aug 02 05:07:32 PM PDT 24 | 9168636 ps | ||
| T12 | /workspace/coverage/sync_alert/0.prim_sync_alert.1431628428 | Aug 02 05:07:32 PM PDT 24 | Aug 02 05:07:33 PM PDT 24 | 9449660 ps | ||
| T13 | /workspace/coverage/sync_alert/15.prim_sync_alert.3848321996 | Aug 02 05:07:32 PM PDT 24 | Aug 02 05:07:33 PM PDT 24 | 9416913 ps | ||
| T34 | /workspace/coverage/sync_alert/19.prim_sync_alert.3697861305 | Aug 02 05:07:31 PM PDT 24 | Aug 02 05:07:31 PM PDT 24 | 8306088 ps | ||
| T35 | /workspace/coverage/sync_alert/17.prim_sync_alert.619191668 | Aug 02 05:07:31 PM PDT 24 | Aug 02 05:07:31 PM PDT 24 | 9590526 ps | ||
| T57 | /workspace/coverage/sync_alert/14.prim_sync_alert.1953468376 | Aug 02 05:07:30 PM PDT 24 | Aug 02 05:07:31 PM PDT 24 | 9340604 ps | ||
| T58 | /workspace/coverage/sync_alert/9.prim_sync_alert.257544845 | Aug 02 05:07:29 PM PDT 24 | Aug 02 05:07:30 PM PDT 24 | 9923573 ps | ||
| T59 | /workspace/coverage/sync_alert/12.prim_sync_alert.3499850941 | Aug 02 05:07:31 PM PDT 24 | Aug 02 05:07:31 PM PDT 24 | 9615561 ps | ||
| T60 | /workspace/coverage/sync_alert/4.prim_sync_alert.1520002520 | Aug 02 05:07:33 PM PDT 24 | Aug 02 05:07:33 PM PDT 24 | 9792989 ps | ||
| T61 | /workspace/coverage/sync_alert/3.prim_sync_alert.2759912483 | Aug 02 05:07:31 PM PDT 24 | Aug 02 05:07:31 PM PDT 24 | 9432160 ps | ||
| T62 | /workspace/coverage/sync_alert/7.prim_sync_alert.1350728667 | Aug 02 05:07:32 PM PDT 24 | Aug 02 05:07:33 PM PDT 24 | 9416353 ps | ||
| T63 | /workspace/coverage/sync_alert/8.prim_sync_alert.520873083 | Aug 02 05:07:32 PM PDT 24 | Aug 02 05:07:32 PM PDT 24 | 9181068 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4080796199 | Aug 02 05:07:32 PM PDT 24 | Aug 02 05:07:33 PM PDT 24 | 26335847 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3948171717 | Aug 02 05:07:48 PM PDT 24 | Aug 02 05:07:48 PM PDT 24 | 26137916 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2559510105 | Aug 02 05:07:49 PM PDT 24 | Aug 02 05:07:49 PM PDT 24 | 28465130 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3379781700 | Aug 02 05:07:47 PM PDT 24 | Aug 02 05:07:47 PM PDT 24 | 26052258 ps | ||
| T14 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1195653868 | Aug 02 05:07:32 PM PDT 24 | Aug 02 05:07:32 PM PDT 24 | 26221846 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1415156841 | Aug 02 05:07:47 PM PDT 24 | Aug 02 05:07:48 PM PDT 24 | 27899155 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3940880817 | Aug 02 05:07:47 PM PDT 24 | Aug 02 05:07:48 PM PDT 24 | 26598707 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2544811764 | Aug 02 05:07:46 PM PDT 24 | Aug 02 05:07:47 PM PDT 24 | 25947152 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2427550170 | Aug 02 05:07:29 PM PDT 24 | Aug 02 05:07:29 PM PDT 24 | 26295385 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3911611298 | Aug 02 05:07:32 PM PDT 24 | Aug 02 05:07:33 PM PDT 24 | 29068544 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2482206109 | Aug 02 05:07:34 PM PDT 24 | Aug 02 05:07:34 PM PDT 24 | 30369247 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3835490690 | Aug 02 05:07:34 PM PDT 24 | Aug 02 05:07:35 PM PDT 24 | 27529340 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3405398546 | Aug 02 05:07:33 PM PDT 24 | Aug 02 05:07:33 PM PDT 24 | 28685951 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1250392135 | Aug 02 05:07:38 PM PDT 24 | Aug 02 05:07:38 PM PDT 24 | 26468160 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2610293605 | Aug 02 05:07:40 PM PDT 24 | Aug 02 05:07:40 PM PDT 24 | 27885975 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2971594316 | Aug 02 05:07:32 PM PDT 24 | Aug 02 05:07:33 PM PDT 24 | 27416315 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3967384312 | Aug 02 05:07:33 PM PDT 24 | Aug 02 05:07:34 PM PDT 24 | 28377110 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3525252456 | Aug 02 05:07:45 PM PDT 24 | Aug 02 05:07:46 PM PDT 24 | 27918792 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4098303361 | Aug 02 05:07:34 PM PDT 24 | Aug 02 05:07:34 PM PDT 24 | 27531906 ps | ||
| T80 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3745851039 | Aug 02 05:07:31 PM PDT 24 | Aug 02 05:07:32 PM PDT 24 | 29050341 ps |
| Test location | /workspace/coverage/default/2.prim_async_alert.3427282566 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11039326 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:05:18 PM PDT 24 |
| Finished | Aug 02 05:05:19 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-804beaf6-1f3a-4ae9-801d-a5d12281d425 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3427282566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3427282566 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.1431628428 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 9449660 ps |
| CPU time | 0.41 seconds |
| Started | Aug 02 05:07:32 PM PDT 24 |
| Finished | Aug 02 05:07:33 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-e1ec55a7-0099-4716-80dd-7539509d76dd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1431628428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1431628428 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.137503781 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 31321405 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:05:37 PM PDT 24 |
| Finished | Aug 02 05:05:38 PM PDT 24 |
| Peak memory | 145356 kb |
| Host | smart-6b626a66-679d-4a14-ae96-e91dc9933973 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=137503781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.137503781 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.924405699 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10360402 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:05:28 PM PDT 24 |
| Finished | Aug 02 05:05:29 PM PDT 24 |
| Peak memory | 145756 kb |
| Host | smart-59ad04bc-f419-46d1-92a2-62c5162beb8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=924405699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.924405699 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.468146330 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30463732 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:05:34 PM PDT 24 |
| Finished | Aug 02 05:05:35 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-c9493b1a-d53e-4028-91bd-cadf61589216 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=468146330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.468146330 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.3279722848 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10976044 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:05:21 PM PDT 24 |
| Finished | Aug 02 05:05:21 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-3caf204f-66be-4c0b-aed1-30531be736a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279722848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3279722848 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.681347727 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12417302 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:05:23 PM PDT 24 |
| Finished | Aug 02 05:05:23 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-7239af1a-b3cc-4d71-9212-330b82e4698b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=681347727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.681347727 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.3158030599 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11977709 ps |
| CPU time | 0.38 seconds |
| Started | Aug 02 05:05:27 PM PDT 24 |
| Finished | Aug 02 05:05:28 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-15239b60-4a5b-40cd-9980-9d26a09d1542 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158030599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3158030599 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.2662159484 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 11321319 ps |
| CPU time | 0.42 seconds |
| Started | Aug 02 05:05:30 PM PDT 24 |
| Finished | Aug 02 05:05:31 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-0183991e-50d2-4fa0-b25a-797a1dd76e86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662159484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2662159484 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.2280949244 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11343129 ps |
| CPU time | 0.38 seconds |
| Started | Aug 02 05:05:30 PM PDT 24 |
| Finished | Aug 02 05:05:31 PM PDT 24 |
| Peak memory | 145680 kb |
| Host | smart-f4ecfe32-a35a-43b2-adf8-e6912afd8a84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280949244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2280949244 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.3928693091 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11835761 ps |
| CPU time | 0.42 seconds |
| Started | Aug 02 05:05:30 PM PDT 24 |
| Finished | Aug 02 05:05:30 PM PDT 24 |
| Peak memory | 145852 kb |
| Host | smart-eb316e59-2d99-4723-b307-276f47514ce5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3928693091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3928693091 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.2215291506 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10810794 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:05:29 PM PDT 24 |
| Finished | Aug 02 05:05:30 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-ef8ed327-79de-4f7a-a2f0-822c3547b180 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215291506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2215291506 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.2775872934 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11581939 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:05:28 PM PDT 24 |
| Finished | Aug 02 05:05:29 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-27951db5-187a-4a3f-8783-41726a6f87ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2775872934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2775872934 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.3826914506 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10976918 ps |
| CPU time | 0.38 seconds |
| Started | Aug 02 05:05:28 PM PDT 24 |
| Finished | Aug 02 05:05:28 PM PDT 24 |
| Peak memory | 145868 kb |
| Host | smart-f81410e6-dfca-4113-b5a7-2bf0938fc19a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3826914506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3826914506 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.2633578726 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11426136 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:05:30 PM PDT 24 |
| Finished | Aug 02 05:05:31 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-ff10f6f7-3068-4585-a665-8a5bd24a80fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2633578726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2633578726 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.1480669967 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11148334 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:05:38 PM PDT 24 |
| Finished | Aug 02 05:05:38 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-4240baba-f252-4d44-b42f-d8d50539af3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1480669967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1480669967 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.419213974 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10718496 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:05:24 PM PDT 24 |
| Finished | Aug 02 05:05:24 PM PDT 24 |
| Peak memory | 145852 kb |
| Host | smart-8a3f5a57-73b4-438b-8cd8-beedfbe0af05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419213974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.419213974 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.3838113279 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11595953 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:05:21 PM PDT 24 |
| Finished | Aug 02 05:05:22 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-abb927d2-6a30-430d-834e-6cccb21a4aa5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3838113279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3838113279 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.2618153819 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11237328 ps |
| CPU time | 0.38 seconds |
| Started | Aug 02 05:05:21 PM PDT 24 |
| Finished | Aug 02 05:05:21 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-e4c77aa7-6b00-4c8c-95a0-6bec3fb2c733 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618153819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2618153819 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.6865456 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11742332 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:05:28 PM PDT 24 |
| Finished | Aug 02 05:05:29 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-86997b24-8fe1-4ca0-a0e7-7945cb78efe6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6865456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.6865456 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.1133358114 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11910168 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:05:27 PM PDT 24 |
| Finished | Aug 02 05:05:28 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-ade79f50-a837-412e-b029-47da7d04ae39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1133358114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1133358114 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.1658619027 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11867162 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:05:28 PM PDT 24 |
| Finished | Aug 02 05:05:29 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-1c9db9aa-7b3c-4cd3-a3d5-b3f315c18d95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658619027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1658619027 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.1984114891 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10228036 ps |
| CPU time | 0.38 seconds |
| Started | Aug 02 05:05:30 PM PDT 24 |
| Finished | Aug 02 05:05:30 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-8ee04137-e7d8-4296-845e-bfaee7431ba8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1984114891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1984114891 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4094582264 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 30067081 ps |
| CPU time | 0.41 seconds |
| Started | Aug 02 05:05:39 PM PDT 24 |
| Finished | Aug 02 05:05:39 PM PDT 24 |
| Peak memory | 145364 kb |
| Host | smart-1ff555f1-61e1-4ceb-9e5d-d89fbe3eab42 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4094582264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4094582264 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1156478802 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30128340 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:05:38 PM PDT 24 |
| Finished | Aug 02 05:05:38 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-df1e2a6d-b533-43a0-b0e6-770231e4fb75 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1156478802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1156478802 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2683812327 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30408455 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:05:34 PM PDT 24 |
| Finished | Aug 02 05:05:35 PM PDT 24 |
| Peak memory | 145368 kb |
| Host | smart-588bc4f8-bc87-4540-9113-bbfc9a7ade44 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2683812327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2683812327 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1313101744 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30651355 ps |
| CPU time | 0.47 seconds |
| Started | Aug 02 05:05:37 PM PDT 24 |
| Finished | Aug 02 05:05:38 PM PDT 24 |
| Peak memory | 145348 kb |
| Host | smart-5cd57985-c10f-431e-a0ad-3ded0c8dd4aa |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1313101744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1313101744 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.857978733 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 28450878 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:05:35 PM PDT 24 |
| Finished | Aug 02 05:05:36 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-0fb0c01f-6568-42dc-83b6-52d13c204b39 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=857978733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.857978733 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3706430263 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 32212399 ps |
| CPU time | 0.41 seconds |
| Started | Aug 02 05:05:36 PM PDT 24 |
| Finished | Aug 02 05:05:37 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-8e772b22-391d-47c3-8423-41c9bacfc737 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3706430263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3706430263 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.310925119 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 31119996 ps |
| CPU time | 0.42 seconds |
| Started | Aug 02 05:05:35 PM PDT 24 |
| Finished | Aug 02 05:05:35 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-1949d32b-c4a1-4d0e-891d-125976d8d3b1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=310925119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.310925119 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.345519622 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30484849 ps |
| CPU time | 0.41 seconds |
| Started | Aug 02 05:05:37 PM PDT 24 |
| Finished | Aug 02 05:05:37 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-94029d8e-7369-451a-b88c-c53dae3cee83 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=345519622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.345519622 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3277034226 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 31053535 ps |
| CPU time | 0.38 seconds |
| Started | Aug 02 05:05:34 PM PDT 24 |
| Finished | Aug 02 05:05:34 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-b2ddffe2-7b98-4324-ae80-9a7cf0a9146f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3277034226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3277034226 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.212342834 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 31343220 ps |
| CPU time | 0.46 seconds |
| Started | Aug 02 05:05:36 PM PDT 24 |
| Finished | Aug 02 05:05:36 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-73fe0687-346f-4b2b-a4d6-71cac78dc7c5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=212342834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.212342834 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4194358186 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 28025188 ps |
| CPU time | 0.41 seconds |
| Started | Aug 02 05:05:38 PM PDT 24 |
| Finished | Aug 02 05:05:39 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-1a1af695-0bd1-4dc3-a0d0-e5caf8219124 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4194358186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.4194358186 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3044248806 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 27608369 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:05:35 PM PDT 24 |
| Finished | Aug 02 05:05:35 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-841c5b01-cf4b-49de-8518-0d87c50f587c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3044248806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3044248806 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.643006231 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 31189991 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:05:35 PM PDT 24 |
| Finished | Aug 02 05:05:36 PM PDT 24 |
| Peak memory | 145336 kb |
| Host | smart-12137e5a-cf13-44cb-a3f5-0422a5ba8286 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=643006231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.643006231 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1169884862 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29550513 ps |
| CPU time | 0.41 seconds |
| Started | Aug 02 05:05:36 PM PDT 24 |
| Finished | Aug 02 05:05:37 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-2f0dd365-5d39-45d2-ad46-b5a56b7a2b56 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1169884862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1169884862 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1255628626 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 30939630 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:05:35 PM PDT 24 |
| Finished | Aug 02 05:05:36 PM PDT 24 |
| Peak memory | 145344 kb |
| Host | smart-500e758a-c776-4f1f-9362-e65e8b53d16c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1255628626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1255628626 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4021745216 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29504303 ps |
| CPU time | 0.41 seconds |
| Started | Aug 02 05:05:39 PM PDT 24 |
| Finished | Aug 02 05:05:40 PM PDT 24 |
| Peak memory | 145364 kb |
| Host | smart-361b0f72-dc1f-4397-83a8-ffb42d45e6ee |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4021745216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.4021745216 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.742611670 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 30056906 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:05:37 PM PDT 24 |
| Finished | Aug 02 05:05:38 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-0d537543-125e-4fc5-8263-e8a906779a33 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=742611670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.742611670 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2493385482 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 29180479 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:05:35 PM PDT 24 |
| Finished | Aug 02 05:05:36 PM PDT 24 |
| Peak memory | 145344 kb |
| Host | smart-d90335ed-9975-447e-a39a-b289b27933c7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2493385482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2493385482 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.1498429900 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9168636 ps |
| CPU time | 0.38 seconds |
| Started | Aug 02 05:07:32 PM PDT 24 |
| Finished | Aug 02 05:07:32 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-1a015897-f577-488b-9fec-77719e72a678 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1498429900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1498429900 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3509950169 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10088674 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:07:34 PM PDT 24 |
| Finished | Aug 02 05:07:35 PM PDT 24 |
| Peak memory | 145480 kb |
| Host | smart-c55b1593-03a3-4808-aa59-d4e4932e59e5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3509950169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3509950169 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.707937979 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9304784 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:07:30 PM PDT 24 |
| Finished | Aug 02 05:07:31 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-df2d47b4-c039-4d63-b7a7-b0785f1c9376 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=707937979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.707937979 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3499850941 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9615561 ps |
| CPU time | 0.38 seconds |
| Started | Aug 02 05:07:31 PM PDT 24 |
| Finished | Aug 02 05:07:31 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-8dde9512-60eb-4fcd-9319-dd3ef92a8260 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3499850941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3499850941 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.467727621 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9524880 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:07:31 PM PDT 24 |
| Finished | Aug 02 05:07:31 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-0b7587ea-29c1-4899-a0e2-8959f131a4db |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=467727621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.467727621 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1953468376 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9340604 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:07:30 PM PDT 24 |
| Finished | Aug 02 05:07:31 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-87783435-93b1-48b0-8367-74fce407767d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1953468376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1953468376 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.3848321996 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 9416913 ps |
| CPU time | 0.41 seconds |
| Started | Aug 02 05:07:32 PM PDT 24 |
| Finished | Aug 02 05:07:33 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-229e46d4-f93d-442b-a147-093559e33544 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3848321996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3848321996 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.2772641248 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8437871 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:07:31 PM PDT 24 |
| Finished | Aug 02 05:07:31 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-ff17b616-d372-49c1-97eb-662a68a0b6bb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2772641248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2772641248 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.619191668 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9590526 ps |
| CPU time | 0.37 seconds |
| Started | Aug 02 05:07:31 PM PDT 24 |
| Finished | Aug 02 05:07:31 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-f7ba616d-c08c-4d35-b83a-beee0ed65a16 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=619191668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.619191668 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.473674605 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10247307 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:07:35 PM PDT 24 |
| Finished | Aug 02 05:07:35 PM PDT 24 |
| Peak memory | 145480 kb |
| Host | smart-175b4757-dcef-4fbe-8dad-6f381fefad12 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=473674605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.473674605 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.3697861305 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8306088 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:07:31 PM PDT 24 |
| Finished | Aug 02 05:07:31 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-c1f3ba50-2f60-41d2-961c-d1573ee7e452 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3697861305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3697861305 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.3952047479 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9995822 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:07:33 PM PDT 24 |
| Finished | Aug 02 05:07:33 PM PDT 24 |
| Peak memory | 145680 kb |
| Host | smart-f601cf21-0e2d-49b4-9a68-56fdc19f0edd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3952047479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3952047479 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.2759912483 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9432160 ps |
| CPU time | 0.43 seconds |
| Started | Aug 02 05:07:31 PM PDT 24 |
| Finished | Aug 02 05:07:31 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-04df162e-b479-4c63-aec4-249420c03bef |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2759912483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2759912483 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.1520002520 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9792989 ps |
| CPU time | 0.38 seconds |
| Started | Aug 02 05:07:33 PM PDT 24 |
| Finished | Aug 02 05:07:33 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-78f6ad89-bba6-483a-88c2-ff565d938699 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1520002520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1520002520 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1407111986 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9174673 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:07:30 PM PDT 24 |
| Finished | Aug 02 05:07:30 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-1a2b834c-02ff-4c3b-966e-c74c2d76d79b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1407111986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1407111986 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1462434042 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8523815 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:07:32 PM PDT 24 |
| Finished | Aug 02 05:07:33 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-c3a1a09c-8a98-477e-b778-ae410ca4f02f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1462434042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1462434042 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.1350728667 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 9416353 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:07:32 PM PDT 24 |
| Finished | Aug 02 05:07:33 PM PDT 24 |
| Peak memory | 145536 kb |
| Host | smart-d83b9655-01bf-4665-8fbe-f41db094f993 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1350728667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1350728667 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.520873083 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 9181068 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:07:32 PM PDT 24 |
| Finished | Aug 02 05:07:32 PM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-1fc245b8-9368-4fcb-8d7f-2a5b3e69067d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=520873083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.520873083 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.257544845 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9923573 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:07:29 PM PDT 24 |
| Finished | Aug 02 05:07:30 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-60129e59-7c1f-42a9-bd00-52973aa7d488 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=257544845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.257544845 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1195653868 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 26221846 ps |
| CPU time | 0.38 seconds |
| Started | Aug 02 05:07:32 PM PDT 24 |
| Finished | Aug 02 05:07:32 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-bc515bb9-fde6-4131-b228-2109fbba4989 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1195653868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1195653868 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3967384312 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 28377110 ps |
| CPU time | 0.41 seconds |
| Started | Aug 02 05:07:33 PM PDT 24 |
| Finished | Aug 02 05:07:34 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-71e6d5e3-8849-4c2d-a817-1b7b57871ce6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3967384312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3967384312 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4098303361 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 27531906 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:07:34 PM PDT 24 |
| Finished | Aug 02 05:07:34 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-8a568832-e9b1-44f1-9939-66b579d8f94b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4098303361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.4098303361 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3525252456 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 27918792 ps |
| CPU time | 0.45 seconds |
| Started | Aug 02 05:07:45 PM PDT 24 |
| Finished | Aug 02 05:07:46 PM PDT 24 |
| Peak memory | 145488 kb |
| Host | smart-a90cf6a1-7db2-4faa-8163-2b7d1204b962 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3525252456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3525252456 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2559510105 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28465130 ps |
| CPU time | 0.41 seconds |
| Started | Aug 02 05:07:49 PM PDT 24 |
| Finished | Aug 02 05:07:49 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-4959ba00-80b0-4bf9-a609-902046567413 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2559510105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2559510105 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3379781700 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26052258 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:07:47 PM PDT 24 |
| Finished | Aug 02 05:07:47 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-39ab233e-3f00-4764-9df2-f7e38a2491d7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3379781700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3379781700 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3948171717 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 26137916 ps |
| CPU time | 0.41 seconds |
| Started | Aug 02 05:07:48 PM PDT 24 |
| Finished | Aug 02 05:07:48 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-674a27ce-75b7-4a0f-8097-f3f1e8a94ed7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3948171717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3948171717 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1250392135 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26468160 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:07:38 PM PDT 24 |
| Finished | Aug 02 05:07:38 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-73d20631-3dea-4a06-83fd-3854d43e6c52 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1250392135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1250392135 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2610293605 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27885975 ps |
| CPU time | 0.42 seconds |
| Started | Aug 02 05:07:40 PM PDT 24 |
| Finished | Aug 02 05:07:40 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-637f19be-095e-4e9c-a751-c16e8bb30d15 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2610293605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2610293605 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3940880817 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26598707 ps |
| CPU time | 0.42 seconds |
| Started | Aug 02 05:07:47 PM PDT 24 |
| Finished | Aug 02 05:07:48 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-41227e4a-984a-420b-8580-60479c8a11bb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3940880817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3940880817 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1415156841 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27899155 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:07:47 PM PDT 24 |
| Finished | Aug 02 05:07:48 PM PDT 24 |
| Peak memory | 145500 kb |
| Host | smart-678b63da-2c06-4eff-bf22-045acaccbcde |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1415156841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1415156841 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2544811764 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 25947152 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:07:46 PM PDT 24 |
| Finished | Aug 02 05:07:47 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-f88bf92e-e58d-48ca-9ca5-1468a6e0bb26 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2544811764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2544811764 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3405398546 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 28685951 ps |
| CPU time | 0.38 seconds |
| Started | Aug 02 05:07:33 PM PDT 24 |
| Finished | Aug 02 05:07:33 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-3186a81a-5a1e-4b35-9524-f2b482f77af0 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3405398546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3405398546 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3911611298 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 29068544 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:07:32 PM PDT 24 |
| Finished | Aug 02 05:07:33 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-18757f2c-40b0-43c1-a5c1-02f183ce3b80 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3911611298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3911611298 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4080796199 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26335847 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:07:32 PM PDT 24 |
| Finished | Aug 02 05:07:33 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-93bf11ee-2b21-4a47-9930-272c652d2771 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4080796199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.4080796199 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2482206109 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 30369247 ps |
| CPU time | 0.41 seconds |
| Started | Aug 02 05:07:34 PM PDT 24 |
| Finished | Aug 02 05:07:34 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-af62305f-7e76-4f15-be46-3237c057034e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2482206109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2482206109 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2971594316 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27416315 ps |
| CPU time | 0.42 seconds |
| Started | Aug 02 05:07:32 PM PDT 24 |
| Finished | Aug 02 05:07:33 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-174b0fc4-4445-4f90-8973-00081559956c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2971594316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2971594316 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2427550170 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 26295385 ps |
| CPU time | 0.39 seconds |
| Started | Aug 02 05:07:29 PM PDT 24 |
| Finished | Aug 02 05:07:29 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-0874dfae-d11d-41ae-a2cd-2d702030f657 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2427550170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2427550170 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3745851039 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 29050341 ps |
| CPU time | 0.4 seconds |
| Started | Aug 02 05:07:31 PM PDT 24 |
| Finished | Aug 02 05:07:32 PM PDT 24 |
| Peak memory | 145660 kb |
| Host | smart-dd2f9c5e-b764-40ed-94a8-51d2e22f335f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3745851039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3745851039 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3835490690 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27529340 ps |
| CPU time | 0.38 seconds |
| Started | Aug 02 05:07:34 PM PDT 24 |
| Finished | Aug 02 05:07:35 PM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-e03ffffb-c15a-48b8-a783-f170cbd4629b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3835490690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3835490690 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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