| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.85 | 100.00 | 97.92 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.88 | 88.88 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/11.prim_async_alert.4151097076 |
| 92.35 | 3.48 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/10.prim_sync_alert.1433749784 |
| 94.11 | 1.76 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 83.72 | 6.98 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.97984612 |
| 94.50 | 0.39 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 2.33 | /workspace/coverage/default/1.prim_async_alert.3670058697 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2171878127 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.2116632947 |
| /workspace/coverage/default/10.prim_async_alert.722406060 |
| /workspace/coverage/default/13.prim_async_alert.1437326224 |
| /workspace/coverage/default/14.prim_async_alert.1138046746 |
| /workspace/coverage/default/15.prim_async_alert.3978453540 |
| /workspace/coverage/default/16.prim_async_alert.2784186200 |
| /workspace/coverage/default/17.prim_async_alert.609297051 |
| /workspace/coverage/default/18.prim_async_alert.1969426263 |
| /workspace/coverage/default/19.prim_async_alert.552660158 |
| /workspace/coverage/default/2.prim_async_alert.4266873264 |
| /workspace/coverage/default/3.prim_async_alert.3081794928 |
| /workspace/coverage/default/4.prim_async_alert.3277140460 |
| /workspace/coverage/default/5.prim_async_alert.3203488978 |
| /workspace/coverage/default/6.prim_async_alert.350159632 |
| /workspace/coverage/default/7.prim_async_alert.898014311 |
| /workspace/coverage/default/8.prim_async_alert.1494032116 |
| /workspace/coverage/default/9.prim_async_alert.3705424921 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.64860428 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.290469523 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4097374721 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.858789082 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.4152482209 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3749260255 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4148303031 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3702642753 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1687826407 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3773998446 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2124731509 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2387938283 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3102524980 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.113296581 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2845853964 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1484405328 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.2785172147 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.2820090976 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.3837454761 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.1873200758 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.3962744565 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.202908874 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.3249120486 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.4224382201 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.1516049329 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.1006470043 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.65421855 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.3239413028 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.402278466 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.3798733178 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.2319514122 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1636966494 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.1475463589 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.1680967557 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.3848446669 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2915067084 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3634213961 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1872866266 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.444475267 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3777566186 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3334222314 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2517935792 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3781639628 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1131407054 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3066451264 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.117366093 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3648372549 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.91266720 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3063211915 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2734294479 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.567339072 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2679835341 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1299390291 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4238600039 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/6.prim_async_alert.350159632 | Aug 03 04:22:21 PM PDT 24 | Aug 03 04:22:22 PM PDT 24 | 11122343 ps | ||
| T2 | /workspace/coverage/default/8.prim_async_alert.1494032116 | Aug 03 04:22:17 PM PDT 24 | Aug 03 04:22:18 PM PDT 24 | 11220967 ps | ||
| T3 | /workspace/coverage/default/13.prim_async_alert.1437326224 | Aug 03 04:22:17 PM PDT 24 | Aug 03 04:22:17 PM PDT 24 | 10286430 ps | ||
| T6 | /workspace/coverage/default/14.prim_async_alert.1138046746 | Aug 03 04:22:51 PM PDT 24 | Aug 03 04:22:52 PM PDT 24 | 11559855 ps | ||
| T7 | /workspace/coverage/default/11.prim_async_alert.4151097076 | Aug 03 04:22:32 PM PDT 24 | Aug 03 04:22:38 PM PDT 24 | 11793927 ps | ||
| T10 | /workspace/coverage/default/0.prim_async_alert.2116632947 | Aug 03 04:23:14 PM PDT 24 | Aug 03 04:23:15 PM PDT 24 | 12222847 ps | ||
| T8 | /workspace/coverage/default/10.prim_async_alert.722406060 | Aug 03 04:22:34 PM PDT 24 | Aug 03 04:22:35 PM PDT 24 | 11395659 ps | ||
| T9 | /workspace/coverage/default/18.prim_async_alert.1969426263 | Aug 03 04:22:40 PM PDT 24 | Aug 03 04:22:40 PM PDT 24 | 12300573 ps | ||
| T17 | /workspace/coverage/default/5.prim_async_alert.3203488978 | Aug 03 04:22:39 PM PDT 24 | Aug 03 04:22:40 PM PDT 24 | 11110320 ps | ||
| T18 | /workspace/coverage/default/15.prim_async_alert.3978453540 | Aug 03 04:23:10 PM PDT 24 | Aug 03 04:23:11 PM PDT 24 | 11382748 ps | ||
| T26 | /workspace/coverage/default/19.prim_async_alert.552660158 | Aug 03 04:23:44 PM PDT 24 | Aug 03 04:23:45 PM PDT 24 | 10334633 ps | ||
| T19 | /workspace/coverage/default/9.prim_async_alert.3705424921 | Aug 03 04:22:34 PM PDT 24 | Aug 03 04:22:35 PM PDT 24 | 11219194 ps | ||
| T16 | /workspace/coverage/default/3.prim_async_alert.3081794928 | Aug 03 04:23:28 PM PDT 24 | Aug 03 04:23:29 PM PDT 24 | 11439616 ps | ||
| T20 | /workspace/coverage/default/17.prim_async_alert.609297051 | Aug 03 04:22:37 PM PDT 24 | Aug 03 04:22:37 PM PDT 24 | 10678344 ps | ||
| T21 | /workspace/coverage/default/1.prim_async_alert.3670058697 | Aug 03 04:23:34 PM PDT 24 | Aug 03 04:23:34 PM PDT 24 | 11932483 ps | ||
| T44 | /workspace/coverage/default/4.prim_async_alert.3277140460 | Aug 03 04:23:44 PM PDT 24 | Aug 03 04:23:45 PM PDT 24 | 10456003 ps | ||
| T45 | /workspace/coverage/default/2.prim_async_alert.4266873264 | Aug 03 04:23:45 PM PDT 24 | Aug 03 04:23:45 PM PDT 24 | 11754604 ps | ||
| T11 | /workspace/coverage/default/7.prim_async_alert.898014311 | Aug 03 04:22:41 PM PDT 24 | Aug 03 04:22:41 PM PDT 24 | 12387185 ps | ||
| T46 | /workspace/coverage/default/16.prim_async_alert.2784186200 | Aug 03 04:23:07 PM PDT 24 | Aug 03 04:23:07 PM PDT 24 | 11076480 ps | ||
| T41 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1687826407 | Aug 03 04:22:47 PM PDT 24 | Aug 03 04:22:47 PM PDT 24 | 29143604 ps | ||
| T12 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.97984612 | Aug 03 04:22:41 PM PDT 24 | Aug 03 04:22:42 PM PDT 24 | 32272164 ps | ||
| T22 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3749260255 | Aug 03 04:22:53 PM PDT 24 | Aug 03 04:22:53 PM PDT 24 | 30644378 ps | ||
| T14 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.858789082 | Aug 03 04:22:44 PM PDT 24 | Aug 03 04:22:44 PM PDT 24 | 30763572 ps | ||
| T23 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.64860428 | Aug 03 04:22:27 PM PDT 24 | Aug 03 04:22:28 PM PDT 24 | 29891154 ps | ||
| T13 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3102524980 | Aug 03 04:22:35 PM PDT 24 | Aug 03 04:22:36 PM PDT 24 | 31061763 ps | ||
| T24 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3773998446 | Aug 03 04:22:55 PM PDT 24 | Aug 03 04:22:56 PM PDT 24 | 30178152 ps | ||
| T42 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1484405328 | Aug 03 04:22:41 PM PDT 24 | Aug 03 04:22:41 PM PDT 24 | 29425760 ps | ||
| T25 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2387938283 | Aug 03 04:22:25 PM PDT 24 | Aug 03 04:22:26 PM PDT 24 | 28280518 ps | ||
| T43 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4148303031 | Aug 03 04:22:34 PM PDT 24 | Aug 03 04:22:35 PM PDT 24 | 31090922 ps | ||
| T47 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.113296581 | Aug 03 04:23:06 PM PDT 24 | Aug 03 04:23:07 PM PDT 24 | 30962863 ps | ||
| T48 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2124731509 | Aug 03 04:23:56 PM PDT 24 | Aug 03 04:23:57 PM PDT 24 | 32206459 ps | ||
| T49 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2845853964 | Aug 03 04:22:28 PM PDT 24 | Aug 03 04:22:28 PM PDT 24 | 29561029 ps | ||
| T50 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3702642753 | Aug 03 04:22:35 PM PDT 24 | Aug 03 04:22:35 PM PDT 24 | 30618107 ps | ||
| T51 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.290469523 | Aug 03 04:22:40 PM PDT 24 | Aug 03 04:22:41 PM PDT 24 | 31838564 ps | ||
| T52 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4097374721 | Aug 03 04:22:31 PM PDT 24 | Aug 03 04:22:32 PM PDT 24 | 31510923 ps | ||
| T53 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.4152482209 | Aug 03 04:22:51 PM PDT 24 | Aug 03 04:22:51 PM PDT 24 | 30637957 ps | ||
| T15 | /workspace/coverage/sync_alert/10.prim_sync_alert.1433749784 | Aug 03 04:22:43 PM PDT 24 | Aug 03 04:22:43 PM PDT 24 | 8939029 ps | ||
| T36 | /workspace/coverage/sync_alert/16.prim_sync_alert.4224382201 | Aug 03 04:23:15 PM PDT 24 | Aug 03 04:23:16 PM PDT 24 | 9005109 ps | ||
| T27 | /workspace/coverage/sync_alert/11.prim_sync_alert.3837454761 | Aug 03 04:22:45 PM PDT 24 | Aug 03 04:22:45 PM PDT 24 | 9168420 ps | ||
| T28 | /workspace/coverage/sync_alert/17.prim_sync_alert.1516049329 | Aug 03 04:22:31 PM PDT 24 | Aug 03 04:22:32 PM PDT 24 | 8869113 ps | ||
| T37 | /workspace/coverage/sync_alert/6.prim_sync_alert.1636966494 | Aug 03 04:23:16 PM PDT 24 | Aug 03 04:23:17 PM PDT 24 | 8101612 ps | ||
| T38 | /workspace/coverage/sync_alert/1.prim_sync_alert.2820090976 | Aug 03 04:22:38 PM PDT 24 | Aug 03 04:22:38 PM PDT 24 | 10138719 ps | ||
| T29 | /workspace/coverage/sync_alert/13.prim_sync_alert.3962744565 | Aug 03 04:23:16 PM PDT 24 | Aug 03 04:23:17 PM PDT 24 | 8782403 ps | ||
| T30 | /workspace/coverage/sync_alert/5.prim_sync_alert.2319514122 | Aug 03 04:22:38 PM PDT 24 | Aug 03 04:22:39 PM PDT 24 | 9037930 ps | ||
| T39 | /workspace/coverage/sync_alert/14.prim_sync_alert.202908874 | Aug 03 04:22:24 PM PDT 24 | Aug 03 04:22:24 PM PDT 24 | 9450019 ps | ||
| T40 | /workspace/coverage/sync_alert/0.prim_sync_alert.2785172147 | Aug 03 04:22:33 PM PDT 24 | Aug 03 04:22:34 PM PDT 24 | 9838779 ps | ||
| T31 | /workspace/coverage/sync_alert/4.prim_sync_alert.3798733178 | Aug 03 04:22:53 PM PDT 24 | Aug 03 04:22:54 PM PDT 24 | 9671988 ps | ||
| T32 | /workspace/coverage/sync_alert/15.prim_sync_alert.3249120486 | Aug 03 04:22:39 PM PDT 24 | Aug 03 04:22:40 PM PDT 24 | 8243652 ps | ||
| T54 | /workspace/coverage/sync_alert/8.prim_sync_alert.1680967557 | Aug 03 04:22:36 PM PDT 24 | Aug 03 04:22:37 PM PDT 24 | 10244211 ps | ||
| T33 | /workspace/coverage/sync_alert/7.prim_sync_alert.1475463589 | Aug 03 04:22:43 PM PDT 24 | Aug 03 04:22:43 PM PDT 24 | 9649487 ps | ||
| T34 | /workspace/coverage/sync_alert/9.prim_sync_alert.3848446669 | Aug 03 04:25:13 PM PDT 24 | Aug 03 04:25:14 PM PDT 24 | 9135043 ps | ||
| T35 | /workspace/coverage/sync_alert/2.prim_sync_alert.3239413028 | Aug 03 04:23:22 PM PDT 24 | Aug 03 04:23:23 PM PDT 24 | 8909552 ps | ||
| T55 | /workspace/coverage/sync_alert/18.prim_sync_alert.1006470043 | Aug 03 04:22:46 PM PDT 24 | Aug 03 04:22:47 PM PDT 24 | 9209654 ps | ||
| T56 | /workspace/coverage/sync_alert/12.prim_sync_alert.1873200758 | Aug 03 04:23:50 PM PDT 24 | Aug 03 04:23:55 PM PDT 24 | 9341843 ps | ||
| T57 | /workspace/coverage/sync_alert/3.prim_sync_alert.402278466 | Aug 03 04:22:35 PM PDT 24 | Aug 03 04:22:35 PM PDT 24 | 8933981 ps | ||
| T58 | /workspace/coverage/sync_alert/19.prim_sync_alert.65421855 | Aug 03 04:22:34 PM PDT 24 | Aug 03 04:22:34 PM PDT 24 | 8692369 ps | ||
| T4 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4238600039 | Aug 03 04:19:38 PM PDT 24 | Aug 03 04:19:39 PM PDT 24 | 25555551 ps | ||
| T59 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3648372549 | Aug 03 04:20:54 PM PDT 24 | Aug 03 04:20:55 PM PDT 24 | 27111786 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3781639628 | Aug 03 04:19:48 PM PDT 24 | Aug 03 04:19:48 PM PDT 24 | 28305282 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1872866266 | Aug 03 04:20:21 PM PDT 24 | Aug 03 04:20:22 PM PDT 24 | 25518879 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2915067084 | Aug 03 04:23:40 PM PDT 24 | Aug 03 04:23:41 PM PDT 24 | 26441582 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3334222314 | Aug 03 04:20:41 PM PDT 24 | Aug 03 04:20:42 PM PDT 24 | 28788614 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.444475267 | Aug 03 04:20:57 PM PDT 24 | Aug 03 04:20:57 PM PDT 24 | 27553328 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3066451264 | Aug 03 04:21:06 PM PDT 24 | Aug 03 04:21:07 PM PDT 24 | 26769038 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2679835341 | Aug 03 04:19:33 PM PDT 24 | Aug 03 04:19:33 PM PDT 24 | 28688829 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1131407054 | Aug 03 04:21:15 PM PDT 24 | Aug 03 04:21:16 PM PDT 24 | 27389923 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3063211915 | Aug 03 04:22:53 PM PDT 24 | Aug 03 04:22:54 PM PDT 24 | 25657225 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2517935792 | Aug 03 04:21:36 PM PDT 24 | Aug 03 04:21:37 PM PDT 24 | 27527441 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.117366093 | Aug 03 04:20:40 PM PDT 24 | Aug 03 04:20:42 PM PDT 24 | 27991173 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2171878127 | Aug 03 04:22:35 PM PDT 24 | Aug 03 04:22:36 PM PDT 24 | 27896320 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3777566186 | Aug 03 04:20:44 PM PDT 24 | Aug 03 04:20:44 PM PDT 24 | 29175648 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.567339072 | Aug 03 04:19:38 PM PDT 24 | Aug 03 04:19:38 PM PDT 24 | 28014636 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3634213961 | Aug 03 04:21:14 PM PDT 24 | Aug 03 04:21:15 PM PDT 24 | 30760064 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2734294479 | Aug 03 04:21:14 PM PDT 24 | Aug 03 04:21:15 PM PDT 24 | 28670551 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1299390291 | Aug 03 04:21:49 PM PDT 24 | Aug 03 04:21:50 PM PDT 24 | 25943875 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.91266720 | Aug 03 04:21:14 PM PDT 24 | Aug 03 04:21:15 PM PDT 24 | 26577102 ps |
| Test location | /workspace/coverage/default/11.prim_async_alert.4151097076 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11793927 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:32 PM PDT 24 |
| Finished | Aug 03 04:22:38 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-53fcf2d9-5b73-41ec-9887-f69dff5834e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4151097076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4151097076 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.1433749784 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8939029 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:22:43 PM PDT 24 |
| Finished | Aug 03 04:22:43 PM PDT 24 |
| Peak memory | 145420 kb |
| Host | smart-66c827bc-b3f7-45c1-a14c-fd62b8da4d97 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1433749784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1433749784 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.97984612 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 32272164 ps |
| CPU time | 0.44 seconds |
| Started | Aug 03 04:22:41 PM PDT 24 |
| Finished | Aug 03 04:22:42 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-16a708e3-14e0-4d9d-a1d1-220c545922ed |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=97984612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.97984612 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.3670058697 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11932483 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:23:34 PM PDT 24 |
| Finished | Aug 03 04:23:34 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-f146c8dd-2229-41b1-90e0-2d1ca9731fe9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670058697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3670058697 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2171878127 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 27896320 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:22:35 PM PDT 24 |
| Finished | Aug 03 04:22:36 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-7d13fa34-dde4-4b4e-957b-062fceae737f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2171878127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2171878127 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.2116632947 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12222847 ps |
| CPU time | 0.37 seconds |
| Started | Aug 03 04:23:14 PM PDT 24 |
| Finished | Aug 03 04:23:15 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-b8594423-bafd-410b-8270-1df156cccc91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116632947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2116632947 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.722406060 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11395659 ps |
| CPU time | 0.41 seconds |
| Started | Aug 03 04:22:34 PM PDT 24 |
| Finished | Aug 03 04:22:35 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-84ad0037-bb9a-4f03-966a-7e344be689aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=722406060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.722406060 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.1437326224 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10286430 ps |
| CPU time | 0.42 seconds |
| Started | Aug 03 04:22:17 PM PDT 24 |
| Finished | Aug 03 04:22:17 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-b11b5ee4-aa6c-4838-a4a4-728889a123cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1437326224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1437326224 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1138046746 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11559855 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:51 PM PDT 24 |
| Finished | Aug 03 04:22:52 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-df88fdd5-3602-4aa8-a4b9-7f112f008f4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1138046746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1138046746 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.3978453540 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11382748 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:23:10 PM PDT 24 |
| Finished | Aug 03 04:23:11 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-aa0036c0-b73d-43f1-8dd7-4edcad7a7a33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3978453540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3978453540 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.2784186200 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11076480 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:23:07 PM PDT 24 |
| Finished | Aug 03 04:23:07 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-114eccbd-5520-4037-9d45-52fe7b44ba68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2784186200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2784186200 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.609297051 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10678344 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:37 PM PDT 24 |
| Finished | Aug 03 04:22:37 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-59d4c879-d5b5-46a0-9d4f-d4f4fe7c4be2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=609297051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.609297051 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.1969426263 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12300573 ps |
| CPU time | 0.38 seconds |
| Started | Aug 03 04:22:40 PM PDT 24 |
| Finished | Aug 03 04:22:40 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-c1918d15-a107-41b5-b7a0-ff91e2e3c80e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969426263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1969426263 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.552660158 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10334633 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:23:44 PM PDT 24 |
| Finished | Aug 03 04:23:45 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-fbc10cfa-3c31-40fb-acd7-46bae8016947 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=552660158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.552660158 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.4266873264 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11754604 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:23:45 PM PDT 24 |
| Finished | Aug 03 04:23:45 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-851737f0-2e99-4739-adac-beed7fd5789b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4266873264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.4266873264 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.3081794928 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11439616 ps |
| CPU time | 0.41 seconds |
| Started | Aug 03 04:23:28 PM PDT 24 |
| Finished | Aug 03 04:23:29 PM PDT 24 |
| Peak memory | 144432 kb |
| Host | smart-a4a8c0e4-c0ab-4166-be30-96da6f38450c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081794928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3081794928 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.3277140460 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10456003 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:23:44 PM PDT 24 |
| Finished | Aug 03 04:23:45 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-2841e293-3958-4f11-a398-4cb9b76a2d25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3277140460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3277140460 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3203488978 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11110320 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:39 PM PDT 24 |
| Finished | Aug 03 04:22:40 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-398d1751-a250-4b05-ae55-6931c9d7453a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3203488978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3203488978 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.350159632 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11122343 ps |
| CPU time | 0.43 seconds |
| Started | Aug 03 04:22:21 PM PDT 24 |
| Finished | Aug 03 04:22:22 PM PDT 24 |
| Peak memory | 145912 kb |
| Host | smart-9d6ab035-25a8-4f23-95c3-48bf57481828 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=350159632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.350159632 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.898014311 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12387185 ps |
| CPU time | 0.46 seconds |
| Started | Aug 03 04:22:41 PM PDT 24 |
| Finished | Aug 03 04:22:41 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-597d0c20-4fec-4576-9a99-977ae0b51ec6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=898014311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.898014311 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.1494032116 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11220967 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:17 PM PDT 24 |
| Finished | Aug 03 04:22:18 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-6d6f03fd-2806-4132-97b3-26c06767202a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1494032116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1494032116 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.3705424921 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11219194 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:34 PM PDT 24 |
| Finished | Aug 03 04:22:35 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-687dcd5e-86e1-4b7f-a055-5edebfece954 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705424921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3705424921 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.64860428 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 29891154 ps |
| CPU time | 0.46 seconds |
| Started | Aug 03 04:22:27 PM PDT 24 |
| Finished | Aug 03 04:22:28 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-be006455-8102-44e9-accf-38f03a867010 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=64860428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.64860428 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.290469523 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 31838564 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:40 PM PDT 24 |
| Finished | Aug 03 04:22:41 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-90dbb17b-717f-49e9-bf02-10a3ec4a7731 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=290469523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.290469523 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4097374721 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 31510923 ps |
| CPU time | 0.41 seconds |
| Started | Aug 03 04:22:31 PM PDT 24 |
| Finished | Aug 03 04:22:32 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-8174a74c-88e7-4e9d-a911-00a1d3c9619f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4097374721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.4097374721 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.858789082 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 30763572 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:22:44 PM PDT 24 |
| Finished | Aug 03 04:22:44 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-70c1da42-c004-48b6-891e-e81859088f31 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=858789082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.858789082 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.4152482209 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30637957 ps |
| CPU time | 0.42 seconds |
| Started | Aug 03 04:22:51 PM PDT 24 |
| Finished | Aug 03 04:22:51 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-2ca8f509-388b-4ab4-b49f-e0baad842671 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4152482209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.4152482209 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3749260255 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 30644378 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:22:53 PM PDT 24 |
| Finished | Aug 03 04:22:53 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-6b23c044-b5be-4ccf-b7ef-473f01aac03d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3749260255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3749260255 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4148303031 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 31090922 ps |
| CPU time | 0.44 seconds |
| Started | Aug 03 04:22:34 PM PDT 24 |
| Finished | Aug 03 04:22:35 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-da11ecf0-f70e-48f2-bebc-a56c5940d5bb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4148303031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.4148303031 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3702642753 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30618107 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:22:35 PM PDT 24 |
| Finished | Aug 03 04:22:35 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-f72e916f-3ab8-4b43-93bb-955ad6be2aa6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3702642753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3702642753 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1687826407 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29143604 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:47 PM PDT 24 |
| Finished | Aug 03 04:22:47 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-bf7e826e-788d-4bc0-aa0c-4b79bd81c9b6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1687826407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1687826407 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3773998446 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 30178152 ps |
| CPU time | 0.41 seconds |
| Started | Aug 03 04:22:55 PM PDT 24 |
| Finished | Aug 03 04:22:56 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-d153ac93-71b2-45ac-8a97-6927aa0e5e18 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3773998446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3773998446 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2124731509 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 32206459 ps |
| CPU time | 0.43 seconds |
| Started | Aug 03 04:23:56 PM PDT 24 |
| Finished | Aug 03 04:23:57 PM PDT 24 |
| Peak memory | 144856 kb |
| Host | smart-3e5f7a36-4f60-417d-8a53-a8907e883fd5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2124731509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2124731509 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2387938283 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 28280518 ps |
| CPU time | 0.38 seconds |
| Started | Aug 03 04:22:25 PM PDT 24 |
| Finished | Aug 03 04:22:26 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-382eb0e9-2caa-454a-91ef-5b95323abcb0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2387938283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2387938283 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3102524980 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 31061763 ps |
| CPU time | 0.41 seconds |
| Started | Aug 03 04:22:35 PM PDT 24 |
| Finished | Aug 03 04:22:36 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-de22cce8-4447-46d4-b6ff-8edbd6b6fe68 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3102524980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3102524980 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.113296581 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 30962863 ps |
| CPU time | 0.38 seconds |
| Started | Aug 03 04:23:06 PM PDT 24 |
| Finished | Aug 03 04:23:07 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-4fab7cb7-a45c-4a0a-9432-5a4f88379ad9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=113296581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.113296581 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2845853964 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29561029 ps |
| CPU time | 0.42 seconds |
| Started | Aug 03 04:22:28 PM PDT 24 |
| Finished | Aug 03 04:22:28 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-f0bece76-47b8-456a-b519-dc3ef6fde934 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2845853964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2845853964 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1484405328 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29425760 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:41 PM PDT 24 |
| Finished | Aug 03 04:22:41 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-1dcabbbb-7af7-421c-898f-d5bbfdeb2317 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1484405328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1484405328 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.2785172147 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9838779 ps |
| CPU time | 0.38 seconds |
| Started | Aug 03 04:22:33 PM PDT 24 |
| Finished | Aug 03 04:22:34 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-ffc182cd-39b5-4ee8-826c-d57175b86dc7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2785172147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2785172147 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.2820090976 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10138719 ps |
| CPU time | 0.38 seconds |
| Started | Aug 03 04:22:38 PM PDT 24 |
| Finished | Aug 03 04:22:38 PM PDT 24 |
| Peak memory | 145420 kb |
| Host | smart-8716e36d-7e9a-4c2b-acb7-e47a9ed56459 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2820090976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2820090976 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.3837454761 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9168420 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:45 PM PDT 24 |
| Finished | Aug 03 04:22:45 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-bc9796ad-dedc-4cd5-a86d-19be697f48c0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3837454761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3837454761 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.1873200758 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9341843 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:23:50 PM PDT 24 |
| Finished | Aug 03 04:23:55 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-2ffc2b6e-2df9-45f7-aa54-ae7660535b85 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1873200758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1873200758 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.3962744565 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8782403 ps |
| CPU time | 0.38 seconds |
| Started | Aug 03 04:23:16 PM PDT 24 |
| Finished | Aug 03 04:23:17 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-fb035a4e-26a9-48df-acd3-db75aa05922a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3962744565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3962744565 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.202908874 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9450019 ps |
| CPU time | 0.41 seconds |
| Started | Aug 03 04:22:24 PM PDT 24 |
| Finished | Aug 03 04:22:24 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-5e63466a-bc8f-4d54-8a0d-bd3e4b77b873 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=202908874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.202908874 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.3249120486 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8243652 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:39 PM PDT 24 |
| Finished | Aug 03 04:22:40 PM PDT 24 |
| Peak memory | 145420 kb |
| Host | smart-219e5d9a-c859-46e9-858e-2340cc3128e3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3249120486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3249120486 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.4224382201 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9005109 ps |
| CPU time | 0.38 seconds |
| Started | Aug 03 04:23:15 PM PDT 24 |
| Finished | Aug 03 04:23:16 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-0f16adce-b059-4491-91e4-d5e1a0883078 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4224382201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.4224382201 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.1516049329 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8869113 ps |
| CPU time | 0.38 seconds |
| Started | Aug 03 04:22:31 PM PDT 24 |
| Finished | Aug 03 04:22:32 PM PDT 24 |
| Peak memory | 145412 kb |
| Host | smart-d8c6caf2-6943-4fe6-8809-9f2501233f83 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1516049329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1516049329 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.1006470043 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 9209654 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:46 PM PDT 24 |
| Finished | Aug 03 04:22:47 PM PDT 24 |
| Peak memory | 145420 kb |
| Host | smart-232f6faa-0f30-49a2-8d9e-33c5e7414940 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1006470043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1006470043 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.65421855 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8692369 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:22:34 PM PDT 24 |
| Finished | Aug 03 04:22:34 PM PDT 24 |
| Peak memory | 145420 kb |
| Host | smart-29d0bdfc-8af8-4400-8c23-71f762c69656 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=65421855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.65421855 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.3239413028 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8909552 ps |
| CPU time | 0.38 seconds |
| Started | Aug 03 04:23:22 PM PDT 24 |
| Finished | Aug 03 04:23:23 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-62b7f784-617e-47f8-a5f1-0912adc90c17 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3239413028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3239413028 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.402278466 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8933981 ps |
| CPU time | 0.37 seconds |
| Started | Aug 03 04:22:35 PM PDT 24 |
| Finished | Aug 03 04:22:35 PM PDT 24 |
| Peak memory | 145412 kb |
| Host | smart-34c5eeec-e0a7-42bf-b3b6-55c61355f9b8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=402278466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.402278466 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.3798733178 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9671988 ps |
| CPU time | 0.37 seconds |
| Started | Aug 03 04:22:53 PM PDT 24 |
| Finished | Aug 03 04:22:54 PM PDT 24 |
| Peak memory | 145388 kb |
| Host | smart-76525f13-8b5c-4985-a320-ed9ea317edba |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3798733178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3798733178 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.2319514122 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9037930 ps |
| CPU time | 0.37 seconds |
| Started | Aug 03 04:22:38 PM PDT 24 |
| Finished | Aug 03 04:22:39 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-c08da6ff-6a18-4cbb-8e18-edbb257da316 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2319514122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2319514122 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1636966494 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8101612 ps |
| CPU time | 0.38 seconds |
| Started | Aug 03 04:23:16 PM PDT 24 |
| Finished | Aug 03 04:23:17 PM PDT 24 |
| Peak memory | 145420 kb |
| Host | smart-bb17d644-a07a-485c-a17e-69a9bde4d912 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1636966494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1636966494 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.1475463589 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9649487 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:43 PM PDT 24 |
| Finished | Aug 03 04:22:43 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-e057b64b-257d-41d7-a717-fac1885ab99c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1475463589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1475463589 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.1680967557 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 10244211 ps |
| CPU time | 0.37 seconds |
| Started | Aug 03 04:22:36 PM PDT 24 |
| Finished | Aug 03 04:22:37 PM PDT 24 |
| Peak memory | 145392 kb |
| Host | smart-ac972050-ef84-4008-8d70-95eb664bfe6b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1680967557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1680967557 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.3848446669 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9135043 ps |
| CPU time | 0.41 seconds |
| Started | Aug 03 04:25:13 PM PDT 24 |
| Finished | Aug 03 04:25:14 PM PDT 24 |
| Peak memory | 145848 kb |
| Host | smart-49a3b411-3338-4949-aaea-c21708703c33 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3848446669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3848446669 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2915067084 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 26441582 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:23:40 PM PDT 24 |
| Finished | Aug 03 04:23:41 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-45c82ff1-9745-47e7-9347-837ccc1efafc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2915067084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2915067084 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3634213961 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 30760064 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:21:14 PM PDT 24 |
| Finished | Aug 03 04:21:15 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-4b9629c3-7b03-4905-af5a-f24d1f9007ef |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3634213961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3634213961 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1872866266 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 25518879 ps |
| CPU time | 0.41 seconds |
| Started | Aug 03 04:20:21 PM PDT 24 |
| Finished | Aug 03 04:20:22 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-cbf2f6a9-67b5-4060-99f8-510f1ea3d5aa |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1872866266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1872866266 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.444475267 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27553328 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:20:57 PM PDT 24 |
| Finished | Aug 03 04:20:57 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-891cad3d-afea-43fd-8410-5e5e24e04fe8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=444475267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.444475267 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3777566186 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 29175648 ps |
| CPU time | 0.41 seconds |
| Started | Aug 03 04:20:44 PM PDT 24 |
| Finished | Aug 03 04:20:44 PM PDT 24 |
| Peak memory | 143872 kb |
| Host | smart-3e465715-a2ac-4af6-a16a-65bb39e563b3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3777566186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3777566186 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3334222314 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 28788614 ps |
| CPU time | 0.43 seconds |
| Started | Aug 03 04:20:41 PM PDT 24 |
| Finished | Aug 03 04:20:42 PM PDT 24 |
| Peak memory | 143936 kb |
| Host | smart-2d946ce2-cb3d-4c88-8317-d769e2e5aaa1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3334222314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3334222314 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2517935792 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27527441 ps |
| CPU time | 0.44 seconds |
| Started | Aug 03 04:21:36 PM PDT 24 |
| Finished | Aug 03 04:21:37 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-3f59970b-b89a-4a22-a39d-0927b8d76e07 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2517935792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2517935792 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3781639628 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 28305282 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:19:48 PM PDT 24 |
| Finished | Aug 03 04:19:48 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-d5ce7eef-5fca-47eb-b2c6-7dfe73aa460e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3781639628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3781639628 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1131407054 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27389923 ps |
| CPU time | 0.43 seconds |
| Started | Aug 03 04:21:15 PM PDT 24 |
| Finished | Aug 03 04:21:16 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-a9154c63-8587-4023-a1fc-b73da5caac20 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1131407054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1131407054 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3066451264 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 26769038 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:21:06 PM PDT 24 |
| Finished | Aug 03 04:21:07 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-94aafb3d-ecf8-432a-a4a7-306a60877bd7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3066451264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3066451264 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.117366093 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27991173 ps |
| CPU time | 0.47 seconds |
| Started | Aug 03 04:20:40 PM PDT 24 |
| Finished | Aug 03 04:20:42 PM PDT 24 |
| Peak memory | 143044 kb |
| Host | smart-60a309de-6cb4-4b74-af60-6affa90183b4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=117366093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.117366093 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3648372549 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 27111786 ps |
| CPU time | 0.41 seconds |
| Started | Aug 03 04:20:54 PM PDT 24 |
| Finished | Aug 03 04:20:55 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-b9a75812-758d-4ea6-b524-646d48066433 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3648372549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3648372549 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.91266720 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 26577102 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:21:14 PM PDT 24 |
| Finished | Aug 03 04:21:15 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-35c1e10f-4161-436a-859d-b2abeb4c47d4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=91266720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.91266720 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3063211915 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 25657225 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:22:53 PM PDT 24 |
| Finished | Aug 03 04:22:54 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-345150d3-dcf2-4b83-88b8-7a220648c3d9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3063211915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3063211915 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2734294479 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28670551 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:21:14 PM PDT 24 |
| Finished | Aug 03 04:21:15 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-d969f8e9-2c94-401c-a2e2-22b95307e75a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2734294479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2734294479 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.567339072 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28014636 ps |
| CPU time | 0.45 seconds |
| Started | Aug 03 04:19:38 PM PDT 24 |
| Finished | Aug 03 04:19:38 PM PDT 24 |
| Peak memory | 145400 kb |
| Host | smart-90715de1-6931-4345-8a33-d7b7aec2797a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=567339072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.567339072 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2679835341 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 28688829 ps |
| CPU time | 0.42 seconds |
| Started | Aug 03 04:19:33 PM PDT 24 |
| Finished | Aug 03 04:19:33 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-7e6ebb48-a6ad-4160-bf80-722939d5ce22 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2679835341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2679835341 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1299390291 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 25943875 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:21:49 PM PDT 24 |
| Finished | Aug 03 04:21:50 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-23f4c266-ebfb-4867-8d06-3d5c07732e53 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1299390291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1299390291 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4238600039 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 25555551 ps |
| CPU time | 0.43 seconds |
| Started | Aug 03 04:19:38 PM PDT 24 |
| Finished | Aug 03 04:19:39 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-b76d590d-bdcd-490c-ad81-d74bbf750769 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4238600039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.4238600039 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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