Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.88 88.88 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/12.prim_async_alert.3058144747
92.01 3.13 100.00 0.00 93.75 0.00 100.00 0.00 85.71 7.14 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/0.prim_sync_alert.3462170946
93.56 1.55 100.00 0.00 93.75 0.00 100.00 0.00 85.71 0.00 95.83 0.00 86.05 9.30 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1480324892
94.50 0.94 100.00 0.00 95.83 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/1.prim_async_alert.135231018
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2353939331
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/12.prim_sync_alert.852683208

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3214589799
/workspace/coverage/default/10.prim_async_alert.2543181235
/workspace/coverage/default/11.prim_async_alert.2431155361
/workspace/coverage/default/13.prim_async_alert.4118966426
/workspace/coverage/default/14.prim_async_alert.4187431306
/workspace/coverage/default/15.prim_async_alert.1458042202
/workspace/coverage/default/16.prim_async_alert.458318483
/workspace/coverage/default/17.prim_async_alert.1471432502
/workspace/coverage/default/18.prim_async_alert.82018987
/workspace/coverage/default/19.prim_async_alert.2251989522
/workspace/coverage/default/2.prim_async_alert.2452911934
/workspace/coverage/default/3.prim_async_alert.3871611295
/workspace/coverage/default/4.prim_async_alert.121130250
/workspace/coverage/default/5.prim_async_alert.2716395007
/workspace/coverage/default/6.prim_async_alert.3119119057
/workspace/coverage/default/7.prim_async_alert.1610453273
/workspace/coverage/default/8.prim_async_alert.767103252
/workspace/coverage/default/9.prim_async_alert.2317069105
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2987571145
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4163462945
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3957879123
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3203777379
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3943383840
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3182097829
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2065455786
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2523501150
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2038606027
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1166895129
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.534483469
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1518765478
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3390148365
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2995197855
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2691677852
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4077701099
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3956087187
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2882494467
/workspace/coverage/sync_alert/1.prim_sync_alert.1846280488
/workspace/coverage/sync_alert/10.prim_sync_alert.1821892397
/workspace/coverage/sync_alert/11.prim_sync_alert.212789688
/workspace/coverage/sync_alert/13.prim_sync_alert.2893108646
/workspace/coverage/sync_alert/14.prim_sync_alert.3732720948
/workspace/coverage/sync_alert/15.prim_sync_alert.3327179385
/workspace/coverage/sync_alert/16.prim_sync_alert.3204436681
/workspace/coverage/sync_alert/17.prim_sync_alert.1214233362
/workspace/coverage/sync_alert/18.prim_sync_alert.3633377416
/workspace/coverage/sync_alert/19.prim_sync_alert.3823779117
/workspace/coverage/sync_alert/2.prim_sync_alert.2199773051
/workspace/coverage/sync_alert/3.prim_sync_alert.3245094473
/workspace/coverage/sync_alert/4.prim_sync_alert.1998409232
/workspace/coverage/sync_alert/5.prim_sync_alert.2511410138
/workspace/coverage/sync_alert/6.prim_sync_alert.1916779375
/workspace/coverage/sync_alert/7.prim_sync_alert.764139714
/workspace/coverage/sync_alert/8.prim_sync_alert.2807607922
/workspace/coverage/sync_alert/9.prim_sync_alert.2784226150
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2310474463
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1516303764
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1777275484
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1116767275
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.408792484
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1212557825
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2548921575
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.80283588
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.562748694
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3195505371
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.765270081
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.946403318
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.730107656
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3666043400
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.701490630
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1288762908
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1189324272
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.368631602
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2340253038
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.921221048



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/13.prim_async_alert.4118966426 Aug 04 04:31:29 PM PDT 24 Aug 04 04:31:30 PM PDT 24 11215477 ps
T2 /workspace/coverage/default/15.prim_async_alert.1458042202 Aug 04 04:31:40 PM PDT 24 Aug 04 04:31:41 PM PDT 24 10513438 ps
T3 /workspace/coverage/default/14.prim_async_alert.4187431306 Aug 04 04:31:26 PM PDT 24 Aug 04 04:31:26 PM PDT 24 10804387 ps
T13 /workspace/coverage/default/4.prim_async_alert.121130250 Aug 04 04:31:42 PM PDT 24 Aug 04 04:31:43 PM PDT 24 11408994 ps
T9 /workspace/coverage/default/12.prim_async_alert.3058144747 Aug 04 04:31:36 PM PDT 24 Aug 04 04:31:37 PM PDT 24 12353944 ps
T17 /workspace/coverage/default/18.prim_async_alert.82018987 Aug 04 04:31:35 PM PDT 24 Aug 04 04:31:35 PM PDT 24 10981800 ps
T7 /workspace/coverage/default/5.prim_async_alert.2716395007 Aug 04 04:31:48 PM PDT 24 Aug 04 04:31:48 PM PDT 24 12177246 ps
T8 /workspace/coverage/default/1.prim_async_alert.135231018 Aug 04 04:31:41 PM PDT 24 Aug 04 04:31:42 PM PDT 24 11091202 ps
T18 /workspace/coverage/default/7.prim_async_alert.1610453273 Aug 04 04:31:21 PM PDT 24 Aug 04 04:31:21 PM PDT 24 10550813 ps
T19 /workspace/coverage/default/10.prim_async_alert.2543181235 Aug 04 04:31:56 PM PDT 24 Aug 04 04:31:56 PM PDT 24 10425177 ps
T48 /workspace/coverage/default/8.prim_async_alert.767103252 Aug 04 04:31:30 PM PDT 24 Aug 04 04:31:31 PM PDT 24 10874129 ps
T12 /workspace/coverage/default/11.prim_async_alert.2431155361 Aug 04 04:31:59 PM PDT 24 Aug 04 04:32:00 PM PDT 24 11435141 ps
T20 /workspace/coverage/default/3.prim_async_alert.3871611295 Aug 04 04:31:33 PM PDT 24 Aug 04 04:31:33 PM PDT 24 10823911 ps
T21 /workspace/coverage/default/16.prim_async_alert.458318483 Aug 04 04:31:34 PM PDT 24 Aug 04 04:31:34 PM PDT 24 10793710 ps
T22 /workspace/coverage/default/6.prim_async_alert.3119119057 Aug 04 04:31:31 PM PDT 24 Aug 04 04:31:31 PM PDT 24 10701167 ps
T15 /workspace/coverage/default/9.prim_async_alert.2317069105 Aug 04 04:31:36 PM PDT 24 Aug 04 04:31:37 PM PDT 24 11074971 ps
T14 /workspace/coverage/default/2.prim_async_alert.2452911934 Aug 04 04:31:41 PM PDT 24 Aug 04 04:31:42 PM PDT 24 12212273 ps
T49 /workspace/coverage/default/17.prim_async_alert.1471432502 Aug 04 04:32:02 PM PDT 24 Aug 04 04:32:03 PM PDT 24 10300293 ps
T50 /workspace/coverage/default/19.prim_async_alert.2251989522 Aug 04 04:31:51 PM PDT 24 Aug 04 04:31:52 PM PDT 24 10979922 ps
T39 /workspace/coverage/default/0.prim_async_alert.3214589799 Aug 04 04:31:39 PM PDT 24 Aug 04 04:31:39 PM PDT 24 10776259 ps
T41 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2995197855 Aug 04 04:32:00 PM PDT 24 Aug 04 04:32:01 PM PDT 24 30889554 ps
T23 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1480324892 Aug 04 04:32:12 PM PDT 24 Aug 04 04:32:13 PM PDT 24 29217056 ps
T4 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2353939331 Aug 04 04:32:17 PM PDT 24 Aug 04 04:32:18 PM PDT 24 30344038 ps
T42 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2882494467 Aug 04 04:32:10 PM PDT 24 Aug 04 04:32:11 PM PDT 24 29698278 ps
T43 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4077701099 Aug 04 04:32:06 PM PDT 24 Aug 04 04:32:06 PM PDT 24 30569360 ps
T16 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3390148365 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:11 PM PDT 24 28043354 ps
T44 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3203777379 Aug 04 04:32:08 PM PDT 24 Aug 04 04:32:09 PM PDT 24 29846222 ps
T45 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4163462945 Aug 04 04:32:21 PM PDT 24 Aug 04 04:32:22 PM PDT 24 31284253 ps
T46 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2523501150 Aug 04 04:32:18 PM PDT 24 Aug 04 04:32:19 PM PDT 24 30170301 ps
T47 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1518765478 Aug 04 04:32:07 PM PDT 24 Aug 04 04:32:07 PM PDT 24 31336750 ps
T51 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3957879123 Aug 04 04:32:21 PM PDT 24 Aug 04 04:32:27 PM PDT 24 29828777 ps
T52 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2038606027 Aug 04 04:32:16 PM PDT 24 Aug 04 04:32:16 PM PDT 24 31872940 ps
T53 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.534483469 Aug 04 04:32:09 PM PDT 24 Aug 04 04:32:09 PM PDT 24 31346082 ps
T54 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2691677852 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:11 PM PDT 24 30492597 ps
T55 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2987571145 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:12 PM PDT 24 30387001 ps
T56 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3956087187 Aug 04 04:32:08 PM PDT 24 Aug 04 04:32:09 PM PDT 24 30073300 ps
T40 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3182097829 Aug 04 04:32:12 PM PDT 24 Aug 04 04:32:12 PM PDT 24 31913260 ps
T57 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3943383840 Aug 04 04:32:35 PM PDT 24 Aug 04 04:32:35 PM PDT 24 30557514 ps
T58 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2065455786 Aug 04 04:32:18 PM PDT 24 Aug 04 04:32:19 PM PDT 24 30730286 ps
T5 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1166895129 Aug 04 04:32:23 PM PDT 24 Aug 04 04:32:28 PM PDT 24 30405845 ps
T24 /workspace/coverage/sync_alert/18.prim_sync_alert.3633377416 Aug 04 04:21:58 PM PDT 24 Aug 04 04:21:58 PM PDT 24 9737391 ps
T34 /workspace/coverage/sync_alert/3.prim_sync_alert.3245094473 Aug 04 04:21:30 PM PDT 24 Aug 04 04:21:30 PM PDT 24 8420999 ps
T25 /workspace/coverage/sync_alert/1.prim_sync_alert.1846280488 Aug 04 04:21:10 PM PDT 24 Aug 04 04:21:11 PM PDT 24 10253953 ps
T35 /workspace/coverage/sync_alert/5.prim_sync_alert.2511410138 Aug 04 04:25:46 PM PDT 24 Aug 04 04:25:46 PM PDT 24 8673229 ps
T26 /workspace/coverage/sync_alert/0.prim_sync_alert.3462170946 Aug 04 04:25:39 PM PDT 24 Aug 04 04:25:40 PM PDT 24 8803811 ps
T36 /workspace/coverage/sync_alert/15.prim_sync_alert.3327179385 Aug 04 04:22:38 PM PDT 24 Aug 04 04:22:38 PM PDT 24 8748811 ps
T37 /workspace/coverage/sync_alert/14.prim_sync_alert.3732720948 Aug 04 04:25:45 PM PDT 24 Aug 04 04:25:45 PM PDT 24 8628779 ps
T10 /workspace/coverage/sync_alert/12.prim_sync_alert.852683208 Aug 04 04:25:45 PM PDT 24 Aug 04 04:25:46 PM PDT 24 9407920 ps
T27 /workspace/coverage/sync_alert/7.prim_sync_alert.764139714 Aug 04 04:23:50 PM PDT 24 Aug 04 04:23:50 PM PDT 24 9288074 ps
T38 /workspace/coverage/sync_alert/10.prim_sync_alert.1821892397 Aug 04 04:21:58 PM PDT 24 Aug 04 04:21:59 PM PDT 24 9304937 ps
T59 /workspace/coverage/sync_alert/6.prim_sync_alert.1916779375 Aug 04 04:26:00 PM PDT 24 Aug 04 04:26:00 PM PDT 24 9530978 ps
T28 /workspace/coverage/sync_alert/8.prim_sync_alert.2807607922 Aug 04 04:22:41 PM PDT 24 Aug 04 04:22:42 PM PDT 24 9506417 ps
T29 /workspace/coverage/sync_alert/17.prim_sync_alert.1214233362 Aug 04 04:25:44 PM PDT 24 Aug 04 04:25:45 PM PDT 24 8289274 ps
T30 /workspace/coverage/sync_alert/13.prim_sync_alert.2893108646 Aug 04 04:23:24 PM PDT 24 Aug 04 04:23:24 PM PDT 24 8377176 ps
T60 /workspace/coverage/sync_alert/4.prim_sync_alert.1998409232 Aug 04 04:22:11 PM PDT 24 Aug 04 04:22:12 PM PDT 24 9830402 ps
T61 /workspace/coverage/sync_alert/19.prim_sync_alert.3823779117 Aug 04 04:25:34 PM PDT 24 Aug 04 04:25:35 PM PDT 24 10360305 ps
T62 /workspace/coverage/sync_alert/11.prim_sync_alert.212789688 Aug 04 04:22:38 PM PDT 24 Aug 04 04:22:39 PM PDT 24 9372101 ps
T63 /workspace/coverage/sync_alert/9.prim_sync_alert.2784226150 Aug 04 04:21:37 PM PDT 24 Aug 04 04:21:37 PM PDT 24 9047964 ps
T31 /workspace/coverage/sync_alert/2.prim_sync_alert.2199773051 Aug 04 04:22:02 PM PDT 24 Aug 04 04:22:03 PM PDT 24 8712078 ps
T64 /workspace/coverage/sync_alert/16.prim_sync_alert.3204436681 Aug 04 04:24:21 PM PDT 24 Aug 04 04:24:22 PM PDT 24 8760402 ps
T6 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2310474463 Aug 04 04:32:32 PM PDT 24 Aug 04 04:32:32 PM PDT 24 27365198 ps
T32 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.368631602 Aug 04 04:32:45 PM PDT 24 Aug 04 04:32:45 PM PDT 24 27665790 ps
T33 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.730107656 Aug 04 04:33:01 PM PDT 24 Aug 04 04:33:02 PM PDT 24 26889153 ps
T65 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.562748694 Aug 04 04:32:18 PM PDT 24 Aug 04 04:32:19 PM PDT 24 28342774 ps
T11 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1189324272 Aug 04 04:32:41 PM PDT 24 Aug 04 04:32:47 PM PDT 24 26470329 ps
T66 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.921221048 Aug 04 04:32:44 PM PDT 24 Aug 04 04:32:44 PM PDT 24 27037224 ps
T67 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3195505371 Aug 04 04:32:36 PM PDT 24 Aug 04 04:32:37 PM PDT 24 26426908 ps
T68 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.701490630 Aug 04 04:32:46 PM PDT 24 Aug 04 04:32:47 PM PDT 24 27405503 ps
T69 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.80283588 Aug 04 04:32:31 PM PDT 24 Aug 04 04:32:32 PM PDT 24 26731725 ps
T70 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1288762908 Aug 04 04:32:46 PM PDT 24 Aug 04 04:32:47 PM PDT 24 29252395 ps
T71 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1516303764 Aug 04 04:33:15 PM PDT 24 Aug 04 04:33:16 PM PDT 24 29315608 ps
T72 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1777275484 Aug 04 04:32:37 PM PDT 24 Aug 04 04:32:37 PM PDT 24 28665352 ps
T73 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1116767275 Aug 04 04:32:29 PM PDT 24 Aug 04 04:32:29 PM PDT 24 26921682 ps
T74 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3666043400 Aug 04 04:32:48 PM PDT 24 Aug 04 04:32:48 PM PDT 24 27197231 ps
T75 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.408792484 Aug 04 04:32:57 PM PDT 24 Aug 04 04:32:58 PM PDT 24 26141155 ps
T76 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2548921575 Aug 04 04:32:18 PM PDT 24 Aug 04 04:32:21 PM PDT 24 27458257 ps
T77 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2340253038 Aug 04 04:32:31 PM PDT 24 Aug 04 04:32:31 PM PDT 24 28466948 ps
T78 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.765270081 Aug 04 04:32:36 PM PDT 24 Aug 04 04:32:37 PM PDT 24 27799055 ps
T79 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.946403318 Aug 04 04:32:35 PM PDT 24 Aug 04 04:32:36 PM PDT 24 27458130 ps
T80 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1212557825 Aug 04 04:32:13 PM PDT 24 Aug 04 04:32:14 PM PDT 24 28077832 ps

Test location /workspace/coverage/default/12.prim_async_alert.3058144747
Short name T9
Test name
Test status
Simulation time 12353944 ps
CPU time 0.38 seconds
Started Aug 04 04:31:36 PM PDT 24
Finished Aug 04 04:31:37 PM PDT 24
Peak memory 145628 kb
Host smart-ad333a28-1ce8-4dfa-adab-50c80b1d8a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058144747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3058144747
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3462170946
Short name T26
Test name
Test status
Simulation time 8803811 ps
CPU time 0.37 seconds
Started Aug 04 04:25:39 PM PDT 24
Finished Aug 04 04:25:40 PM PDT 24
Peak memory 145212 kb
Host smart-019af203-81e8-4fa6-999f-1c3c55c01ff7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3462170946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3462170946
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1480324892
Short name T23
Test name
Test status
Simulation time 29217056 ps
CPU time 0.43 seconds
Started Aug 04 04:32:12 PM PDT 24
Finished Aug 04 04:32:13 PM PDT 24
Peak memory 145248 kb
Host smart-5cfcdec2-cda3-42f4-8d03-863f4cd8cda5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1480324892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1480324892
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.135231018
Short name T8
Test name
Test status
Simulation time 11091202 ps
CPU time 0.37 seconds
Started Aug 04 04:31:41 PM PDT 24
Finished Aug 04 04:31:42 PM PDT 24
Peak memory 145620 kb
Host smart-cacfb3e3-4a57-4259-9928-cdd740ae934f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135231018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.135231018
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2353939331
Short name T4
Test name
Test status
Simulation time 30344038 ps
CPU time 0.42 seconds
Started Aug 04 04:32:17 PM PDT 24
Finished Aug 04 04:32:18 PM PDT 24
Peak memory 145200 kb
Host smart-f5fda7b9-c337-4e21-9303-b8a546597295
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2353939331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2353939331
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.852683208
Short name T10
Test name
Test status
Simulation time 9407920 ps
CPU time 0.39 seconds
Started Aug 04 04:25:45 PM PDT 24
Finished Aug 04 04:25:46 PM PDT 24
Peak memory 145200 kb
Host smart-1125157b-4d8a-4731-a3f5-55a978d29d2e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=852683208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.852683208
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3214589799
Short name T39
Test name
Test status
Simulation time 10776259 ps
CPU time 0.39 seconds
Started Aug 04 04:31:39 PM PDT 24
Finished Aug 04 04:31:39 PM PDT 24
Peak memory 145768 kb
Host smart-ea066699-ad67-46a4-b13b-dacc2f6da91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214589799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3214589799
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2543181235
Short name T19
Test name
Test status
Simulation time 10425177 ps
CPU time 0.39 seconds
Started Aug 04 04:31:56 PM PDT 24
Finished Aug 04 04:31:56 PM PDT 24
Peak memory 145668 kb
Host smart-bba15c29-3a09-4f82-94af-0ef01afff13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543181235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2543181235
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2431155361
Short name T12
Test name
Test status
Simulation time 11435141 ps
CPU time 0.38 seconds
Started Aug 04 04:31:59 PM PDT 24
Finished Aug 04 04:32:00 PM PDT 24
Peak memory 145648 kb
Host smart-0b0e3e76-fe57-487c-a7f0-2301c3eedb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431155361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2431155361
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.4118966426
Short name T1
Test name
Test status
Simulation time 11215477 ps
CPU time 0.39 seconds
Started Aug 04 04:31:29 PM PDT 24
Finished Aug 04 04:31:30 PM PDT 24
Peak memory 145668 kb
Host smart-06985e20-5789-4646-984a-57b30577daa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118966426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.4118966426
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.4187431306
Short name T3
Test name
Test status
Simulation time 10804387 ps
CPU time 0.39 seconds
Started Aug 04 04:31:26 PM PDT 24
Finished Aug 04 04:31:26 PM PDT 24
Peak memory 145892 kb
Host smart-84596a67-47eb-462d-90dc-8037b626315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187431306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.4187431306
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1458042202
Short name T2
Test name
Test status
Simulation time 10513438 ps
CPU time 0.41 seconds
Started Aug 04 04:31:40 PM PDT 24
Finished Aug 04 04:31:41 PM PDT 24
Peak memory 145668 kb
Host smart-45353423-93fd-49a9-aad3-9e17d810a9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458042202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1458042202
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.458318483
Short name T21
Test name
Test status
Simulation time 10793710 ps
CPU time 0.37 seconds
Started Aug 04 04:31:34 PM PDT 24
Finished Aug 04 04:31:34 PM PDT 24
Peak memory 145692 kb
Host smart-31f34cf9-f1e4-4a3e-b906-c51f2964e581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458318483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.458318483
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1471432502
Short name T49
Test name
Test status
Simulation time 10300293 ps
CPU time 0.37 seconds
Started Aug 04 04:32:02 PM PDT 24
Finished Aug 04 04:32:03 PM PDT 24
Peak memory 145668 kb
Host smart-b2b6fccc-4b56-4bd8-b6fd-45610da72c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471432502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1471432502
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.82018987
Short name T17
Test name
Test status
Simulation time 10981800 ps
CPU time 0.39 seconds
Started Aug 04 04:31:35 PM PDT 24
Finished Aug 04 04:31:35 PM PDT 24
Peak memory 145628 kb
Host smart-7e29691a-3181-4487-82cf-257d219bc14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82018987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.82018987
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2251989522
Short name T50
Test name
Test status
Simulation time 10979922 ps
CPU time 0.37 seconds
Started Aug 04 04:31:51 PM PDT 24
Finished Aug 04 04:31:52 PM PDT 24
Peak memory 145672 kb
Host smart-7ab9c7d0-a131-4f4c-bd36-b51623b45d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251989522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2251989522
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2452911934
Short name T14
Test name
Test status
Simulation time 12212273 ps
CPU time 0.39 seconds
Started Aug 04 04:31:41 PM PDT 24
Finished Aug 04 04:31:42 PM PDT 24
Peak memory 145680 kb
Host smart-4fa2c517-623b-4374-8ee8-f25eb66564d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452911934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2452911934
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3871611295
Short name T20
Test name
Test status
Simulation time 10823911 ps
CPU time 0.4 seconds
Started Aug 04 04:31:33 PM PDT 24
Finished Aug 04 04:31:33 PM PDT 24
Peak memory 145796 kb
Host smart-cafff68c-c6f1-4013-83e1-1924c44d9790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871611295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3871611295
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.121130250
Short name T13
Test name
Test status
Simulation time 11408994 ps
CPU time 0.39 seconds
Started Aug 04 04:31:42 PM PDT 24
Finished Aug 04 04:31:43 PM PDT 24
Peak memory 145624 kb
Host smart-78890e34-d8e1-4234-88d0-037e8dce3dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121130250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.121130250
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2716395007
Short name T7
Test name
Test status
Simulation time 12177246 ps
CPU time 0.41 seconds
Started Aug 04 04:31:48 PM PDT 24
Finished Aug 04 04:31:48 PM PDT 24
Peak memory 145732 kb
Host smart-5a744bf0-e138-4715-a48e-51ce3c1a9b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716395007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2716395007
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3119119057
Short name T22
Test name
Test status
Simulation time 10701167 ps
CPU time 0.41 seconds
Started Aug 04 04:31:31 PM PDT 24
Finished Aug 04 04:31:31 PM PDT 24
Peak memory 145796 kb
Host smart-e038b85d-3f6a-4b49-904d-76794574a4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119119057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3119119057
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1610453273
Short name T18
Test name
Test status
Simulation time 10550813 ps
CPU time 0.36 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:21 PM PDT 24
Peak memory 145660 kb
Host smart-fe0b2bb9-5e37-4455-98b8-b6cae940c4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610453273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1610453273
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.767103252
Short name T48
Test name
Test status
Simulation time 10874129 ps
CPU time 0.4 seconds
Started Aug 04 04:31:30 PM PDT 24
Finished Aug 04 04:31:31 PM PDT 24
Peak memory 145660 kb
Host smart-abc45cbf-3bac-4f88-9068-5322953cf8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767103252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.767103252
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2317069105
Short name T15
Test name
Test status
Simulation time 11074971 ps
CPU time 0.38 seconds
Started Aug 04 04:31:36 PM PDT 24
Finished Aug 04 04:31:37 PM PDT 24
Peak memory 145620 kb
Host smart-9d1c1a8d-2f7e-4b69-af26-e0e1883cccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317069105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2317069105
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2987571145
Short name T55
Test name
Test status
Simulation time 30387001 ps
CPU time 0.43 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:12 PM PDT 24
Peak memory 145244 kb
Host smart-e53c7118-5dda-4e3d-9b25-4a7359fc99fa
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2987571145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2987571145
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4163462945
Short name T45
Test name
Test status
Simulation time 31284253 ps
CPU time 0.39 seconds
Started Aug 04 04:32:21 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 145240 kb
Host smart-c30cd734-64f6-4a22-97d1-69b7b564bf62
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4163462945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.4163462945
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3957879123
Short name T51
Test name
Test status
Simulation time 29828777 ps
CPU time 0.4 seconds
Started Aug 04 04:32:21 PM PDT 24
Finished Aug 04 04:32:27 PM PDT 24
Peak memory 145184 kb
Host smart-d548d0c1-0e2c-423e-920d-4a23548e20a6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3957879123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3957879123
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3203777379
Short name T44
Test name
Test status
Simulation time 29846222 ps
CPU time 0.39 seconds
Started Aug 04 04:32:08 PM PDT 24
Finished Aug 04 04:32:09 PM PDT 24
Peak memory 145200 kb
Host smart-d0cd2be2-a1cd-4545-92b8-29a3e823223e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3203777379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3203777379
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3943383840
Short name T57
Test name
Test status
Simulation time 30557514 ps
CPU time 0.38 seconds
Started Aug 04 04:32:35 PM PDT 24
Finished Aug 04 04:32:35 PM PDT 24
Peak memory 145172 kb
Host smart-e0e2deba-26ca-4365-a43a-5da6e7a044d2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3943383840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3943383840
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3182097829
Short name T40
Test name
Test status
Simulation time 31913260 ps
CPU time 0.4 seconds
Started Aug 04 04:32:12 PM PDT 24
Finished Aug 04 04:32:12 PM PDT 24
Peak memory 145208 kb
Host smart-acbe4885-ac77-4775-8687-06bfcb1c2c4c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3182097829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3182097829
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2065455786
Short name T58
Test name
Test status
Simulation time 30730286 ps
CPU time 0.39 seconds
Started Aug 04 04:32:18 PM PDT 24
Finished Aug 04 04:32:19 PM PDT 24
Peak memory 145200 kb
Host smart-d134cd78-b6b1-46bc-8c8f-1f455141754e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2065455786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2065455786
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2523501150
Short name T46
Test name
Test status
Simulation time 30170301 ps
CPU time 0.39 seconds
Started Aug 04 04:32:18 PM PDT 24
Finished Aug 04 04:32:19 PM PDT 24
Peak memory 145304 kb
Host smart-02d6673e-4642-45dd-9cb7-a275ea96cd7a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2523501150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2523501150
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2038606027
Short name T52
Test name
Test status
Simulation time 31872940 ps
CPU time 0.4 seconds
Started Aug 04 04:32:16 PM PDT 24
Finished Aug 04 04:32:16 PM PDT 24
Peak memory 145256 kb
Host smart-990aec2c-12c0-4f87-be9a-eb939f1d1531
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2038606027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2038606027
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1166895129
Short name T5
Test name
Test status
Simulation time 30405845 ps
CPU time 0.4 seconds
Started Aug 04 04:32:23 PM PDT 24
Finished Aug 04 04:32:28 PM PDT 24
Peak memory 145308 kb
Host smart-3083830c-53ae-4f98-97e7-61e8c1e53b82
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1166895129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1166895129
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.534483469
Short name T53
Test name
Test status
Simulation time 31346082 ps
CPU time 0.41 seconds
Started Aug 04 04:32:09 PM PDT 24
Finished Aug 04 04:32:09 PM PDT 24
Peak memory 145208 kb
Host smart-f4d1d390-2a89-48b9-8494-a19eb5ccdef5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=534483469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.534483469
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1518765478
Short name T47
Test name
Test status
Simulation time 31336750 ps
CPU time 0.4 seconds
Started Aug 04 04:32:07 PM PDT 24
Finished Aug 04 04:32:07 PM PDT 24
Peak memory 145240 kb
Host smart-a30d18ad-faf9-4102-9a8d-38aa4c2677f1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1518765478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1518765478
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3390148365
Short name T16
Test name
Test status
Simulation time 28043354 ps
CPU time 0.38 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:11 PM PDT 24
Peak memory 145216 kb
Host smart-b5e466e9-a0d2-4d98-9152-eec152a4033b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3390148365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3390148365
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2995197855
Short name T41
Test name
Test status
Simulation time 30889554 ps
CPU time 0.43 seconds
Started Aug 04 04:32:00 PM PDT 24
Finished Aug 04 04:32:01 PM PDT 24
Peak memory 145412 kb
Host smart-94adafed-0e5f-4fd3-ba1c-0273d7f3b5e5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2995197855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2995197855
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2691677852
Short name T54
Test name
Test status
Simulation time 30492597 ps
CPU time 0.4 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:11 PM PDT 24
Peak memory 145192 kb
Host smart-1f56d524-a30e-4105-b19e-30057ff94755
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2691677852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2691677852
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4077701099
Short name T43
Test name
Test status
Simulation time 30569360 ps
CPU time 0.44 seconds
Started Aug 04 04:32:06 PM PDT 24
Finished Aug 04 04:32:06 PM PDT 24
Peak memory 145212 kb
Host smart-0bdc794f-c318-428c-9cf3-42eda9999684
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4077701099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.4077701099
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3956087187
Short name T56
Test name
Test status
Simulation time 30073300 ps
CPU time 0.4 seconds
Started Aug 04 04:32:08 PM PDT 24
Finished Aug 04 04:32:09 PM PDT 24
Peak memory 145232 kb
Host smart-4e293e72-ace4-4f8d-8671-15413dd8e858
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3956087187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3956087187
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2882494467
Short name T42
Test name
Test status
Simulation time 29698278 ps
CPU time 0.39 seconds
Started Aug 04 04:32:10 PM PDT 24
Finished Aug 04 04:32:11 PM PDT 24
Peak memory 145220 kb
Host smart-0a6e0703-8aef-47cc-97f3-272cb7f838a5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2882494467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2882494467
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1846280488
Short name T25
Test name
Test status
Simulation time 10253953 ps
CPU time 0.39 seconds
Started Aug 04 04:21:10 PM PDT 24
Finished Aug 04 04:21:11 PM PDT 24
Peak memory 145316 kb
Host smart-3128d34b-25f5-4ee9-9cf4-a2a128cc9c2c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1846280488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1846280488
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1821892397
Short name T38
Test name
Test status
Simulation time 9304937 ps
CPU time 0.39 seconds
Started Aug 04 04:21:58 PM PDT 24
Finished Aug 04 04:21:59 PM PDT 24
Peak memory 145424 kb
Host smart-52150f4c-80eb-4642-9a87-5267b62d4e6b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1821892397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1821892397
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.212789688
Short name T62
Test name
Test status
Simulation time 9372101 ps
CPU time 0.4 seconds
Started Aug 04 04:22:38 PM PDT 24
Finished Aug 04 04:22:39 PM PDT 24
Peak memory 145420 kb
Host smart-1aaa6856-86b1-4e7f-9e7b-ed5d708333b8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=212789688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.212789688
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2893108646
Short name T30
Test name
Test status
Simulation time 8377176 ps
CPU time 0.38 seconds
Started Aug 04 04:23:24 PM PDT 24
Finished Aug 04 04:23:24 PM PDT 24
Peak memory 145404 kb
Host smart-56f1cfee-e38b-4bf0-8d84-18d66b5b74c4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2893108646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2893108646
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3732720948
Short name T37
Test name
Test status
Simulation time 8628779 ps
CPU time 0.37 seconds
Started Aug 04 04:25:45 PM PDT 24
Finished Aug 04 04:25:45 PM PDT 24
Peak memory 144568 kb
Host smart-1a55cb58-bbbe-4888-ae78-819fe2ac85fd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3732720948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3732720948
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3327179385
Short name T36
Test name
Test status
Simulation time 8748811 ps
CPU time 0.4 seconds
Started Aug 04 04:22:38 PM PDT 24
Finished Aug 04 04:22:38 PM PDT 24
Peak memory 145420 kb
Host smart-454aa06a-c26d-45f4-a97d-67214e39fcb2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3327179385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3327179385
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3204436681
Short name T64
Test name
Test status
Simulation time 8760402 ps
CPU time 0.4 seconds
Started Aug 04 04:24:21 PM PDT 24
Finished Aug 04 04:24:22 PM PDT 24
Peak memory 145484 kb
Host smart-a5add00f-c8ba-4d14-9892-04a512356712
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3204436681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3204436681
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1214233362
Short name T29
Test name
Test status
Simulation time 8289274 ps
CPU time 0.4 seconds
Started Aug 04 04:25:44 PM PDT 24
Finished Aug 04 04:25:45 PM PDT 24
Peak memory 145412 kb
Host smart-6cf38897-ddc7-4949-a55c-50c5e1b41484
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1214233362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1214233362
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3633377416
Short name T24
Test name
Test status
Simulation time 9737391 ps
CPU time 0.43 seconds
Started Aug 04 04:21:58 PM PDT 24
Finished Aug 04 04:21:58 PM PDT 24
Peak memory 145404 kb
Host smart-b8e26034-024f-4632-b6e5-1bc29bcb314c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3633377416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3633377416
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3823779117
Short name T61
Test name
Test status
Simulation time 10360305 ps
CPU time 0.41 seconds
Started Aug 04 04:25:34 PM PDT 24
Finished Aug 04 04:25:35 PM PDT 24
Peak memory 144336 kb
Host smart-f925fd4c-727e-4bdf-bb7a-599f68fdc736
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3823779117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3823779117
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2199773051
Short name T31
Test name
Test status
Simulation time 8712078 ps
CPU time 0.4 seconds
Started Aug 04 04:22:02 PM PDT 24
Finished Aug 04 04:22:03 PM PDT 24
Peak memory 145476 kb
Host smart-a39e913a-0cb9-4fc9-8318-f357cd417c17
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2199773051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2199773051
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3245094473
Short name T34
Test name
Test status
Simulation time 8420999 ps
CPU time 0.38 seconds
Started Aug 04 04:21:30 PM PDT 24
Finished Aug 04 04:21:30 PM PDT 24
Peak memory 145476 kb
Host smart-8d6ca5ff-0637-4f94-86d6-f2e4c31253f9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3245094473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3245094473
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1998409232
Short name T60
Test name
Test status
Simulation time 9830402 ps
CPU time 0.39 seconds
Started Aug 04 04:22:11 PM PDT 24
Finished Aug 04 04:22:12 PM PDT 24
Peak memory 145308 kb
Host smart-1644b7f7-7e19-40b6-81fc-fb55dd3a658e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1998409232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1998409232
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2511410138
Short name T35
Test name
Test status
Simulation time 8673229 ps
CPU time 0.36 seconds
Started Aug 04 04:25:46 PM PDT 24
Finished Aug 04 04:25:46 PM PDT 24
Peak memory 145348 kb
Host smart-df5218d2-b3c6-4d11-a119-fba7358391a1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2511410138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2511410138
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1916779375
Short name T59
Test name
Test status
Simulation time 9530978 ps
CPU time 0.36 seconds
Started Aug 04 04:26:00 PM PDT 24
Finished Aug 04 04:26:00 PM PDT 24
Peak memory 145384 kb
Host smart-d4cba4ff-661c-4ef4-a16b-4859e6fac2cf
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1916779375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1916779375
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.764139714
Short name T27
Test name
Test status
Simulation time 9288074 ps
CPU time 0.39 seconds
Started Aug 04 04:23:50 PM PDT 24
Finished Aug 04 04:23:50 PM PDT 24
Peak memory 145388 kb
Host smart-e12c81e5-8c42-4ea3-b103-5efa95870fc0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=764139714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.764139714
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2807607922
Short name T28
Test name
Test status
Simulation time 9506417 ps
CPU time 0.39 seconds
Started Aug 04 04:22:41 PM PDT 24
Finished Aug 04 04:22:42 PM PDT 24
Peak memory 145356 kb
Host smart-2054d78f-a82b-405a-bbbb-60d5e1e7decc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2807607922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2807607922
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2784226150
Short name T63
Test name
Test status
Simulation time 9047964 ps
CPU time 0.42 seconds
Started Aug 04 04:21:37 PM PDT 24
Finished Aug 04 04:21:37 PM PDT 24
Peak memory 145436 kb
Host smart-7df4f106-4c0f-4174-b854-97a640f4e574
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2784226150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2784226150
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2310474463
Short name T6
Test name
Test status
Simulation time 27365198 ps
CPU time 0.41 seconds
Started Aug 04 04:32:32 PM PDT 24
Finished Aug 04 04:32:32 PM PDT 24
Peak memory 145488 kb
Host smart-551551d8-d269-4b2e-90ba-ae31b3fc59ea
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2310474463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2310474463
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1516303764
Short name T71
Test name
Test status
Simulation time 29315608 ps
CPU time 0.43 seconds
Started Aug 04 04:33:15 PM PDT 24
Finished Aug 04 04:33:16 PM PDT 24
Peak memory 145828 kb
Host smart-d1a1d2a9-9303-4214-937b-ff29a5f73780
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1516303764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1516303764
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1777275484
Short name T72
Test name
Test status
Simulation time 28665352 ps
CPU time 0.39 seconds
Started Aug 04 04:32:37 PM PDT 24
Finished Aug 04 04:32:37 PM PDT 24
Peak memory 145616 kb
Host smart-1f7e162c-8e16-47af-8812-9d69f5a4709d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1777275484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1777275484
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1116767275
Short name T73
Test name
Test status
Simulation time 26921682 ps
CPU time 0.39 seconds
Started Aug 04 04:32:29 PM PDT 24
Finished Aug 04 04:32:29 PM PDT 24
Peak memory 145480 kb
Host smart-d2c0542a-9d63-4cf1-a6b4-faf51dc7e877
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1116767275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1116767275
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.408792484
Short name T75
Test name
Test status
Simulation time 26141155 ps
CPU time 0.41 seconds
Started Aug 04 04:32:57 PM PDT 24
Finished Aug 04 04:32:58 PM PDT 24
Peak memory 145628 kb
Host smart-d47bbec5-ff70-4398-aec0-d82ee7040401
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=408792484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.408792484
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1212557825
Short name T80
Test name
Test status
Simulation time 28077832 ps
CPU time 0.38 seconds
Started Aug 04 04:32:13 PM PDT 24
Finished Aug 04 04:32:14 PM PDT 24
Peak memory 145480 kb
Host smart-537e433f-bdbc-47d4-9065-62d2c7d37671
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1212557825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1212557825
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2548921575
Short name T76
Test name
Test status
Simulation time 27458257 ps
CPU time 0.38 seconds
Started Aug 04 04:32:18 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 145476 kb
Host smart-00ec45aa-698c-4c5b-9182-250b5393d085
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2548921575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2548921575
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.80283588
Short name T69
Test name
Test status
Simulation time 26731725 ps
CPU time 0.38 seconds
Started Aug 04 04:32:31 PM PDT 24
Finished Aug 04 04:32:32 PM PDT 24
Peak memory 145508 kb
Host smart-9b20de36-232c-43fd-b370-80672448bda4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=80283588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.80283588
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.562748694
Short name T65
Test name
Test status
Simulation time 28342774 ps
CPU time 0.38 seconds
Started Aug 04 04:32:18 PM PDT 24
Finished Aug 04 04:32:19 PM PDT 24
Peak memory 145588 kb
Host smart-a5e5bc7a-364b-42f2-adb3-7ba403efc666
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=562748694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.562748694
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3195505371
Short name T67
Test name
Test status
Simulation time 26426908 ps
CPU time 0.39 seconds
Started Aug 04 04:32:36 PM PDT 24
Finished Aug 04 04:32:37 PM PDT 24
Peak memory 145480 kb
Host smart-f414b52a-66fb-41da-ba91-424687a5fcfd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3195505371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3195505371
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.765270081
Short name T78
Test name
Test status
Simulation time 27799055 ps
CPU time 0.39 seconds
Started Aug 04 04:32:36 PM PDT 24
Finished Aug 04 04:32:37 PM PDT 24
Peak memory 145456 kb
Host smart-c7545e08-b8a2-4d3e-a8e9-7712755723de
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=765270081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.765270081
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.946403318
Short name T79
Test name
Test status
Simulation time 27458130 ps
CPU time 0.38 seconds
Started Aug 04 04:32:35 PM PDT 24
Finished Aug 04 04:32:36 PM PDT 24
Peak memory 145456 kb
Host smart-8f993186-70c8-43af-b438-489f4405503f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=946403318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.946403318
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.730107656
Short name T33
Test name
Test status
Simulation time 26889153 ps
CPU time 0.44 seconds
Started Aug 04 04:33:01 PM PDT 24
Finished Aug 04 04:33:02 PM PDT 24
Peak memory 145480 kb
Host smart-881d23d5-8d2a-4570-be91-21b4af2e7b06
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=730107656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.730107656
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3666043400
Short name T74
Test name
Test status
Simulation time 27197231 ps
CPU time 0.4 seconds
Started Aug 04 04:32:48 PM PDT 24
Finished Aug 04 04:32:48 PM PDT 24
Peak memory 145516 kb
Host smart-4c707e77-67e7-4d31-8ad2-615a9b7eb88c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3666043400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3666043400
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.701490630
Short name T68
Test name
Test status
Simulation time 27405503 ps
CPU time 0.4 seconds
Started Aug 04 04:32:46 PM PDT 24
Finished Aug 04 04:32:47 PM PDT 24
Peak memory 145492 kb
Host smart-942f9a3c-634d-4ddc-a3b4-ca6ab37df017
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=701490630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.701490630
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1288762908
Short name T70
Test name
Test status
Simulation time 29252395 ps
CPU time 0.38 seconds
Started Aug 04 04:32:46 PM PDT 24
Finished Aug 04 04:32:47 PM PDT 24
Peak memory 145452 kb
Host smart-65aefac8-c0e5-42d3-ab3b-4bdbeeb9d969
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1288762908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1288762908
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1189324272
Short name T11
Test name
Test status
Simulation time 26470329 ps
CPU time 0.39 seconds
Started Aug 04 04:32:41 PM PDT 24
Finished Aug 04 04:32:47 PM PDT 24
Peak memory 145452 kb
Host smart-885bab63-46e0-446c-a454-a81a395e6ad7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1189324272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1189324272
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.368631602
Short name T32
Test name
Test status
Simulation time 27665790 ps
CPU time 0.39 seconds
Started Aug 04 04:32:45 PM PDT 24
Finished Aug 04 04:32:45 PM PDT 24
Peak memory 145464 kb
Host smart-ec9dbed1-11a8-425d-b1bb-d7f57a80f3e3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=368631602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.368631602
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2340253038
Short name T77
Test name
Test status
Simulation time 28466948 ps
CPU time 0.38 seconds
Started Aug 04 04:32:31 PM PDT 24
Finished Aug 04 04:32:31 PM PDT 24
Peak memory 145472 kb
Host smart-d6295743-e8ad-4f29-b85b-ca12c2b447db
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2340253038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2340253038
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.921221048
Short name T66
Test name
Test status
Simulation time 27037224 ps
CPU time 0.37 seconds
Started Aug 04 04:32:44 PM PDT 24
Finished Aug 04 04:32:44 PM PDT 24
Peak memory 145464 kb
Host smart-53c29aa5-ab86-48f0-8907-a546bee58560
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=921221048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.921221048
Directory /workspace/9.prim_sync_fatal_alert/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%