Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 78
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.47 89.47 100.00 100.00 93.75 93.75 100.00 100.00 82.14 82.14 95.83 95.83 65.12 65.12 /workspace/coverage/default/6.prim_async_alert.3623544616
92.35 2.88 100.00 0.00 95.83 2.08 100.00 0.00 85.71 3.57 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/10.prim_sync_alert.516538055
93.86 1.51 100.00 0.00 97.92 2.08 100.00 0.00 85.71 0.00 95.83 0.00 83.72 6.98 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1246705025
94.85 0.98 100.00 0.00 97.92 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 2.33 /workspace/coverage/default/0.prim_async_alert.3768253275
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2643941724

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.4215692335
/workspace/coverage/default/10.prim_async_alert.154088878
/workspace/coverage/default/11.prim_async_alert.2784091760
/workspace/coverage/default/12.prim_async_alert.3607890141
/workspace/coverage/default/13.prim_async_alert.3591037873
/workspace/coverage/default/14.prim_async_alert.2429669188
/workspace/coverage/default/15.prim_async_alert.76389209
/workspace/coverage/default/16.prim_async_alert.4109244677
/workspace/coverage/default/17.prim_async_alert.1039502987
/workspace/coverage/default/18.prim_async_alert.784456460
/workspace/coverage/default/19.prim_async_alert.2897847704
/workspace/coverage/default/2.prim_async_alert.514431294
/workspace/coverage/default/3.prim_async_alert.3270050444
/workspace/coverage/default/4.prim_async_alert.3006091596
/workspace/coverage/default/5.prim_async_alert.3682264725
/workspace/coverage/default/7.prim_async_alert.3447117510
/workspace/coverage/default/8.prim_async_alert.29287810
/workspace/coverage/default/9.prim_async_alert.1700884925
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1994783521
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3041314029
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3977329103
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2463755565
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2366861194
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2245142769
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.356145336
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.886128847
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1094615868
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4211290864
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3043785678
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2045407471
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3565294374
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3173397980
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.900301457
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.260628991
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1993485583
/workspace/coverage/sync_alert/0.prim_sync_alert.1316730926
/workspace/coverage/sync_alert/1.prim_sync_alert.1363090708
/workspace/coverage/sync_alert/11.prim_sync_alert.2676729233
/workspace/coverage/sync_alert/12.prim_sync_alert.2651111222
/workspace/coverage/sync_alert/13.prim_sync_alert.3377495000
/workspace/coverage/sync_alert/14.prim_sync_alert.168130642
/workspace/coverage/sync_alert/15.prim_sync_alert.415296158
/workspace/coverage/sync_alert/16.prim_sync_alert.4126186726
/workspace/coverage/sync_alert/17.prim_sync_alert.2842416211
/workspace/coverage/sync_alert/18.prim_sync_alert.2267977381
/workspace/coverage/sync_alert/19.prim_sync_alert.803717671
/workspace/coverage/sync_alert/2.prim_sync_alert.2549436318
/workspace/coverage/sync_alert/3.prim_sync_alert.4192964187
/workspace/coverage/sync_alert/4.prim_sync_alert.2369177547
/workspace/coverage/sync_alert/5.prim_sync_alert.1990552547
/workspace/coverage/sync_alert/6.prim_sync_alert.3873722752
/workspace/coverage/sync_alert/7.prim_sync_alert.1123061225
/workspace/coverage/sync_alert/8.prim_sync_alert.1555323421
/workspace/coverage/sync_alert/9.prim_sync_alert.1115525004
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2295885597
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3730940943
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1215545387
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3522520281
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1861546226
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2883076900
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2241060386
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3788285277
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3441733018
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2787539753
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.535747145
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3813752283
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3590615333
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.499496532
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.722032692
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3751514242
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2590060245
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1710622495
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2395470599



Total test records in report: 78
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/19.prim_async_alert.2897847704 Aug 05 05:09:03 PM PDT 24 Aug 05 05:09:04 PM PDT 24 10772435 ps
T2 /workspace/coverage/default/6.prim_async_alert.3623544616 Aug 05 05:08:40 PM PDT 24 Aug 05 05:08:41 PM PDT 24 12811635 ps
T3 /workspace/coverage/default/14.prim_async_alert.2429669188 Aug 05 05:08:54 PM PDT 24 Aug 05 05:08:54 PM PDT 24 11012444 ps
T13 /workspace/coverage/default/10.prim_async_alert.154088878 Aug 05 05:08:38 PM PDT 24 Aug 05 05:08:38 PM PDT 24 11843759 ps
T18 /workspace/coverage/default/17.prim_async_alert.1039502987 Aug 05 05:08:53 PM PDT 24 Aug 05 05:08:54 PM PDT 24 11853226 ps
T8 /workspace/coverage/default/7.prim_async_alert.3447117510 Aug 05 05:08:40 PM PDT 24 Aug 05 05:08:40 PM PDT 24 11164967 ps
T19 /workspace/coverage/default/2.prim_async_alert.514431294 Aug 05 05:08:40 PM PDT 24 Aug 05 05:08:40 PM PDT 24 10278727 ps
T16 /workspace/coverage/default/3.prim_async_alert.3270050444 Aug 05 05:08:50 PM PDT 24 Aug 05 05:08:50 PM PDT 24 11421877 ps
T17 /workspace/coverage/default/0.prim_async_alert.3768253275 Aug 05 05:08:42 PM PDT 24 Aug 05 05:08:43 PM PDT 24 10555276 ps
T14 /workspace/coverage/default/5.prim_async_alert.3682264725 Aug 05 05:08:45 PM PDT 24 Aug 05 05:08:45 PM PDT 24 11436448 ps
T6 /workspace/coverage/default/1.prim_async_alert.4215692335 Aug 05 05:08:50 PM PDT 24 Aug 05 05:08:51 PM PDT 24 10890821 ps
T20 /workspace/coverage/default/8.prim_async_alert.29287810 Aug 05 05:08:51 PM PDT 24 Aug 05 05:08:51 PM PDT 24 11147063 ps
T9 /workspace/coverage/default/16.prim_async_alert.4109244677 Aug 05 05:08:44 PM PDT 24 Aug 05 05:08:44 PM PDT 24 12462339 ps
T43 /workspace/coverage/default/9.prim_async_alert.1700884925 Aug 05 05:08:38 PM PDT 24 Aug 05 05:08:39 PM PDT 24 11659544 ps
T7 /workspace/coverage/default/4.prim_async_alert.3006091596 Aug 05 05:08:42 PM PDT 24 Aug 05 05:08:42 PM PDT 24 12215972 ps
T44 /workspace/coverage/default/15.prim_async_alert.76389209 Aug 05 05:08:51 PM PDT 24 Aug 05 05:08:51 PM PDT 24 11408545 ps
T45 /workspace/coverage/default/13.prim_async_alert.3591037873 Aug 05 05:08:53 PM PDT 24 Aug 05 05:08:54 PM PDT 24 11899524 ps
T46 /workspace/coverage/default/12.prim_async_alert.3607890141 Aug 05 05:08:40 PM PDT 24 Aug 05 05:08:41 PM PDT 24 11874647 ps
T47 /workspace/coverage/default/18.prim_async_alert.784456460 Aug 05 05:08:45 PM PDT 24 Aug 05 05:08:46 PM PDT 24 11282425 ps
T48 /workspace/coverage/default/11.prim_async_alert.2784091760 Aug 05 05:08:45 PM PDT 24 Aug 05 05:08:45 PM PDT 24 10758162 ps
T15 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1994783521 Aug 05 04:24:42 PM PDT 24 Aug 05 04:24:42 PM PDT 24 31954516 ps
T34 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.356145336 Aug 05 04:23:26 PM PDT 24 Aug 05 04:23:27 PM PDT 24 28463830 ps
T35 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1246705025 Aug 05 04:23:18 PM PDT 24 Aug 05 04:23:18 PM PDT 24 29081347 ps
T36 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3173397980 Aug 05 04:23:09 PM PDT 24 Aug 05 04:23:09 PM PDT 24 30804991 ps
T37 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3977329103 Aug 05 04:23:24 PM PDT 24 Aug 05 04:23:24 PM PDT 24 31611113 ps
T38 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1993485583 Aug 05 04:23:21 PM PDT 24 Aug 05 04:23:21 PM PDT 24 29918290 ps
T39 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2245142769 Aug 05 04:23:35 PM PDT 24 Aug 05 04:23:36 PM PDT 24 30441981 ps
T40 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3043785678 Aug 05 04:23:31 PM PDT 24 Aug 05 04:23:32 PM PDT 24 30040947 ps
T41 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3565294374 Aug 05 04:23:36 PM PDT 24 Aug 05 04:23:37 PM PDT 24 31207761 ps
T42 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1094615868 Aug 05 04:24:40 PM PDT 24 Aug 05 04:24:40 PM PDT 24 31424472 ps
T49 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2045407471 Aug 05 04:24:57 PM PDT 24 Aug 05 04:24:58 PM PDT 24 31099995 ps
T50 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3041314029 Aug 05 04:23:41 PM PDT 24 Aug 05 04:23:41 PM PDT 24 30037578 ps
T51 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.886128847 Aug 05 04:23:33 PM PDT 24 Aug 05 04:23:34 PM PDT 24 29685515 ps
T52 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4211290864 Aug 05 04:23:16 PM PDT 24 Aug 05 04:23:16 PM PDT 24 30183871 ps
T53 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.260628991 Aug 05 04:23:15 PM PDT 24 Aug 05 04:23:16 PM PDT 24 28492430 ps
T54 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.900301457 Aug 05 04:23:34 PM PDT 24 Aug 05 04:23:35 PM PDT 24 29824970 ps
T55 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2463755565 Aug 05 04:23:15 PM PDT 24 Aug 05 04:23:15 PM PDT 24 29444076 ps
T56 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2366861194 Aug 05 04:24:29 PM PDT 24 Aug 05 04:24:29 PM PDT 24 29986769 ps
T29 /workspace/coverage/sync_alert/7.prim_sync_alert.1123061225 Aug 05 05:13:07 PM PDT 24 Aug 05 05:13:08 PM PDT 24 8802062 ps
T10 /workspace/coverage/sync_alert/10.prim_sync_alert.516538055 Aug 05 05:13:08 PM PDT 24 Aug 05 05:13:08 PM PDT 24 8487199 ps
T21 /workspace/coverage/sync_alert/1.prim_sync_alert.1363090708 Aug 05 05:13:06 PM PDT 24 Aug 05 05:13:07 PM PDT 24 9269268 ps
T30 /workspace/coverage/sync_alert/16.prim_sync_alert.4126186726 Aug 05 05:13:16 PM PDT 24 Aug 05 05:13:16 PM PDT 24 9807378 ps
T22 /workspace/coverage/sync_alert/9.prim_sync_alert.1115525004 Aug 05 05:13:07 PM PDT 24 Aug 05 05:13:08 PM PDT 24 9797061 ps
T23 /workspace/coverage/sync_alert/14.prim_sync_alert.168130642 Aug 05 05:13:12 PM PDT 24 Aug 05 05:13:12 PM PDT 24 8941356 ps
T24 /workspace/coverage/sync_alert/19.prim_sync_alert.803717671 Aug 05 05:13:11 PM PDT 24 Aug 05 05:13:11 PM PDT 24 10382392 ps
T31 /workspace/coverage/sync_alert/18.prim_sync_alert.2267977381 Aug 05 05:13:17 PM PDT 24 Aug 05 05:13:17 PM PDT 24 10213573 ps
T32 /workspace/coverage/sync_alert/6.prim_sync_alert.3873722752 Aug 05 05:13:09 PM PDT 24 Aug 05 05:13:10 PM PDT 24 8682984 ps
T33 /workspace/coverage/sync_alert/17.prim_sync_alert.2842416211 Aug 05 05:13:10 PM PDT 24 Aug 05 05:13:10 PM PDT 24 10045668 ps
T57 /workspace/coverage/sync_alert/13.prim_sync_alert.3377495000 Aug 05 05:13:13 PM PDT 24 Aug 05 05:13:14 PM PDT 24 9441350 ps
T11 /workspace/coverage/sync_alert/12.prim_sync_alert.2651111222 Aug 05 05:13:08 PM PDT 24 Aug 05 05:13:08 PM PDT 24 9832488 ps
T58 /workspace/coverage/sync_alert/5.prim_sync_alert.1990552547 Aug 05 05:13:08 PM PDT 24 Aug 05 05:13:09 PM PDT 24 9316049 ps
T59 /workspace/coverage/sync_alert/3.prim_sync_alert.4192964187 Aug 05 05:13:10 PM PDT 24 Aug 05 05:13:10 PM PDT 24 9341655 ps
T25 /workspace/coverage/sync_alert/15.prim_sync_alert.415296158 Aug 05 05:13:14 PM PDT 24 Aug 05 05:13:14 PM PDT 24 8731947 ps
T26 /workspace/coverage/sync_alert/0.prim_sync_alert.1316730926 Aug 05 05:13:08 PM PDT 24 Aug 05 05:13:08 PM PDT 24 8791333 ps
T27 /workspace/coverage/sync_alert/11.prim_sync_alert.2676729233 Aug 05 05:13:08 PM PDT 24 Aug 05 05:13:08 PM PDT 24 9442765 ps
T60 /workspace/coverage/sync_alert/4.prim_sync_alert.2369177547 Aug 05 05:13:09 PM PDT 24 Aug 05 05:13:10 PM PDT 24 9714334 ps
T28 /workspace/coverage/sync_alert/8.prim_sync_alert.1555323421 Aug 05 05:13:04 PM PDT 24 Aug 05 05:13:05 PM PDT 24 8347794 ps
T61 /workspace/coverage/sync_alert/2.prim_sync_alert.2549436318 Aug 05 05:13:10 PM PDT 24 Aug 05 05:13:10 PM PDT 24 8821867 ps
T4 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3813752283 Aug 05 05:25:43 PM PDT 24 Aug 05 05:25:44 PM PDT 24 27611855 ps
T62 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1710622495 Aug 05 05:25:43 PM PDT 24 Aug 05 05:25:44 PM PDT 24 25104720 ps
T63 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1215545387 Aug 05 05:25:44 PM PDT 24 Aug 05 05:25:44 PM PDT 24 26119584 ps
T64 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2241060386 Aug 05 05:25:40 PM PDT 24 Aug 05 05:25:40 PM PDT 24 28147541 ps
T5 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2643941724 Aug 05 05:25:42 PM PDT 24 Aug 05 05:25:42 PM PDT 24 27911202 ps
T65 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3522520281 Aug 05 05:25:43 PM PDT 24 Aug 05 05:25:43 PM PDT 24 27771169 ps
T66 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1861546226 Aug 05 05:25:46 PM PDT 24 Aug 05 05:25:47 PM PDT 24 26249400 ps
T67 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2295885597 Aug 05 05:25:43 PM PDT 24 Aug 05 05:25:44 PM PDT 24 27004524 ps
T68 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2787539753 Aug 05 05:25:46 PM PDT 24 Aug 05 05:25:46 PM PDT 24 26518270 ps
T69 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3788285277 Aug 05 05:25:41 PM PDT 24 Aug 05 05:25:42 PM PDT 24 30113413 ps
T12 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3730940943 Aug 05 05:25:42 PM PDT 24 Aug 05 05:25:42 PM PDT 24 26748527 ps
T70 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2590060245 Aug 05 05:25:42 PM PDT 24 Aug 05 05:25:42 PM PDT 24 27394764 ps
T71 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.499496532 Aug 05 05:25:42 PM PDT 24 Aug 05 05:25:42 PM PDT 24 29244264 ps
T72 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3590615333 Aug 05 05:25:40 PM PDT 24 Aug 05 05:25:41 PM PDT 24 26384700 ps
T73 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.722032692 Aug 05 05:25:44 PM PDT 24 Aug 05 05:25:45 PM PDT 24 27402310 ps
T74 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3441733018 Aug 05 05:25:42 PM PDT 24 Aug 05 05:25:43 PM PDT 24 26558710 ps
T75 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2883076900 Aug 05 05:25:43 PM PDT 24 Aug 05 05:25:44 PM PDT 24 26683309 ps
T76 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.535747145 Aug 05 05:25:46 PM PDT 24 Aug 05 05:25:47 PM PDT 24 27351422 ps
T77 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2395470599 Aug 05 05:25:47 PM PDT 24 Aug 05 05:25:47 PM PDT 24 27113729 ps
T78 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3751514242 Aug 05 05:25:43 PM PDT 24 Aug 05 05:25:43 PM PDT 24 25382091 ps

Test location /workspace/coverage/default/6.prim_async_alert.3623544616
Short name T2
Test name
Test status
Simulation time 12811635 ps
CPU time 0.44 seconds
Started Aug 05 05:08:40 PM PDT 24
Finished Aug 05 05:08:41 PM PDT 24
Peak memory 145784 kb
Host smart-b861014e-689f-4291-a499-e53e08d121e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623544616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3623544616
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.516538055
Short name T10
Test name
Test status
Simulation time 8487199 ps
CPU time 0.38 seconds
Started Aug 05 05:13:08 PM PDT 24
Finished Aug 05 05:13:08 PM PDT 24
Peak memory 145556 kb
Host smart-94a7ab15-5cf1-4381-b41e-811788d24b0a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=516538055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.516538055
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1246705025
Short name T35
Test name
Test status
Simulation time 29081347 ps
CPU time 0.39 seconds
Started Aug 05 04:23:18 PM PDT 24
Finished Aug 05 04:23:18 PM PDT 24
Peak memory 145152 kb
Host smart-bffce8c8-7619-49d1-834c-a63b13cfbb62
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1246705025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1246705025
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3768253275
Short name T17
Test name
Test status
Simulation time 10555276 ps
CPU time 0.39 seconds
Started Aug 05 05:08:42 PM PDT 24
Finished Aug 05 05:08:43 PM PDT 24
Peak memory 145732 kb
Host smart-d9916241-6078-4aa7-a5c9-10779c8ddbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768253275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3768253275
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2643941724
Short name T5
Test name
Test status
Simulation time 27911202 ps
CPU time 0.4 seconds
Started Aug 05 05:25:42 PM PDT 24
Finished Aug 05 05:25:42 PM PDT 24
Peak memory 145520 kb
Host smart-1ec16b4a-86c1-4d65-889c-2211975bbf15
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2643941724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2643941724
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.4215692335
Short name T6
Test name
Test status
Simulation time 10890821 ps
CPU time 0.38 seconds
Started Aug 05 05:08:50 PM PDT 24
Finished Aug 05 05:08:51 PM PDT 24
Peak memory 145648 kb
Host smart-07e1a215-55c7-44ac-bb03-fea569d2ee71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215692335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.4215692335
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.154088878
Short name T13
Test name
Test status
Simulation time 11843759 ps
CPU time 0.43 seconds
Started Aug 05 05:08:38 PM PDT 24
Finished Aug 05 05:08:38 PM PDT 24
Peak memory 145696 kb
Host smart-2a7683c3-968a-4745-b339-7175f5312c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154088878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.154088878
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2784091760
Short name T48
Test name
Test status
Simulation time 10758162 ps
CPU time 0.38 seconds
Started Aug 05 05:08:45 PM PDT 24
Finished Aug 05 05:08:45 PM PDT 24
Peak memory 145696 kb
Host smart-c204b784-d6e6-48ef-b3f4-2362a86ac2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784091760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2784091760
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.3607890141
Short name T46
Test name
Test status
Simulation time 11874647 ps
CPU time 0.39 seconds
Started Aug 05 05:08:40 PM PDT 24
Finished Aug 05 05:08:41 PM PDT 24
Peak memory 145728 kb
Host smart-8e2b0a4c-f0d3-46b5-a67c-ff39e70b4705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607890141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3607890141
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3591037873
Short name T45
Test name
Test status
Simulation time 11899524 ps
CPU time 0.4 seconds
Started Aug 05 05:08:53 PM PDT 24
Finished Aug 05 05:08:54 PM PDT 24
Peak memory 145784 kb
Host smart-bab5b03a-4402-4f83-ac86-6c4e39ea3f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591037873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3591037873
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2429669188
Short name T3
Test name
Test status
Simulation time 11012444 ps
CPU time 0.4 seconds
Started Aug 05 05:08:54 PM PDT 24
Finished Aug 05 05:08:54 PM PDT 24
Peak memory 145796 kb
Host smart-fbf1c8b0-0c8d-4f1f-bfa8-57af6dc95d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429669188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2429669188
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.76389209
Short name T44
Test name
Test status
Simulation time 11408545 ps
CPU time 0.42 seconds
Started Aug 05 05:08:51 PM PDT 24
Finished Aug 05 05:08:51 PM PDT 24
Peak memory 145652 kb
Host smart-2f355186-0df2-4640-8d07-7a8c907a1267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76389209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.76389209
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.4109244677
Short name T9
Test name
Test status
Simulation time 12462339 ps
CPU time 0.38 seconds
Started Aug 05 05:08:44 PM PDT 24
Finished Aug 05 05:08:44 PM PDT 24
Peak memory 145792 kb
Host smart-2f2ada37-1fd9-494d-8af1-318e07ff3f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109244677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.4109244677
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1039502987
Short name T18
Test name
Test status
Simulation time 11853226 ps
CPU time 0.39 seconds
Started Aug 05 05:08:53 PM PDT 24
Finished Aug 05 05:08:54 PM PDT 24
Peak memory 145792 kb
Host smart-bab7deaa-853a-4b75-abe9-22f77dfc6196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039502987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1039502987
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.784456460
Short name T47
Test name
Test status
Simulation time 11282425 ps
CPU time 0.38 seconds
Started Aug 05 05:08:45 PM PDT 24
Finished Aug 05 05:08:46 PM PDT 24
Peak memory 145704 kb
Host smart-aa1997cc-3f9f-4287-8386-0516f6e53a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784456460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.784456460
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2897847704
Short name T1
Test name
Test status
Simulation time 10772435 ps
CPU time 0.38 seconds
Started Aug 05 05:09:03 PM PDT 24
Finished Aug 05 05:09:04 PM PDT 24
Peak memory 145676 kb
Host smart-b4fb4554-d576-424c-bb49-ed5497ff2ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897847704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2897847704
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.514431294
Short name T19
Test name
Test status
Simulation time 10278727 ps
CPU time 0.39 seconds
Started Aug 05 05:08:40 PM PDT 24
Finished Aug 05 05:08:40 PM PDT 24
Peak memory 145788 kb
Host smart-e1f1da2d-0fca-40ce-99d5-eb669c42ddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514431294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.514431294
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3270050444
Short name T16
Test name
Test status
Simulation time 11421877 ps
CPU time 0.38 seconds
Started Aug 05 05:08:50 PM PDT 24
Finished Aug 05 05:08:50 PM PDT 24
Peak memory 145648 kb
Host smart-59b0df80-7389-4226-b81d-8eb9984df9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270050444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3270050444
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3006091596
Short name T7
Test name
Test status
Simulation time 12215972 ps
CPU time 0.39 seconds
Started Aug 05 05:08:42 PM PDT 24
Finished Aug 05 05:08:42 PM PDT 24
Peak memory 145796 kb
Host smart-79a25ccb-875e-4145-a80a-52ad9e99c0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006091596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3006091596
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3682264725
Short name T14
Test name
Test status
Simulation time 11436448 ps
CPU time 0.38 seconds
Started Aug 05 05:08:45 PM PDT 24
Finished Aug 05 05:08:45 PM PDT 24
Peak memory 145788 kb
Host smart-d5291f21-0edf-419b-bfee-9dec82d2ca90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682264725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3682264725
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3447117510
Short name T8
Test name
Test status
Simulation time 11164967 ps
CPU time 0.41 seconds
Started Aug 05 05:08:40 PM PDT 24
Finished Aug 05 05:08:40 PM PDT 24
Peak memory 145728 kb
Host smart-e1c571fe-ad71-4f6d-9495-98c4bbac9734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447117510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3447117510
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.29287810
Short name T20
Test name
Test status
Simulation time 11147063 ps
CPU time 0.42 seconds
Started Aug 05 05:08:51 PM PDT 24
Finished Aug 05 05:08:51 PM PDT 24
Peak memory 145656 kb
Host smart-cda37725-da03-497c-bb25-b683bc578b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29287810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.29287810
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1700884925
Short name T43
Test name
Test status
Simulation time 11659544 ps
CPU time 0.38 seconds
Started Aug 05 05:08:38 PM PDT 24
Finished Aug 05 05:08:39 PM PDT 24
Peak memory 145768 kb
Host smart-1a89cdbc-856b-4b11-96c6-c627f2c75f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700884925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1700884925
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1994783521
Short name T15
Test name
Test status
Simulation time 31954516 ps
CPU time 0.38 seconds
Started Aug 05 04:24:42 PM PDT 24
Finished Aug 05 04:24:42 PM PDT 24
Peak memory 145180 kb
Host smart-c7075392-624e-4024-b54e-c9389fb66fab
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1994783521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1994783521
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3041314029
Short name T50
Test name
Test status
Simulation time 30037578 ps
CPU time 0.41 seconds
Started Aug 05 04:23:41 PM PDT 24
Finished Aug 05 04:23:41 PM PDT 24
Peak memory 145200 kb
Host smart-e7882574-432b-4b77-ac79-d21074bcd1f8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3041314029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3041314029
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3977329103
Short name T37
Test name
Test status
Simulation time 31611113 ps
CPU time 0.42 seconds
Started Aug 05 04:23:24 PM PDT 24
Finished Aug 05 04:23:24 PM PDT 24
Peak memory 145128 kb
Host smart-c4935c25-9c33-4970-9ff2-500b71dfc534
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3977329103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3977329103
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2463755565
Short name T55
Test name
Test status
Simulation time 29444076 ps
CPU time 0.39 seconds
Started Aug 05 04:23:15 PM PDT 24
Finished Aug 05 04:23:15 PM PDT 24
Peak memory 145164 kb
Host smart-dcbfd256-8146-4e90-831e-24fe7f30dd5f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2463755565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2463755565
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2366861194
Short name T56
Test name
Test status
Simulation time 29986769 ps
CPU time 0.4 seconds
Started Aug 05 04:24:29 PM PDT 24
Finished Aug 05 04:24:29 PM PDT 24
Peak memory 145116 kb
Host smart-b74c6374-3bea-4681-80f0-7320774c5cd0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2366861194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2366861194
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2245142769
Short name T39
Test name
Test status
Simulation time 30441981 ps
CPU time 0.39 seconds
Started Aug 05 04:23:35 PM PDT 24
Finished Aug 05 04:23:36 PM PDT 24
Peak memory 145156 kb
Host smart-5b156ddf-92df-415a-9a94-bf934fa2369a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2245142769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2245142769
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.356145336
Short name T34
Test name
Test status
Simulation time 28463830 ps
CPU time 0.41 seconds
Started Aug 05 04:23:26 PM PDT 24
Finished Aug 05 04:23:27 PM PDT 24
Peak memory 145132 kb
Host smart-580f5254-219f-42d7-b691-747207ccccec
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=356145336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.356145336
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.886128847
Short name T51
Test name
Test status
Simulation time 29685515 ps
CPU time 0.38 seconds
Started Aug 05 04:23:33 PM PDT 24
Finished Aug 05 04:23:34 PM PDT 24
Peak memory 145180 kb
Host smart-36b3407a-26cb-41b1-8bf4-982880657a5a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=886128847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.886128847
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1094615868
Short name T42
Test name
Test status
Simulation time 31424472 ps
CPU time 0.39 seconds
Started Aug 05 04:24:40 PM PDT 24
Finished Aug 05 04:24:40 PM PDT 24
Peak memory 145056 kb
Host smart-a6948824-bd42-4539-8726-3ddb220cae62
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1094615868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1094615868
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4211290864
Short name T52
Test name
Test status
Simulation time 30183871 ps
CPU time 0.4 seconds
Started Aug 05 04:23:16 PM PDT 24
Finished Aug 05 04:23:16 PM PDT 24
Peak memory 145104 kb
Host smart-3bf112f2-df7c-4622-8546-0e15b1ee6161
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4211290864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4211290864
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3043785678
Short name T40
Test name
Test status
Simulation time 30040947 ps
CPU time 0.4 seconds
Started Aug 05 04:23:31 PM PDT 24
Finished Aug 05 04:23:32 PM PDT 24
Peak memory 145196 kb
Host smart-64d44abe-6816-4848-b6de-47b4070cf7f5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3043785678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3043785678
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2045407471
Short name T49
Test name
Test status
Simulation time 31099995 ps
CPU time 0.38 seconds
Started Aug 05 04:24:57 PM PDT 24
Finished Aug 05 04:24:58 PM PDT 24
Peak memory 145200 kb
Host smart-ff44e3d0-b6b3-4b4f-9cf2-4dd9273bf361
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2045407471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2045407471
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3565294374
Short name T41
Test name
Test status
Simulation time 31207761 ps
CPU time 0.41 seconds
Started Aug 05 04:23:36 PM PDT 24
Finished Aug 05 04:23:37 PM PDT 24
Peak memory 145172 kb
Host smart-f5715799-a7fe-4e89-9f63-6822b47db3b3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3565294374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3565294374
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3173397980
Short name T36
Test name
Test status
Simulation time 30804991 ps
CPU time 0.4 seconds
Started Aug 05 04:23:09 PM PDT 24
Finished Aug 05 04:23:09 PM PDT 24
Peak memory 145124 kb
Host smart-869b503b-8618-4b5a-afdc-9befdeff23eb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3173397980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3173397980
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.900301457
Short name T54
Test name
Test status
Simulation time 29824970 ps
CPU time 0.4 seconds
Started Aug 05 04:23:34 PM PDT 24
Finished Aug 05 04:23:35 PM PDT 24
Peak memory 145200 kb
Host smart-2cd80b9c-6931-4d40-982b-de6ad174b90b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=900301457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.900301457
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.260628991
Short name T53
Test name
Test status
Simulation time 28492430 ps
CPU time 0.43 seconds
Started Aug 05 04:23:15 PM PDT 24
Finished Aug 05 04:23:16 PM PDT 24
Peak memory 144856 kb
Host smart-9bebfb95-5e7c-43bf-a147-b4391fd29f5f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=260628991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.260628991
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1993485583
Short name T38
Test name
Test status
Simulation time 29918290 ps
CPU time 0.4 seconds
Started Aug 05 04:23:21 PM PDT 24
Finished Aug 05 04:23:21 PM PDT 24
Peak memory 145004 kb
Host smart-9ce830bb-d5a3-451b-92b1-60e37dead558
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1993485583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1993485583
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1316730926
Short name T26
Test name
Test status
Simulation time 8791333 ps
CPU time 0.39 seconds
Started Aug 05 05:13:08 PM PDT 24
Finished Aug 05 05:13:08 PM PDT 24
Peak memory 145596 kb
Host smart-11acbe22-aa03-4f99-a34b-d61ee061e335
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1316730926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1316730926
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1363090708
Short name T21
Test name
Test status
Simulation time 9269268 ps
CPU time 0.39 seconds
Started Aug 05 05:13:06 PM PDT 24
Finished Aug 05 05:13:07 PM PDT 24
Peak memory 145604 kb
Host smart-8c568579-fd84-4423-960b-bc3e4342d8f1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1363090708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1363090708
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2676729233
Short name T27
Test name
Test status
Simulation time 9442765 ps
CPU time 0.37 seconds
Started Aug 05 05:13:08 PM PDT 24
Finished Aug 05 05:13:08 PM PDT 24
Peak memory 145472 kb
Host smart-44ba497b-aaeb-4bcd-a2b3-d044e5dde8cf
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2676729233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2676729233
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2651111222
Short name T11
Test name
Test status
Simulation time 9832488 ps
CPU time 0.4 seconds
Started Aug 05 05:13:08 PM PDT 24
Finished Aug 05 05:13:08 PM PDT 24
Peak memory 145496 kb
Host smart-9a563e1e-5ce5-4572-b8ae-2cd2c1b93ebd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2651111222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2651111222
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3377495000
Short name T57
Test name
Test status
Simulation time 9441350 ps
CPU time 0.38 seconds
Started Aug 05 05:13:13 PM PDT 24
Finished Aug 05 05:13:14 PM PDT 24
Peak memory 145600 kb
Host smart-da984226-23cc-4d83-b7b9-79e2f4d8f3da
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3377495000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3377495000
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.168130642
Short name T23
Test name
Test status
Simulation time 8941356 ps
CPU time 0.38 seconds
Started Aug 05 05:13:12 PM PDT 24
Finished Aug 05 05:13:12 PM PDT 24
Peak memory 145564 kb
Host smart-09a4ff77-52ac-4894-ab60-09913ce01ab8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=168130642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.168130642
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.415296158
Short name T25
Test name
Test status
Simulation time 8731947 ps
CPU time 0.39 seconds
Started Aug 05 05:13:14 PM PDT 24
Finished Aug 05 05:13:14 PM PDT 24
Peak memory 145580 kb
Host smart-27921e59-e91c-4fe0-bc87-c08c16bc8454
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=415296158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.415296158
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.4126186726
Short name T30
Test name
Test status
Simulation time 9807378 ps
CPU time 0.37 seconds
Started Aug 05 05:13:16 PM PDT 24
Finished Aug 05 05:13:16 PM PDT 24
Peak memory 145572 kb
Host smart-3d0cf6f1-48e8-4a4a-b122-9521d37cea43
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4126186726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.4126186726
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2842416211
Short name T33
Test name
Test status
Simulation time 10045668 ps
CPU time 0.45 seconds
Started Aug 05 05:13:10 PM PDT 24
Finished Aug 05 05:13:10 PM PDT 24
Peak memory 145444 kb
Host smart-ecfd16d4-e7bc-4e5c-9c8f-b42872640cde
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2842416211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2842416211
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2267977381
Short name T31
Test name
Test status
Simulation time 10213573 ps
CPU time 0.38 seconds
Started Aug 05 05:13:17 PM PDT 24
Finished Aug 05 05:13:17 PM PDT 24
Peak memory 145572 kb
Host smart-13f88f04-3132-4127-9f7c-893f1007a7ab
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2267977381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2267977381
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.803717671
Short name T24
Test name
Test status
Simulation time 10382392 ps
CPU time 0.39 seconds
Started Aug 05 05:13:11 PM PDT 24
Finished Aug 05 05:13:11 PM PDT 24
Peak memory 145524 kb
Host smart-b4bec210-3003-49d4-a906-4fd5bf63559d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=803717671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.803717671
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2549436318
Short name T61
Test name
Test status
Simulation time 8821867 ps
CPU time 0.37 seconds
Started Aug 05 05:13:10 PM PDT 24
Finished Aug 05 05:13:10 PM PDT 24
Peak memory 145580 kb
Host smart-fe638c0f-35f8-4ca3-8261-0d57ba12e7b8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2549436318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2549436318
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.4192964187
Short name T59
Test name
Test status
Simulation time 9341655 ps
CPU time 0.4 seconds
Started Aug 05 05:13:10 PM PDT 24
Finished Aug 05 05:13:10 PM PDT 24
Peak memory 145580 kb
Host smart-069e1524-f666-4d93-9002-c5095d149aaa
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4192964187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.4192964187
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2369177547
Short name T60
Test name
Test status
Simulation time 9714334 ps
CPU time 0.42 seconds
Started Aug 05 05:13:09 PM PDT 24
Finished Aug 05 05:13:10 PM PDT 24
Peak memory 145536 kb
Host smart-3568a93c-8c53-45bc-ae80-d554a41b9926
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2369177547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2369177547
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1990552547
Short name T58
Test name
Test status
Simulation time 9316049 ps
CPU time 0.39 seconds
Started Aug 05 05:13:08 PM PDT 24
Finished Aug 05 05:13:09 PM PDT 24
Peak memory 145596 kb
Host smart-3d31c07b-9789-4ee5-8dae-27bd28ef95fb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1990552547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1990552547
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3873722752
Short name T32
Test name
Test status
Simulation time 8682984 ps
CPU time 0.42 seconds
Started Aug 05 05:13:09 PM PDT 24
Finished Aug 05 05:13:10 PM PDT 24
Peak memory 145536 kb
Host smart-4445fe55-a9af-44b2-abca-975f79c67c09
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3873722752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3873722752
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1123061225
Short name T29
Test name
Test status
Simulation time 8802062 ps
CPU time 0.38 seconds
Started Aug 05 05:13:07 PM PDT 24
Finished Aug 05 05:13:08 PM PDT 24
Peak memory 145540 kb
Host smart-8adb671e-d9fa-4d8d-a4ce-ab5c3acd12ce
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1123061225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1123061225
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1555323421
Short name T28
Test name
Test status
Simulation time 8347794 ps
CPU time 0.38 seconds
Started Aug 05 05:13:04 PM PDT 24
Finished Aug 05 05:13:05 PM PDT 24
Peak memory 145484 kb
Host smart-85785f8b-51df-4bea-83c9-72fcf0f47519
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1555323421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1555323421
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1115525004
Short name T22
Test name
Test status
Simulation time 9797061 ps
CPU time 0.38 seconds
Started Aug 05 05:13:07 PM PDT 24
Finished Aug 05 05:13:08 PM PDT 24
Peak memory 145472 kb
Host smart-56ccc2b5-0b1a-4627-abc3-d5aa88cdc7f0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1115525004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1115525004
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2295885597
Short name T67
Test name
Test status
Simulation time 27004524 ps
CPU time 0.46 seconds
Started Aug 05 05:25:43 PM PDT 24
Finished Aug 05 05:25:44 PM PDT 24
Peak memory 145560 kb
Host smart-cb5580f8-d9c4-45af-bcda-f5891664c9ac
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2295885597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2295885597
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3730940943
Short name T12
Test name
Test status
Simulation time 26748527 ps
CPU time 0.39 seconds
Started Aug 05 05:25:42 PM PDT 24
Finished Aug 05 05:25:42 PM PDT 24
Peak memory 145500 kb
Host smart-97cbf789-de88-4716-a533-58bb58503c86
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3730940943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3730940943
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1215545387
Short name T63
Test name
Test status
Simulation time 26119584 ps
CPU time 0.4 seconds
Started Aug 05 05:25:44 PM PDT 24
Finished Aug 05 05:25:44 PM PDT 24
Peak memory 145596 kb
Host smart-64873554-fb4a-4dcd-8870-3a729f6c1560
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1215545387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1215545387
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3522520281
Short name T65
Test name
Test status
Simulation time 27771169 ps
CPU time 0.41 seconds
Started Aug 05 05:25:43 PM PDT 24
Finished Aug 05 05:25:43 PM PDT 24
Peak memory 145580 kb
Host smart-bd005a03-6cd8-4090-a732-28a98247b100
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3522520281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3522520281
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1861546226
Short name T66
Test name
Test status
Simulation time 26249400 ps
CPU time 0.38 seconds
Started Aug 05 05:25:46 PM PDT 24
Finished Aug 05 05:25:47 PM PDT 24
Peak memory 145592 kb
Host smart-e1e86adc-5b7b-421a-9c81-52fa7b805be5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1861546226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1861546226
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2883076900
Short name T75
Test name
Test status
Simulation time 26683309 ps
CPU time 0.4 seconds
Started Aug 05 05:25:43 PM PDT 24
Finished Aug 05 05:25:44 PM PDT 24
Peak memory 145488 kb
Host smart-98681714-72bb-4e25-bb3f-6a891501edf0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2883076900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2883076900
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2241060386
Short name T64
Test name
Test status
Simulation time 28147541 ps
CPU time 0.4 seconds
Started Aug 05 05:25:40 PM PDT 24
Finished Aug 05 05:25:40 PM PDT 24
Peak memory 145616 kb
Host smart-28d9af7c-b29c-4e34-b35c-a2eb64d1de84
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2241060386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2241060386
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3788285277
Short name T69
Test name
Test status
Simulation time 30113413 ps
CPU time 0.45 seconds
Started Aug 05 05:25:41 PM PDT 24
Finished Aug 05 05:25:42 PM PDT 24
Peak memory 145564 kb
Host smart-4300607b-8bfe-4cee-aa18-27358451da19
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3788285277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3788285277
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3441733018
Short name T74
Test name
Test status
Simulation time 26558710 ps
CPU time 0.42 seconds
Started Aug 05 05:25:42 PM PDT 24
Finished Aug 05 05:25:43 PM PDT 24
Peak memory 145592 kb
Host smart-12889df1-4224-4f2f-bdf0-e97d5996c8c9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3441733018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3441733018
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2787539753
Short name T68
Test name
Test status
Simulation time 26518270 ps
CPU time 0.42 seconds
Started Aug 05 05:25:46 PM PDT 24
Finished Aug 05 05:25:46 PM PDT 24
Peak memory 145700 kb
Host smart-9b52374c-48dd-424e-a383-e29e42b8e114
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2787539753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2787539753
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.535747145
Short name T76
Test name
Test status
Simulation time 27351422 ps
CPU time 0.4 seconds
Started Aug 05 05:25:46 PM PDT 24
Finished Aug 05 05:25:47 PM PDT 24
Peak memory 145588 kb
Host smart-10fa675b-f937-467c-a78d-515e88b33be2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=535747145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.535747145
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3813752283
Short name T4
Test name
Test status
Simulation time 27611855 ps
CPU time 0.41 seconds
Started Aug 05 05:25:43 PM PDT 24
Finished Aug 05 05:25:44 PM PDT 24
Peak memory 145604 kb
Host smart-65b37998-f10c-41bf-b892-87f63f90e894
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3813752283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3813752283
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3590615333
Short name T72
Test name
Test status
Simulation time 26384700 ps
CPU time 0.39 seconds
Started Aug 05 05:25:40 PM PDT 24
Finished Aug 05 05:25:41 PM PDT 24
Peak memory 145568 kb
Host smart-20b8e3bd-1e17-4d9b-b254-2e2f2d3cebeb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3590615333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3590615333
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.499496532
Short name T71
Test name
Test status
Simulation time 29244264 ps
CPU time 0.41 seconds
Started Aug 05 05:25:42 PM PDT 24
Finished Aug 05 05:25:42 PM PDT 24
Peak memory 145600 kb
Host smart-46817709-481b-4c10-b135-58986eb88803
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=499496532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.499496532
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.722032692
Short name T73
Test name
Test status
Simulation time 27402310 ps
CPU time 0.43 seconds
Started Aug 05 05:25:44 PM PDT 24
Finished Aug 05 05:25:45 PM PDT 24
Peak memory 145496 kb
Host smart-4dda58f3-e98e-4b2a-a94a-3b9aa1ca7355
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=722032692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.722032692
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3751514242
Short name T78
Test name
Test status
Simulation time 25382091 ps
CPU time 0.4 seconds
Started Aug 05 05:25:43 PM PDT 24
Finished Aug 05 05:25:43 PM PDT 24
Peak memory 145584 kb
Host smart-1652832a-7a67-4197-b22e-a769555e942e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3751514242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3751514242
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2590060245
Short name T70
Test name
Test status
Simulation time 27394764 ps
CPU time 0.41 seconds
Started Aug 05 05:25:42 PM PDT 24
Finished Aug 05 05:25:42 PM PDT 24
Peak memory 145608 kb
Host smart-4156909b-7ca8-4a3f-964d-cb5141721576
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2590060245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2590060245
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1710622495
Short name T62
Test name
Test status
Simulation time 25104720 ps
CPU time 0.39 seconds
Started Aug 05 05:25:43 PM PDT 24
Finished Aug 05 05:25:44 PM PDT 24
Peak memory 145484 kb
Host smart-8b390fbc-6163-473e-9b3d-92ba8ac7be65
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1710622495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1710622495
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2395470599
Short name T77
Test name
Test status
Simulation time 27113729 ps
CPU time 0.39 seconds
Started Aug 05 05:25:47 PM PDT 24
Finished Aug 05 05:25:47 PM PDT 24
Peak memory 145688 kb
Host smart-4f3d5384-526d-405d-944b-b88b4fd90269
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2395470599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2395470599
Directory /workspace/9.prim_sync_fatal_alert/latest
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