Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 77
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.42 88.42 100.00 100.00 95.83 95.83 96.43 96.43 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/12.prim_async_alert.2701908898
91.55 3.13 100.00 0.00 95.83 0.00 96.43 0.00 82.14 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/0.prim_sync_alert.295515516
93.31 1.76 100.00 0.00 95.83 0.00 100.00 3.57 82.14 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.414943728
94.50 1.19 100.00 0.00 95.83 0.00 100.00 0.00 89.29 7.14 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4197912129
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2457713765
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/6.prim_sync_alert.2992055754

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2478136678
/workspace/coverage/default/1.prim_async_alert.4006173841
/workspace/coverage/default/10.prim_async_alert.2827711103
/workspace/coverage/default/11.prim_async_alert.3294857785
/workspace/coverage/default/13.prim_async_alert.4027873613
/workspace/coverage/default/14.prim_async_alert.2116568877
/workspace/coverage/default/15.prim_async_alert.2542545475
/workspace/coverage/default/16.prim_async_alert.3584596764
/workspace/coverage/default/17.prim_async_alert.4202352092
/workspace/coverage/default/18.prim_async_alert.3123504098
/workspace/coverage/default/19.prim_async_alert.438672630
/workspace/coverage/default/3.prim_async_alert.1454768273
/workspace/coverage/default/4.prim_async_alert.2032500147
/workspace/coverage/default/5.prim_async_alert.3326295308
/workspace/coverage/default/6.prim_async_alert.1360616460
/workspace/coverage/default/7.prim_async_alert.224662450
/workspace/coverage/default/8.prim_async_alert.240445249
/workspace/coverage/default/9.prim_async_alert.2448855985
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2850388986
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1674276884
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2336292625
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1023803612
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.555068033
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4236805591
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2025533669
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2198095564
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1271059425
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3588314197
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1918698477
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3465366809
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3581808577
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3398687810
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.998557591
/workspace/coverage/sync_alert/1.prim_sync_alert.347216148
/workspace/coverage/sync_alert/10.prim_sync_alert.1239185539
/workspace/coverage/sync_alert/11.prim_sync_alert.4052831131
/workspace/coverage/sync_alert/12.prim_sync_alert.3161562879
/workspace/coverage/sync_alert/13.prim_sync_alert.2160686545
/workspace/coverage/sync_alert/14.prim_sync_alert.1808330852
/workspace/coverage/sync_alert/15.prim_sync_alert.1352488837
/workspace/coverage/sync_alert/16.prim_sync_alert.1194873667
/workspace/coverage/sync_alert/17.prim_sync_alert.3075002711
/workspace/coverage/sync_alert/18.prim_sync_alert.4008583809
/workspace/coverage/sync_alert/19.prim_sync_alert.1199997727
/workspace/coverage/sync_alert/2.prim_sync_alert.3195342393
/workspace/coverage/sync_alert/3.prim_sync_alert.526771439
/workspace/coverage/sync_alert/4.prim_sync_alert.4163700244
/workspace/coverage/sync_alert/5.prim_sync_alert.3753709082
/workspace/coverage/sync_alert/7.prim_sync_alert.3891190401
/workspace/coverage/sync_alert/8.prim_sync_alert.2366519031
/workspace/coverage/sync_alert/9.prim_sync_alert.3463493179
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.38303910
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.725699771
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3517541660
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3925847044
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3311378569
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.41160278
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1726773914
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4231659487
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2292657300
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3245709286
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3929821189
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3914470864
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3200656851
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1525991351
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3326397617
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.316142391
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1251462733
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3155729672
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.359449
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3883238179



Total test records in report: 77
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.prim_async_alert.2478136678 Aug 06 06:38:01 PM PDT 24 Aug 06 06:38:01 PM PDT 24 11067261 ps
T2 /workspace/coverage/default/7.prim_async_alert.224662450 Aug 06 06:38:01 PM PDT 24 Aug 06 06:38:02 PM PDT 24 10875581 ps
T3 /workspace/coverage/default/9.prim_async_alert.2448855985 Aug 06 06:38:01 PM PDT 24 Aug 06 06:38:02 PM PDT 24 11697291 ps
T9 /workspace/coverage/default/10.prim_async_alert.2827711103 Aug 06 06:38:00 PM PDT 24 Aug 06 06:38:00 PM PDT 24 11341537 ps
T7 /workspace/coverage/default/12.prim_async_alert.2701908898 Aug 06 06:38:02 PM PDT 24 Aug 06 06:38:03 PM PDT 24 10800931 ps
T19 /workspace/coverage/default/18.prim_async_alert.3123504098 Aug 06 06:37:59 PM PDT 24 Aug 06 06:38:00 PM PDT 24 10739218 ps
T20 /workspace/coverage/default/16.prim_async_alert.3584596764 Aug 06 06:37:59 PM PDT 24 Aug 06 06:38:00 PM PDT 24 10940120 ps
T11 /workspace/coverage/default/6.prim_async_alert.1360616460 Aug 06 06:37:59 PM PDT 24 Aug 06 06:38:00 PM PDT 24 11773713 ps
T8 /workspace/coverage/default/13.prim_async_alert.4027873613 Aug 06 06:37:58 PM PDT 24 Aug 06 06:37:59 PM PDT 24 10917995 ps
T21 /workspace/coverage/default/5.prim_async_alert.3326295308 Aug 06 06:38:01 PM PDT 24 Aug 06 06:38:02 PM PDT 24 11218643 ps
T12 /workspace/coverage/default/8.prim_async_alert.240445249 Aug 06 06:38:02 PM PDT 24 Aug 06 06:38:02 PM PDT 24 11112522 ps
T46 /workspace/coverage/default/4.prim_async_alert.2032500147 Aug 06 06:38:03 PM PDT 24 Aug 06 06:38:04 PM PDT 24 11940023 ps
T22 /workspace/coverage/default/11.prim_async_alert.3294857785 Aug 06 06:38:00 PM PDT 24 Aug 06 06:38:00 PM PDT 24 11934305 ps
T23 /workspace/coverage/default/3.prim_async_alert.1454768273 Aug 06 06:38:02 PM PDT 24 Aug 06 06:38:03 PM PDT 24 12262708 ps
T24 /workspace/coverage/default/14.prim_async_alert.2116568877 Aug 06 06:37:58 PM PDT 24 Aug 06 06:37:59 PM PDT 24 10450945 ps
T47 /workspace/coverage/default/17.prim_async_alert.4202352092 Aug 06 06:38:00 PM PDT 24 Aug 06 06:38:00 PM PDT 24 10658524 ps
T15 /workspace/coverage/default/15.prim_async_alert.2542545475 Aug 06 06:38:02 PM PDT 24 Aug 06 06:38:03 PM PDT 24 12853880 ps
T48 /workspace/coverage/default/1.prim_async_alert.4006173841 Aug 06 06:38:00 PM PDT 24 Aug 06 06:38:00 PM PDT 24 10990369 ps
T49 /workspace/coverage/default/19.prim_async_alert.438672630 Aug 06 06:37:59 PM PDT 24 Aug 06 06:38:00 PM PDT 24 10724701 ps
T41 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1918698477 Aug 06 06:38:01 PM PDT 24 Aug 06 06:38:01 PM PDT 24 29635291 ps
T42 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.414943728 Aug 06 06:38:02 PM PDT 24 Aug 06 06:38:02 PM PDT 24 31193494 ps
T43 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.998557591 Aug 06 06:38:08 PM PDT 24 Aug 06 06:38:08 PM PDT 24 31597059 ps
T16 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3398687810 Aug 06 06:38:00 PM PDT 24 Aug 06 06:38:01 PM PDT 24 29180252 ps
T4 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3581808577 Aug 06 06:38:00 PM PDT 24 Aug 06 06:38:01 PM PDT 24 30212271 ps
T5 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2457713765 Aug 06 06:38:03 PM PDT 24 Aug 06 06:38:04 PM PDT 24 29915875 ps
T17 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.555068033 Aug 06 06:38:03 PM PDT 24 Aug 06 06:38:03 PM PDT 24 32884629 ps
T44 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4236805591 Aug 06 06:38:04 PM PDT 24 Aug 06 06:38:04 PM PDT 24 28539697 ps
T45 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2850388986 Aug 06 06:37:59 PM PDT 24 Aug 06 06:37:59 PM PDT 24 30969630 ps
T6 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1271059425 Aug 06 06:38:01 PM PDT 24 Aug 06 06:38:02 PM PDT 24 32448038 ps
T50 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3465366809 Aug 06 06:38:02 PM PDT 24 Aug 06 06:38:03 PM PDT 24 30224326 ps
T51 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3588314197 Aug 06 06:38:03 PM PDT 24 Aug 06 06:38:03 PM PDT 24 31117518 ps
T13 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4197912129 Aug 06 06:38:06 PM PDT 24 Aug 06 06:38:07 PM PDT 24 30763665 ps
T39 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2336292625 Aug 06 06:38:01 PM PDT 24 Aug 06 06:38:01 PM PDT 24 30268164 ps
T52 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2198095564 Aug 06 06:37:59 PM PDT 24 Aug 06 06:38:00 PM PDT 24 32520486 ps
T53 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1674276884 Aug 06 06:38:03 PM PDT 24 Aug 06 06:38:04 PM PDT 24 28718686 ps
T40 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2025533669 Aug 06 06:38:08 PM PDT 24 Aug 06 06:38:08 PM PDT 24 28983503 ps
T54 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1023803612 Aug 06 06:38:02 PM PDT 24 Aug 06 06:38:03 PM PDT 24 30158012 ps
T34 /workspace/coverage/sync_alert/14.prim_sync_alert.1808330852 Aug 06 06:48:56 PM PDT 24 Aug 06 06:48:57 PM PDT 24 8313025 ps
T25 /workspace/coverage/sync_alert/16.prim_sync_alert.1194873667 Aug 06 06:48:58 PM PDT 24 Aug 06 06:48:58 PM PDT 24 9072658 ps
T35 /workspace/coverage/sync_alert/17.prim_sync_alert.3075002711 Aug 06 06:48:59 PM PDT 24 Aug 06 06:49:00 PM PDT 24 8620290 ps
T26 /workspace/coverage/sync_alert/18.prim_sync_alert.4008583809 Aug 06 06:48:57 PM PDT 24 Aug 06 06:48:58 PM PDT 24 8840488 ps
T18 /workspace/coverage/sync_alert/13.prim_sync_alert.2160686545 Aug 06 06:49:00 PM PDT 24 Aug 06 06:49:01 PM PDT 24 9806744 ps
T27 /workspace/coverage/sync_alert/0.prim_sync_alert.295515516 Aug 06 06:48:58 PM PDT 24 Aug 06 06:48:59 PM PDT 24 9329936 ps
T36 /workspace/coverage/sync_alert/4.prim_sync_alert.4163700244 Aug 06 06:48:59 PM PDT 24 Aug 06 06:48:59 PM PDT 24 10276841 ps
T37 /workspace/coverage/sync_alert/12.prim_sync_alert.3161562879 Aug 06 06:48:58 PM PDT 24 Aug 06 06:48:59 PM PDT 24 9343262 ps
T38 /workspace/coverage/sync_alert/11.prim_sync_alert.4052831131 Aug 06 06:48:59 PM PDT 24 Aug 06 06:49:00 PM PDT 24 8927062 ps
T28 /workspace/coverage/sync_alert/9.prim_sync_alert.3463493179 Aug 06 06:48:59 PM PDT 24 Aug 06 06:48:59 PM PDT 24 9291621 ps
T29 /workspace/coverage/sync_alert/7.prim_sync_alert.3891190401 Aug 06 06:49:01 PM PDT 24 Aug 06 06:49:01 PM PDT 24 8958778 ps
T55 /workspace/coverage/sync_alert/8.prim_sync_alert.2366519031 Aug 06 06:48:57 PM PDT 24 Aug 06 06:48:57 PM PDT 24 9266306 ps
T56 /workspace/coverage/sync_alert/19.prim_sync_alert.1199997727 Aug 06 06:48:58 PM PDT 24 Aug 06 06:48:59 PM PDT 24 8347350 ps
T30 /workspace/coverage/sync_alert/10.prim_sync_alert.1239185539 Aug 06 06:49:01 PM PDT 24 Aug 06 06:49:01 PM PDT 24 8488439 ps
T10 /workspace/coverage/sync_alert/6.prim_sync_alert.2992055754 Aug 06 06:49:00 PM PDT 24 Aug 06 06:49:00 PM PDT 24 8129583 ps
T31 /workspace/coverage/sync_alert/15.prim_sync_alert.1352488837 Aug 06 06:48:59 PM PDT 24 Aug 06 06:49:00 PM PDT 24 9756539 ps
T32 /workspace/coverage/sync_alert/2.prim_sync_alert.3195342393 Aug 06 06:49:00 PM PDT 24 Aug 06 06:49:00 PM PDT 24 9190200 ps
T33 /workspace/coverage/sync_alert/5.prim_sync_alert.3753709082 Aug 06 06:48:57 PM PDT 24 Aug 06 06:48:58 PM PDT 24 8896062 ps
T57 /workspace/coverage/sync_alert/1.prim_sync_alert.347216148 Aug 06 06:48:58 PM PDT 24 Aug 06 06:48:59 PM PDT 24 9241143 ps
T58 /workspace/coverage/sync_alert/3.prim_sync_alert.526771439 Aug 06 06:49:02 PM PDT 24 Aug 06 06:49:03 PM PDT 24 9634325 ps
T59 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3517541660 Aug 06 04:35:45 PM PDT 24 Aug 06 04:35:45 PM PDT 24 28611507 ps
T14 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3200656851 Aug 06 04:35:34 PM PDT 24 Aug 06 04:35:34 PM PDT 24 28959952 ps
T60 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3245709286 Aug 06 04:35:52 PM PDT 24 Aug 06 04:35:52 PM PDT 24 28906222 ps
T61 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.38303910 Aug 06 04:35:50 PM PDT 24 Aug 06 04:35:51 PM PDT 24 25782950 ps
T62 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2292657300 Aug 06 04:36:45 PM PDT 24 Aug 06 04:36:46 PM PDT 24 28546726 ps
T63 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3155729672 Aug 06 04:35:35 PM PDT 24 Aug 06 04:35:35 PM PDT 24 27069418 ps
T64 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3326397617 Aug 06 04:35:48 PM PDT 24 Aug 06 04:35:49 PM PDT 24 27316521 ps
T65 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3914470864 Aug 06 04:35:48 PM PDT 24 Aug 06 04:35:49 PM PDT 24 29895390 ps
T66 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3929821189 Aug 06 04:35:51 PM PDT 24 Aug 06 04:35:52 PM PDT 24 29557811 ps
T67 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3925847044 Aug 06 04:35:34 PM PDT 24 Aug 06 04:35:35 PM PDT 24 26829848 ps
T68 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1525991351 Aug 06 04:35:34 PM PDT 24 Aug 06 04:35:35 PM PDT 24 28534295 ps
T69 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1726773914 Aug 06 04:35:37 PM PDT 24 Aug 06 04:35:37 PM PDT 24 27010652 ps
T70 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3311378569 Aug 06 04:35:35 PM PDT 24 Aug 06 04:35:35 PM PDT 24 25822148 ps
T71 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4231659487 Aug 06 04:35:35 PM PDT 24 Aug 06 04:35:35 PM PDT 24 26863528 ps
T72 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1251462733 Aug 06 04:35:32 PM PDT 24 Aug 06 04:35:33 PM PDT 24 27922041 ps
T73 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.316142391 Aug 06 04:35:32 PM PDT 24 Aug 06 04:35:32 PM PDT 24 26378133 ps
T74 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3883238179 Aug 06 04:35:34 PM PDT 24 Aug 06 04:35:35 PM PDT 24 28042119 ps
T75 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.725699771 Aug 06 04:35:34 PM PDT 24 Aug 06 04:35:35 PM PDT 24 27463324 ps
T76 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.41160278 Aug 06 04:35:43 PM PDT 24 Aug 06 04:35:43 PM PDT 24 26013482 ps
T77 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.359449 Aug 06 04:35:52 PM PDT 24 Aug 06 04:35:52 PM PDT 24 26211424 ps

Test location /workspace/coverage/default/12.prim_async_alert.2701908898
Short name T7
Test name
Test status
Simulation time 10800931 ps
CPU time 0.39 seconds
Started Aug 06 06:38:02 PM PDT 24
Finished Aug 06 06:38:03 PM PDT 24
Peak memory 145792 kb
Host smart-644ecff1-9360-4df3-8fcd-0bc130ae64e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701908898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2701908898
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.295515516
Short name T27
Test name
Test status
Simulation time 9329936 ps
CPU time 0.38 seconds
Started Aug 06 06:48:58 PM PDT 24
Finished Aug 06 06:48:59 PM PDT 24
Peak memory 145560 kb
Host smart-2bedd7f6-07da-434d-aa25-53859d774877
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=295515516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.295515516
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.414943728
Short name T42
Test name
Test status
Simulation time 31193494 ps
CPU time 0.45 seconds
Started Aug 06 06:38:02 PM PDT 24
Finished Aug 06 06:38:02 PM PDT 24
Peak memory 145300 kb
Host smart-8504623d-3bd9-422b-9d8f-d779d13b73a7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=414943728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.414943728
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4197912129
Short name T13
Test name
Test status
Simulation time 30763665 ps
CPU time 0.43 seconds
Started Aug 06 06:38:06 PM PDT 24
Finished Aug 06 06:38:07 PM PDT 24
Peak memory 145324 kb
Host smart-01410299-a579-4cc2-a343-e5bfa4f17dab
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4197912129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.4197912129
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2457713765
Short name T5
Test name
Test status
Simulation time 29915875 ps
CPU time 0.41 seconds
Started Aug 06 06:38:03 PM PDT 24
Finished Aug 06 06:38:04 PM PDT 24
Peak memory 144140 kb
Host smart-749e9d66-6f91-4e09-9f59-dbfb6a5c1f12
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2457713765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2457713765
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2992055754
Short name T10
Test name
Test status
Simulation time 8129583 ps
CPU time 0.41 seconds
Started Aug 06 06:49:00 PM PDT 24
Finished Aug 06 06:49:00 PM PDT 24
Peak memory 145564 kb
Host smart-25b1f3d8-176d-474b-85a9-0f8cb7cf558c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2992055754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2992055754
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2478136678
Short name T1
Test name
Test status
Simulation time 11067261 ps
CPU time 0.39 seconds
Started Aug 06 06:38:01 PM PDT 24
Finished Aug 06 06:38:01 PM PDT 24
Peak memory 145748 kb
Host smart-c1d73c3e-5cf3-4aa4-ab06-f668bb4795e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478136678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2478136678
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.4006173841
Short name T48
Test name
Test status
Simulation time 10990369 ps
CPU time 0.4 seconds
Started Aug 06 06:38:00 PM PDT 24
Finished Aug 06 06:38:00 PM PDT 24
Peak memory 145764 kb
Host smart-5aeb52ca-424e-44b8-8e9a-a3c66df3bc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006173841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.4006173841
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2827711103
Short name T9
Test name
Test status
Simulation time 11341537 ps
CPU time 0.48 seconds
Started Aug 06 06:38:00 PM PDT 24
Finished Aug 06 06:38:00 PM PDT 24
Peak memory 145660 kb
Host smart-6bc5f33c-43bc-4d14-b7ed-4dbc035d500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827711103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2827711103
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3294857785
Short name T22
Test name
Test status
Simulation time 11934305 ps
CPU time 0.39 seconds
Started Aug 06 06:38:00 PM PDT 24
Finished Aug 06 06:38:00 PM PDT 24
Peak memory 145700 kb
Host smart-a4b28a10-6763-48ca-920c-72a2d2ae2535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294857785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3294857785
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.4027873613
Short name T8
Test name
Test status
Simulation time 10917995 ps
CPU time 0.37 seconds
Started Aug 06 06:37:58 PM PDT 24
Finished Aug 06 06:37:59 PM PDT 24
Peak memory 145696 kb
Host smart-e815dd23-8b0e-481f-a072-9b3f335fa88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027873613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.4027873613
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2116568877
Short name T24
Test name
Test status
Simulation time 10450945 ps
CPU time 0.38 seconds
Started Aug 06 06:37:58 PM PDT 24
Finished Aug 06 06:37:59 PM PDT 24
Peak memory 145768 kb
Host smart-6bdd6f92-0c18-43d4-b7eb-b36b05081325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116568877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2116568877
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.2542545475
Short name T15
Test name
Test status
Simulation time 12853880 ps
CPU time 0.38 seconds
Started Aug 06 06:38:02 PM PDT 24
Finished Aug 06 06:38:03 PM PDT 24
Peak memory 145756 kb
Host smart-e72072cd-a630-4cb0-84af-aa9bffd0b726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542545475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2542545475
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3584596764
Short name T20
Test name
Test status
Simulation time 10940120 ps
CPU time 0.39 seconds
Started Aug 06 06:37:59 PM PDT 24
Finished Aug 06 06:38:00 PM PDT 24
Peak memory 145764 kb
Host smart-df61b222-b5e1-4ea2-b6bd-f4c28d8397d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584596764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3584596764
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.4202352092
Short name T47
Test name
Test status
Simulation time 10658524 ps
CPU time 0.39 seconds
Started Aug 06 06:38:00 PM PDT 24
Finished Aug 06 06:38:00 PM PDT 24
Peak memory 145764 kb
Host smart-4b4ee2c1-67ad-435b-b1a4-83211743f343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202352092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.4202352092
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3123504098
Short name T19
Test name
Test status
Simulation time 10739218 ps
CPU time 0.39 seconds
Started Aug 06 06:37:59 PM PDT 24
Finished Aug 06 06:38:00 PM PDT 24
Peak memory 145772 kb
Host smart-47d61037-5e4d-42c6-8498-5652d8990a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123504098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3123504098
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.438672630
Short name T49
Test name
Test status
Simulation time 10724701 ps
CPU time 0.39 seconds
Started Aug 06 06:37:59 PM PDT 24
Finished Aug 06 06:38:00 PM PDT 24
Peak memory 145784 kb
Host smart-02eff633-db62-474a-b86d-e0ee4b8b6a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438672630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.438672630
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1454768273
Short name T23
Test name
Test status
Simulation time 12262708 ps
CPU time 0.46 seconds
Started Aug 06 06:38:02 PM PDT 24
Finished Aug 06 06:38:03 PM PDT 24
Peak memory 145776 kb
Host smart-b196ca4f-9056-4df7-9687-1f4796c511ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454768273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1454768273
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2032500147
Short name T46
Test name
Test status
Simulation time 11940023 ps
CPU time 0.39 seconds
Started Aug 06 06:38:03 PM PDT 24
Finished Aug 06 06:38:04 PM PDT 24
Peak memory 145764 kb
Host smart-4595bca4-f586-4b39-a68c-3e47b5d7a3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032500147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2032500147
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3326295308
Short name T21
Test name
Test status
Simulation time 11218643 ps
CPU time 0.41 seconds
Started Aug 06 06:38:01 PM PDT 24
Finished Aug 06 06:38:02 PM PDT 24
Peak memory 145748 kb
Host smart-bab06fb8-ea28-40f0-b14d-b73688c98124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326295308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3326295308
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1360616460
Short name T11
Test name
Test status
Simulation time 11773713 ps
CPU time 0.38 seconds
Started Aug 06 06:37:59 PM PDT 24
Finished Aug 06 06:38:00 PM PDT 24
Peak memory 145740 kb
Host smart-a5d67aa5-0f18-4e0d-8e8f-e4e31ab99726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360616460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1360616460
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.224662450
Short name T2
Test name
Test status
Simulation time 10875581 ps
CPU time 0.4 seconds
Started Aug 06 06:38:01 PM PDT 24
Finished Aug 06 06:38:02 PM PDT 24
Peak memory 145732 kb
Host smart-be49c4c0-01bb-406e-80aa-e57b8470d196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224662450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.224662450
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.240445249
Short name T12
Test name
Test status
Simulation time 11112522 ps
CPU time 0.45 seconds
Started Aug 06 06:38:02 PM PDT 24
Finished Aug 06 06:38:02 PM PDT 24
Peak memory 145796 kb
Host smart-f8ff72f1-af07-4c42-8663-4ec09d3981c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240445249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.240445249
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2448855985
Short name T3
Test name
Test status
Simulation time 11697291 ps
CPU time 0.41 seconds
Started Aug 06 06:38:01 PM PDT 24
Finished Aug 06 06:38:02 PM PDT 24
Peak memory 145724 kb
Host smart-c0f666f7-5455-4649-9149-04b7b02b5afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448855985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2448855985
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2850388986
Short name T45
Test name
Test status
Simulation time 30969630 ps
CPU time 0.4 seconds
Started Aug 06 06:37:59 PM PDT 24
Finished Aug 06 06:37:59 PM PDT 24
Peak memory 145240 kb
Host smart-5fe22656-9674-440c-bf8e-d2f01e13a151
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2850388986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2850388986
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1674276884
Short name T53
Test name
Test status
Simulation time 28718686 ps
CPU time 0.4 seconds
Started Aug 06 06:38:03 PM PDT 24
Finished Aug 06 06:38:04 PM PDT 24
Peak memory 143968 kb
Host smart-ca64e6bb-c865-4d58-a0db-6135d39799e3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1674276884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1674276884
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2336292625
Short name T39
Test name
Test status
Simulation time 30268164 ps
CPU time 0.42 seconds
Started Aug 06 06:38:01 PM PDT 24
Finished Aug 06 06:38:01 PM PDT 24
Peak memory 145268 kb
Host smart-e5f86235-24f2-4d2d-b77b-fb3bafb8fb2a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2336292625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2336292625
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1023803612
Short name T54
Test name
Test status
Simulation time 30158012 ps
CPU time 0.39 seconds
Started Aug 06 06:38:02 PM PDT 24
Finished Aug 06 06:38:03 PM PDT 24
Peak memory 145304 kb
Host smart-7679def4-b6f6-41e4-96f5-751c9d923c7e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1023803612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1023803612
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.555068033
Short name T17
Test name
Test status
Simulation time 32884629 ps
CPU time 0.41 seconds
Started Aug 06 06:38:03 PM PDT 24
Finished Aug 06 06:38:03 PM PDT 24
Peak memory 145320 kb
Host smart-dd15775f-c780-4311-99cf-eb11cd4b76fc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=555068033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.555068033
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4236805591
Short name T44
Test name
Test status
Simulation time 28539697 ps
CPU time 0.44 seconds
Started Aug 06 06:38:04 PM PDT 24
Finished Aug 06 06:38:04 PM PDT 24
Peak memory 145292 kb
Host smart-5f96bf0a-a43c-485c-b419-d004eef33460
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4236805591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.4236805591
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2025533669
Short name T40
Test name
Test status
Simulation time 28983503 ps
CPU time 0.41 seconds
Started Aug 06 06:38:08 PM PDT 24
Finished Aug 06 06:38:08 PM PDT 24
Peak memory 145324 kb
Host smart-436cb1c6-40bf-4c03-82cd-3b8cf9aefdb1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2025533669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2025533669
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2198095564
Short name T52
Test name
Test status
Simulation time 32520486 ps
CPU time 0.39 seconds
Started Aug 06 06:37:59 PM PDT 24
Finished Aug 06 06:38:00 PM PDT 24
Peak memory 145284 kb
Host smart-ccfe86c6-f6a6-440d-ab2c-9646865373d2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2198095564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2198095564
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1271059425
Short name T6
Test name
Test status
Simulation time 32448038 ps
CPU time 0.41 seconds
Started Aug 06 06:38:01 PM PDT 24
Finished Aug 06 06:38:02 PM PDT 24
Peak memory 145296 kb
Host smart-627e20b8-40c1-4155-99bd-3029c13d2254
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1271059425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1271059425
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3588314197
Short name T51
Test name
Test status
Simulation time 31117518 ps
CPU time 0.38 seconds
Started Aug 06 06:38:03 PM PDT 24
Finished Aug 06 06:38:03 PM PDT 24
Peak memory 145320 kb
Host smart-fbb21d00-6ca6-40b5-9131-e03fe6f19c93
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3588314197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3588314197
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1918698477
Short name T41
Test name
Test status
Simulation time 29635291 ps
CPU time 0.4 seconds
Started Aug 06 06:38:01 PM PDT 24
Finished Aug 06 06:38:01 PM PDT 24
Peak memory 145324 kb
Host smart-1ed494ac-1832-41c6-bdf5-584423c703da
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1918698477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1918698477
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3465366809
Short name T50
Test name
Test status
Simulation time 30224326 ps
CPU time 0.38 seconds
Started Aug 06 06:38:02 PM PDT 24
Finished Aug 06 06:38:03 PM PDT 24
Peak memory 145296 kb
Host smart-9d3a3c37-2af2-4851-9ed5-ad0b1cccce67
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3465366809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3465366809
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3581808577
Short name T4
Test name
Test status
Simulation time 30212271 ps
CPU time 0.41 seconds
Started Aug 06 06:38:00 PM PDT 24
Finished Aug 06 06:38:01 PM PDT 24
Peak memory 145324 kb
Host smart-2826d3d4-5063-4342-b497-1d5d9c0c41d1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3581808577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3581808577
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3398687810
Short name T16
Test name
Test status
Simulation time 29180252 ps
CPU time 0.39 seconds
Started Aug 06 06:38:00 PM PDT 24
Finished Aug 06 06:38:01 PM PDT 24
Peak memory 145268 kb
Host smart-fc5a333f-9bd7-44c3-bc46-2501bfc19910
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3398687810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3398687810
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.998557591
Short name T43
Test name
Test status
Simulation time 31597059 ps
CPU time 0.4 seconds
Started Aug 06 06:38:08 PM PDT 24
Finished Aug 06 06:38:08 PM PDT 24
Peak memory 145324 kb
Host smart-60c1967e-e22f-4d5c-93da-1d2ed9719dde
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=998557591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.998557591
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.347216148
Short name T57
Test name
Test status
Simulation time 9241143 ps
CPU time 0.39 seconds
Started Aug 06 06:48:58 PM PDT 24
Finished Aug 06 06:48:59 PM PDT 24
Peak memory 145584 kb
Host smart-d8fe343f-c6c9-4d9b-9a01-44f44b11e8d4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=347216148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.347216148
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1239185539
Short name T30
Test name
Test status
Simulation time 8488439 ps
CPU time 0.39 seconds
Started Aug 06 06:49:01 PM PDT 24
Finished Aug 06 06:49:01 PM PDT 24
Peak memory 145544 kb
Host smart-d3ea9c92-fd9b-4ea5-9f9b-fe41509393c3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1239185539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1239185539
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.4052831131
Short name T38
Test name
Test status
Simulation time 8927062 ps
CPU time 0.38 seconds
Started Aug 06 06:48:59 PM PDT 24
Finished Aug 06 06:49:00 PM PDT 24
Peak memory 145584 kb
Host smart-7d58bb65-b8a0-4f8e-96d5-d684528db555
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4052831131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.4052831131
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3161562879
Short name T37
Test name
Test status
Simulation time 9343262 ps
CPU time 0.36 seconds
Started Aug 06 06:48:58 PM PDT 24
Finished Aug 06 06:48:59 PM PDT 24
Peak memory 145560 kb
Host smart-a8403d1a-40bd-45f8-9fc9-0f2bd273a26a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3161562879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3161562879
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2160686545
Short name T18
Test name
Test status
Simulation time 9806744 ps
CPU time 0.4 seconds
Started Aug 06 06:49:00 PM PDT 24
Finished Aug 06 06:49:01 PM PDT 24
Peak memory 145480 kb
Host smart-874e5499-3d38-4e0b-9c20-832d57cfc157
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2160686545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2160686545
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.1808330852
Short name T34
Test name
Test status
Simulation time 8313025 ps
CPU time 0.37 seconds
Started Aug 06 06:48:56 PM PDT 24
Finished Aug 06 06:48:57 PM PDT 24
Peak memory 145580 kb
Host smart-f35852bf-0680-4b50-a65e-f0dd5e095708
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1808330852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1808330852
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1352488837
Short name T31
Test name
Test status
Simulation time 9756539 ps
CPU time 0.44 seconds
Started Aug 06 06:48:59 PM PDT 24
Finished Aug 06 06:49:00 PM PDT 24
Peak memory 145580 kb
Host smart-e2f4f606-739a-47d7-a6e0-d126f05d1a3d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1352488837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1352488837
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1194873667
Short name T25
Test name
Test status
Simulation time 9072658 ps
CPU time 0.38 seconds
Started Aug 06 06:48:58 PM PDT 24
Finished Aug 06 06:48:58 PM PDT 24
Peak memory 145580 kb
Host smart-a74b8215-badf-453e-8fdf-29050d4b2e30
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1194873667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1194873667
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3075002711
Short name T35
Test name
Test status
Simulation time 8620290 ps
CPU time 0.39 seconds
Started Aug 06 06:48:59 PM PDT 24
Finished Aug 06 06:49:00 PM PDT 24
Peak memory 145588 kb
Host smart-3a825380-a9c3-4b99-beea-b89a0a0a1bd9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3075002711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3075002711
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.4008583809
Short name T26
Test name
Test status
Simulation time 8840488 ps
CPU time 0.4 seconds
Started Aug 06 06:48:57 PM PDT 24
Finished Aug 06 06:48:58 PM PDT 24
Peak memory 145552 kb
Host smart-6dd950a2-b57b-4f23-ad82-bc47ec4a032f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4008583809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.4008583809
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1199997727
Short name T56
Test name
Test status
Simulation time 8347350 ps
CPU time 0.39 seconds
Started Aug 06 06:48:58 PM PDT 24
Finished Aug 06 06:48:59 PM PDT 24
Peak memory 145540 kb
Host smart-cf89b15b-a053-404a-96e9-f5d179801fc9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1199997727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1199997727
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3195342393
Short name T32
Test name
Test status
Simulation time 9190200 ps
CPU time 0.4 seconds
Started Aug 06 06:49:00 PM PDT 24
Finished Aug 06 06:49:00 PM PDT 24
Peak memory 145564 kb
Host smart-b9539fa6-6fb4-4df6-a9dd-130c6b489a82
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3195342393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3195342393
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.526771439
Short name T58
Test name
Test status
Simulation time 9634325 ps
CPU time 0.38 seconds
Started Aug 06 06:49:02 PM PDT 24
Finished Aug 06 06:49:03 PM PDT 24
Peak memory 145504 kb
Host smart-dc11b32e-7533-473e-a090-8169e7a57905
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=526771439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.526771439
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.4163700244
Short name T36
Test name
Test status
Simulation time 10276841 ps
CPU time 0.39 seconds
Started Aug 06 06:48:59 PM PDT 24
Finished Aug 06 06:48:59 PM PDT 24
Peak memory 145568 kb
Host smart-47d0b2b9-c599-4095-ba7a-98c597a693bc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4163700244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.4163700244
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3753709082
Short name T33
Test name
Test status
Simulation time 8896062 ps
CPU time 0.39 seconds
Started Aug 06 06:48:57 PM PDT 24
Finished Aug 06 06:48:58 PM PDT 24
Peak memory 145560 kb
Host smart-7706f8bd-d32b-474e-8294-f44540a28d43
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3753709082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3753709082
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3891190401
Short name T29
Test name
Test status
Simulation time 8958778 ps
CPU time 0.38 seconds
Started Aug 06 06:49:01 PM PDT 24
Finished Aug 06 06:49:01 PM PDT 24
Peak memory 145552 kb
Host smart-2dd67904-f367-48bf-a36b-d906c03fbc10
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3891190401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3891190401
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2366519031
Short name T55
Test name
Test status
Simulation time 9266306 ps
CPU time 0.37 seconds
Started Aug 06 06:48:57 PM PDT 24
Finished Aug 06 06:48:57 PM PDT 24
Peak memory 145528 kb
Host smart-de52ce3e-2587-42c6-a257-64e87e45244e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2366519031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2366519031
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3463493179
Short name T28
Test name
Test status
Simulation time 9291621 ps
CPU time 0.38 seconds
Started Aug 06 06:48:59 PM PDT 24
Finished Aug 06 06:48:59 PM PDT 24
Peak memory 145556 kb
Host smart-5318f180-4640-481f-863d-6d683a765e6f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3463493179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3463493179
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.38303910
Short name T61
Test name
Test status
Simulation time 25782950 ps
CPU time 0.39 seconds
Started Aug 06 04:35:50 PM PDT 24
Finished Aug 06 04:35:51 PM PDT 24
Peak memory 145420 kb
Host smart-8da83d2c-e75f-42dd-a6fe-1f00a8376da9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=38303910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.38303910
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.725699771
Short name T75
Test name
Test status
Simulation time 27463324 ps
CPU time 0.4 seconds
Started Aug 06 04:35:34 PM PDT 24
Finished Aug 06 04:35:35 PM PDT 24
Peak memory 145456 kb
Host smart-b5cb5322-796a-4def-b9d6-bc2dcfa86aa2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=725699771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.725699771
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3517541660
Short name T59
Test name
Test status
Simulation time 28611507 ps
CPU time 0.4 seconds
Started Aug 06 04:35:45 PM PDT 24
Finished Aug 06 04:35:45 PM PDT 24
Peak memory 145488 kb
Host smart-1090ca60-69f9-43cb-ad31-387f7746c0b5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3517541660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3517541660
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3925847044
Short name T67
Test name
Test status
Simulation time 26829848 ps
CPU time 0.4 seconds
Started Aug 06 04:35:34 PM PDT 24
Finished Aug 06 04:35:35 PM PDT 24
Peak memory 145464 kb
Host smart-c4cd2208-1a33-4015-8794-9634188691cc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3925847044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3925847044
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3311378569
Short name T70
Test name
Test status
Simulation time 25822148 ps
CPU time 0.42 seconds
Started Aug 06 04:35:35 PM PDT 24
Finished Aug 06 04:35:35 PM PDT 24
Peak memory 145448 kb
Host smart-fce97903-2989-4208-9d89-6d093351f077
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3311378569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3311378569
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.41160278
Short name T76
Test name
Test status
Simulation time 26013482 ps
CPU time 0.42 seconds
Started Aug 06 04:35:43 PM PDT 24
Finished Aug 06 04:35:43 PM PDT 24
Peak memory 145440 kb
Host smart-6590203a-a990-4d81-9554-abe1eeb8f2b5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=41160278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.41160278
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1726773914
Short name T69
Test name
Test status
Simulation time 27010652 ps
CPU time 0.38 seconds
Started Aug 06 04:35:37 PM PDT 24
Finished Aug 06 04:35:37 PM PDT 24
Peak memory 145424 kb
Host smart-9d32c59b-1ae0-420e-97ae-facdc553f9d8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1726773914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1726773914
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4231659487
Short name T71
Test name
Test status
Simulation time 26863528 ps
CPU time 0.4 seconds
Started Aug 06 04:35:35 PM PDT 24
Finished Aug 06 04:35:35 PM PDT 24
Peak memory 145452 kb
Host smart-2fa7ef7e-bca0-43fa-ac06-c94b206c1355
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4231659487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.4231659487
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2292657300
Short name T62
Test name
Test status
Simulation time 28546726 ps
CPU time 0.51 seconds
Started Aug 06 04:36:45 PM PDT 24
Finished Aug 06 04:36:46 PM PDT 24
Peak memory 145868 kb
Host smart-b8edc2af-cf6d-4a8b-8c76-3b44ffc2bf67
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2292657300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2292657300
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3245709286
Short name T60
Test name
Test status
Simulation time 28906222 ps
CPU time 0.44 seconds
Started Aug 06 04:35:52 PM PDT 24
Finished Aug 06 04:35:52 PM PDT 24
Peak memory 145464 kb
Host smart-99d21825-a916-40aa-9637-c7c418161549
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3245709286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3245709286
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3929821189
Short name T66
Test name
Test status
Simulation time 29557811 ps
CPU time 0.4 seconds
Started Aug 06 04:35:51 PM PDT 24
Finished Aug 06 04:35:52 PM PDT 24
Peak memory 145464 kb
Host smart-a6c0388d-cea1-422a-aec0-71b08bc940c9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3929821189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3929821189
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3914470864
Short name T65
Test name
Test status
Simulation time 29895390 ps
CPU time 0.38 seconds
Started Aug 06 04:35:48 PM PDT 24
Finished Aug 06 04:35:49 PM PDT 24
Peak memory 145448 kb
Host smart-351aab50-d466-4a26-bca3-1286017e7a1e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3914470864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3914470864
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3200656851
Short name T14
Test name
Test status
Simulation time 28959952 ps
CPU time 0.38 seconds
Started Aug 06 04:35:34 PM PDT 24
Finished Aug 06 04:35:34 PM PDT 24
Peak memory 145440 kb
Host smart-73730811-ee08-46ea-94bc-bd7e082dd933
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3200656851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3200656851
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1525991351
Short name T68
Test name
Test status
Simulation time 28534295 ps
CPU time 0.41 seconds
Started Aug 06 04:35:34 PM PDT 24
Finished Aug 06 04:35:35 PM PDT 24
Peak memory 145440 kb
Host smart-621998a2-1d64-4cd6-85cf-45e4e71d3e7d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1525991351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1525991351
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3326397617
Short name T64
Test name
Test status
Simulation time 27316521 ps
CPU time 0.39 seconds
Started Aug 06 04:35:48 PM PDT 24
Finished Aug 06 04:35:49 PM PDT 24
Peak memory 145476 kb
Host smart-22e673f7-1c48-4b38-9a81-81da382ad262
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3326397617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3326397617
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.316142391
Short name T73
Test name
Test status
Simulation time 26378133 ps
CPU time 0.4 seconds
Started Aug 06 04:35:32 PM PDT 24
Finished Aug 06 04:35:32 PM PDT 24
Peak memory 145468 kb
Host smart-4530fb0f-dcb2-44ed-84da-3859280b832e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=316142391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.316142391
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1251462733
Short name T72
Test name
Test status
Simulation time 27922041 ps
CPU time 0.4 seconds
Started Aug 06 04:35:32 PM PDT 24
Finished Aug 06 04:35:33 PM PDT 24
Peak memory 145452 kb
Host smart-8a2f8aab-bf85-4763-a881-187d696345a9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1251462733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1251462733
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3155729672
Short name T63
Test name
Test status
Simulation time 27069418 ps
CPU time 0.39 seconds
Started Aug 06 04:35:35 PM PDT 24
Finished Aug 06 04:35:35 PM PDT 24
Peak memory 145444 kb
Host smart-e6179d6e-0844-40b2-86a1-75f7b9d0a6aa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3155729672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3155729672
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.359449
Short name T77
Test name
Test status
Simulation time 26211424 ps
CPU time 0.41 seconds
Started Aug 06 04:35:52 PM PDT 24
Finished Aug 06 04:35:52 PM PDT 24
Peak memory 145460 kb
Host smart-c9ba2e7c-670c-46a2-afaf-fb9f0815157f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=359449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.359449
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3883238179
Short name T74
Test name
Test status
Simulation time 28042119 ps
CPU time 0.4 seconds
Started Aug 06 04:35:34 PM PDT 24
Finished Aug 06 04:35:35 PM PDT 24
Peak memory 145444 kb
Host smart-bbc51f20-1ca8-42c9-9fa7-144154dca96e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3883238179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3883238179
Directory /workspace/9.prim_sync_fatal_alert/latest
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