| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.85 | 100.00 | 97.92 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.08 | 88.08 | 100.00 | 100.00 | 93.75 | 93.75 | 96.43 | 96.43 | 75.00 | 75.00 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/3.prim_async_alert.1131518375 |
| 91.80 | 3.72 | 100.00 | 0.00 | 93.75 | 0.00 | 96.43 | 0.00 | 85.71 | 10.71 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/0.prim_sync_alert.316132942 |
| 94.25 | 2.45 | 100.00 | 0.00 | 97.92 | 4.17 | 100.00 | 3.57 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3192932484 |
| 94.85 | 0.60 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1245632001 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.4286698796 |
| /workspace/coverage/default/1.prim_async_alert.161236184 |
| /workspace/coverage/default/10.prim_async_alert.1901563265 |
| /workspace/coverage/default/11.prim_async_alert.3930364271 |
| /workspace/coverage/default/12.prim_async_alert.3260989798 |
| /workspace/coverage/default/13.prim_async_alert.4055600172 |
| /workspace/coverage/default/14.prim_async_alert.1048945255 |
| /workspace/coverage/default/15.prim_async_alert.3140344877 |
| /workspace/coverage/default/16.prim_async_alert.48137962 |
| /workspace/coverage/default/17.prim_async_alert.1388085733 |
| /workspace/coverage/default/18.prim_async_alert.3167576973 |
| /workspace/coverage/default/19.prim_async_alert.1371664550 |
| /workspace/coverage/default/2.prim_async_alert.992969437 |
| /workspace/coverage/default/4.prim_async_alert.3075305261 |
| /workspace/coverage/default/5.prim_async_alert.3408623645 |
| /workspace/coverage/default/6.prim_async_alert.2498192412 |
| /workspace/coverage/default/7.prim_async_alert.2575883040 |
| /workspace/coverage/default/8.prim_async_alert.4016529389 |
| /workspace/coverage/default/9.prim_async_alert.3787216949 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2194444342 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3517150125 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.297825715 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.270788132 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3533791031 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1475079007 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3410418017 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1876096410 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3214879582 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.695670695 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3548583424 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2195023039 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2237510977 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3487633478 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1119447573 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3403014178 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.1075237515 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.4256763764 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1942635468 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.945159702 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1828627120 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1094388582 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.2993389365 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.3016975634 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.2859872272 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.959776105 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.2628061704 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2560756830 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3547745960 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.1559139850 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.2085996904 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.3270999448 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.2676359660 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.667968087 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.1228369146 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.195427167 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4266179028 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1348531509 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.65694362 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1470076768 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2968482384 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4103709663 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1015987664 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1849735376 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3155097274 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.476522258 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3981745381 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3601114722 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3660134383 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2378299663 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2886142413 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3395580668 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1944656979 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3269865060 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.419791640 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/13.prim_async_alert.4055600172 | Aug 07 04:29:18 PM PDT 24 | Aug 07 04:29:19 PM PDT 24 | 11388867 ps | ||
| T2 | /workspace/coverage/default/18.prim_async_alert.3167576973 | Aug 07 04:29:18 PM PDT 24 | Aug 07 04:29:18 PM PDT 24 | 12030901 ps | ||
| T3 | /workspace/coverage/default/6.prim_async_alert.2498192412 | Aug 07 04:22:07 PM PDT 24 | Aug 07 04:22:07 PM PDT 24 | 11634870 ps | ||
| T12 | /workspace/coverage/default/12.prim_async_alert.3260989798 | Aug 07 04:29:24 PM PDT 24 | Aug 07 04:29:25 PM PDT 24 | 11809367 ps | ||
| T7 | /workspace/coverage/default/3.prim_async_alert.1131518375 | Aug 07 04:24:47 PM PDT 24 | Aug 07 04:24:47 PM PDT 24 | 11824565 ps | ||
| T20 | /workspace/coverage/default/1.prim_async_alert.161236184 | Aug 07 04:24:06 PM PDT 24 | Aug 07 04:24:07 PM PDT 24 | 10587560 ps | ||
| T18 | /workspace/coverage/default/0.prim_async_alert.4286698796 | Aug 07 04:24:55 PM PDT 24 | Aug 07 04:24:56 PM PDT 24 | 10814603 ps | ||
| T19 | /workspace/coverage/default/4.prim_async_alert.3075305261 | Aug 07 04:21:10 PM PDT 24 | Aug 07 04:21:11 PM PDT 24 | 11128682 ps | ||
| T8 | /workspace/coverage/default/8.prim_async_alert.4016529389 | Aug 07 04:20:31 PM PDT 24 | Aug 07 04:20:31 PM PDT 24 | 10906483 ps | ||
| T21 | /workspace/coverage/default/19.prim_async_alert.1371664550 | Aug 07 04:29:22 PM PDT 24 | Aug 07 04:29:22 PM PDT 24 | 11352053 ps | ||
| T9 | /workspace/coverage/default/16.prim_async_alert.48137962 | Aug 07 04:29:15 PM PDT 24 | Aug 07 04:29:16 PM PDT 24 | 10755339 ps | ||
| T44 | /workspace/coverage/default/14.prim_async_alert.1048945255 | Aug 07 04:29:15 PM PDT 24 | Aug 07 04:29:16 PM PDT 24 | 11333721 ps | ||
| T22 | /workspace/coverage/default/17.prim_async_alert.1388085733 | Aug 07 04:29:20 PM PDT 24 | Aug 07 04:29:21 PM PDT 24 | 10707246 ps | ||
| T45 | /workspace/coverage/default/10.prim_async_alert.1901563265 | Aug 07 04:29:12 PM PDT 24 | Aug 07 04:29:13 PM PDT 24 | 11331074 ps | ||
| T15 | /workspace/coverage/default/11.prim_async_alert.3930364271 | Aug 07 04:29:17 PM PDT 24 | Aug 07 04:29:17 PM PDT 24 | 10702982 ps | ||
| T10 | /workspace/coverage/default/2.prim_async_alert.992969437 | Aug 07 04:21:35 PM PDT 24 | Aug 07 04:21:36 PM PDT 24 | 11816533 ps | ||
| T46 | /workspace/coverage/default/7.prim_async_alert.2575883040 | Aug 07 04:24:18 PM PDT 24 | Aug 07 04:24:18 PM PDT 24 | 11059230 ps | ||
| T47 | /workspace/coverage/default/15.prim_async_alert.3140344877 | Aug 07 04:29:15 PM PDT 24 | Aug 07 04:29:16 PM PDT 24 | 10602679 ps | ||
| T11 | /workspace/coverage/default/9.prim_async_alert.3787216949 | Aug 07 04:19:52 PM PDT 24 | Aug 07 04:19:52 PM PDT 24 | 11004307 ps | ||
| T48 | /workspace/coverage/default/5.prim_async_alert.3408623645 | Aug 07 04:20:41 PM PDT 24 | Aug 07 04:20:41 PM PDT 24 | 10330185 ps | ||
| T4 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3192932484 | Aug 07 04:33:22 PM PDT 24 | Aug 07 04:33:23 PM PDT 24 | 28834090 ps | ||
| T36 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2237510977 | Aug 07 04:19:52 PM PDT 24 | Aug 07 04:19:53 PM PDT 24 | 29212388 ps | ||
| T5 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3214879582 | Aug 07 04:33:16 PM PDT 24 | Aug 07 04:33:16 PM PDT 24 | 31235248 ps | ||
| T37 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1119447573 | Aug 07 04:19:06 PM PDT 24 | Aug 07 04:19:07 PM PDT 24 | 31901621 ps | ||
| T38 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3487633478 | Aug 07 04:20:24 PM PDT 24 | Aug 07 04:20:25 PM PDT 24 | 31562082 ps | ||
| T39 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3517150125 | Aug 07 04:19:44 PM PDT 24 | Aug 07 04:19:45 PM PDT 24 | 33139104 ps | ||
| T40 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1876096410 | Aug 07 04:33:14 PM PDT 24 | Aug 07 04:33:14 PM PDT 24 | 30306999 ps | ||
| T41 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2194444342 | Aug 07 04:20:07 PM PDT 24 | Aug 07 04:20:08 PM PDT 24 | 29204184 ps | ||
| T42 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.270788132 | Aug 07 04:32:52 PM PDT 24 | Aug 07 04:32:53 PM PDT 24 | 30564588 ps | ||
| T43 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.695670695 | Aug 07 04:32:53 PM PDT 24 | Aug 07 04:32:53 PM PDT 24 | 28704158 ps | ||
| T49 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1475079007 | Aug 07 04:32:48 PM PDT 24 | Aug 07 04:32:49 PM PDT 24 | 31169469 ps | ||
| T6 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1245632001 | Aug 07 04:32:52 PM PDT 24 | Aug 07 04:32:52 PM PDT 24 | 29871668 ps | ||
| T50 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2195023039 | Aug 07 04:20:07 PM PDT 24 | Aug 07 04:20:08 PM PDT 24 | 31252329 ps | ||
| T51 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3533791031 | Aug 07 04:32:53 PM PDT 24 | Aug 07 04:32:53 PM PDT 24 | 31894742 ps | ||
| T52 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.297825715 | Aug 07 04:33:30 PM PDT 24 | Aug 07 04:33:35 PM PDT 24 | 30366546 ps | ||
| T53 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3410418017 | Aug 07 04:32:49 PM PDT 24 | Aug 07 04:32:49 PM PDT 24 | 30889886 ps | ||
| T54 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3548583424 | Aug 07 04:20:05 PM PDT 24 | Aug 07 04:20:06 PM PDT 24 | 30326606 ps | ||
| T55 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3403014178 | Aug 07 04:19:52 PM PDT 24 | Aug 07 04:19:52 PM PDT 24 | 28707374 ps | ||
| T31 | /workspace/coverage/sync_alert/7.prim_sync_alert.2676359660 | Aug 07 04:33:44 PM PDT 24 | Aug 07 04:33:44 PM PDT 24 | 8503212 ps | ||
| T23 | /workspace/coverage/sync_alert/6.prim_sync_alert.3270999448 | Aug 07 04:33:00 PM PDT 24 | Aug 07 04:33:01 PM PDT 24 | 9528519 ps | ||
| T16 | /workspace/coverage/sync_alert/10.prim_sync_alert.4256763764 | Aug 07 04:33:33 PM PDT 24 | Aug 07 04:33:33 PM PDT 24 | 9572618 ps | ||
| T24 | /workspace/coverage/sync_alert/19.prim_sync_alert.2628061704 | Aug 07 04:33:29 PM PDT 24 | Aug 07 04:33:30 PM PDT 24 | 9326904 ps | ||
| T17 | /workspace/coverage/sync_alert/0.prim_sync_alert.316132942 | Aug 07 04:32:55 PM PDT 24 | Aug 07 04:32:56 PM PDT 24 | 9311863 ps | ||
| T32 | /workspace/coverage/sync_alert/13.prim_sync_alert.1828627120 | Aug 07 04:33:03 PM PDT 24 | Aug 07 04:33:03 PM PDT 24 | 9799922 ps | ||
| T33 | /workspace/coverage/sync_alert/5.prim_sync_alert.2085996904 | Aug 07 04:32:53 PM PDT 24 | Aug 07 04:32:54 PM PDT 24 | 9268112 ps | ||
| T25 | /workspace/coverage/sync_alert/3.prim_sync_alert.3547745960 | Aug 07 04:32:52 PM PDT 24 | Aug 07 04:32:53 PM PDT 24 | 9931761 ps | ||
| T34 | /workspace/coverage/sync_alert/17.prim_sync_alert.2859872272 | Aug 07 04:33:14 PM PDT 24 | Aug 07 04:33:19 PM PDT 24 | 8716011 ps | ||
| T35 | /workspace/coverage/sync_alert/1.prim_sync_alert.1075237515 | Aug 07 04:32:43 PM PDT 24 | Aug 07 04:32:43 PM PDT 24 | 9531476 ps | ||
| T56 | /workspace/coverage/sync_alert/2.prim_sync_alert.2560756830 | Aug 07 04:33:08 PM PDT 24 | Aug 07 04:33:08 PM PDT 24 | 8760825 ps | ||
| T26 | /workspace/coverage/sync_alert/8.prim_sync_alert.667968087 | Aug 07 04:32:59 PM PDT 24 | Aug 07 04:33:00 PM PDT 24 | 9328608 ps | ||
| T57 | /workspace/coverage/sync_alert/4.prim_sync_alert.1559139850 | Aug 07 04:32:58 PM PDT 24 | Aug 07 04:32:58 PM PDT 24 | 9592063 ps | ||
| T58 | /workspace/coverage/sync_alert/11.prim_sync_alert.1942635468 | Aug 07 04:32:57 PM PDT 24 | Aug 07 04:32:58 PM PDT 24 | 9248099 ps | ||
| T59 | /workspace/coverage/sync_alert/9.prim_sync_alert.1228369146 | Aug 07 04:33:05 PM PDT 24 | Aug 07 04:33:06 PM PDT 24 | 8679159 ps | ||
| T27 | /workspace/coverage/sync_alert/18.prim_sync_alert.959776105 | Aug 07 04:33:02 PM PDT 24 | Aug 07 04:33:03 PM PDT 24 | 10285509 ps | ||
| T28 | /workspace/coverage/sync_alert/14.prim_sync_alert.1094388582 | Aug 07 04:33:00 PM PDT 24 | Aug 07 04:33:01 PM PDT 24 | 8801152 ps | ||
| T29 | /workspace/coverage/sync_alert/15.prim_sync_alert.2993389365 | Aug 07 04:33:26 PM PDT 24 | Aug 07 04:33:27 PM PDT 24 | 9581638 ps | ||
| T30 | /workspace/coverage/sync_alert/12.prim_sync_alert.945159702 | Aug 07 04:32:56 PM PDT 24 | Aug 07 04:32:57 PM PDT 24 | 8958556 ps | ||
| T60 | /workspace/coverage/sync_alert/16.prim_sync_alert.3016975634 | Aug 07 04:32:56 PM PDT 24 | Aug 07 04:32:56 PM PDT 24 | 9783765 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2968482384 | Aug 07 04:33:00 PM PDT 24 | Aug 07 04:33:00 PM PDT 24 | 26778046 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1015987664 | Aug 07 04:32:58 PM PDT 24 | Aug 07 04:32:58 PM PDT 24 | 25104309 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.419791640 | Aug 07 04:32:58 PM PDT 24 | Aug 07 04:32:58 PM PDT 24 | 27853055 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3269865060 | Aug 07 04:33:02 PM PDT 24 | Aug 07 04:33:03 PM PDT 24 | 26568962 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4266179028 | Aug 07 04:33:28 PM PDT 24 | Aug 07 04:33:33 PM PDT 24 | 29251657 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2378299663 | Aug 07 04:33:19 PM PDT 24 | Aug 07 04:33:20 PM PDT 24 | 29491821 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3660134383 | Aug 07 04:32:56 PM PDT 24 | Aug 07 04:32:57 PM PDT 24 | 26881132 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.476522258 | Aug 07 04:33:31 PM PDT 24 | Aug 07 04:33:32 PM PDT 24 | 27042497 ps | ||
| T13 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1849735376 | Aug 07 04:32:54 PM PDT 24 | Aug 07 04:32:55 PM PDT 24 | 27424471 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4103709663 | Aug 07 04:33:13 PM PDT 24 | Aug 07 04:33:14 PM PDT 24 | 25783999 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2886142413 | Aug 07 04:32:54 PM PDT 24 | Aug 07 04:32:54 PM PDT 24 | 28710096 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3601114722 | Aug 07 04:32:59 PM PDT 24 | Aug 07 04:33:00 PM PDT 24 | 27354710 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1470076768 | Aug 07 04:33:11 PM PDT 24 | Aug 07 04:33:11 PM PDT 24 | 27643335 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3395580668 | Aug 07 04:33:01 PM PDT 24 | Aug 07 04:33:02 PM PDT 24 | 27240912 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.195427167 | Aug 07 04:33:20 PM PDT 24 | Aug 07 04:33:20 PM PDT 24 | 26233568 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.65694362 | Aug 07 04:33:06 PM PDT 24 | Aug 07 04:33:06 PM PDT 24 | 26678030 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1348531509 | Aug 07 04:33:14 PM PDT 24 | Aug 07 04:33:15 PM PDT 24 | 27486375 ps | ||
| T14 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1944656979 | Aug 07 04:33:22 PM PDT 24 | Aug 07 04:33:23 PM PDT 24 | 26737421 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3155097274 | Aug 07 04:33:17 PM PDT 24 | Aug 07 04:33:17 PM PDT 24 | 27724890 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3981745381 | Aug 07 04:32:54 PM PDT 24 | Aug 07 04:32:55 PM PDT 24 | 27554569 ps |
| Test location | /workspace/coverage/default/3.prim_async_alert.1131518375 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11824565 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:24:47 PM PDT 24 |
| Finished | Aug 07 04:24:47 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-34615bca-ce0e-4cf2-b64a-65021634b4fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1131518375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1131518375 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.316132942 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9311863 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:32:55 PM PDT 24 |
| Finished | Aug 07 04:32:56 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-c8f73d51-f95b-4c9c-bcc5-29fb2505c57f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=316132942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.316132942 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3192932484 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28834090 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:33:22 PM PDT 24 |
| Finished | Aug 07 04:33:23 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-5b2cbf18-7a68-4a96-a568-ca6aedf4e110 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3192932484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3192932484 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1245632001 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 29871668 ps |
| CPU time | 0.42 seconds |
| Started | Aug 07 04:32:52 PM PDT 24 |
| Finished | Aug 07 04:32:52 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-3be35c76-ebd5-48fc-95af-7cd8eb093f03 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1245632001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1245632001 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.4286698796 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10814603 ps |
| CPU time | 0.41 seconds |
| Started | Aug 07 04:24:55 PM PDT 24 |
| Finished | Aug 07 04:24:56 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-f18f2d8b-a785-4b9a-957a-028651569d70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4286698796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.4286698796 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.161236184 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10587560 ps |
| CPU time | 0.37 seconds |
| Started | Aug 07 04:24:06 PM PDT 24 |
| Finished | Aug 07 04:24:07 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-08161f7d-e53e-417e-80e4-0c38522606d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161236184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.161236184 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.1901563265 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11331074 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:29:12 PM PDT 24 |
| Finished | Aug 07 04:29:13 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-6fe83036-2b91-4d6a-be75-a9d3d2735532 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901563265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1901563265 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.3930364271 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10702982 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:29:17 PM PDT 24 |
| Finished | Aug 07 04:29:17 PM PDT 24 |
| Peak memory | 145752 kb |
| Host | smart-23a0c02a-97ba-4789-b368-203b0cfb11d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3930364271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3930364271 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.3260989798 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11809367 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:29:24 PM PDT 24 |
| Finished | Aug 07 04:29:25 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-95a80b89-b011-479e-ac07-dde12d47b6c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260989798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3260989798 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.4055600172 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11388867 ps |
| CPU time | 0.37 seconds |
| Started | Aug 07 04:29:18 PM PDT 24 |
| Finished | Aug 07 04:29:19 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-bc3313b1-9ed8-4172-a97b-d1dc397395be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055600172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.4055600172 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1048945255 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11333721 ps |
| CPU time | 0.42 seconds |
| Started | Aug 07 04:29:15 PM PDT 24 |
| Finished | Aug 07 04:29:16 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-64078f91-cc9a-494d-ab9e-530337791dfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1048945255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1048945255 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.3140344877 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10602679 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:29:15 PM PDT 24 |
| Finished | Aug 07 04:29:16 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-405bbf9e-a524-4cdd-a430-c174a16777e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140344877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3140344877 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.48137962 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10755339 ps |
| CPU time | 0.37 seconds |
| Started | Aug 07 04:29:15 PM PDT 24 |
| Finished | Aug 07 04:29:16 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-03d12035-549a-4e81-a433-ea7e141a98a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48137962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.48137962 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.1388085733 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10707246 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:29:20 PM PDT 24 |
| Finished | Aug 07 04:29:21 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-55ea3a93-868c-4834-939d-e3a0cfce2eb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1388085733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1388085733 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.3167576973 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12030901 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:29:18 PM PDT 24 |
| Finished | Aug 07 04:29:18 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-415660ce-c90e-4a77-b638-7d74a120479e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3167576973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3167576973 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.1371664550 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11352053 ps |
| CPU time | 0.37 seconds |
| Started | Aug 07 04:29:22 PM PDT 24 |
| Finished | Aug 07 04:29:22 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-3a0b6038-0d1e-4386-add6-f91a7f1c05e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1371664550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1371664550 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.992969437 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11816533 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:21:35 PM PDT 24 |
| Finished | Aug 07 04:21:36 PM PDT 24 |
| Peak memory | 145692 kb |
| Host | smart-4790c455-a1c9-472b-8610-d35394ef0424 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=992969437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.992969437 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.3075305261 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11128682 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:21:10 PM PDT 24 |
| Finished | Aug 07 04:21:11 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-7fef1e4b-7b86-4477-b59e-968847021111 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3075305261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3075305261 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3408623645 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10330185 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:20:41 PM PDT 24 |
| Finished | Aug 07 04:20:41 PM PDT 24 |
| Peak memory | 145660 kb |
| Host | smart-55668766-d496-478f-a06b-9849a0f4e6d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3408623645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3408623645 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2498192412 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11634870 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:22:07 PM PDT 24 |
| Finished | Aug 07 04:22:07 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-c27806fb-31a9-4287-b456-581f73eb2b70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498192412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2498192412 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.2575883040 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11059230 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:24:18 PM PDT 24 |
| Finished | Aug 07 04:24:18 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-19ac19ad-d26a-4ba7-b1c1-fa43e4cefa72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575883040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2575883040 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.4016529389 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10906483 ps |
| CPU time | 0.41 seconds |
| Started | Aug 07 04:20:31 PM PDT 24 |
| Finished | Aug 07 04:20:31 PM PDT 24 |
| Peak memory | 145900 kb |
| Host | smart-24891946-3870-4a21-b122-06b4cae92cae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016529389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.4016529389 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.3787216949 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11004307 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:19:52 PM PDT 24 |
| Finished | Aug 07 04:19:52 PM PDT 24 |
| Peak memory | 144316 kb |
| Host | smart-90f02b4b-9207-4729-b293-ed609ef2a95c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787216949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3787216949 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2194444342 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29204184 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:20:07 PM PDT 24 |
| Finished | Aug 07 04:20:08 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-1ff96a8b-9a9f-4dfc-8c29-3859d31a6ce4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2194444342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2194444342 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3517150125 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 33139104 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:19:44 PM PDT 24 |
| Finished | Aug 07 04:19:45 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-b66d2be6-4b2f-4c36-902c-9b2dd82e905e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3517150125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3517150125 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.297825715 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30366546 ps |
| CPU time | 0.41 seconds |
| Started | Aug 07 04:33:30 PM PDT 24 |
| Finished | Aug 07 04:33:35 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-9dbaf5d3-31c2-4454-8be5-97c534c52739 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=297825715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.297825715 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.270788132 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30564588 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:32:52 PM PDT 24 |
| Finished | Aug 07 04:32:53 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-fc715cf4-95f0-4801-a344-1267f9e4f20a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=270788132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.270788132 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3533791031 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 31894742 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:32:53 PM PDT 24 |
| Finished | Aug 07 04:32:53 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-8d48b650-d37c-4200-80f9-da46a5fc9d8f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3533791031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3533791031 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1475079007 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 31169469 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:32:48 PM PDT 24 |
| Finished | Aug 07 04:32:49 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-f7bff4f4-2854-44b5-8183-26d96291c378 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1475079007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1475079007 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3410418017 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30889886 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:32:49 PM PDT 24 |
| Finished | Aug 07 04:32:49 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-fb9d3aab-854c-45a0-8e13-4046259754b4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3410418017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3410418017 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1876096410 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 30306999 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:33:14 PM PDT 24 |
| Finished | Aug 07 04:33:14 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-c4b15e04-f367-4976-bc72-9d6f33c2995e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1876096410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1876096410 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3214879582 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 31235248 ps |
| CPU time | 0.41 seconds |
| Started | Aug 07 04:33:16 PM PDT 24 |
| Finished | Aug 07 04:33:16 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-d2f9f845-bdcf-49e3-9db1-05ee8586aaab |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3214879582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3214879582 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.695670695 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 28704158 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:32:53 PM PDT 24 |
| Finished | Aug 07 04:32:53 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-8910b6b3-aeec-4cb9-b98a-ee877b69183d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=695670695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.695670695 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3548583424 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30326606 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:20:05 PM PDT 24 |
| Finished | Aug 07 04:20:06 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-09aa3e75-798b-42c9-a64c-5159690af7ff |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3548583424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3548583424 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2195023039 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 31252329 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:20:07 PM PDT 24 |
| Finished | Aug 07 04:20:08 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-a3591f51-8b8b-470f-a5a3-224c38f9ca34 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2195023039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2195023039 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2237510977 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 29212388 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:19:52 PM PDT 24 |
| Finished | Aug 07 04:19:53 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-b468d163-f971-4679-af40-b6f657a3ebbd |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2237510977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2237510977 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3487633478 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 31562082 ps |
| CPU time | 0.44 seconds |
| Started | Aug 07 04:20:24 PM PDT 24 |
| Finished | Aug 07 04:20:25 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-326e0758-0348-4aa4-b645-870fe189e347 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3487633478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3487633478 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1119447573 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 31901621 ps |
| CPU time | 0.45 seconds |
| Started | Aug 07 04:19:06 PM PDT 24 |
| Finished | Aug 07 04:19:07 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-7c7659a7-7384-4373-9db7-d7be9e0dc8f1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1119447573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1119447573 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3403014178 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 28707374 ps |
| CPU time | 0.41 seconds |
| Started | Aug 07 04:19:52 PM PDT 24 |
| Finished | Aug 07 04:19:52 PM PDT 24 |
| Peak memory | 143904 kb |
| Host | smart-3decdec3-9912-433b-ad8d-6f0b34f9430d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3403014178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3403014178 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.1075237515 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9531476 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:32:43 PM PDT 24 |
| Finished | Aug 07 04:32:43 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-d9113bbb-1594-4c30-8b84-f014ea4bdfeb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1075237515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1075237515 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.4256763764 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9572618 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:33:33 PM PDT 24 |
| Finished | Aug 07 04:33:33 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-b2df1c97-be13-4089-bef8-b84b450aaa9a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4256763764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.4256763764 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1942635468 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9248099 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:32:57 PM PDT 24 |
| Finished | Aug 07 04:32:58 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-665c748f-33db-41d6-b5c7-808eae80b26f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1942635468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1942635468 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.945159702 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8958556 ps |
| CPU time | 0.37 seconds |
| Started | Aug 07 04:32:56 PM PDT 24 |
| Finished | Aug 07 04:32:57 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-6bbf79bd-4cf0-40bd-8aae-3bde48f5538d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=945159702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.945159702 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1828627120 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9799922 ps |
| CPU time | 0.41 seconds |
| Started | Aug 07 04:33:03 PM PDT 24 |
| Finished | Aug 07 04:33:03 PM PDT 24 |
| Peak memory | 145524 kb |
| Host | smart-8fd569cc-bb12-48ab-9b10-acc23fac0adf |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1828627120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1828627120 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1094388582 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8801152 ps |
| CPU time | 0.37 seconds |
| Started | Aug 07 04:33:00 PM PDT 24 |
| Finished | Aug 07 04:33:01 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-0bd75067-2b29-408f-96fb-fb27531083f1 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1094388582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1094388582 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.2993389365 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9581638 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:33:26 PM PDT 24 |
| Finished | Aug 07 04:33:27 PM PDT 24 |
| Peak memory | 145524 kb |
| Host | smart-46f2f533-dfaf-4a91-981a-c592b3cf29db |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2993389365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2993389365 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.3016975634 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9783765 ps |
| CPU time | 0.45 seconds |
| Started | Aug 07 04:32:56 PM PDT 24 |
| Finished | Aug 07 04:32:56 PM PDT 24 |
| Peak memory | 145508 kb |
| Host | smart-e9d09353-3164-40f0-bfe1-1af07a45d9c8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3016975634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3016975634 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.2859872272 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8716011 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:33:14 PM PDT 24 |
| Finished | Aug 07 04:33:19 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-1f203594-a687-4281-9019-31230e554f05 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2859872272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2859872272 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.959776105 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10285509 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:33:02 PM PDT 24 |
| Finished | Aug 07 04:33:03 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-e4a47e57-9358-4c66-8141-19e9830f423f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=959776105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.959776105 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.2628061704 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9326904 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:33:29 PM PDT 24 |
| Finished | Aug 07 04:33:30 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-db05c32e-ee0e-4650-80c3-95d54871d053 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2628061704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2628061704 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2560756830 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8760825 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:33:08 PM PDT 24 |
| Finished | Aug 07 04:33:08 PM PDT 24 |
| Peak memory | 145508 kb |
| Host | smart-3c17d714-ebf0-401d-a67b-135184bd71b2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2560756830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2560756830 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3547745960 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9931761 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:32:52 PM PDT 24 |
| Finished | Aug 07 04:32:53 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-22ce31b6-04af-426e-9beb-304cdbe8c580 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3547745960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3547745960 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.1559139850 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9592063 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:32:58 PM PDT 24 |
| Finished | Aug 07 04:32:58 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-e2f64287-9982-4fc1-879e-f530635966a6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1559139850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1559139850 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.2085996904 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9268112 ps |
| CPU time | 0.37 seconds |
| Started | Aug 07 04:32:53 PM PDT 24 |
| Finished | Aug 07 04:32:54 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-a35e3ef0-2eeb-4d8b-97a3-974a81734fd5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2085996904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2085996904 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.3270999448 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9528519 ps |
| CPU time | 0.37 seconds |
| Started | Aug 07 04:33:00 PM PDT 24 |
| Finished | Aug 07 04:33:01 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-7229e0ab-34e0-4873-84f0-509ee7df0285 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3270999448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3270999448 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.2676359660 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8503212 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:33:44 PM PDT 24 |
| Finished | Aug 07 04:33:44 PM PDT 24 |
| Peak memory | 145448 kb |
| Host | smart-edad8f14-b9ec-4940-a007-4cc6f607add4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2676359660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2676359660 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.667968087 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9328608 ps |
| CPU time | 0.42 seconds |
| Started | Aug 07 04:32:59 PM PDT 24 |
| Finished | Aug 07 04:33:00 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-9fdb35d3-3fa6-4e91-bc3b-2ada78c00a53 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=667968087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.667968087 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.1228369146 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8679159 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:33:05 PM PDT 24 |
| Finished | Aug 07 04:33:06 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-9c3bc163-c9ea-4b90-b858-1a14e49ede36 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1228369146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1228369146 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.195427167 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26233568 ps |
| CPU time | 0.37 seconds |
| Started | Aug 07 04:33:20 PM PDT 24 |
| Finished | Aug 07 04:33:20 PM PDT 24 |
| Peak memory | 145476 kb |
| Host | smart-c1a2f609-ca31-4fe1-bd0b-64c056b91e0a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=195427167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.195427167 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4266179028 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 29251657 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:33:28 PM PDT 24 |
| Finished | Aug 07 04:33:33 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-69929f65-1b0f-4549-b8b5-f9c786482d5b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4266179028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.4266179028 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1348531509 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27486375 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:33:14 PM PDT 24 |
| Finished | Aug 07 04:33:15 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-534826ed-a3d5-4f4b-b2ee-8f52805a5fa9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1348531509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1348531509 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.65694362 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26678030 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:33:06 PM PDT 24 |
| Finished | Aug 07 04:33:06 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-32eae041-4543-4557-949a-88ed7f03bd00 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=65694362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.65694362 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1470076768 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27643335 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:33:11 PM PDT 24 |
| Finished | Aug 07 04:33:11 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-71faf8b6-483b-4753-ba84-fe4d15f8c4fe |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1470076768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1470076768 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2968482384 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 26778046 ps |
| CPU time | 0.44 seconds |
| Started | Aug 07 04:33:00 PM PDT 24 |
| Finished | Aug 07 04:33:00 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-5c4439b0-0993-4ac3-bcb4-984b2ad72ec5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2968482384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2968482384 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4103709663 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 25783999 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:33:13 PM PDT 24 |
| Finished | Aug 07 04:33:14 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-2683fd4f-91c9-4a84-a6a8-c0bc872bbc17 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4103709663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.4103709663 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1015987664 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 25104309 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:32:58 PM PDT 24 |
| Finished | Aug 07 04:32:58 PM PDT 24 |
| Peak memory | 145420 kb |
| Host | smart-4fb4d9ac-4a77-4b72-b4b2-1b98307d655a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1015987664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1015987664 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1849735376 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 27424471 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:32:54 PM PDT 24 |
| Finished | Aug 07 04:32:55 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-b3d7ce44-ea06-4fef-ad26-e96895a4aa86 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1849735376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1849735376 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3155097274 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27724890 ps |
| CPU time | 0.41 seconds |
| Started | Aug 07 04:33:17 PM PDT 24 |
| Finished | Aug 07 04:33:17 PM PDT 24 |
| Peak memory | 145516 kb |
| Host | smart-9b002405-027e-440f-b2ce-b29552e2c8ae |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3155097274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3155097274 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.476522258 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27042497 ps |
| CPU time | 0.42 seconds |
| Started | Aug 07 04:33:31 PM PDT 24 |
| Finished | Aug 07 04:33:32 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-fd0bd94b-6c75-40de-bf70-f0decf30cccf |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=476522258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.476522258 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3981745381 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 27554569 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:32:54 PM PDT 24 |
| Finished | Aug 07 04:32:55 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-3a8dcc07-1337-44f5-b4ce-3f177ecb5189 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3981745381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3981745381 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3601114722 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27354710 ps |
| CPU time | 0.42 seconds |
| Started | Aug 07 04:32:59 PM PDT 24 |
| Finished | Aug 07 04:33:00 PM PDT 24 |
| Peak memory | 145860 kb |
| Host | smart-c162fc39-51f0-43e3-aaac-3601a10d3915 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3601114722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3601114722 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3660134383 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26881132 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:32:56 PM PDT 24 |
| Finished | Aug 07 04:32:57 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-9c4d9924-03ab-49d1-994f-2562a07721e7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3660134383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3660134383 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2378299663 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 29491821 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:33:19 PM PDT 24 |
| Finished | Aug 07 04:33:20 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-da58c1f6-d082-4d78-ad0a-09fc7244ab98 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2378299663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2378299663 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2886142413 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28710096 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:32:54 PM PDT 24 |
| Finished | Aug 07 04:32:54 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-b4df78e3-3b66-4a71-bf7e-00f6075a73ac |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2886142413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2886142413 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3395580668 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27240912 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:33:01 PM PDT 24 |
| Finished | Aug 07 04:33:02 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-ed967347-ec24-4bf2-92a2-1060d07be0c2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3395580668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3395580668 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1944656979 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 26737421 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:33:22 PM PDT 24 |
| Finished | Aug 07 04:33:23 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-740ff11a-6b5b-48ae-baaf-f1023c0bcfb3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1944656979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1944656979 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3269865060 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26568962 ps |
| CPU time | 0.41 seconds |
| Started | Aug 07 04:33:02 PM PDT 24 |
| Finished | Aug 07 04:33:03 PM PDT 24 |
| Peak memory | 145512 kb |
| Host | smart-76b3f513-4c4c-486c-9ae0-e84b0c88113f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3269865060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3269865060 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.419791640 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27853055 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:32:58 PM PDT 24 |
| Finished | Aug 07 04:32:58 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-457970c2-ae72-47ff-b402-7ad0ff6bfec0 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=419791640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.419791640 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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