| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.85 | 100.00 | 97.92 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.28 | 88.28 | 100.00 | 100.00 | 93.75 | 93.75 | 96.43 | 96.43 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/17.prim_async_alert.1524160019 |
| 91.41 | 3.13 | 100.00 | 0.00 | 93.75 | 0.00 | 96.43 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/2.prim_sync_alert.3118598670 |
| 93.90 | 2.49 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 3.57 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 9.30 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1547279924 |
| 94.50 | 0.60 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/1.prim_async_alert.1701488486 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2967040134 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.627139863 |
| /workspace/coverage/default/10.prim_async_alert.2825959077 |
| /workspace/coverage/default/11.prim_async_alert.2479280321 |
| /workspace/coverage/default/12.prim_async_alert.1932878699 |
| /workspace/coverage/default/13.prim_async_alert.3730539722 |
| /workspace/coverage/default/14.prim_async_alert.1343647889 |
| /workspace/coverage/default/15.prim_async_alert.3048375339 |
| /workspace/coverage/default/16.prim_async_alert.2555841133 |
| /workspace/coverage/default/18.prim_async_alert.1343068384 |
| /workspace/coverage/default/19.prim_async_alert.941746385 |
| /workspace/coverage/default/2.prim_async_alert.171820214 |
| /workspace/coverage/default/3.prim_async_alert.3409366041 |
| /workspace/coverage/default/4.prim_async_alert.164202848 |
| /workspace/coverage/default/5.prim_async_alert.1636022376 |
| /workspace/coverage/default/6.prim_async_alert.2704935236 |
| /workspace/coverage/default/7.prim_async_alert.3905818180 |
| /workspace/coverage/default/8.prim_async_alert.2500120258 |
| /workspace/coverage/default/9.prim_async_alert.582939435 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4110929167 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3396114746 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.35936298 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.897744090 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3836119307 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2279204054 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3654346014 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2651559663 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4043850648 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.688990747 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4097441188 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2238336134 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1268890471 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3084860279 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1284637540 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2290813627 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.3897077749 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.11139908 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.191430151 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.2311994383 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3649444493 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.834087952 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1783026853 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.2313392912 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.636691898 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.3868571324 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.3762669338 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.2556093553 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.1450011423 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.1190513408 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.1255589667 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1902602278 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.650789542 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.3935909142 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.1564755538 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.332269427 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.585094520 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3653281125 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1720803313 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1083554786 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1011656776 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1025204647 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.174941401 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2721555491 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3310283740 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2310971573 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3985232831 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2507939027 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3978644297 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2572060502 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.33668467 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3473861086 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.622312005 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.481075078 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4057961447 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/11.prim_async_alert.2479280321 | Aug 08 05:14:17 PM PDT 24 | Aug 08 05:14:17 PM PDT 24 | 12768199 ps | ||
| T2 | /workspace/coverage/default/12.prim_async_alert.1932878699 | Aug 08 05:14:19 PM PDT 24 | Aug 08 05:14:19 PM PDT 24 | 11524117 ps | ||
| T3 | /workspace/coverage/default/3.prim_async_alert.3409366041 | Aug 08 05:14:09 PM PDT 24 | Aug 08 05:14:09 PM PDT 24 | 11404735 ps | ||
| T8 | /workspace/coverage/default/14.prim_async_alert.1343647889 | Aug 08 05:14:11 PM PDT 24 | Aug 08 05:14:12 PM PDT 24 | 11102269 ps | ||
| T10 | /workspace/coverage/default/10.prim_async_alert.2825959077 | Aug 08 05:14:10 PM PDT 24 | Aug 08 05:14:10 PM PDT 24 | 11305663 ps | ||
| T14 | /workspace/coverage/default/9.prim_async_alert.582939435 | Aug 08 05:14:06 PM PDT 24 | Aug 08 05:14:06 PM PDT 24 | 11149612 ps | ||
| T15 | /workspace/coverage/default/18.prim_async_alert.1343068384 | Aug 08 05:14:13 PM PDT 24 | Aug 08 05:14:13 PM PDT 24 | 10585538 ps | ||
| T7 | /workspace/coverage/default/17.prim_async_alert.1524160019 | Aug 08 05:14:08 PM PDT 24 | Aug 08 05:14:09 PM PDT 24 | 11313061 ps | ||
| T16 | /workspace/coverage/default/13.prim_async_alert.3730539722 | Aug 08 05:14:23 PM PDT 24 | Aug 08 05:14:23 PM PDT 24 | 11807642 ps | ||
| T17 | /workspace/coverage/default/19.prim_async_alert.941746385 | Aug 08 05:14:20 PM PDT 24 | Aug 08 05:14:21 PM PDT 24 | 11324836 ps | ||
| T18 | /workspace/coverage/default/0.prim_async_alert.627139863 | Aug 08 05:14:12 PM PDT 24 | Aug 08 05:14:13 PM PDT 24 | 11748587 ps | ||
| T37 | /workspace/coverage/default/2.prim_async_alert.171820214 | Aug 08 05:14:14 PM PDT 24 | Aug 08 05:14:15 PM PDT 24 | 10998507 ps | ||
| T19 | /workspace/coverage/default/15.prim_async_alert.3048375339 | Aug 08 05:14:16 PM PDT 24 | Aug 08 05:14:16 PM PDT 24 | 11192358 ps | ||
| T20 | /workspace/coverage/default/16.prim_async_alert.2555841133 | Aug 08 05:14:08 PM PDT 24 | Aug 08 05:14:08 PM PDT 24 | 11462797 ps | ||
| T47 | /workspace/coverage/default/6.prim_async_alert.2704935236 | Aug 08 05:14:12 PM PDT 24 | Aug 08 05:14:13 PM PDT 24 | 11878639 ps | ||
| T48 | /workspace/coverage/default/4.prim_async_alert.164202848 | Aug 08 05:14:15 PM PDT 24 | Aug 08 05:14:15 PM PDT 24 | 11016854 ps | ||
| T12 | /workspace/coverage/default/5.prim_async_alert.1636022376 | Aug 08 05:14:17 PM PDT 24 | Aug 08 05:14:18 PM PDT 24 | 11491137 ps | ||
| T21 | /workspace/coverage/default/8.prim_async_alert.2500120258 | Aug 08 05:14:06 PM PDT 24 | Aug 08 05:14:06 PM PDT 24 | 10057228 ps | ||
| T9 | /workspace/coverage/default/1.prim_async_alert.1701488486 | Aug 08 05:14:11 PM PDT 24 | Aug 08 05:14:12 PM PDT 24 | 11308036 ps | ||
| T11 | /workspace/coverage/default/7.prim_async_alert.3905818180 | Aug 08 05:14:13 PM PDT 24 | Aug 08 05:14:13 PM PDT 24 | 12164127 ps | ||
| T13 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1547279924 | Aug 08 05:15:11 PM PDT 24 | Aug 08 05:15:11 PM PDT 24 | 29483598 ps | ||
| T4 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2967040134 | Aug 08 05:15:19 PM PDT 24 | Aug 08 05:15:19 PM PDT 24 | 28952452 ps | ||
| T39 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4043850648 | Aug 08 05:15:10 PM PDT 24 | Aug 08 05:15:10 PM PDT 24 | 30642371 ps | ||
| T40 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2651559663 | Aug 08 05:15:17 PM PDT 24 | Aug 08 05:15:18 PM PDT 24 | 29871851 ps | ||
| T41 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3396114746 | Aug 08 05:15:35 PM PDT 24 | Aug 08 05:15:36 PM PDT 24 | 31106511 ps | ||
| T42 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3654346014 | Aug 08 05:15:24 PM PDT 24 | Aug 08 05:15:24 PM PDT 24 | 28894457 ps | ||
| T43 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4110929167 | Aug 08 05:15:15 PM PDT 24 | Aug 08 05:15:15 PM PDT 24 | 31208869 ps | ||
| T44 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2238336134 | Aug 08 05:15:17 PM PDT 24 | Aug 08 05:15:17 PM PDT 24 | 30166985 ps | ||
| T45 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.688990747 | Aug 08 05:15:11 PM PDT 24 | Aug 08 05:15:13 PM PDT 24 | 30287928 ps | ||
| T46 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2279204054 | Aug 08 05:15:27 PM PDT 24 | Aug 08 05:15:27 PM PDT 24 | 29223436 ps | ||
| T49 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3836119307 | Aug 08 05:15:32 PM PDT 24 | Aug 08 05:15:33 PM PDT 24 | 27877127 ps | ||
| T50 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.897744090 | Aug 08 05:15:14 PM PDT 24 | Aug 08 05:15:14 PM PDT 24 | 30420083 ps | ||
| T51 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4097441188 | Aug 08 05:15:19 PM PDT 24 | Aug 08 05:15:20 PM PDT 24 | 30690302 ps | ||
| T52 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1284637540 | Aug 08 05:15:17 PM PDT 24 | Aug 08 05:15:18 PM PDT 24 | 30600035 ps | ||
| T53 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1268890471 | Aug 08 05:15:14 PM PDT 24 | Aug 08 05:15:15 PM PDT 24 | 29032475 ps | ||
| T54 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.35936298 | Aug 08 05:15:15 PM PDT 24 | Aug 08 05:15:16 PM PDT 24 | 29850058 ps | ||
| T55 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2290813627 | Aug 08 05:15:10 PM PDT 24 | Aug 08 05:15:10 PM PDT 24 | 30728229 ps | ||
| T56 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3084860279 | Aug 08 05:15:10 PM PDT 24 | Aug 08 05:15:11 PM PDT 24 | 33196597 ps | ||
| T31 | /workspace/coverage/sync_alert/2.prim_sync_alert.3118598670 | Aug 08 05:15:14 PM PDT 24 | Aug 08 05:15:15 PM PDT 24 | 8944312 ps | ||
| T22 | /workspace/coverage/sync_alert/13.prim_sync_alert.834087952 | Aug 08 05:15:14 PM PDT 24 | Aug 08 05:15:15 PM PDT 24 | 9247804 ps | ||
| T32 | /workspace/coverage/sync_alert/4.prim_sync_alert.1190513408 | Aug 08 05:15:15 PM PDT 24 | Aug 08 05:15:15 PM PDT 24 | 8917668 ps | ||
| T23 | /workspace/coverage/sync_alert/17.prim_sync_alert.3868571324 | Aug 08 05:15:26 PM PDT 24 | Aug 08 05:15:26 PM PDT 24 | 9485139 ps | ||
| T24 | /workspace/coverage/sync_alert/1.prim_sync_alert.11139908 | Aug 08 05:15:12 PM PDT 24 | Aug 08 05:15:13 PM PDT 24 | 9699811 ps | ||
| T33 | /workspace/coverage/sync_alert/12.prim_sync_alert.3649444493 | Aug 08 05:15:25 PM PDT 24 | Aug 08 05:15:25 PM PDT 24 | 9771756 ps | ||
| T25 | /workspace/coverage/sync_alert/8.prim_sync_alert.3935909142 | Aug 08 05:15:12 PM PDT 24 | Aug 08 05:15:13 PM PDT 24 | 9180683 ps | ||
| T34 | /workspace/coverage/sync_alert/7.prim_sync_alert.650789542 | Aug 08 05:15:14 PM PDT 24 | Aug 08 05:15:15 PM PDT 24 | 9209026 ps | ||
| T35 | /workspace/coverage/sync_alert/16.prim_sync_alert.636691898 | Aug 08 05:15:14 PM PDT 24 | Aug 08 05:15:15 PM PDT 24 | 7960267 ps | ||
| T36 | /workspace/coverage/sync_alert/5.prim_sync_alert.1255589667 | Aug 08 05:15:15 PM PDT 24 | Aug 08 05:15:15 PM PDT 24 | 10192791 ps | ||
| T38 | /workspace/coverage/sync_alert/0.prim_sync_alert.3897077749 | Aug 08 05:15:21 PM PDT 24 | Aug 08 05:15:22 PM PDT 24 | 9108424 ps | ||
| T57 | /workspace/coverage/sync_alert/15.prim_sync_alert.2313392912 | Aug 08 05:15:16 PM PDT 24 | Aug 08 05:15:17 PM PDT 24 | 8375087 ps | ||
| T58 | /workspace/coverage/sync_alert/18.prim_sync_alert.3762669338 | Aug 08 05:15:12 PM PDT 24 | Aug 08 05:15:13 PM PDT 24 | 9395016 ps | ||
| T59 | /workspace/coverage/sync_alert/10.prim_sync_alert.191430151 | Aug 08 05:15:13 PM PDT 24 | Aug 08 05:15:14 PM PDT 24 | 8482740 ps | ||
| T26 | /workspace/coverage/sync_alert/3.prim_sync_alert.1450011423 | Aug 08 05:15:15 PM PDT 24 | Aug 08 05:15:16 PM PDT 24 | 9024190 ps | ||
| T60 | /workspace/coverage/sync_alert/19.prim_sync_alert.2556093553 | Aug 08 05:15:17 PM PDT 24 | Aug 08 05:15:17 PM PDT 24 | 8638425 ps | ||
| T27 | /workspace/coverage/sync_alert/6.prim_sync_alert.1902602278 | Aug 08 05:15:22 PM PDT 24 | Aug 08 05:15:23 PM PDT 24 | 10188994 ps | ||
| T28 | /workspace/coverage/sync_alert/14.prim_sync_alert.1783026853 | Aug 08 05:15:16 PM PDT 24 | Aug 08 05:15:17 PM PDT 24 | 10142637 ps | ||
| T29 | /workspace/coverage/sync_alert/11.prim_sync_alert.2311994383 | Aug 08 05:15:14 PM PDT 24 | Aug 08 05:15:15 PM PDT 24 | 10461934 ps | ||
| T30 | /workspace/coverage/sync_alert/9.prim_sync_alert.1564755538 | Aug 08 05:15:23 PM PDT 24 | Aug 08 05:15:23 PM PDT 24 | 8618485 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2572060502 | Aug 08 05:15:17 PM PDT 24 | Aug 08 05:15:17 PM PDT 24 | 27953664 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3985232831 | Aug 08 05:15:42 PM PDT 24 | Aug 08 05:15:42 PM PDT 24 | 31280521 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1011656776 | Aug 08 05:15:14 PM PDT 24 | Aug 08 05:15:14 PM PDT 24 | 27916651 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2310971573 | Aug 08 05:15:18 PM PDT 24 | Aug 08 05:15:18 PM PDT 24 | 27434511 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.481075078 | Aug 08 05:15:11 PM PDT 24 | Aug 08 05:15:13 PM PDT 24 | 26743329 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3310283740 | Aug 08 05:15:15 PM PDT 24 | Aug 08 05:15:16 PM PDT 24 | 28144866 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.332269427 | Aug 08 05:15:30 PM PDT 24 | Aug 08 05:15:31 PM PDT 24 | 28308758 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4057961447 | Aug 08 05:15:18 PM PDT 24 | Aug 08 05:15:18 PM PDT 24 | 27611636 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2507939027 | Aug 08 05:15:09 PM PDT 24 | Aug 08 05:15:10 PM PDT 24 | 27099533 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.585094520 | Aug 08 05:15:18 PM PDT 24 | Aug 08 05:15:19 PM PDT 24 | 27819566 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.622312005 | Aug 08 05:15:38 PM PDT 24 | Aug 08 05:15:39 PM PDT 24 | 27764562 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1720803313 | Aug 08 05:15:18 PM PDT 24 | Aug 08 05:15:18 PM PDT 24 | 27436718 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2721555491 | Aug 08 05:15:18 PM PDT 24 | Aug 08 05:15:19 PM PDT 24 | 27538937 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1083554786 | Aug 08 05:15:20 PM PDT 24 | Aug 08 05:15:20 PM PDT 24 | 28824314 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.33668467 | Aug 08 05:15:10 PM PDT 24 | Aug 08 05:15:10 PM PDT 24 | 25952037 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.174941401 | Aug 08 05:15:21 PM PDT 24 | Aug 08 05:15:21 PM PDT 24 | 26658670 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3473861086 | Aug 08 05:15:11 PM PDT 24 | Aug 08 05:15:11 PM PDT 24 | 26191987 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1025204647 | Aug 08 05:15:16 PM PDT 24 | Aug 08 05:15:17 PM PDT 24 | 27143855 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3978644297 | Aug 08 05:15:14 PM PDT 24 | Aug 08 05:15:14 PM PDT 24 | 29848547 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3653281125 | Aug 08 05:15:19 PM PDT 24 | Aug 08 05:15:19 PM PDT 24 | 26535114 ps |
| Test location | /workspace/coverage/default/17.prim_async_alert.1524160019 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11313061 ps |
| CPU time | 0.42 seconds |
| Started | Aug 08 05:14:08 PM PDT 24 |
| Finished | Aug 08 05:14:09 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-9664e85e-50e9-4bc6-b17c-88d175836517 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1524160019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1524160019 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.3118598670 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8944312 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:14 PM PDT 24 |
| Finished | Aug 08 05:15:15 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-feea2b1c-cf26-4af0-9fad-08550997a1dd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3118598670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3118598670 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1547279924 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 29483598 ps |
| CPU time | 0.41 seconds |
| Started | Aug 08 05:15:11 PM PDT 24 |
| Finished | Aug 08 05:15:11 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-af0cf092-141a-4180-bada-c401283b6b51 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1547279924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1547279924 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1701488486 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11308036 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:14:11 PM PDT 24 |
| Finished | Aug 08 05:14:12 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-92a60bce-e200-409f-bf71-5b41d8ff9164 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1701488486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1701488486 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2967040134 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28952452 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:19 PM PDT 24 |
| Finished | Aug 08 05:15:19 PM PDT 24 |
| Peak memory | 145344 kb |
| Host | smart-8d643fd8-e3ef-4c9e-b6cc-771f4d7dc09c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2967040134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2967040134 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.627139863 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11748587 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:14:12 PM PDT 24 |
| Finished | Aug 08 05:14:13 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-b23da1e9-e2e4-4e0b-900c-8fbe0fd7a942 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627139863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.627139863 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.2825959077 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11305663 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:14:10 PM PDT 24 |
| Finished | Aug 08 05:14:10 PM PDT 24 |
| Peak memory | 145728 kb |
| Host | smart-1b9450f8-dbfa-41b7-8ecb-fc9f60e5f3fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2825959077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2825959077 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.2479280321 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12768199 ps |
| CPU time | 0.42 seconds |
| Started | Aug 08 05:14:17 PM PDT 24 |
| Finished | Aug 08 05:14:17 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-7abf6bc2-15fb-4a7f-89f1-3b98fa6dbb08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479280321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2479280321 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.1932878699 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11524117 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:14:19 PM PDT 24 |
| Finished | Aug 08 05:14:19 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-6c721bf7-0789-45dc-be8d-94d44b9f0edf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932878699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1932878699 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3730539722 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11807642 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:14:23 PM PDT 24 |
| Finished | Aug 08 05:14:23 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-0a43de25-9e66-4392-b0c9-510df8997fbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730539722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3730539722 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1343647889 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11102269 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:14:11 PM PDT 24 |
| Finished | Aug 08 05:14:12 PM PDT 24 |
| Peak memory | 145728 kb |
| Host | smart-90b45a5c-a392-43c4-9484-31e31bf69098 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1343647889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1343647889 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.3048375339 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11192358 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:14:16 PM PDT 24 |
| Finished | Aug 08 05:14:16 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-7d953baf-8fc3-4218-94c2-cd2ebd5dcc89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048375339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3048375339 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.2555841133 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11462797 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:14:08 PM PDT 24 |
| Finished | Aug 08 05:14:08 PM PDT 24 |
| Peak memory | 145708 kb |
| Host | smart-677291fa-a2ca-49ea-8607-ad32ef61017d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555841133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2555841133 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.1343068384 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10585538 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:14:13 PM PDT 24 |
| Finished | Aug 08 05:14:13 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-3f0d0e87-3210-4513-b204-a0ddc4cba4c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1343068384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1343068384 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.941746385 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11324836 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:14:20 PM PDT 24 |
| Finished | Aug 08 05:14:21 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-e14c0f8e-bd85-49d4-ad44-5135f3f97368 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=941746385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.941746385 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.171820214 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10998507 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:14:14 PM PDT 24 |
| Finished | Aug 08 05:14:15 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-a44c4b12-69c6-4e83-9e46-c3508fb353af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=171820214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.171820214 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.3409366041 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11404735 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:14:09 PM PDT 24 |
| Finished | Aug 08 05:14:09 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-120417da-5f8e-4f6c-8a08-1309960e5913 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409366041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3409366041 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.164202848 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11016854 ps |
| CPU time | 0.41 seconds |
| Started | Aug 08 05:14:15 PM PDT 24 |
| Finished | Aug 08 05:14:15 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-5da28215-4d99-4a42-af82-8b79adae7f17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=164202848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.164202848 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.1636022376 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11491137 ps |
| CPU time | 0.42 seconds |
| Started | Aug 08 05:14:17 PM PDT 24 |
| Finished | Aug 08 05:14:18 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-cd562ba4-b205-48a4-85a1-c8a84341f065 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636022376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1636022376 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2704935236 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11878639 ps |
| CPU time | 0.41 seconds |
| Started | Aug 08 05:14:12 PM PDT 24 |
| Finished | Aug 08 05:14:13 PM PDT 24 |
| Peak memory | 145748 kb |
| Host | smart-4727f86a-cdd9-4311-b6d4-5e06ee7cb255 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704935236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2704935236 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.3905818180 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12164127 ps |
| CPU time | 0.37 seconds |
| Started | Aug 08 05:14:13 PM PDT 24 |
| Finished | Aug 08 05:14:13 PM PDT 24 |
| Peak memory | 145680 kb |
| Host | smart-cf40a942-db9a-4d08-8234-e0fd9fe32cb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905818180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3905818180 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.2500120258 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10057228 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:14:06 PM PDT 24 |
| Finished | Aug 08 05:14:06 PM PDT 24 |
| Peak memory | 145900 kb |
| Host | smart-6d49ddc0-915b-4da6-aace-01e7aa79e0af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2500120258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2500120258 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.582939435 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11149612 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:14:06 PM PDT 24 |
| Finished | Aug 08 05:14:06 PM PDT 24 |
| Peak memory | 145680 kb |
| Host | smart-4e58460c-82d3-47bd-8bf7-50d0a1f6a325 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=582939435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.582939435 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4110929167 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 31208869 ps |
| CPU time | 0.41 seconds |
| Started | Aug 08 05:15:15 PM PDT 24 |
| Finished | Aug 08 05:15:15 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-827ec289-51dc-497b-9e71-8a43cfb6cdcb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4110929167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4110929167 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3396114746 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 31106511 ps |
| CPU time | 0.42 seconds |
| Started | Aug 08 05:15:35 PM PDT 24 |
| Finished | Aug 08 05:15:36 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-c21f777b-bb02-46cd-be68-81a4b86b0a08 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3396114746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3396114746 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.35936298 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 29850058 ps |
| CPU time | 0.44 seconds |
| Started | Aug 08 05:15:15 PM PDT 24 |
| Finished | Aug 08 05:15:16 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-805137f1-1642-4f57-b3a5-96a70856193e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=35936298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.35936298 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.897744090 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30420083 ps |
| CPU time | 0.41 seconds |
| Started | Aug 08 05:15:14 PM PDT 24 |
| Finished | Aug 08 05:15:14 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-ba727919-30a5-4b85-9421-868a41a48757 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=897744090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.897744090 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3836119307 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 27877127 ps |
| CPU time | 0.41 seconds |
| Started | Aug 08 05:15:32 PM PDT 24 |
| Finished | Aug 08 05:15:33 PM PDT 24 |
| Peak memory | 145272 kb |
| Host | smart-ea3226ae-438f-41aa-8b9b-166a0899bd66 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3836119307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3836119307 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2279204054 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29223436 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:15:27 PM PDT 24 |
| Finished | Aug 08 05:15:27 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-fdaa5084-6595-49fd-bcce-dae1f21d2ea1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2279204054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2279204054 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3654346014 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 28894457 ps |
| CPU time | 0.41 seconds |
| Started | Aug 08 05:15:24 PM PDT 24 |
| Finished | Aug 08 05:15:24 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-8515c295-4f7f-4b27-9082-16d56b47ed6e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3654346014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3654346014 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2651559663 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29871851 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:15:17 PM PDT 24 |
| Finished | Aug 08 05:15:18 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-3648094a-08af-4c0b-b83c-3dd41e1860e8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2651559663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2651559663 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4043850648 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 30642371 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:15:10 PM PDT 24 |
| Finished | Aug 08 05:15:10 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-55de6ee9-67bf-4ad7-b753-ebeba2051683 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4043850648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.4043850648 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.688990747 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30287928 ps |
| CPU time | 0.43 seconds |
| Started | Aug 08 05:15:11 PM PDT 24 |
| Finished | Aug 08 05:15:13 PM PDT 24 |
| Peak memory | 145276 kb |
| Host | smart-4143c7f7-3bfa-4c50-8226-e7afb7fc2cb3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=688990747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.688990747 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4097441188 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30690302 ps |
| CPU time | 0.43 seconds |
| Started | Aug 08 05:15:19 PM PDT 24 |
| Finished | Aug 08 05:15:20 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-59f05d55-8827-4469-b44b-ca60c7aacf3a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4097441188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.4097441188 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2238336134 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30166985 ps |
| CPU time | 0.42 seconds |
| Started | Aug 08 05:15:17 PM PDT 24 |
| Finished | Aug 08 05:15:17 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-54ce2ba9-8c92-4c6d-9ad7-e42f2f637092 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2238336134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2238336134 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1268890471 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 29032475 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:14 PM PDT 24 |
| Finished | Aug 08 05:15:15 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-564d9529-b540-43ff-b03c-88ad59dd162e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1268890471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1268890471 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3084860279 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 33196597 ps |
| CPU time | 0.41 seconds |
| Started | Aug 08 05:15:10 PM PDT 24 |
| Finished | Aug 08 05:15:11 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-20daf5ab-84b5-4c2b-a300-76331592e153 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3084860279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3084860279 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1284637540 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30600035 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:15:17 PM PDT 24 |
| Finished | Aug 08 05:15:18 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-6fe23988-47b4-46f1-93a8-0bf017da068e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1284637540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1284637540 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2290813627 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 30728229 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:15:10 PM PDT 24 |
| Finished | Aug 08 05:15:10 PM PDT 24 |
| Peak memory | 145260 kb |
| Host | smart-9d262cf5-c591-409a-b005-9da307b4ffa8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2290813627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2290813627 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.3897077749 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9108424 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:15:21 PM PDT 24 |
| Finished | Aug 08 05:15:22 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-85c527e2-18ac-4156-a7f3-4a1d547f9c13 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3897077749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3897077749 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.11139908 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9699811 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:12 PM PDT 24 |
| Finished | Aug 08 05:15:13 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-ed0d03fd-5d91-42e7-b4f2-31bb73577b88 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=11139908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.11139908 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.191430151 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8482740 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:15:13 PM PDT 24 |
| Finished | Aug 08 05:15:14 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-d6c4e625-a861-4dda-86b5-583986f36722 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=191430151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.191430151 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.2311994383 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10461934 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:14 PM PDT 24 |
| Finished | Aug 08 05:15:15 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-8bc0a527-8f0c-4b7d-9860-cdf321cbee89 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2311994383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2311994383 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3649444493 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9771756 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:25 PM PDT 24 |
| Finished | Aug 08 05:15:25 PM PDT 24 |
| Peak memory | 145488 kb |
| Host | smart-d48777d9-41e4-492f-8f40-3d59a6f69e41 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3649444493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3649444493 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.834087952 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9247804 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:14 PM PDT 24 |
| Finished | Aug 08 05:15:15 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-95e66c60-2391-4663-90d9-0f2772a3531f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=834087952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.834087952 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1783026853 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10142637 ps |
| CPU time | 0.37 seconds |
| Started | Aug 08 05:15:16 PM PDT 24 |
| Finished | Aug 08 05:15:17 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-9c2751d5-d766-463d-b637-35b621d30520 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1783026853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1783026853 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.2313392912 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8375087 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:15:16 PM PDT 24 |
| Finished | Aug 08 05:15:17 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-7ce9dbeb-195c-4237-b383-57da8a01f932 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2313392912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2313392912 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.636691898 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7960267 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:15:14 PM PDT 24 |
| Finished | Aug 08 05:15:15 PM PDT 24 |
| Peak memory | 145392 kb |
| Host | smart-7b8e4e28-63a7-4c8b-a87e-c6e7306b6094 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=636691898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.636691898 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.3868571324 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9485139 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:26 PM PDT 24 |
| Finished | Aug 08 05:15:26 PM PDT 24 |
| Peak memory | 145520 kb |
| Host | smart-c01bdecb-ecc9-491f-8e39-06f3015c8d91 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3868571324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3868571324 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.3762669338 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9395016 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:15:12 PM PDT 24 |
| Finished | Aug 08 05:15:13 PM PDT 24 |
| Peak memory | 145520 kb |
| Host | smart-9e2b6011-dc32-47ba-aa61-4d50237f80f5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3762669338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3762669338 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.2556093553 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8638425 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:15:17 PM PDT 24 |
| Finished | Aug 08 05:15:17 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-88c89174-38db-4a69-ab23-a2b229064bbc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2556093553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2556093553 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.1450011423 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9024190 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:15:15 PM PDT 24 |
| Finished | Aug 08 05:15:16 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-20bbcb52-d9b9-4453-b018-c18de41406d0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1450011423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1450011423 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.1190513408 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8917668 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:15 PM PDT 24 |
| Finished | Aug 08 05:15:15 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-cd10a86e-1ba6-4e12-8b71-72867849daba |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1190513408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1190513408 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1255589667 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10192791 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:15 PM PDT 24 |
| Finished | Aug 08 05:15:15 PM PDT 24 |
| Peak memory | 145524 kb |
| Host | smart-83bfed59-0e90-4abf-95b7-339212e30e23 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1255589667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1255589667 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1902602278 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10188994 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:15:22 PM PDT 24 |
| Finished | Aug 08 05:15:23 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-d1e70de2-c34c-4867-9add-8edfeec03396 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1902602278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1902602278 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.650789542 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9209026 ps |
| CPU time | 0.37 seconds |
| Started | Aug 08 05:15:14 PM PDT 24 |
| Finished | Aug 08 05:15:15 PM PDT 24 |
| Peak memory | 145476 kb |
| Host | smart-e54c3f4a-d96c-4a07-9766-bd37f715a797 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=650789542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.650789542 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.3935909142 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9180683 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:15:12 PM PDT 24 |
| Finished | Aug 08 05:15:13 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-c54e6c18-eba3-4b57-b517-ecb5e4a2be44 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3935909142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3935909142 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.1564755538 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8618485 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:23 PM PDT 24 |
| Finished | Aug 08 05:15:23 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-7bb12f0d-c020-4ba5-b9e2-3f59e16f9327 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1564755538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1564755538 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.332269427 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28308758 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:30 PM PDT 24 |
| Finished | Aug 08 05:15:31 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-c1784049-95a2-4f77-a33e-d45db9261900 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=332269427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.332269427 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.585094520 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27819566 ps |
| CPU time | 0.42 seconds |
| Started | Aug 08 05:15:18 PM PDT 24 |
| Finished | Aug 08 05:15:19 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-516400d4-69b7-4c4b-9b6a-98533a06ba01 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=585094520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.585094520 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3653281125 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26535114 ps |
| CPU time | 0.38 seconds |
| Started | Aug 08 05:15:19 PM PDT 24 |
| Finished | Aug 08 05:15:19 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-f2f9af3e-dc75-44b2-a2ba-05bfd5189413 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3653281125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3653281125 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1720803313 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27436718 ps |
| CPU time | 0.41 seconds |
| Started | Aug 08 05:15:18 PM PDT 24 |
| Finished | Aug 08 05:15:18 PM PDT 24 |
| Peak memory | 145500 kb |
| Host | smart-368b4edb-2203-4fea-9f32-30b3e36b2106 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1720803313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1720803313 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1083554786 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28824314 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:20 PM PDT 24 |
| Finished | Aug 08 05:15:20 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-cc18bdd6-a055-4480-a61a-3e1e78e52632 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1083554786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1083554786 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1011656776 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27916651 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:14 PM PDT 24 |
| Finished | Aug 08 05:15:14 PM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-a16e50b5-3b76-4a3d-b8ad-164969e36ee5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1011656776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1011656776 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1025204647 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27143855 ps |
| CPU time | 0.44 seconds |
| Started | Aug 08 05:15:16 PM PDT 24 |
| Finished | Aug 08 05:15:17 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-5fe443ca-1d83-484f-88f0-9f5e1cb96d59 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1025204647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1025204647 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.174941401 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26658670 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:21 PM PDT 24 |
| Finished | Aug 08 05:15:21 PM PDT 24 |
| Peak memory | 145520 kb |
| Host | smart-744f59e6-4fb7-42aa-b011-fe1f20e93021 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=174941401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.174941401 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2721555491 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27538937 ps |
| CPU time | 0.41 seconds |
| Started | Aug 08 05:15:18 PM PDT 24 |
| Finished | Aug 08 05:15:19 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-bbfa2196-5846-42a6-8636-502c3a883d02 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2721555491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2721555491 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3310283740 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 28144866 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:15:15 PM PDT 24 |
| Finished | Aug 08 05:15:16 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-69beebb9-7645-41a3-a364-39819ea22eb7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3310283740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3310283740 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2310971573 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27434511 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:18 PM PDT 24 |
| Finished | Aug 08 05:15:18 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-33730d35-df83-4f15-89b9-34066e72f13e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2310971573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2310971573 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3985232831 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 31280521 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:15:42 PM PDT 24 |
| Finished | Aug 08 05:15:42 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-9a64150e-12b2-45fd-9132-3ebe8689805e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3985232831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3985232831 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2507939027 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27099533 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:15:09 PM PDT 24 |
| Finished | Aug 08 05:15:10 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-48086c3f-69c6-49f4-893a-912530a7affe |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2507939027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2507939027 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3978644297 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 29848547 ps |
| CPU time | 0.42 seconds |
| Started | Aug 08 05:15:14 PM PDT 24 |
| Finished | Aug 08 05:15:14 PM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-05906aa0-5cb1-4614-9e36-0811ac8518d9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3978644297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3978644297 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2572060502 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 27953664 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:15:17 PM PDT 24 |
| Finished | Aug 08 05:15:17 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-436067b5-2b67-4e4d-8570-f06bbe0e8fc9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2572060502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2572060502 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.33668467 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 25952037 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:10 PM PDT 24 |
| Finished | Aug 08 05:15:10 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-f5b99979-b72e-4449-be5f-fa8c3dd0118c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=33668467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.33668467 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3473861086 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26191987 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:15:11 PM PDT 24 |
| Finished | Aug 08 05:15:11 PM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-c1c7921a-f388-4112-9c24-e3819d120c99 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3473861086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3473861086 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.622312005 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27764562 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:38 PM PDT 24 |
| Finished | Aug 08 05:15:39 PM PDT 24 |
| Peak memory | 145512 kb |
| Host | smart-8733db24-10d9-492f-8f5e-9a094d042d2c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=622312005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.622312005 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.481075078 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26743329 ps |
| CPU time | 0.4 seconds |
| Started | Aug 08 05:15:11 PM PDT 24 |
| Finished | Aug 08 05:15:13 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-7537e6de-ffbd-4bf8-9fb8-fdde03bb02e7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=481075078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.481075078 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4057961447 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27611636 ps |
| CPU time | 0.39 seconds |
| Started | Aug 08 05:15:18 PM PDT 24 |
| Finished | Aug 08 05:15:18 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-e71068af-0806-4880-b302-7cd0914f3aa6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4057961447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.4057961447 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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