Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.23 89.23 100.00 100.00 95.83 95.83 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/5.prim_async_alert.3998312481
92.35 3.13 100.00 0.00 95.83 0.00 100.00 0.00 85.71 7.14 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/12.prim_sync_alert.861407029
94.11 1.76 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 83.72 6.98 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2455120662
94.50 0.39 100.00 0.00 95.83 0.00 100.00 0.00 89.29 0.00 95.83 0.00 86.05 2.33 /workspace/coverage/default/1.prim_async_alert.3011372866
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.369549286

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3966524384
/workspace/coverage/default/10.prim_async_alert.2715907824
/workspace/coverage/default/12.prim_async_alert.3846874310
/workspace/coverage/default/13.prim_async_alert.3394561864
/workspace/coverage/default/14.prim_async_alert.3445642383
/workspace/coverage/default/15.prim_async_alert.361768911
/workspace/coverage/default/16.prim_async_alert.3902938389
/workspace/coverage/default/17.prim_async_alert.873181328
/workspace/coverage/default/18.prim_async_alert.1146293242
/workspace/coverage/default/19.prim_async_alert.3356658820
/workspace/coverage/default/2.prim_async_alert.2099122452
/workspace/coverage/default/3.prim_async_alert.1612219582
/workspace/coverage/default/4.prim_async_alert.3104435721
/workspace/coverage/default/6.prim_async_alert.3927202432
/workspace/coverage/default/7.prim_async_alert.227569455
/workspace/coverage/default/8.prim_async_alert.429561975
/workspace/coverage/default/9.prim_async_alert.2763672962
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2126950099
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4110363476
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1536035129
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3203178967
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4226643514
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3778116590
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2052317360
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2822668972
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2112226028
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.879564950
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3186886739
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2222759571
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.646488954
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4015411551
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.86106486
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1342704415
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.202090346
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2366220827
/workspace/coverage/sync_alert/0.prim_sync_alert.2666657158
/workspace/coverage/sync_alert/1.prim_sync_alert.3318268005
/workspace/coverage/sync_alert/10.prim_sync_alert.1576535485
/workspace/coverage/sync_alert/11.prim_sync_alert.1125783469
/workspace/coverage/sync_alert/13.prim_sync_alert.2952200740
/workspace/coverage/sync_alert/14.prim_sync_alert.3581991285
/workspace/coverage/sync_alert/15.prim_sync_alert.2102300969
/workspace/coverage/sync_alert/16.prim_sync_alert.2894240794
/workspace/coverage/sync_alert/17.prim_sync_alert.3613306539
/workspace/coverage/sync_alert/18.prim_sync_alert.617591539
/workspace/coverage/sync_alert/19.prim_sync_alert.3477627476
/workspace/coverage/sync_alert/2.prim_sync_alert.2731157066
/workspace/coverage/sync_alert/3.prim_sync_alert.2987427266
/workspace/coverage/sync_alert/4.prim_sync_alert.1254029070
/workspace/coverage/sync_alert/5.prim_sync_alert.1178468143
/workspace/coverage/sync_alert/6.prim_sync_alert.2976684442
/workspace/coverage/sync_alert/7.prim_sync_alert.1518772697
/workspace/coverage/sync_alert/8.prim_sync_alert.2549801309
/workspace/coverage/sync_alert/9.prim_sync_alert.380338508
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3372407509
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.291646904
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2559284063
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1219661880
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3472428528
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3269677948
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2960711511
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1817411580
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.213613370
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2598594300
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1641806266
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1163071821
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1134612546
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3855921470
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.491326154
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2132331173
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3957540052
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1700444764
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.928515142
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2511461798



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/9.prim_async_alert.2763672962 Aug 09 04:21:55 PM PDT 24 Aug 09 04:21:55 PM PDT 24 11200689 ps
T2 /workspace/coverage/default/12.prim_async_alert.3846874310 Aug 09 04:26:14 PM PDT 24 Aug 09 04:26:15 PM PDT 24 11511468 ps
T3 /workspace/coverage/default/5.prim_async_alert.3998312481 Aug 09 04:21:09 PM PDT 24 Aug 09 04:21:09 PM PDT 24 11939125 ps
T8 /workspace/coverage/default/16.prim_async_alert.3902938389 Aug 09 04:25:12 PM PDT 24 Aug 09 04:25:13 PM PDT 24 11880528 ps
T16 /workspace/coverage/default/19.prim_async_alert.3356658820 Aug 09 04:26:19 PM PDT 24 Aug 09 04:26:20 PM PDT 24 11063854 ps
T7 /workspace/coverage/default/7.prim_async_alert.227569455 Aug 09 04:26:06 PM PDT 24 Aug 09 04:26:07 PM PDT 24 12093069 ps
T17 /workspace/coverage/default/14.prim_async_alert.3445642383 Aug 09 04:25:37 PM PDT 24 Aug 09 04:25:38 PM PDT 24 11817855 ps
T18 /workspace/coverage/default/15.prim_async_alert.361768911 Aug 09 04:26:10 PM PDT 24 Aug 09 04:26:11 PM PDT 24 11101558 ps
T19 /workspace/coverage/default/18.prim_async_alert.1146293242 Aug 09 04:25:25 PM PDT 24 Aug 09 04:25:26 PM PDT 24 11538872 ps
T20 /workspace/coverage/default/8.prim_async_alert.429561975 Aug 09 04:24:00 PM PDT 24 Aug 09 04:24:00 PM PDT 24 11506556 ps
T27 /workspace/coverage/default/17.prim_async_alert.873181328 Aug 09 04:25:12 PM PDT 24 Aug 09 04:25:13 PM PDT 24 11529867 ps
T28 /workspace/coverage/default/0.prim_async_alert.3966524384 Aug 09 04:25:48 PM PDT 24 Aug 09 04:25:49 PM PDT 24 10910335 ps
T21 /workspace/coverage/default/10.prim_async_alert.2715907824 Aug 09 04:23:20 PM PDT 24 Aug 09 04:23:21 PM PDT 24 11169862 ps
T11 /workspace/coverage/default/2.prim_async_alert.2099122452 Aug 09 04:21:59 PM PDT 24 Aug 09 04:21:59 PM PDT 24 11361799 ps
T50 /workspace/coverage/default/4.prim_async_alert.3104435721 Aug 09 04:21:17 PM PDT 24 Aug 09 04:21:17 PM PDT 24 10663439 ps
T22 /workspace/coverage/default/3.prim_async_alert.1612219582 Aug 09 04:20:40 PM PDT 24 Aug 09 04:20:41 PM PDT 24 12071327 ps
T51 /workspace/coverage/default/6.prim_async_alert.3927202432 Aug 09 04:24:00 PM PDT 24 Aug 09 04:24:00 PM PDT 24 10128518 ps
T23 /workspace/coverage/default/1.prim_async_alert.3011372866 Aug 09 04:20:49 PM PDT 24 Aug 09 04:20:50 PM PDT 24 10571269 ps
T24 /workspace/coverage/default/13.prim_async_alert.3394561864 Aug 09 04:26:29 PM PDT 24 Aug 09 04:26:30 PM PDT 24 10689322 ps
T44 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4110363476 Aug 09 04:21:32 PM PDT 24 Aug 09 04:21:33 PM PDT 24 30036949 ps
T25 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.646488954 Aug 09 04:25:20 PM PDT 24 Aug 09 04:25:21 PM PDT 24 27725394 ps
T9 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2455120662 Aug 09 04:25:39 PM PDT 24 Aug 09 04:25:40 PM PDT 24 29344977 ps
T45 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2052317360 Aug 09 04:25:21 PM PDT 24 Aug 09 04:25:21 PM PDT 24 30784146 ps
T46 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3778116590 Aug 09 04:25:39 PM PDT 24 Aug 09 04:25:40 PM PDT 24 30885290 ps
T14 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.86106486 Aug 09 04:25:38 PM PDT 24 Aug 09 04:25:39 PM PDT 24 30566578 ps
T26 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3203178967 Aug 09 04:24:10 PM PDT 24 Aug 09 04:24:11 PM PDT 24 28974938 ps
T47 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2126950099 Aug 09 04:20:49 PM PDT 24 Aug 09 04:20:50 PM PDT 24 30261712 ps
T48 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4015411551 Aug 09 04:20:41 PM PDT 24 Aug 09 04:20:42 PM PDT 24 29772999 ps
T49 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2366220827 Aug 09 04:25:45 PM PDT 24 Aug 09 04:25:45 PM PDT 24 29475474 ps
T52 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2222759571 Aug 09 04:25:04 PM PDT 24 Aug 09 04:25:05 PM PDT 24 30123794 ps
T4 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.202090346 Aug 09 04:25:39 PM PDT 24 Aug 09 04:25:40 PM PDT 24 29618840 ps
T53 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4226643514 Aug 09 04:25:55 PM PDT 24 Aug 09 04:25:56 PM PDT 24 30262888 ps
T15 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.879564950 Aug 09 04:25:38 PM PDT 24 Aug 09 04:25:38 PM PDT 24 29706482 ps
T12 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3186886739 Aug 09 04:23:02 PM PDT 24 Aug 09 04:23:02 PM PDT 24 30555161 ps
T13 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1342704415 Aug 09 04:23:13 PM PDT 24 Aug 09 04:23:14 PM PDT 24 32147721 ps
T54 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2822668972 Aug 09 04:25:39 PM PDT 24 Aug 09 04:25:40 PM PDT 24 29824187 ps
T55 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2112226028 Aug 09 04:25:04 PM PDT 24 Aug 09 04:25:05 PM PDT 24 30347735 ps
T56 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1536035129 Aug 09 04:24:18 PM PDT 24 Aug 09 04:24:18 PM PDT 24 31249713 ps
T5 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.369549286 Aug 09 04:25:46 PM PDT 24 Aug 09 04:25:46 PM PDT 24 28927683 ps
T37 /workspace/coverage/sync_alert/5.prim_sync_alert.1178468143 Aug 09 04:25:32 PM PDT 24 Aug 09 04:25:33 PM PDT 24 8526079 ps
T29 /workspace/coverage/sync_alert/17.prim_sync_alert.3613306539 Aug 09 04:23:35 PM PDT 24 Aug 09 04:23:35 PM PDT 24 8822975 ps
T38 /workspace/coverage/sync_alert/0.prim_sync_alert.2666657158 Aug 09 04:25:31 PM PDT 24 Aug 09 04:25:32 PM PDT 24 9393202 ps
T30 /workspace/coverage/sync_alert/14.prim_sync_alert.3581991285 Aug 09 04:20:50 PM PDT 24 Aug 09 04:20:51 PM PDT 24 9208850 ps
T39 /workspace/coverage/sync_alert/13.prim_sync_alert.2952200740 Aug 09 04:25:45 PM PDT 24 Aug 09 04:25:45 PM PDT 24 9194094 ps
T40 /workspace/coverage/sync_alert/3.prim_sync_alert.2987427266 Aug 09 04:25:39 PM PDT 24 Aug 09 04:25:40 PM PDT 24 9100906 ps
T41 /workspace/coverage/sync_alert/10.prim_sync_alert.1576535485 Aug 09 04:21:40 PM PDT 24 Aug 09 04:21:40 PM PDT 24 9265495 ps
T31 /workspace/coverage/sync_alert/12.prim_sync_alert.861407029 Aug 09 04:23:58 PM PDT 24 Aug 09 04:23:59 PM PDT 24 10062259 ps
T42 /workspace/coverage/sync_alert/11.prim_sync_alert.1125783469 Aug 09 04:21:34 PM PDT 24 Aug 09 04:21:35 PM PDT 24 9198525 ps
T43 /workspace/coverage/sync_alert/7.prim_sync_alert.1518772697 Aug 09 04:20:50 PM PDT 24 Aug 09 04:20:51 PM PDT 24 9821212 ps
T32 /workspace/coverage/sync_alert/8.prim_sync_alert.2549801309 Aug 09 04:26:12 PM PDT 24 Aug 09 04:26:13 PM PDT 24 8531864 ps
T57 /workspace/coverage/sync_alert/18.prim_sync_alert.617591539 Aug 09 04:22:11 PM PDT 24 Aug 09 04:22:11 PM PDT 24 9088641 ps
T10 /workspace/coverage/sync_alert/16.prim_sync_alert.2894240794 Aug 09 04:20:53 PM PDT 24 Aug 09 04:20:53 PM PDT 24 8719701 ps
T33 /workspace/coverage/sync_alert/9.prim_sync_alert.380338508 Aug 09 04:26:14 PM PDT 24 Aug 09 04:26:14 PM PDT 24 10245359 ps
T34 /workspace/coverage/sync_alert/19.prim_sync_alert.3477627476 Aug 09 04:25:39 PM PDT 24 Aug 09 04:25:40 PM PDT 24 8463870 ps
T58 /workspace/coverage/sync_alert/2.prim_sync_alert.2731157066 Aug 09 04:22:58 PM PDT 24 Aug 09 04:22:59 PM PDT 24 8290752 ps
T59 /workspace/coverage/sync_alert/1.prim_sync_alert.3318268005 Aug 09 04:25:38 PM PDT 24 Aug 09 04:25:38 PM PDT 24 10988166 ps
T35 /workspace/coverage/sync_alert/6.prim_sync_alert.2976684442 Aug 09 04:22:32 PM PDT 24 Aug 09 04:22:32 PM PDT 24 8495484 ps
T60 /workspace/coverage/sync_alert/4.prim_sync_alert.1254029070 Aug 09 04:21:32 PM PDT 24 Aug 09 04:21:33 PM PDT 24 9585528 ps
T36 /workspace/coverage/sync_alert/15.prim_sync_alert.2102300969 Aug 09 04:23:57 PM PDT 24 Aug 09 04:23:58 PM PDT 24 9058864 ps
T61 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3269677948 Aug 09 04:21:30 PM PDT 24 Aug 09 04:21:30 PM PDT 24 24485080 ps
T62 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.291646904 Aug 09 04:24:29 PM PDT 24 Aug 09 04:24:30 PM PDT 24 27744105 ps
T63 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1641806266 Aug 09 04:26:14 PM PDT 24 Aug 09 04:26:14 PM PDT 24 27790737 ps
T64 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1700444764 Aug 09 04:23:05 PM PDT 24 Aug 09 04:23:05 PM PDT 24 29127073 ps
T6 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3472428528 Aug 09 04:25:08 PM PDT 24 Aug 09 04:25:09 PM PDT 24 26875283 ps
T65 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2132331173 Aug 09 04:25:46 PM PDT 24 Aug 09 04:25:47 PM PDT 24 26413994 ps
T66 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1219661880 Aug 09 04:23:58 PM PDT 24 Aug 09 04:23:59 PM PDT 24 27058080 ps
T67 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.213613370 Aug 09 04:25:32 PM PDT 24 Aug 09 04:25:33 PM PDT 24 28204444 ps
T68 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1163071821 Aug 09 04:21:30 PM PDT 24 Aug 09 04:21:31 PM PDT 24 28218250 ps
T69 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1134612546 Aug 09 04:22:39 PM PDT 24 Aug 09 04:22:39 PM PDT 24 26606940 ps
T70 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.491326154 Aug 09 04:21:01 PM PDT 24 Aug 09 04:21:02 PM PDT 24 27222157 ps
T71 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2960711511 Aug 09 04:21:04 PM PDT 24 Aug 09 04:21:04 PM PDT 24 26285540 ps
T72 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2598594300 Aug 09 04:25:31 PM PDT 24 Aug 09 04:25:32 PM PDT 24 27375045 ps
T73 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1817411580 Aug 09 04:22:23 PM PDT 24 Aug 09 04:22:24 PM PDT 24 28299842 ps
T74 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2559284063 Aug 09 04:21:38 PM PDT 24 Aug 09 04:21:38 PM PDT 24 27921169 ps
T75 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3372407509 Aug 09 04:25:21 PM PDT 24 Aug 09 04:25:22 PM PDT 24 26513799 ps
T76 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3957540052 Aug 09 04:24:01 PM PDT 24 Aug 09 04:24:02 PM PDT 24 28357932 ps
T77 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2511461798 Aug 09 04:22:42 PM PDT 24 Aug 09 04:22:42 PM PDT 24 26733560 ps
T78 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3855921470 Aug 09 04:22:30 PM PDT 24 Aug 09 04:22:30 PM PDT 24 27924879 ps
T79 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.928515142 Aug 09 04:25:55 PM PDT 24 Aug 09 04:25:55 PM PDT 24 28529911 ps

Test location /workspace/coverage/default/5.prim_async_alert.3998312481
Short name T3
Test name
Test status
Simulation time 11939125 ps
CPU time 0.39 seconds
Started Aug 09 04:21:09 PM PDT 24
Finished Aug 09 04:21:09 PM PDT 24
Peak memory 145652 kb
Host smart-31935230-28b9-48ed-8168-8def3513a986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998312481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3998312481
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.861407029
Short name T31
Test name
Test status
Simulation time 10062259 ps
CPU time 0.43 seconds
Started Aug 09 04:23:58 PM PDT 24
Finished Aug 09 04:23:59 PM PDT 24
Peak memory 145708 kb
Host smart-7fbeadfc-add0-46d8-841b-798a6c290572
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=861407029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.861407029
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2455120662
Short name T9
Test name
Test status
Simulation time 29344977 ps
CPU time 0.45 seconds
Started Aug 09 04:25:39 PM PDT 24
Finished Aug 09 04:25:40 PM PDT 24
Peak memory 144788 kb
Host smart-6a5dd6db-3863-4f05-a744-f411700364e2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2455120662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2455120662
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3011372866
Short name T23
Test name
Test status
Simulation time 10571269 ps
CPU time 0.39 seconds
Started Aug 09 04:20:49 PM PDT 24
Finished Aug 09 04:20:50 PM PDT 24
Peak memory 145572 kb
Host smart-e3569d10-20b2-411d-8d98-6b397b20e8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011372866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3011372866
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.369549286
Short name T5
Test name
Test status
Simulation time 28927683 ps
CPU time 0.39 seconds
Started Aug 09 04:25:46 PM PDT 24
Finished Aug 09 04:25:46 PM PDT 24
Peak memory 145184 kb
Host smart-c25f1225-5b21-444b-b7d2-ddb4b8f8b54b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=369549286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.369549286
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3966524384
Short name T28
Test name
Test status
Simulation time 10910335 ps
CPU time 0.43 seconds
Started Aug 09 04:25:48 PM PDT 24
Finished Aug 09 04:25:49 PM PDT 24
Peak memory 144832 kb
Host smart-1eee76ff-c73d-4923-8b86-3f2a718f0f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966524384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3966524384
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2715907824
Short name T21
Test name
Test status
Simulation time 11169862 ps
CPU time 0.39 seconds
Started Aug 09 04:23:20 PM PDT 24
Finished Aug 09 04:23:21 PM PDT 24
Peak memory 145664 kb
Host smart-797d2294-08fc-497c-ae35-763bf3fc459c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715907824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2715907824
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.3846874310
Short name T2
Test name
Test status
Simulation time 11511468 ps
CPU time 0.44 seconds
Started Aug 09 04:26:14 PM PDT 24
Finished Aug 09 04:26:15 PM PDT 24
Peak memory 144432 kb
Host smart-9139fe6f-1866-45a4-a865-2adac1c0c177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846874310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3846874310
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3394561864
Short name T24
Test name
Test status
Simulation time 10689322 ps
CPU time 0.36 seconds
Started Aug 09 04:26:29 PM PDT 24
Finished Aug 09 04:26:30 PM PDT 24
Peak memory 145628 kb
Host smart-e540bd76-fd80-4083-9465-13257fa21967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394561864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3394561864
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.3445642383
Short name T17
Test name
Test status
Simulation time 11817855 ps
CPU time 0.42 seconds
Started Aug 09 04:25:37 PM PDT 24
Finished Aug 09 04:25:38 PM PDT 24
Peak memory 143844 kb
Host smart-934f6409-a38f-4e00-8e4b-df7982401bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445642383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3445642383
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.361768911
Short name T18
Test name
Test status
Simulation time 11101558 ps
CPU time 0.43 seconds
Started Aug 09 04:26:10 PM PDT 24
Finished Aug 09 04:26:11 PM PDT 24
Peak memory 144144 kb
Host smart-2cf9a9e1-3821-47e3-abe5-82de0028de48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361768911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.361768911
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3902938389
Short name T8
Test name
Test status
Simulation time 11880528 ps
CPU time 0.42 seconds
Started Aug 09 04:25:12 PM PDT 24
Finished Aug 09 04:25:13 PM PDT 24
Peak memory 144132 kb
Host smart-71b8aa86-746b-436d-9e1d-39fd4c8e102d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902938389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3902938389
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.873181328
Short name T27
Test name
Test status
Simulation time 11529867 ps
CPU time 0.42 seconds
Started Aug 09 04:25:12 PM PDT 24
Finished Aug 09 04:25:13 PM PDT 24
Peak memory 144168 kb
Host smart-269d046f-a66a-4b1f-8c5b-61a3236763a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873181328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.873181328
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1146293242
Short name T19
Test name
Test status
Simulation time 11538872 ps
CPU time 0.37 seconds
Started Aug 09 04:25:25 PM PDT 24
Finished Aug 09 04:25:26 PM PDT 24
Peak memory 145640 kb
Host smart-1fd4bc35-f62c-462f-b2e5-fa10665aafbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146293242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1146293242
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3356658820
Short name T16
Test name
Test status
Simulation time 11063854 ps
CPU time 0.42 seconds
Started Aug 09 04:26:19 PM PDT 24
Finished Aug 09 04:26:20 PM PDT 24
Peak memory 145164 kb
Host smart-7a48e766-951f-4d9b-ae97-faec2ce29bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356658820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3356658820
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2099122452
Short name T11
Test name
Test status
Simulation time 11361799 ps
CPU time 0.41 seconds
Started Aug 09 04:21:59 PM PDT 24
Finished Aug 09 04:21:59 PM PDT 24
Peak memory 145664 kb
Host smart-1f51622c-f770-4fb4-a399-61d436ac8af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099122452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2099122452
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1612219582
Short name T22
Test name
Test status
Simulation time 12071327 ps
CPU time 0.39 seconds
Started Aug 09 04:20:40 PM PDT 24
Finished Aug 09 04:20:41 PM PDT 24
Peak memory 145496 kb
Host smart-f5c189c6-b937-4377-9261-e2c27753f043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612219582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1612219582
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3104435721
Short name T50
Test name
Test status
Simulation time 10663439 ps
CPU time 0.4 seconds
Started Aug 09 04:21:17 PM PDT 24
Finished Aug 09 04:21:17 PM PDT 24
Peak memory 145900 kb
Host smart-619e53ba-10ae-44f2-a56c-04cfc809fde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104435721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3104435721
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3927202432
Short name T51
Test name
Test status
Simulation time 10128518 ps
CPU time 0.41 seconds
Started Aug 09 04:24:00 PM PDT 24
Finished Aug 09 04:24:00 PM PDT 24
Peak memory 145668 kb
Host smart-84a177cf-7416-4552-b73f-b500f40f072c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927202432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3927202432
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.227569455
Short name T7
Test name
Test status
Simulation time 12093069 ps
CPU time 0.43 seconds
Started Aug 09 04:26:06 PM PDT 24
Finished Aug 09 04:26:07 PM PDT 24
Peak memory 145236 kb
Host smart-4548ef29-f8fe-4cfb-b862-d4039987be7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227569455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.227569455
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.429561975
Short name T20
Test name
Test status
Simulation time 11506556 ps
CPU time 0.42 seconds
Started Aug 09 04:24:00 PM PDT 24
Finished Aug 09 04:24:00 PM PDT 24
Peak memory 145668 kb
Host smart-0107ed2f-d0d9-48c3-abf8-9a2c1de7137e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429561975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.429561975
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2763672962
Short name T1
Test name
Test status
Simulation time 11200689 ps
CPU time 0.41 seconds
Started Aug 09 04:21:55 PM PDT 24
Finished Aug 09 04:21:55 PM PDT 24
Peak memory 145900 kb
Host smart-39ae6806-0eff-42af-873b-414f6b81b1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763672962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2763672962
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2126950099
Short name T47
Test name
Test status
Simulation time 30261712 ps
CPU time 0.42 seconds
Started Aug 09 04:20:49 PM PDT 24
Finished Aug 09 04:20:50 PM PDT 24
Peak memory 145088 kb
Host smart-883bb181-5f02-4191-ad9f-a940616f0de9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2126950099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2126950099
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4110363476
Short name T44
Test name
Test status
Simulation time 30036949 ps
CPU time 0.43 seconds
Started Aug 09 04:21:32 PM PDT 24
Finished Aug 09 04:21:33 PM PDT 24
Peak memory 145180 kb
Host smart-f8601039-a8b4-43b9-9357-a842be4b938b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4110363476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.4110363476
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1536035129
Short name T56
Test name
Test status
Simulation time 31249713 ps
CPU time 0.41 seconds
Started Aug 09 04:24:18 PM PDT 24
Finished Aug 09 04:24:18 PM PDT 24
Peak memory 145420 kb
Host smart-04f81ba4-766f-42b3-802e-dd8e21335cb7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1536035129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1536035129
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3203178967
Short name T26
Test name
Test status
Simulation time 28974938 ps
CPU time 0.4 seconds
Started Aug 09 04:24:10 PM PDT 24
Finished Aug 09 04:24:11 PM PDT 24
Peak memory 145212 kb
Host smart-922149d8-439a-4a01-9482-42a42a0f13ed
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3203178967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3203178967
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4226643514
Short name T53
Test name
Test status
Simulation time 30262888 ps
CPU time 0.4 seconds
Started Aug 09 04:25:55 PM PDT 24
Finished Aug 09 04:25:56 PM PDT 24
Peak memory 145176 kb
Host smart-5a6cd48c-0140-47c9-9842-5a42b2fc8b6d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4226643514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.4226643514
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3778116590
Short name T46
Test name
Test status
Simulation time 30885290 ps
CPU time 0.4 seconds
Started Aug 09 04:25:39 PM PDT 24
Finished Aug 09 04:25:40 PM PDT 24
Peak memory 144388 kb
Host smart-257b9f4e-c856-4065-bf1e-650379a8b00c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3778116590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3778116590
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2052317360
Short name T45
Test name
Test status
Simulation time 30784146 ps
CPU time 0.41 seconds
Started Aug 09 04:25:21 PM PDT 24
Finished Aug 09 04:25:21 PM PDT 24
Peak memory 145168 kb
Host smart-4f6a2d0d-0e35-4f73-96c5-297e98c14cb6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2052317360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2052317360
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2822668972
Short name T54
Test name
Test status
Simulation time 29824187 ps
CPU time 0.43 seconds
Started Aug 09 04:25:39 PM PDT 24
Finished Aug 09 04:25:40 PM PDT 24
Peak memory 144788 kb
Host smart-661ccc18-9160-464c-97f6-fcc5eefc7800
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2822668972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2822668972
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2112226028
Short name T55
Test name
Test status
Simulation time 30347735 ps
CPU time 0.41 seconds
Started Aug 09 04:25:04 PM PDT 24
Finished Aug 09 04:25:05 PM PDT 24
Peak memory 144172 kb
Host smart-27bb63b1-412f-4ae1-9b85-5b9ab5382d91
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2112226028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2112226028
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.879564950
Short name T15
Test name
Test status
Simulation time 29706482 ps
CPU time 0.38 seconds
Started Aug 09 04:25:38 PM PDT 24
Finished Aug 09 04:25:38 PM PDT 24
Peak memory 145152 kb
Host smart-9cf4834a-9d99-4259-8930-5fc9fae70ca6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=879564950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.879564950
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3186886739
Short name T12
Test name
Test status
Simulation time 30555161 ps
CPU time 0.49 seconds
Started Aug 09 04:23:02 PM PDT 24
Finished Aug 09 04:23:02 PM PDT 24
Peak memory 145220 kb
Host smart-19a06c11-d06b-4526-9944-ed7072229104
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3186886739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3186886739
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2222759571
Short name T52
Test name
Test status
Simulation time 30123794 ps
CPU time 0.41 seconds
Started Aug 09 04:25:04 PM PDT 24
Finished Aug 09 04:25:05 PM PDT 24
Peak memory 143968 kb
Host smart-11d2045e-bb14-410b-9856-89f6554618f6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2222759571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2222759571
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.646488954
Short name T25
Test name
Test status
Simulation time 27725394 ps
CPU time 0.39 seconds
Started Aug 09 04:25:20 PM PDT 24
Finished Aug 09 04:25:21 PM PDT 24
Peak memory 145124 kb
Host smart-c80071bb-d023-4495-bbe3-e3ac3ce5019d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=646488954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.646488954
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4015411551
Short name T48
Test name
Test status
Simulation time 29772999 ps
CPU time 0.52 seconds
Started Aug 09 04:20:41 PM PDT 24
Finished Aug 09 04:20:42 PM PDT 24
Peak memory 144712 kb
Host smart-c5a3e5fa-869b-4bab-ac53-d7b27cf6d1ce
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4015411551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.4015411551
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.86106486
Short name T14
Test name
Test status
Simulation time 30566578 ps
CPU time 0.39 seconds
Started Aug 09 04:25:38 PM PDT 24
Finished Aug 09 04:25:39 PM PDT 24
Peak memory 145176 kb
Host smart-d8ece26c-f39e-4b27-8e2b-a16aa87411e3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=86106486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.86106486
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1342704415
Short name T13
Test name
Test status
Simulation time 32147721 ps
CPU time 0.41 seconds
Started Aug 09 04:23:13 PM PDT 24
Finished Aug 09 04:23:14 PM PDT 24
Peak memory 145156 kb
Host smart-d97636b8-640d-41d8-8a5a-663466d3940d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1342704415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1342704415
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.202090346
Short name T4
Test name
Test status
Simulation time 29618840 ps
CPU time 0.39 seconds
Started Aug 09 04:25:39 PM PDT 24
Finished Aug 09 04:25:40 PM PDT 24
Peak memory 145176 kb
Host smart-b6ee036e-9e43-4d46-bbd3-1720d895a6ed
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=202090346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.202090346
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2366220827
Short name T49
Test name
Test status
Simulation time 29475474 ps
CPU time 0.4 seconds
Started Aug 09 04:25:45 PM PDT 24
Finished Aug 09 04:25:45 PM PDT 24
Peak memory 145136 kb
Host smart-377b3630-7b67-4f52-ba3a-138aa36016a8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2366220827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2366220827
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2666657158
Short name T38
Test name
Test status
Simulation time 9393202 ps
CPU time 0.46 seconds
Started Aug 09 04:25:31 PM PDT 24
Finished Aug 09 04:25:32 PM PDT 24
Peak memory 144424 kb
Host smart-1ecbc33e-4704-4aec-a6ff-6615268f0cbd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2666657158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2666657158
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3318268005
Short name T59
Test name
Test status
Simulation time 10988166 ps
CPU time 0.39 seconds
Started Aug 09 04:25:38 PM PDT 24
Finished Aug 09 04:25:38 PM PDT 24
Peak memory 145440 kb
Host smart-1bec67da-3860-403e-b41a-56c0e77da0b1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3318268005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3318268005
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1576535485
Short name T41
Test name
Test status
Simulation time 9265495 ps
CPU time 0.4 seconds
Started Aug 09 04:21:40 PM PDT 24
Finished Aug 09 04:21:40 PM PDT 24
Peak memory 145444 kb
Host smart-86f0757c-55de-4be0-97bc-2f837fbe56ff
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1576535485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1576535485
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1125783469
Short name T42
Test name
Test status
Simulation time 9198525 ps
CPU time 0.52 seconds
Started Aug 09 04:21:34 PM PDT 24
Finished Aug 09 04:21:35 PM PDT 24
Peak memory 144492 kb
Host smart-d8b44e48-b7b2-4278-884e-7640f5188a09
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1125783469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1125783469
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2952200740
Short name T39
Test name
Test status
Simulation time 9194094 ps
CPU time 0.38 seconds
Started Aug 09 04:25:45 PM PDT 24
Finished Aug 09 04:25:45 PM PDT 24
Peak memory 145476 kb
Host smart-e9a1c407-3e0b-4e47-8fcc-01bffbf64777
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2952200740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2952200740
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3581991285
Short name T30
Test name
Test status
Simulation time 9208850 ps
CPU time 0.38 seconds
Started Aug 09 04:20:50 PM PDT 24
Finished Aug 09 04:20:51 PM PDT 24
Peak memory 145328 kb
Host smart-3abf1ab7-f1b6-49d6-a8f3-3cf321604ac5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3581991285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3581991285
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2102300969
Short name T36
Test name
Test status
Simulation time 9058864 ps
CPU time 0.4 seconds
Started Aug 09 04:23:57 PM PDT 24
Finished Aug 09 04:23:58 PM PDT 24
Peak memory 145712 kb
Host smart-0a0fa133-54ad-49f7-9184-eee0e66d273d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2102300969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2102300969
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2894240794
Short name T10
Test name
Test status
Simulation time 8719701 ps
CPU time 0.38 seconds
Started Aug 09 04:20:53 PM PDT 24
Finished Aug 09 04:20:53 PM PDT 24
Peak memory 145452 kb
Host smart-eb2d66a4-be3d-4bd0-bf07-d04e64c4f43e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2894240794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2894240794
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3613306539
Short name T29
Test name
Test status
Simulation time 8822975 ps
CPU time 0.42 seconds
Started Aug 09 04:23:35 PM PDT 24
Finished Aug 09 04:23:35 PM PDT 24
Peak memory 145484 kb
Host smart-ac350736-bad6-45a1-bdab-eb17a66da274
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3613306539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3613306539
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.617591539
Short name T57
Test name
Test status
Simulation time 9088641 ps
CPU time 0.43 seconds
Started Aug 09 04:22:11 PM PDT 24
Finished Aug 09 04:22:11 PM PDT 24
Peak memory 145452 kb
Host smart-9e244d3c-15ab-4706-85c0-3294bba9924c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=617591539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.617591539
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3477627476
Short name T34
Test name
Test status
Simulation time 8463870 ps
CPU time 0.37 seconds
Started Aug 09 04:25:39 PM PDT 24
Finished Aug 09 04:25:40 PM PDT 24
Peak memory 145448 kb
Host smart-73e910a5-fdb6-453c-aa4d-c9bfb325a973
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3477627476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3477627476
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2731157066
Short name T58
Test name
Test status
Simulation time 8290752 ps
CPU time 0.39 seconds
Started Aug 09 04:22:58 PM PDT 24
Finished Aug 09 04:22:59 PM PDT 24
Peak memory 145452 kb
Host smart-3e1abec6-b848-41f2-8229-92e4d8834bf2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2731157066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2731157066
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2987427266
Short name T40
Test name
Test status
Simulation time 9100906 ps
CPU time 0.37 seconds
Started Aug 09 04:25:39 PM PDT 24
Finished Aug 09 04:25:40 PM PDT 24
Peak memory 145032 kb
Host smart-0fe02bc5-701a-4b85-bada-295aa996f606
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2987427266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2987427266
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1254029070
Short name T60
Test name
Test status
Simulation time 9585528 ps
CPU time 0.42 seconds
Started Aug 09 04:21:32 PM PDT 24
Finished Aug 09 04:21:33 PM PDT 24
Peak memory 145444 kb
Host smart-abd28168-3c58-4e50-a847-2237f0debd00
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1254029070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1254029070
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1178468143
Short name T37
Test name
Test status
Simulation time 8526079 ps
CPU time 0.41 seconds
Started Aug 09 04:25:32 PM PDT 24
Finished Aug 09 04:25:33 PM PDT 24
Peak memory 144108 kb
Host smart-0edd876f-6068-421e-b13f-75fdb73838b2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1178468143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1178468143
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2976684442
Short name T35
Test name
Test status
Simulation time 8495484 ps
CPU time 0.39 seconds
Started Aug 09 04:22:32 PM PDT 24
Finished Aug 09 04:22:32 PM PDT 24
Peak memory 145708 kb
Host smart-56ea9ccd-8ac6-44cf-a045-bc54a7bd8f4b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2976684442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2976684442
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1518772697
Short name T43
Test name
Test status
Simulation time 9821212 ps
CPU time 0.39 seconds
Started Aug 09 04:20:50 PM PDT 24
Finished Aug 09 04:20:51 PM PDT 24
Peak memory 145308 kb
Host smart-08d02ce5-601e-43b4-a00d-db387dc69396
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1518772697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1518772697
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2549801309
Short name T32
Test name
Test status
Simulation time 8531864 ps
CPU time 0.4 seconds
Started Aug 09 04:26:12 PM PDT 24
Finished Aug 09 04:26:13 PM PDT 24
Peak memory 144260 kb
Host smart-8068d12c-c74b-4f0f-a5b9-62d057ff7a18
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2549801309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2549801309
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.380338508
Short name T33
Test name
Test status
Simulation time 10245359 ps
CPU time 0.38 seconds
Started Aug 09 04:26:14 PM PDT 24
Finished Aug 09 04:26:14 PM PDT 24
Peak memory 144760 kb
Host smart-204b31be-60b5-4815-8b5c-3fe167a7de30
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=380338508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.380338508
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3372407509
Short name T75
Test name
Test status
Simulation time 26513799 ps
CPU time 0.37 seconds
Started Aug 09 04:25:21 PM PDT 24
Finished Aug 09 04:25:22 PM PDT 24
Peak memory 145452 kb
Host smart-aa568946-7804-4e2b-bba5-4433bdc8b7eb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3372407509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3372407509
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.291646904
Short name T62
Test name
Test status
Simulation time 27744105 ps
CPU time 0.4 seconds
Started Aug 09 04:24:29 PM PDT 24
Finished Aug 09 04:24:30 PM PDT 24
Peak memory 145468 kb
Host smart-f2e963a7-7218-40d4-8b56-d8e1f577a833
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=291646904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.291646904
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2559284063
Short name T74
Test name
Test status
Simulation time 27921169 ps
CPU time 0.4 seconds
Started Aug 09 04:21:38 PM PDT 24
Finished Aug 09 04:21:38 PM PDT 24
Peak memory 145456 kb
Host smart-53416fb1-804f-47e0-84fb-1e72a597d6af
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2559284063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2559284063
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1219661880
Short name T66
Test name
Test status
Simulation time 27058080 ps
CPU time 0.42 seconds
Started Aug 09 04:23:58 PM PDT 24
Finished Aug 09 04:23:59 PM PDT 24
Peak memory 145716 kb
Host smart-c918fc1b-2760-4c8d-9ba8-53e6e4c66102
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1219661880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1219661880
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3472428528
Short name T6
Test name
Test status
Simulation time 26875283 ps
CPU time 0.42 seconds
Started Aug 09 04:25:08 PM PDT 24
Finished Aug 09 04:25:09 PM PDT 24
Peak memory 144364 kb
Host smart-905d5957-cac9-45ce-a2e4-f039a797a222
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3472428528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3472428528
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3269677948
Short name T61
Test name
Test status
Simulation time 24485080 ps
CPU time 0.39 seconds
Started Aug 09 04:21:30 PM PDT 24
Finished Aug 09 04:21:30 PM PDT 24
Peak memory 145476 kb
Host smart-acc21b94-6958-4cdf-9cde-70caadac4700
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3269677948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3269677948
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2960711511
Short name T71
Test name
Test status
Simulation time 26285540 ps
CPU time 0.45 seconds
Started Aug 09 04:21:04 PM PDT 24
Finished Aug 09 04:21:04 PM PDT 24
Peak memory 145364 kb
Host smart-f13ddc27-3e90-4eb8-846a-f2eaaa41fc0f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2960711511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2960711511
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1817411580
Short name T73
Test name
Test status
Simulation time 28299842 ps
CPU time 0.46 seconds
Started Aug 09 04:22:23 PM PDT 24
Finished Aug 09 04:22:24 PM PDT 24
Peak memory 145460 kb
Host smart-4adf59c6-58f8-4a5f-b25b-1b892b0c6e76
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1817411580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1817411580
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.213613370
Short name T67
Test name
Test status
Simulation time 28204444 ps
CPU time 0.41 seconds
Started Aug 09 04:25:32 PM PDT 24
Finished Aug 09 04:25:33 PM PDT 24
Peak memory 145204 kb
Host smart-4f3ebe20-ec92-4cce-98c4-195a205d440e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=213613370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.213613370
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2598594300
Short name T72
Test name
Test status
Simulation time 27375045 ps
CPU time 0.42 seconds
Started Aug 09 04:25:31 PM PDT 24
Finished Aug 09 04:25:32 PM PDT 24
Peak memory 144464 kb
Host smart-d47dd1a6-132c-4952-8816-219237c409a2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2598594300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2598594300
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1641806266
Short name T63
Test name
Test status
Simulation time 27790737 ps
CPU time 0.4 seconds
Started Aug 09 04:26:14 PM PDT 24
Finished Aug 09 04:26:14 PM PDT 24
Peak memory 145200 kb
Host smart-4ee85d94-1ef8-497f-b66c-39a7c20ae191
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1641806266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1641806266
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1163071821
Short name T68
Test name
Test status
Simulation time 28218250 ps
CPU time 0.42 seconds
Started Aug 09 04:21:30 PM PDT 24
Finished Aug 09 04:21:31 PM PDT 24
Peak memory 145476 kb
Host smart-4b3efa5e-d195-4e4a-b9dd-7a98488fec0f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1163071821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1163071821
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1134612546
Short name T69
Test name
Test status
Simulation time 26606940 ps
CPU time 0.44 seconds
Started Aug 09 04:22:39 PM PDT 24
Finished Aug 09 04:22:39 PM PDT 24
Peak memory 145464 kb
Host smart-3025b657-893c-41a5-9449-666267a10aec
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1134612546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1134612546
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3855921470
Short name T78
Test name
Test status
Simulation time 27924879 ps
CPU time 0.4 seconds
Started Aug 09 04:22:30 PM PDT 24
Finished Aug 09 04:22:30 PM PDT 24
Peak memory 144252 kb
Host smart-993f1c97-e189-4dca-bccc-964fcca19c3e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3855921470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3855921470
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.491326154
Short name T70
Test name
Test status
Simulation time 27222157 ps
CPU time 0.4 seconds
Started Aug 09 04:21:01 PM PDT 24
Finished Aug 09 04:21:02 PM PDT 24
Peak memory 145428 kb
Host smart-26fa8de1-2492-4ed7-8f23-995d2bc247d2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=491326154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.491326154
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2132331173
Short name T65
Test name
Test status
Simulation time 26413994 ps
CPU time 0.38 seconds
Started Aug 09 04:25:46 PM PDT 24
Finished Aug 09 04:25:47 PM PDT 24
Peak memory 145452 kb
Host smart-6c83f915-688a-4e3b-ba03-389ddd72f9fc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2132331173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2132331173
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3957540052
Short name T76
Test name
Test status
Simulation time 28357932 ps
CPU time 0.4 seconds
Started Aug 09 04:24:01 PM PDT 24
Finished Aug 09 04:24:02 PM PDT 24
Peak memory 145460 kb
Host smart-6f8fcbf4-e6b1-49e4-8bae-66da68f504d9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3957540052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3957540052
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1700444764
Short name T64
Test name
Test status
Simulation time 29127073 ps
CPU time 0.39 seconds
Started Aug 09 04:23:05 PM PDT 24
Finished Aug 09 04:23:05 PM PDT 24
Peak memory 145472 kb
Host smart-6334d372-fc6d-4e20-8340-39502e9b78bb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1700444764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1700444764
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.928515142
Short name T79
Test name
Test status
Simulation time 28529911 ps
CPU time 0.39 seconds
Started Aug 09 04:25:55 PM PDT 24
Finished Aug 09 04:25:55 PM PDT 24
Peak memory 145280 kb
Host smart-315d6e80-492b-4e9f-99b2-17939099c205
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=928515142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.928515142
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2511461798
Short name T77
Test name
Test status
Simulation time 26733560 ps
CPU time 0.41 seconds
Started Aug 09 04:22:42 PM PDT 24
Finished Aug 09 04:22:42 PM PDT 24
Peak memory 145628 kb
Host smart-159a12b9-8f95-4f43-a745-75d32ecc7c49
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2511461798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2511461798
Directory /workspace/9.prim_sync_fatal_alert/latest
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